1 /* 2 * Copyright (C) 1995 Linus Torvalds 3 * 4 * Pentium III FXSR, SSE support 5 * Gareth Hughes <gareth@valinux.com>, May 2000 6 */ 7 8 /* 9 * This file handles the architecture-dependent parts of process handling.. 10 */ 11 12 #include <linux/cpu.h> 13 #include <linux/errno.h> 14 #include <linux/sched.h> 15 #include <linux/sched/task.h> 16 #include <linux/sched/task_stack.h> 17 #include <linux/fs.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/elfcore.h> 21 #include <linux/smp.h> 22 #include <linux/stddef.h> 23 #include <linux/slab.h> 24 #include <linux/vmalloc.h> 25 #include <linux/user.h> 26 #include <linux/interrupt.h> 27 #include <linux/delay.h> 28 #include <linux/reboot.h> 29 #include <linux/mc146818rtc.h> 30 #include <linux/export.h> 31 #include <linux/kallsyms.h> 32 #include <linux/ptrace.h> 33 #include <linux/personality.h> 34 #include <linux/percpu.h> 35 #include <linux/prctl.h> 36 #include <linux/ftrace.h> 37 #include <linux/uaccess.h> 38 #include <linux/io.h> 39 #include <linux/kdebug.h> 40 #include <linux/syscalls.h> 41 42 #include <asm/ldt.h> 43 #include <asm/processor.h> 44 #include <asm/fpu/sched.h> 45 #include <asm/desc.h> 46 47 #include <linux/err.h> 48 49 #include <asm/tlbflush.h> 50 #include <asm/cpu.h> 51 #include <asm/debugreg.h> 52 #include <asm/switch_to.h> 53 #include <asm/vm86.h> 54 #include <asm/resctrl.h> 55 #include <asm/proto.h> 56 57 #include "process.h" 58 59 void __show_regs(struct pt_regs *regs, enum show_regs_mode mode, 60 const char *log_lvl) 61 { 62 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; 63 unsigned long d0, d1, d2, d3, d6, d7; 64 unsigned short gs; 65 66 if (user_mode(regs)) 67 gs = get_user_gs(regs); 68 else 69 savesegment(gs, gs); 70 71 show_ip(regs, log_lvl); 72 73 printk("%sEAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n", 74 log_lvl, regs->ax, regs->bx, regs->cx, regs->dx); 75 printk("%sESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n", 76 log_lvl, regs->si, regs->di, regs->bp, regs->sp); 77 printk("%sDS: %04x ES: %04x FS: %04x GS: %04x SS: %04x EFLAGS: %08lx\n", 78 log_lvl, (u16)regs->ds, (u16)regs->es, (u16)regs->fs, gs, regs->ss, regs->flags); 79 80 if (mode != SHOW_REGS_ALL) 81 return; 82 83 cr0 = read_cr0(); 84 cr2 = read_cr2(); 85 cr3 = __read_cr3(); 86 cr4 = __read_cr4(); 87 printk("%sCR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n", 88 log_lvl, cr0, cr2, cr3, cr4); 89 90 get_debugreg(d0, 0); 91 get_debugreg(d1, 1); 92 get_debugreg(d2, 2); 93 get_debugreg(d3, 3); 94 get_debugreg(d6, 6); 95 get_debugreg(d7, 7); 96 97 /* Only print out debug registers if they are in their non-default state. */ 98 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) && 99 (d6 == DR6_RESERVED) && (d7 == 0x400)) 100 return; 101 102 printk("%sDR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n", 103 log_lvl, d0, d1, d2, d3); 104 printk("%sDR6: %08lx DR7: %08lx\n", 105 log_lvl, d6, d7); 106 } 107 108 void release_thread(struct task_struct *dead_task) 109 { 110 BUG_ON(dead_task->mm); 111 release_vm86_irqs(dead_task); 112 } 113 114 void 115 start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp) 116 { 117 set_user_gs(regs, 0); 118 regs->fs = 0; 119 regs->ds = __USER_DS; 120 regs->es = __USER_DS; 121 regs->ss = __USER_DS; 122 regs->cs = __USER_CS; 123 regs->ip = new_ip; 124 regs->sp = new_sp; 125 regs->flags = X86_EFLAGS_IF; 126 } 127 EXPORT_SYMBOL_GPL(start_thread); 128 129 130 /* 131 * switch_to(x,y) should switch tasks from x to y. 132 * 133 * We fsave/fwait so that an exception goes off at the right time 134 * (as a call from the fsave or fwait in effect) rather than to 135 * the wrong process. Lazy FP saving no longer makes any sense 136 * with modern CPU's, and this simplifies a lot of things (SMP 137 * and UP become the same). 138 * 139 * NOTE! We used to use the x86 hardware context switching. The 140 * reason for not using it any more becomes apparent when you 141 * try to recover gracefully from saved state that is no longer 142 * valid (stale segment register values in particular). With the 143 * hardware task-switch, there is no way to fix up bad state in 144 * a reasonable manner. 145 * 146 * The fact that Intel documents the hardware task-switching to 147 * be slow is a fairly red herring - this code is not noticeably 148 * faster. However, there _is_ some room for improvement here, 149 * so the performance issues may eventually be a valid point. 150 * More important, however, is the fact that this allows us much 151 * more flexibility. 152 * 153 * The return value (in %ax) will be the "prev" task after 154 * the task-switch, and shows up in ret_from_fork in entry.S, 155 * for example. 156 */ 157 __visible __notrace_funcgraph struct task_struct * 158 __switch_to(struct task_struct *prev_p, struct task_struct *next_p) 159 { 160 struct thread_struct *prev = &prev_p->thread, 161 *next = &next_p->thread; 162 struct fpu *prev_fpu = &prev->fpu; 163 int cpu = smp_processor_id(); 164 165 /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */ 166 167 if (!test_thread_flag(TIF_NEED_FPU_LOAD)) 168 switch_fpu_prepare(prev_fpu, cpu); 169 170 /* 171 * Save away %gs. No need to save %fs, as it was saved on the 172 * stack on entry. No need to save %es and %ds, as those are 173 * always kernel segments while inside the kernel. Doing this 174 * before setting the new TLS descriptors avoids the situation 175 * where we temporarily have non-reloadable segments in %fs 176 * and %gs. This could be an issue if the NMI handler ever 177 * used %fs or %gs (it does not today), or if the kernel is 178 * running inside of a hypervisor layer. 179 */ 180 lazy_save_gs(prev->gs); 181 182 /* 183 * Load the per-thread Thread-Local Storage descriptor. 184 */ 185 load_TLS(next, cpu); 186 187 switch_to_extra(prev_p, next_p); 188 189 /* 190 * Leave lazy mode, flushing any hypercalls made here. 191 * This must be done before restoring TLS segments so 192 * the GDT and LDT are properly updated. 193 */ 194 arch_end_context_switch(next_p); 195 196 /* 197 * Reload esp0 and cpu_current_top_of_stack. This changes 198 * current_thread_info(). Refresh the SYSENTER configuration in 199 * case prev or next is vm86. 200 */ 201 update_task_stack(next_p); 202 refresh_sysenter_cs(next); 203 this_cpu_write(cpu_current_top_of_stack, 204 (unsigned long)task_stack_page(next_p) + 205 THREAD_SIZE); 206 207 /* 208 * Restore %gs if needed (which is common) 209 */ 210 if (prev->gs | next->gs) 211 lazy_load_gs(next->gs); 212 213 this_cpu_write(current_task, next_p); 214 215 switch_fpu_finish(); 216 217 /* Load the Intel cache allocation PQR MSR. */ 218 resctrl_sched_in(); 219 220 return prev_p; 221 } 222 223 SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2) 224 { 225 return do_arch_prctl_common(current, option, arg2); 226 } 227