1 #include <linux/errno.h> 2 #include <linux/kernel.h> 3 #include <linux/mm.h> 4 #include <linux/smp.h> 5 #include <linux/slab.h> 6 #include <linux/sched.h> 7 #include <linux/module.h> 8 #include <linux/pm.h> 9 #include <linux/clockchips.h> 10 #include <asm/system.h> 11 12 unsigned long idle_halt; 13 EXPORT_SYMBOL(idle_halt); 14 unsigned long idle_nomwait; 15 EXPORT_SYMBOL(idle_nomwait); 16 17 struct kmem_cache *task_xstate_cachep; 18 static int force_mwait __cpuinitdata; 19 20 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 21 { 22 *dst = *src; 23 if (src->thread.xstate) { 24 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep, 25 GFP_KERNEL); 26 if (!dst->thread.xstate) 27 return -ENOMEM; 28 WARN_ON((unsigned long)dst->thread.xstate & 15); 29 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size); 30 } 31 return 0; 32 } 33 34 void free_thread_xstate(struct task_struct *tsk) 35 { 36 if (tsk->thread.xstate) { 37 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate); 38 tsk->thread.xstate = NULL; 39 } 40 } 41 42 void free_thread_info(struct thread_info *ti) 43 { 44 free_thread_xstate(ti->task); 45 free_pages((unsigned long)ti, get_order(THREAD_SIZE)); 46 } 47 48 void arch_task_cache_init(void) 49 { 50 task_xstate_cachep = 51 kmem_cache_create("task_xstate", xstate_size, 52 __alignof__(union thread_xstate), 53 SLAB_PANIC, NULL); 54 } 55 56 /* 57 * Idle related variables and functions 58 */ 59 unsigned long boot_option_idle_override = 0; 60 EXPORT_SYMBOL(boot_option_idle_override); 61 62 /* 63 * Powermanagement idle function, if any.. 64 */ 65 void (*pm_idle)(void); 66 EXPORT_SYMBOL(pm_idle); 67 68 #ifdef CONFIG_X86_32 69 /* 70 * This halt magic was a workaround for ancient floppy DMA 71 * wreckage. It should be safe to remove. 72 */ 73 static int hlt_counter; 74 void disable_hlt(void) 75 { 76 hlt_counter++; 77 } 78 EXPORT_SYMBOL(disable_hlt); 79 80 void enable_hlt(void) 81 { 82 hlt_counter--; 83 } 84 EXPORT_SYMBOL(enable_hlt); 85 86 static inline int hlt_use_halt(void) 87 { 88 return (!hlt_counter && boot_cpu_data.hlt_works_ok); 89 } 90 #else 91 static inline int hlt_use_halt(void) 92 { 93 return 1; 94 } 95 #endif 96 97 /* 98 * We use this if we don't have any better 99 * idle routine.. 100 */ 101 void default_idle(void) 102 { 103 if (hlt_use_halt()) { 104 current_thread_info()->status &= ~TS_POLLING; 105 /* 106 * TS_POLLING-cleared state must be visible before we 107 * test NEED_RESCHED: 108 */ 109 smp_mb(); 110 111 if (!need_resched()) 112 safe_halt(); /* enables interrupts racelessly */ 113 else 114 local_irq_enable(); 115 current_thread_info()->status |= TS_POLLING; 116 } else { 117 local_irq_enable(); 118 /* loop is done by the caller */ 119 cpu_relax(); 120 } 121 } 122 #ifdef CONFIG_APM_MODULE 123 EXPORT_SYMBOL(default_idle); 124 #endif 125 126 static void do_nothing(void *unused) 127 { 128 } 129 130 /* 131 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of 132 * pm_idle and update to new pm_idle value. Required while changing pm_idle 133 * handler on SMP systems. 134 * 135 * Caller must have changed pm_idle to the new value before the call. Old 136 * pm_idle value will not be used by any CPU after the return of this function. 137 */ 138 void cpu_idle_wait(void) 139 { 140 smp_mb(); 141 /* kick all the CPUs so that they exit out of pm_idle */ 142 smp_call_function(do_nothing, NULL, 1); 143 } 144 EXPORT_SYMBOL_GPL(cpu_idle_wait); 145 146 /* 147 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI, 148 * which can obviate IPI to trigger checking of need_resched. 149 * We execute MONITOR against need_resched and enter optimized wait state 150 * through MWAIT. Whenever someone changes need_resched, we would be woken 151 * up from MWAIT (without an IPI). 152 * 153 * New with Core Duo processors, MWAIT can take some hints based on CPU 154 * capability. 155 */ 156 void mwait_idle_with_hints(unsigned long ax, unsigned long cx) 157 { 158 if (!need_resched()) { 159 __monitor((void *)¤t_thread_info()->flags, 0, 0); 160 smp_mb(); 161 if (!need_resched()) 162 __mwait(ax, cx); 163 } 164 } 165 166 /* Default MONITOR/MWAIT with no hints, used for default C1 state */ 167 static void mwait_idle(void) 168 { 169 if (!need_resched()) { 170 __monitor((void *)¤t_thread_info()->flags, 0, 0); 171 smp_mb(); 172 if (!need_resched()) 173 __sti_mwait(0, 0); 174 else 175 local_irq_enable(); 176 } else 177 local_irq_enable(); 178 } 179 180 /* 181 * On SMP it's slightly faster (but much more power-consuming!) 182 * to poll the ->work.need_resched flag instead of waiting for the 183 * cross-CPU IPI to arrive. Use this option with caution. 184 */ 185 static void poll_idle(void) 186 { 187 local_irq_enable(); 188 while (!need_resched()) 189 cpu_relax(); 190 } 191 192 /* 193 * mwait selection logic: 194 * 195 * It depends on the CPU. For AMD CPUs that support MWAIT this is 196 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings 197 * then depend on a clock divisor and current Pstate of the core. If 198 * all cores of a processor are in halt state (C1) the processor can 199 * enter the C1E (C1 enhanced) state. If mwait is used this will never 200 * happen. 201 * 202 * idle=mwait overrides this decision and forces the usage of mwait. 203 */ 204 static int __cpuinitdata force_mwait; 205 206 #define MWAIT_INFO 0x05 207 #define MWAIT_ECX_EXTENDED_INFO 0x01 208 #define MWAIT_EDX_C1 0xf0 209 210 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) 211 { 212 u32 eax, ebx, ecx, edx; 213 214 if (force_mwait) 215 return 1; 216 217 if (c->cpuid_level < MWAIT_INFO) 218 return 0; 219 220 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx); 221 /* Check, whether EDX has extended info about MWAIT */ 222 if (!(ecx & MWAIT_ECX_EXTENDED_INFO)) 223 return 1; 224 225 /* 226 * edx enumeratios MONITOR/MWAIT extensions. Check, whether 227 * C1 supports MWAIT 228 */ 229 return (edx & MWAIT_EDX_C1); 230 } 231 232 /* 233 * Check for AMD CPUs, which have potentially C1E support 234 */ 235 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c) 236 { 237 if (c->x86_vendor != X86_VENDOR_AMD) 238 return 0; 239 240 if (c->x86 < 0x0F) 241 return 0; 242 243 /* Family 0x0f models < rev F do not have C1E */ 244 if (c->x86 == 0x0f && c->x86_model < 0x40) 245 return 0; 246 247 return 1; 248 } 249 250 static cpumask_t c1e_mask = CPU_MASK_NONE; 251 static int c1e_detected; 252 253 void c1e_remove_cpu(int cpu) 254 { 255 cpu_clear(cpu, c1e_mask); 256 } 257 258 /* 259 * C1E aware idle routine. We check for C1E active in the interrupt 260 * pending message MSR. If we detect C1E, then we handle it the same 261 * way as C3 power states (local apic timer and TSC stop) 262 */ 263 static void c1e_idle(void) 264 { 265 if (need_resched()) 266 return; 267 268 if (!c1e_detected) { 269 u32 lo, hi; 270 271 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); 272 if (lo & K8_INTP_C1E_ACTIVE_MASK) { 273 c1e_detected = 1; 274 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 275 mark_tsc_unstable("TSC halt in AMD C1E"); 276 printk(KERN_INFO "System has AMD C1E enabled\n"); 277 set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E); 278 } 279 } 280 281 if (c1e_detected) { 282 int cpu = smp_processor_id(); 283 284 if (!cpu_isset(cpu, c1e_mask)) { 285 cpu_set(cpu, c1e_mask); 286 /* 287 * Force broadcast so ACPI can not interfere. Needs 288 * to run with interrupts enabled as it uses 289 * smp_function_call. 290 */ 291 local_irq_enable(); 292 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, 293 &cpu); 294 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n", 295 cpu); 296 local_irq_disable(); 297 } 298 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); 299 300 default_idle(); 301 302 /* 303 * The switch back from broadcast mode needs to be 304 * called with interrupts disabled. 305 */ 306 local_irq_disable(); 307 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); 308 local_irq_enable(); 309 } else 310 default_idle(); 311 } 312 313 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) 314 { 315 #ifdef CONFIG_X86_SMP 316 if (pm_idle == poll_idle && smp_num_siblings > 1) { 317 printk(KERN_WARNING "WARNING: polling idle and HT enabled," 318 " performance may degrade.\n"); 319 } 320 #endif 321 if (pm_idle) 322 return; 323 324 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { 325 /* 326 * One CPU supports mwait => All CPUs supports mwait 327 */ 328 printk(KERN_INFO "using mwait in idle threads.\n"); 329 pm_idle = mwait_idle; 330 } else if (check_c1e_idle(c)) { 331 printk(KERN_INFO "using C1E aware idle routine\n"); 332 pm_idle = c1e_idle; 333 } else 334 pm_idle = default_idle; 335 } 336 337 static int __init idle_setup(char *str) 338 { 339 if (!str) 340 return -EINVAL; 341 342 if (!strcmp(str, "poll")) { 343 printk("using polling idle threads.\n"); 344 pm_idle = poll_idle; 345 } else if (!strcmp(str, "mwait")) 346 force_mwait = 1; 347 else if (!strcmp(str, "halt")) { 348 /* 349 * When the boot option of idle=halt is added, halt is 350 * forced to be used for CPU idle. In such case CPU C2/C3 351 * won't be used again. 352 * To continue to load the CPU idle driver, don't touch 353 * the boot_option_idle_override. 354 */ 355 pm_idle = default_idle; 356 idle_halt = 1; 357 return 0; 358 } else if (!strcmp(str, "nomwait")) { 359 /* 360 * If the boot option of "idle=nomwait" is added, 361 * it means that mwait will be disabled for CPU C2/C3 362 * states. In such case it won't touch the variable 363 * of boot_option_idle_override. 364 */ 365 idle_nomwait = 1; 366 return 0; 367 } else 368 return -1; 369 370 boot_option_idle_override = 1; 371 return 0; 372 } 373 early_param("idle", idle_setup); 374 375