1 /* 2 * Intel Multiprocessor Specification 1.1 and 1.4 3 * compliant MP-table parsing routines. 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> 6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> 7 * (c) 2008 Alexey Starikovskiy <astarikovskiy@suse.de> 8 */ 9 10 #include <linux/mm.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/bootmem.h> 14 #include <linux/kernel_stat.h> 15 #include <linux/mc146818rtc.h> 16 #include <linux/bitops.h> 17 #include <linux/acpi.h> 18 #include <linux/module.h> 19 20 #include <asm/smp.h> 21 #include <asm/mtrr.h> 22 #include <asm/mpspec.h> 23 #include <asm/pgalloc.h> 24 #include <asm/io_apic.h> 25 #include <asm/proto.h> 26 #include <asm/acpi.h> 27 #include <asm/bios_ebda.h> 28 29 #include <mach_apic.h> 30 #ifdef CONFIG_X86_32 31 #include <mach_apicdef.h> 32 #include <mach_mpparse.h> 33 #endif 34 35 /* Have we found an MP table */ 36 int smp_found_config; 37 38 /* 39 * Various Linux-internal data structures created from the 40 * MP-table. 41 */ 42 #if defined (CONFIG_MCA) || defined (CONFIG_EISA) 43 int mp_bus_id_to_type[MAX_MP_BUSSES]; 44 #endif 45 46 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); 47 int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 }; 48 49 static int mp_current_pci_id; 50 51 int pic_mode; 52 53 /* 54 * Intel MP BIOS table parsing routines: 55 */ 56 57 /* 58 * Checksum an MP configuration block. 59 */ 60 61 static int __init mpf_checksum(unsigned char *mp, int len) 62 { 63 int sum = 0; 64 65 while (len--) 66 sum += *mp++; 67 68 return sum & 0xFF; 69 } 70 71 #ifdef CONFIG_X86_NUMAQ 72 /* 73 * Have to match translation table entries to main table entries by counter 74 * hence the mpc_record variable .... can't see a less disgusting way of 75 * doing this .... 76 */ 77 78 static int mpc_record; 79 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] 80 __cpuinitdata; 81 #endif 82 83 static void __cpuinit MP_processor_info(struct mpc_config_processor *m) 84 { 85 int apicid; 86 char *bootup_cpu = ""; 87 88 if (!(m->mpc_cpuflag & CPU_ENABLED)) { 89 disabled_cpus++; 90 return; 91 } 92 #ifdef CONFIG_X86_NUMAQ 93 apicid = mpc_apic_id(m, translation_table[mpc_record]); 94 #else 95 apicid = m->mpc_apicid; 96 #endif 97 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { 98 bootup_cpu = " (Bootup-CPU)"; 99 boot_cpu_physical_apicid = m->mpc_apicid; 100 } 101 102 printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu); 103 generic_processor_info(apicid, m->mpc_apicver); 104 } 105 106 static void __init MP_bus_info(struct mpc_config_bus *m) 107 { 108 char str[7]; 109 110 memcpy(str, m->mpc_bustype, 6); 111 str[6] = 0; 112 113 #ifdef CONFIG_X86_NUMAQ 114 mpc_oem_bus_info(m, str, translation_table[mpc_record]); 115 #else 116 Dprintk("Bus #%d is %s\n", m->mpc_busid, str); 117 #endif 118 119 #if MAX_MP_BUSSES < 256 120 if (m->mpc_busid >= MAX_MP_BUSSES) { 121 printk(KERN_WARNING "MP table busid value (%d) for bustype %s " 122 " is too large, max. supported is %d\n", 123 m->mpc_busid, str, MAX_MP_BUSSES - 1); 124 return; 125 } 126 #endif 127 128 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) { 129 set_bit(m->mpc_busid, mp_bus_not_pci); 130 #if defined(CONFIG_EISA) || defined (CONFIG_MCA) 131 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA; 132 #endif 133 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) { 134 #ifdef CONFIG_X86_NUMAQ 135 mpc_oem_pci_bus(m, translation_table[mpc_record]); 136 #endif 137 clear_bit(m->mpc_busid, mp_bus_not_pci); 138 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; 139 mp_current_pci_id++; 140 #if defined(CONFIG_EISA) || defined (CONFIG_MCA) 141 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI; 142 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) { 143 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA; 144 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA) - 1) == 0) { 145 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA; 146 #endif 147 } else 148 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str); 149 } 150 151 #ifdef CONFIG_X86_IO_APIC 152 153 static int bad_ioapic(unsigned long address) 154 { 155 if (nr_ioapics >= MAX_IO_APICS) { 156 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " 157 "(found %d)\n", MAX_IO_APICS, nr_ioapics); 158 panic("Recompile kernel with bigger MAX_IO_APICS!\n"); 159 } 160 if (!address) { 161 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" 162 " found in table, skipping!\n"); 163 return 1; 164 } 165 return 0; 166 } 167 168 static void __init MP_ioapic_info(struct mpc_config_ioapic *m) 169 { 170 if (!(m->mpc_flags & MPC_APIC_USABLE)) 171 return; 172 173 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n", 174 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr); 175 176 if (bad_ioapic(m->mpc_apicaddr)) 177 return; 178 179 mp_ioapics[nr_ioapics] = *m; 180 nr_ioapics++; 181 } 182 183 static void __init MP_intsrc_info(struct mpc_config_intsrc *m) 184 { 185 mp_irqs[mp_irq_entries] = *m; 186 Dprintk("Int: type %d, pol %d, trig %d, bus %d," 187 " IRQ %02x, APIC ID %x, APIC INT %02x\n", 188 m->mpc_irqtype, m->mpc_irqflag & 3, 189 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, 190 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); 191 if (++mp_irq_entries == MAX_IRQ_SOURCES) 192 panic("Max # of irq sources exceeded!!\n"); 193 } 194 195 #endif 196 197 static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m) 198 { 199 Dprintk("Lint: type %d, pol %d, trig %d, bus %d," 200 " IRQ %02x, APIC ID %x, APIC LINT %02x\n", 201 m->mpc_irqtype, m->mpc_irqflag & 3, 202 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid, 203 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); 204 } 205 206 #ifdef CONFIG_X86_NUMAQ 207 static void __init MP_translation_info(struct mpc_config_translation *m) 208 { 209 printk(KERN_INFO 210 "Translation: record %d, type %d, quad %d, global %d, local %d\n", 211 mpc_record, m->trans_type, m->trans_quad, m->trans_global, 212 m->trans_local); 213 214 if (mpc_record >= MAX_MPC_ENTRY) 215 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n"); 216 else 217 translation_table[mpc_record] = m; /* stash this for later */ 218 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad)) 219 node_set_online(m->trans_quad); 220 } 221 222 /* 223 * Read/parse the MPC oem tables 224 */ 225 226 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, 227 unsigned short oemsize) 228 { 229 int count = sizeof(*oemtable); /* the header size */ 230 unsigned char *oemptr = ((unsigned char *)oemtable) + count; 231 232 mpc_record = 0; 233 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", 234 oemtable); 235 if (memcmp(oemtable->oem_signature, MPC_OEM_SIGNATURE, 4)) { 236 printk(KERN_WARNING 237 "SMP mpc oemtable: bad signature [%c%c%c%c]!\n", 238 oemtable->oem_signature[0], oemtable->oem_signature[1], 239 oemtable->oem_signature[2], oemtable->oem_signature[3]); 240 return; 241 } 242 if (mpf_checksum((unsigned char *)oemtable, oemtable->oem_length)) { 243 printk(KERN_WARNING "SMP oem mptable: checksum error!\n"); 244 return; 245 } 246 while (count < oemtable->oem_length) { 247 switch (*oemptr) { 248 case MP_TRANSLATION: 249 { 250 struct mpc_config_translation *m = 251 (struct mpc_config_translation *)oemptr; 252 MP_translation_info(m); 253 oemptr += sizeof(*m); 254 count += sizeof(*m); 255 ++mpc_record; 256 break; 257 } 258 default: 259 { 260 printk(KERN_WARNING 261 "Unrecognised OEM table entry type! - %d\n", 262 (int)*oemptr); 263 return; 264 } 265 } 266 } 267 } 268 269 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem, 270 char *productid) 271 { 272 if (strncmp(oem, "IBM NUMA", 8)) 273 printk("Warning! May not be a NUMA-Q system!\n"); 274 if (mpc->mpc_oemptr) 275 smp_read_mpc_oem((struct mp_config_oemtable *)mpc->mpc_oemptr, 276 mpc->mpc_oemsize); 277 } 278 #endif /* CONFIG_X86_NUMAQ */ 279 280 /* 281 * Read/parse the MPC 282 */ 283 284 static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early) 285 { 286 char str[16]; 287 char oem[10]; 288 int count = sizeof(*mpc); 289 unsigned char *mpt = ((unsigned char *)mpc) + count; 290 291 if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) { 292 printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n", 293 mpc->mpc_signature[0], mpc->mpc_signature[1], 294 mpc->mpc_signature[2], mpc->mpc_signature[3]); 295 return 0; 296 } 297 if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) { 298 printk(KERN_ERR "MPTABLE: checksum error!\n"); 299 return 0; 300 } 301 if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) { 302 printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n", 303 mpc->mpc_spec); 304 return 0; 305 } 306 if (!mpc->mpc_lapic) { 307 printk(KERN_ERR "MPTABLE: null local APIC address!\n"); 308 return 0; 309 } 310 memcpy(oem, mpc->mpc_oem, 8); 311 oem[8] = 0; 312 printk(KERN_INFO "MPTABLE: OEM ID: %s ", oem); 313 314 memcpy(str, mpc->mpc_productid, 12); 315 str[12] = 0; 316 printk("Product ID: %s ", str); 317 318 #ifdef CONFIG_X86_32 319 mps_oem_check(mpc, oem, str); 320 #endif 321 printk(KERN_INFO "MPTABLE: Product ID: %s ", str); 322 323 printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->mpc_lapic); 324 325 /* save the local APIC address, it might be non-default */ 326 if (!acpi_lapic) 327 mp_lapic_addr = mpc->mpc_lapic; 328 329 if (early) 330 return 1; 331 332 /* 333 * Now process the configuration blocks. 334 */ 335 #ifdef CONFIG_X86_NUMAQ 336 mpc_record = 0; 337 #endif 338 while (count < mpc->mpc_length) { 339 switch (*mpt) { 340 case MP_PROCESSOR: 341 { 342 struct mpc_config_processor *m = 343 (struct mpc_config_processor *)mpt; 344 /* ACPI may have already provided this data */ 345 if (!acpi_lapic) 346 MP_processor_info(m); 347 mpt += sizeof(*m); 348 count += sizeof(*m); 349 break; 350 } 351 case MP_BUS: 352 { 353 struct mpc_config_bus *m = 354 (struct mpc_config_bus *)mpt; 355 MP_bus_info(m); 356 mpt += sizeof(*m); 357 count += sizeof(*m); 358 break; 359 } 360 case MP_IOAPIC: 361 { 362 #ifdef CONFIG_X86_IO_APIC 363 struct mpc_config_ioapic *m = 364 (struct mpc_config_ioapic *)mpt; 365 MP_ioapic_info(m); 366 #endif 367 mpt += sizeof(struct mpc_config_ioapic); 368 count += sizeof(struct mpc_config_ioapic); 369 break; 370 } 371 case MP_INTSRC: 372 { 373 #ifdef CONFIG_X86_IO_APIC 374 struct mpc_config_intsrc *m = 375 (struct mpc_config_intsrc *)mpt; 376 377 MP_intsrc_info(m); 378 #endif 379 mpt += sizeof(struct mpc_config_intsrc); 380 count += sizeof(struct mpc_config_intsrc); 381 break; 382 } 383 case MP_LINTSRC: 384 { 385 struct mpc_config_lintsrc *m = 386 (struct mpc_config_lintsrc *)mpt; 387 MP_lintsrc_info(m); 388 mpt += sizeof(*m); 389 count += sizeof(*m); 390 break; 391 } 392 default: 393 /* wrong mptable */ 394 printk(KERN_ERR "Your mptable is wrong, contact your HW vendor!\n"); 395 printk(KERN_ERR "type %x\n", *mpt); 396 print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16, 397 1, mpc, mpc->mpc_length, 1); 398 count = mpc->mpc_length; 399 break; 400 } 401 #ifdef CONFIG_X86_NUMAQ 402 ++mpc_record; 403 #endif 404 } 405 setup_apic_routing(); 406 if (!num_processors) 407 printk(KERN_ERR "MPTABLE: no processors registered!\n"); 408 return num_processors; 409 } 410 411 #ifdef CONFIG_X86_IO_APIC 412 413 static int __init ELCR_trigger(unsigned int irq) 414 { 415 unsigned int port; 416 417 port = 0x4d0 + (irq >> 3); 418 return (inb(port) >> (irq & 7)) & 1; 419 } 420 421 static void __init construct_default_ioirq_mptable(int mpc_default_type) 422 { 423 struct mpc_config_intsrc intsrc; 424 int i; 425 int ELCR_fallback = 0; 426 427 intsrc.mpc_type = MP_INTSRC; 428 intsrc.mpc_irqflag = 0; /* conforming */ 429 intsrc.mpc_srcbus = 0; 430 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; 431 432 intsrc.mpc_irqtype = mp_INT; 433 434 /* 435 * If true, we have an ISA/PCI system with no IRQ entries 436 * in the MP table. To prevent the PCI interrupts from being set up 437 * incorrectly, we try to use the ELCR. The sanity check to see if 438 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can 439 * never be level sensitive, so we simply see if the ELCR agrees. 440 * If it does, we assume it's valid. 441 */ 442 if (mpc_default_type == 5) { 443 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... " 444 "falling back to ELCR\n"); 445 446 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || 447 ELCR_trigger(13)) 448 printk(KERN_ERR "ELCR contains invalid data... " 449 "not using ELCR\n"); 450 else { 451 printk(KERN_INFO 452 "Using ELCR to identify PCI interrupts\n"); 453 ELCR_fallback = 1; 454 } 455 } 456 457 for (i = 0; i < 16; i++) { 458 switch (mpc_default_type) { 459 case 2: 460 if (i == 0 || i == 13) 461 continue; /* IRQ0 & IRQ13 not connected */ 462 /* fall through */ 463 default: 464 if (i == 2) 465 continue; /* IRQ2 is never connected */ 466 } 467 468 if (ELCR_fallback) { 469 /* 470 * If the ELCR indicates a level-sensitive interrupt, we 471 * copy that information over to the MP table in the 472 * irqflag field (level sensitive, active high polarity). 473 */ 474 if (ELCR_trigger(i)) 475 intsrc.mpc_irqflag = 13; 476 else 477 intsrc.mpc_irqflag = 0; 478 } 479 480 intsrc.mpc_srcbusirq = i; 481 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ 482 MP_intsrc_info(&intsrc); 483 } 484 485 intsrc.mpc_irqtype = mp_ExtINT; 486 intsrc.mpc_srcbusirq = 0; 487 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ 488 MP_intsrc_info(&intsrc); 489 } 490 491 #endif 492 493 static inline void __init construct_default_ISA_mptable(int mpc_default_type) 494 { 495 struct mpc_config_processor processor; 496 struct mpc_config_bus bus; 497 #ifdef CONFIG_X86_IO_APIC 498 struct mpc_config_ioapic ioapic; 499 #endif 500 struct mpc_config_lintsrc lintsrc; 501 int linttypes[2] = { mp_ExtINT, mp_NMI }; 502 int i; 503 504 /* 505 * local APIC has default address 506 */ 507 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 508 509 /* 510 * 2 CPUs, numbered 0 & 1. 511 */ 512 processor.mpc_type = MP_PROCESSOR; 513 /* Either an integrated APIC or a discrete 82489DX. */ 514 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; 515 processor.mpc_cpuflag = CPU_ENABLED; 516 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | 517 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask; 518 processor.mpc_featureflag = boot_cpu_data.x86_capability[0]; 519 processor.mpc_reserved[0] = 0; 520 processor.mpc_reserved[1] = 0; 521 for (i = 0; i < 2; i++) { 522 processor.mpc_apicid = i; 523 MP_processor_info(&processor); 524 } 525 526 bus.mpc_type = MP_BUS; 527 bus.mpc_busid = 0; 528 switch (mpc_default_type) { 529 default: 530 printk(KERN_ERR "???\nUnknown standard configuration %d\n", 531 mpc_default_type); 532 /* fall through */ 533 case 1: 534 case 5: 535 memcpy(bus.mpc_bustype, "ISA ", 6); 536 break; 537 case 2: 538 case 6: 539 case 3: 540 memcpy(bus.mpc_bustype, "EISA ", 6); 541 break; 542 case 4: 543 case 7: 544 memcpy(bus.mpc_bustype, "MCA ", 6); 545 } 546 MP_bus_info(&bus); 547 if (mpc_default_type > 4) { 548 bus.mpc_busid = 1; 549 memcpy(bus.mpc_bustype, "PCI ", 6); 550 MP_bus_info(&bus); 551 } 552 553 #ifdef CONFIG_X86_IO_APIC 554 ioapic.mpc_type = MP_IOAPIC; 555 ioapic.mpc_apicid = 2; 556 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; 557 ioapic.mpc_flags = MPC_APIC_USABLE; 558 ioapic.mpc_apicaddr = 0xFEC00000; 559 MP_ioapic_info(&ioapic); 560 561 /* 562 * We set up most of the low 16 IO-APIC pins according to MPS rules. 563 */ 564 construct_default_ioirq_mptable(mpc_default_type); 565 #endif 566 lintsrc.mpc_type = MP_LINTSRC; 567 lintsrc.mpc_irqflag = 0; /* conforming */ 568 lintsrc.mpc_srcbusid = 0; 569 lintsrc.mpc_srcbusirq = 0; 570 lintsrc.mpc_destapic = MP_APIC_ALL; 571 for (i = 0; i < 2; i++) { 572 lintsrc.mpc_irqtype = linttypes[i]; 573 lintsrc.mpc_destapiclint = i; 574 MP_lintsrc_info(&lintsrc); 575 } 576 } 577 578 static struct intel_mp_floating *mpf_found; 579 580 /* 581 * Scan the memory blocks for an SMP configuration block. 582 */ 583 static void __init __get_smp_config(unsigned early) 584 { 585 struct intel_mp_floating *mpf = mpf_found; 586 587 if (acpi_lapic && early) 588 return; 589 /* 590 * ACPI supports both logical (e.g. Hyper-Threading) and physical 591 * processors, where MPS only supports physical. 592 */ 593 if (acpi_lapic && acpi_ioapic) { 594 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration " 595 "information\n"); 596 return; 597 } else if (acpi_lapic) 598 printk(KERN_INFO "Using ACPI for processor (LAPIC) " 599 "configuration information\n"); 600 601 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", 602 mpf->mpf_specification); 603 #ifdef CONFIG_X86_32 604 if (mpf->mpf_feature2 & (1 << 7)) { 605 printk(KERN_INFO " IMCR and PIC compatibility mode.\n"); 606 pic_mode = 1; 607 } else { 608 printk(KERN_INFO " Virtual Wire compatibility mode.\n"); 609 pic_mode = 0; 610 } 611 #endif 612 /* 613 * Now see if we need to read further. 614 */ 615 if (mpf->mpf_feature1 != 0) { 616 if (early) { 617 /* 618 * local APIC has default address 619 */ 620 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 621 return; 622 } 623 624 printk(KERN_INFO "Default MP configuration #%d\n", 625 mpf->mpf_feature1); 626 construct_default_ISA_mptable(mpf->mpf_feature1); 627 628 } else if (mpf->mpf_physptr) { 629 630 /* 631 * Read the physical hardware table. Anything here will 632 * override the defaults. 633 */ 634 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) { 635 smp_found_config = 0; 636 printk(KERN_ERR 637 "BIOS bug, MP table errors detected!...\n"); 638 printk(KERN_ERR "... disabling SMP support. " 639 "(tell your hw vendor)\n"); 640 return; 641 } 642 643 if (early) 644 return; 645 #ifdef CONFIG_X86_IO_APIC 646 /* 647 * If there are no explicit MP IRQ entries, then we are 648 * broken. We set up most of the low 16 IO-APIC pins to 649 * ISA defaults and hope it will work. 650 */ 651 if (!mp_irq_entries) { 652 struct mpc_config_bus bus; 653 654 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, " 655 "using default mptable. " 656 "(tell your hw vendor)\n"); 657 658 bus.mpc_type = MP_BUS; 659 bus.mpc_busid = 0; 660 memcpy(bus.mpc_bustype, "ISA ", 6); 661 MP_bus_info(&bus); 662 663 construct_default_ioirq_mptable(0); 664 } 665 #endif 666 } else 667 BUG(); 668 669 if (!early) 670 printk(KERN_INFO "Processors: %d\n", num_processors); 671 /* 672 * Only use the first configuration found. 673 */ 674 } 675 676 void __init early_get_smp_config(void) 677 { 678 __get_smp_config(1); 679 } 680 681 void __init get_smp_config(void) 682 { 683 __get_smp_config(0); 684 } 685 686 static int __init smp_scan_config(unsigned long base, unsigned long length, 687 unsigned reserve) 688 { 689 unsigned int *bp = phys_to_virt(base); 690 struct intel_mp_floating *mpf; 691 692 Dprintk("Scan SMP from %p for %ld bytes.\n", bp, length); 693 BUILD_BUG_ON(sizeof(*mpf) != 16); 694 695 while (length > 0) { 696 mpf = (struct intel_mp_floating *)bp; 697 if ((*bp == SMP_MAGIC_IDENT) && 698 (mpf->mpf_length == 1) && 699 !mpf_checksum((unsigned char *)bp, 16) && 700 ((mpf->mpf_specification == 1) 701 || (mpf->mpf_specification == 4))) { 702 703 smp_found_config = 1; 704 mpf_found = mpf; 705 #ifdef CONFIG_X86_32 706 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n", 707 mpf, virt_to_phys(mpf)); 708 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE, 709 BOOTMEM_DEFAULT); 710 if (mpf->mpf_physptr) { 711 /* 712 * We cannot access to MPC table to compute 713 * table size yet, as only few megabytes from 714 * the bottom is mapped now. 715 * PC-9800's MPC table places on the very last 716 * of physical memory; so that simply reserving 717 * PAGE_SIZE from mpg->mpf_physptr yields BUG() 718 * in reserve_bootmem. 719 */ 720 unsigned long size = PAGE_SIZE; 721 unsigned long end = max_low_pfn * PAGE_SIZE; 722 if (mpf->mpf_physptr + size > end) 723 size = end - mpf->mpf_physptr; 724 reserve_bootmem(mpf->mpf_physptr, size, 725 BOOTMEM_DEFAULT); 726 } 727 728 #else 729 if (!reserve) 730 return 1; 731 732 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE); 733 if (mpf->mpf_physptr) 734 reserve_bootmem_generic(mpf->mpf_physptr, 735 PAGE_SIZE); 736 #endif 737 return 1; 738 } 739 bp += 4; 740 length -= 16; 741 } 742 return 0; 743 } 744 745 static void __init __find_smp_config(unsigned reserve) 746 { 747 unsigned int address; 748 749 /* 750 * FIXME: Linux assumes you have 640K of base ram.. 751 * this continues the error... 752 * 753 * 1) Scan the bottom 1K for a signature 754 * 2) Scan the top 1K of base RAM 755 * 3) Scan the 64K of bios 756 */ 757 if (smp_scan_config(0x0, 0x400, reserve) || 758 smp_scan_config(639 * 0x400, 0x400, reserve) || 759 smp_scan_config(0xF0000, 0x10000, reserve)) 760 return; 761 /* 762 * If it is an SMP machine we should know now, unless the 763 * configuration is in an EISA/MCA bus machine with an 764 * extended bios data area. 765 * 766 * there is a real-mode segmented pointer pointing to the 767 * 4K EBDA area at 0x40E, calculate and scan it here. 768 * 769 * NOTE! There are Linux loaders that will corrupt the EBDA 770 * area, and as such this kind of SMP config may be less 771 * trustworthy, simply because the SMP table may have been 772 * stomped on during early boot. These loaders are buggy and 773 * should be fixed. 774 * 775 * MP1.4 SPEC states to only scan first 1K of 4K EBDA. 776 */ 777 778 address = get_bios_ebda(); 779 if (address) 780 smp_scan_config(address, 0x400, reserve); 781 } 782 783 void __init early_find_smp_config(void) 784 { 785 __find_smp_config(0); 786 } 787 788 void __init find_smp_config(void) 789 { 790 __find_smp_config(1); 791 } 792 793 /* -------------------------------------------------------------------------- 794 ACPI-based MP Configuration 795 -------------------------------------------------------------------------- */ 796 797 /* 798 * Keep this outside and initialized to 0, for !CONFIG_ACPI builds: 799 */ 800 int es7000_plat; 801 802 #ifdef CONFIG_ACPI 803 804 #ifdef CONFIG_X86_IO_APIC 805 806 #define MP_ISA_BUS 0 807 808 extern struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS]; 809 810 static int mp_find_ioapic(int gsi) 811 { 812 int i = 0; 813 814 /* Find the IOAPIC that manages this GSI. */ 815 for (i = 0; i < nr_ioapics; i++) { 816 if ((gsi >= mp_ioapic_routing[i].gsi_base) 817 && (gsi <= mp_ioapic_routing[i].gsi_end)) 818 return i; 819 } 820 821 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); 822 return -1; 823 } 824 825 static u8 __init uniq_ioapic_id(u8 id) 826 { 827 #ifdef CONFIG_X86_32 828 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 829 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) 830 return io_apic_get_unique_id(nr_ioapics, id); 831 else 832 return id; 833 #else 834 int i; 835 DECLARE_BITMAP(used, 256); 836 bitmap_zero(used, 256); 837 for (i = 0; i < nr_ioapics; i++) { 838 struct mpc_config_ioapic *ia = &mp_ioapics[i]; 839 __set_bit(ia->mpc_apicid, used); 840 } 841 if (!test_bit(id, used)) 842 return id; 843 return find_first_zero_bit(used, 256); 844 #endif 845 } 846 847 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) 848 { 849 int idx = 0; 850 851 if (bad_ioapic(address)) 852 return; 853 854 idx = nr_ioapics; 855 856 mp_ioapics[idx].mpc_type = MP_IOAPIC; 857 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; 858 mp_ioapics[idx].mpc_apicaddr = address; 859 860 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); 861 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id); 862 #ifdef CONFIG_X86_32 863 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx); 864 #else 865 mp_ioapics[idx].mpc_apicver = 0; 866 #endif 867 /* 868 * Build basic GSI lookup table to facilitate gsi->io_apic lookups 869 * and to prevent reprogramming of IOAPIC pins (PCI GSIs). 870 */ 871 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; 872 mp_ioapic_routing[idx].gsi_base = gsi_base; 873 mp_ioapic_routing[idx].gsi_end = gsi_base + 874 io_apic_get_redir_entries(idx); 875 876 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " 877 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, 878 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr, 879 mp_ioapic_routing[idx].gsi_base, mp_ioapic_routing[idx].gsi_end); 880 881 nr_ioapics++; 882 } 883 884 void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) 885 { 886 struct mpc_config_intsrc intsrc; 887 int ioapic = -1; 888 int pin = -1; 889 890 /* 891 * Convert 'gsi' to 'ioapic.pin'. 892 */ 893 ioapic = mp_find_ioapic(gsi); 894 if (ioapic < 0) 895 return; 896 pin = gsi - mp_ioapic_routing[ioapic].gsi_base; 897 898 /* 899 * TBD: This check is for faulty timer entries, where the override 900 * erroneously sets the trigger to level, resulting in a HUGE 901 * increase of timer interrupts! 902 */ 903 if ((bus_irq == 0) && (trigger == 3)) 904 trigger = 1; 905 906 intsrc.mpc_type = MP_INTSRC; 907 intsrc.mpc_irqtype = mp_INT; 908 intsrc.mpc_irqflag = (trigger << 2) | polarity; 909 intsrc.mpc_srcbus = MP_ISA_BUS; 910 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ 911 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ 912 intsrc.mpc_dstirq = pin; /* INTIN# */ 913 914 MP_intsrc_info(&intsrc); 915 } 916 917 void __init mp_config_acpi_legacy_irqs(void) 918 { 919 struct mpc_config_intsrc intsrc; 920 int i = 0; 921 int ioapic = -1; 922 923 #if defined (CONFIG_MCA) || defined (CONFIG_EISA) 924 /* 925 * Fabricate the legacy ISA bus (bus #31). 926 */ 927 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA; 928 #endif 929 set_bit(MP_ISA_BUS, mp_bus_not_pci); 930 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS); 931 932 /* 933 * Older generations of ES7000 have no legacy identity mappings 934 */ 935 if (es7000_plat == 1) 936 return; 937 938 /* 939 * Locate the IOAPIC that manages the ISA IRQs (0-15). 940 */ 941 ioapic = mp_find_ioapic(0); 942 if (ioapic < 0) 943 return; 944 945 intsrc.mpc_type = MP_INTSRC; 946 intsrc.mpc_irqflag = 0; /* Conforming */ 947 intsrc.mpc_srcbus = MP_ISA_BUS; 948 #ifdef CONFIG_X86_IO_APIC 949 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; 950 #endif 951 /* 952 * Use the default configuration for the IRQs 0-15. Unless 953 * overridden by (MADT) interrupt source override entries. 954 */ 955 for (i = 0; i < 16; i++) { 956 int idx; 957 958 for (idx = 0; idx < mp_irq_entries; idx++) { 959 struct mpc_config_intsrc *irq = mp_irqs + idx; 960 961 /* Do we already have a mapping for this ISA IRQ? */ 962 if (irq->mpc_srcbus == MP_ISA_BUS 963 && irq->mpc_srcbusirq == i) 964 break; 965 966 /* Do we already have a mapping for this IOAPIC pin */ 967 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && 968 (irq->mpc_dstirq == i)) 969 break; 970 } 971 972 if (idx != mp_irq_entries) { 973 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); 974 continue; /* IRQ already used */ 975 } 976 977 intsrc.mpc_irqtype = mp_INT; 978 intsrc.mpc_srcbusirq = i; /* Identity mapped */ 979 intsrc.mpc_dstirq = i; 980 981 MP_intsrc_info(&intsrc); 982 } 983 } 984 985 int mp_register_gsi(u32 gsi, int triggering, int polarity) 986 { 987 int ioapic; 988 int ioapic_pin; 989 #ifdef CONFIG_X86_32 990 #define MAX_GSI_NUM 4096 991 #define IRQ_COMPRESSION_START 64 992 993 static int pci_irq = IRQ_COMPRESSION_START; 994 /* 995 * Mapping between Global System Interrupts, which 996 * represent all possible interrupts, and IRQs 997 * assigned to actual devices. 998 */ 999 static int gsi_to_irq[MAX_GSI_NUM]; 1000 #else 1001 1002 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC) 1003 return gsi; 1004 #endif 1005 1006 /* Don't set up the ACPI SCI because it's already set up */ 1007 if (acpi_gbl_FADT.sci_interrupt == gsi) 1008 return gsi; 1009 1010 ioapic = mp_find_ioapic(gsi); 1011 if (ioapic < 0) { 1012 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); 1013 return gsi; 1014 } 1015 1016 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base; 1017 1018 #ifdef CONFIG_X86_32 1019 if (ioapic_renumber_irq) 1020 gsi = ioapic_renumber_irq(ioapic, gsi); 1021 #endif 1022 1023 /* 1024 * Avoid pin reprogramming. PRTs typically include entries 1025 * with redundant pin->gsi mappings (but unique PCI devices); 1026 * we only program the IOAPIC on the first. 1027 */ 1028 if (ioapic_pin > MP_MAX_IOAPIC_PIN) { 1029 printk(KERN_ERR "Invalid reference to IOAPIC pin " 1030 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, 1031 ioapic_pin); 1032 return gsi; 1033 } 1034 if (test_bit(ioapic_pin, mp_ioapic_routing[ioapic].pin_programmed)) { 1035 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", 1036 mp_ioapic_routing[ioapic].apic_id, ioapic_pin); 1037 #ifdef CONFIG_X86_32 1038 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]); 1039 #else 1040 return gsi; 1041 #endif 1042 } 1043 1044 set_bit(ioapic_pin, mp_ioapic_routing[ioapic].pin_programmed); 1045 #ifdef CONFIG_X86_32 1046 /* 1047 * For GSI >= 64, use IRQ compression 1048 */ 1049 if ((gsi >= IRQ_COMPRESSION_START) 1050 && (triggering == ACPI_LEVEL_SENSITIVE)) { 1051 /* 1052 * For PCI devices assign IRQs in order, avoiding gaps 1053 * due to unused I/O APIC pins. 1054 */ 1055 int irq = gsi; 1056 if (gsi < MAX_GSI_NUM) { 1057 /* 1058 * Retain the VIA chipset work-around (gsi > 15), but 1059 * avoid a problem where the 8254 timer (IRQ0) is setup 1060 * via an override (so it's not on pin 0 of the ioapic), 1061 * and at the same time, the pin 0 interrupt is a PCI 1062 * type. The gsi > 15 test could cause these two pins 1063 * to be shared as IRQ0, and they are not shareable. 1064 * So test for this condition, and if necessary, avoid 1065 * the pin collision. 1066 */ 1067 gsi = pci_irq++; 1068 /* 1069 * Don't assign IRQ used by ACPI SCI 1070 */ 1071 if (gsi == acpi_gbl_FADT.sci_interrupt) 1072 gsi = pci_irq++; 1073 gsi_to_irq[irq] = gsi; 1074 } else { 1075 printk(KERN_ERR "GSI %u is too high\n", gsi); 1076 return gsi; 1077 } 1078 } 1079 #endif 1080 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, 1081 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, 1082 polarity == ACPI_ACTIVE_HIGH ? 0 : 1); 1083 return gsi; 1084 } 1085 1086 #endif /* CONFIG_X86_IO_APIC */ 1087 #endif /* CONFIG_ACPI */ 1088