xref: /openbmc/linux/arch/x86/kernel/irqinit.c (revision 6774def6)
1 #include <linux/linkage.h>
2 #include <linux/errno.h>
3 #include <linux/signal.h>
4 #include <linux/sched.h>
5 #include <linux/ioport.h>
6 #include <linux/interrupt.h>
7 #include <linux/timex.h>
8 #include <linux/random.h>
9 #include <linux/kprobes.h>
10 #include <linux/init.h>
11 #include <linux/kernel_stat.h>
12 #include <linux/device.h>
13 #include <linux/bitops.h>
14 #include <linux/acpi.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 
18 #include <linux/atomic.h>
19 #include <asm/timer.h>
20 #include <asm/hw_irq.h>
21 #include <asm/pgtable.h>
22 #include <asm/desc.h>
23 #include <asm/apic.h>
24 #include <asm/setup.h>
25 #include <asm/i8259.h>
26 #include <asm/traps.h>
27 #include <asm/prom.h>
28 
29 /*
30  * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
31  * (these are usually mapped to vectors 0x30-0x3f)
32  */
33 
34 /*
35  * The IO-APIC gives us many more interrupt sources. Most of these
36  * are unused but an SMP system is supposed to have enough memory ...
37  * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
38  * across the spectrum, so we really want to be prepared to get all
39  * of these. Plus, more powerful systems might have more than 64
40  * IO-APIC registers.
41  *
42  * (these are usually mapped into the 0x30-0xff vector range)
43  */
44 
45 /*
46  * IRQ2 is cascade interrupt to second interrupt controller
47  */
48 static struct irqaction irq2 = {
49 	.handler = no_action,
50 	.name = "cascade",
51 	.flags = IRQF_NO_THREAD,
52 };
53 
54 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
55 	[0 ... NR_VECTORS - 1] = VECTOR_UNDEFINED,
56 };
57 
58 int vector_used_by_percpu_irq(unsigned int vector)
59 {
60 	int cpu;
61 
62 	for_each_online_cpu(cpu) {
63 		if (per_cpu(vector_irq, cpu)[vector] > VECTOR_UNDEFINED)
64 			return 1;
65 	}
66 
67 	return 0;
68 }
69 
70 void __init init_ISA_irqs(void)
71 {
72 	struct irq_chip *chip = legacy_pic->chip;
73 	int i;
74 
75 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
76 	init_bsp_APIC();
77 #endif
78 	legacy_pic->init(0);
79 
80 	for (i = 0; i < nr_legacy_irqs(); i++)
81 		irq_set_chip_and_handler(i, chip, handle_level_irq);
82 }
83 
84 void __init init_IRQ(void)
85 {
86 	int i;
87 
88 	/*
89 	 * On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15.
90 	 * If these IRQ's are handled by legacy interrupt-controllers like PIC,
91 	 * then this configuration will likely be static after the boot. If
92 	 * these IRQ's are handled by more mordern controllers like IO-APIC,
93 	 * then this vector space can be freed and re-used dynamically as the
94 	 * irq's migrate etc.
95 	 */
96 	for (i = 0; i < nr_legacy_irqs(); i++)
97 		per_cpu(vector_irq, 0)[IRQ0_VECTOR + i] = i;
98 
99 	x86_init.irqs.intr_init();
100 }
101 
102 /*
103  * Setup the vector to irq mappings.
104  */
105 void setup_vector_irq(int cpu)
106 {
107 #ifndef CONFIG_X86_IO_APIC
108 	int irq;
109 
110 	/*
111 	 * On most of the platforms, legacy PIC delivers the interrupts on the
112 	 * boot cpu. But there are certain platforms where PIC interrupts are
113 	 * delivered to multiple cpu's. If the legacy IRQ is handled by the
114 	 * legacy PIC, for the new cpu that is coming online, setup the static
115 	 * legacy vector to irq mapping:
116 	 */
117 	for (irq = 0; irq < nr_legacy_irqs(); irq++)
118 		per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq;
119 #endif
120 
121 	__setup_vector_irq(cpu);
122 }
123 
124 static void __init smp_intr_init(void)
125 {
126 #ifdef CONFIG_SMP
127 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
128 	/*
129 	 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
130 	 * IPI, driven by wakeup.
131 	 */
132 	alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
133 
134 	/* IPI for generic function call */
135 	alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
136 
137 	/* IPI for generic single function call */
138 	alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
139 			call_function_single_interrupt);
140 
141 	/* Low priority IPI to cleanup after moving an irq */
142 	set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
143 	set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);
144 
145 	/* IPI used for rebooting/stopping */
146 	alloc_intr_gate(REBOOT_VECTOR, reboot_interrupt);
147 #endif
148 #endif /* CONFIG_SMP */
149 }
150 
151 static void __init apic_intr_init(void)
152 {
153 	smp_intr_init();
154 
155 #ifdef CONFIG_X86_THERMAL_VECTOR
156 	alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
157 #endif
158 #ifdef CONFIG_X86_MCE_THRESHOLD
159 	alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
160 #endif
161 
162 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
163 	/* self generated IPI for local APIC timer */
164 	alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
165 
166 	/* IPI for X86 platform specific use */
167 	alloc_intr_gate(X86_PLATFORM_IPI_VECTOR, x86_platform_ipi);
168 #ifdef CONFIG_HAVE_KVM
169 	/* IPI for KVM to deliver posted interrupt */
170 	alloc_intr_gate(POSTED_INTR_VECTOR, kvm_posted_intr_ipi);
171 #endif
172 
173 	/* IPI vectors for APIC spurious and error interrupts */
174 	alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
175 	alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
176 
177 	/* IRQ work interrupts: */
178 # ifdef CONFIG_IRQ_WORK
179 	alloc_intr_gate(IRQ_WORK_VECTOR, irq_work_interrupt);
180 # endif
181 
182 #endif
183 }
184 
185 void __init native_init_IRQ(void)
186 {
187 	int i;
188 
189 	/* Execute any quirks before the call gates are initialised: */
190 	x86_init.irqs.pre_vector_init();
191 
192 	apic_intr_init();
193 
194 	/*
195 	 * Cover the whole vector space, no vector can escape
196 	 * us. (some of these will be overridden and become
197 	 * 'special' SMP interrupts)
198 	 */
199 	i = FIRST_EXTERNAL_VECTOR;
200 	for_each_clear_bit_from(i, used_vectors, NR_VECTORS) {
201 		/* IA32_SYSCALL_VECTOR could be used in trap_init already. */
202 		set_intr_gate(i, interrupt[i - FIRST_EXTERNAL_VECTOR]);
203 	}
204 
205 	if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs())
206 		setup_irq(2, &irq2);
207 
208 #ifdef CONFIG_X86_32
209 	irq_ctx_init(smp_processor_id());
210 #endif
211 }
212