1 #include <linux/linkage.h> 2 #include <linux/errno.h> 3 #include <linux/signal.h> 4 #include <linux/sched.h> 5 #include <linux/ioport.h> 6 #include <linux/interrupt.h> 7 #include <linux/timex.h> 8 #include <linux/random.h> 9 #include <linux/kprobes.h> 10 #include <linux/init.h> 11 #include <linux/kernel_stat.h> 12 #include <linux/device.h> 13 #include <linux/bitops.h> 14 #include <linux/acpi.h> 15 #include <linux/io.h> 16 #include <linux/delay.h> 17 18 #include <linux/atomic.h> 19 #include <asm/timer.h> 20 #include <asm/hw_irq.h> 21 #include <asm/pgtable.h> 22 #include <asm/desc.h> 23 #include <asm/apic.h> 24 #include <asm/setup.h> 25 #include <asm/i8259.h> 26 #include <asm/traps.h> 27 #include <asm/prom.h> 28 29 /* 30 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: 31 * (these are usually mapped to vectors 0x30-0x3f) 32 */ 33 34 /* 35 * The IO-APIC gives us many more interrupt sources. Most of these 36 * are unused but an SMP system is supposed to have enough memory ... 37 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all 38 * across the spectrum, so we really want to be prepared to get all 39 * of these. Plus, more powerful systems might have more than 64 40 * IO-APIC registers. 41 * 42 * (these are usually mapped into the 0x30-0xff vector range) 43 */ 44 45 /* 46 * IRQ2 is cascade interrupt to second interrupt controller 47 */ 48 static struct irqaction irq2 = { 49 .handler = no_action, 50 .name = "cascade", 51 .flags = IRQF_NO_THREAD, 52 }; 53 54 DEFINE_PER_CPU(vector_irq_t, vector_irq) = { 55 [0 ... NR_VECTORS - 1] = VECTOR_UNUSED, 56 }; 57 58 void __init init_ISA_irqs(void) 59 { 60 struct irq_chip *chip = legacy_pic->chip; 61 int i; 62 63 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC) 64 init_bsp_APIC(); 65 #endif 66 legacy_pic->init(0); 67 68 for (i = 0; i < nr_legacy_irqs(); i++) 69 irq_set_chip_and_handler(i, chip, handle_level_irq); 70 } 71 72 void __init init_IRQ(void) 73 { 74 int i; 75 76 /* 77 * On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15. 78 * If these IRQ's are handled by legacy interrupt-controllers like PIC, 79 * then this configuration will likely be static after the boot. If 80 * these IRQ's are handled by more mordern controllers like IO-APIC, 81 * then this vector space can be freed and re-used dynamically as the 82 * irq's migrate etc. 83 */ 84 for (i = 0; i < nr_legacy_irqs(); i++) 85 per_cpu(vector_irq, 0)[ISA_IRQ_VECTOR(i)] = irq_to_desc(i); 86 87 x86_init.irqs.intr_init(); 88 } 89 90 void __init native_init_IRQ(void) 91 { 92 /* Execute any quirks before the call gates are initialised: */ 93 x86_init.irqs.pre_vector_init(); 94 95 idt_setup_apic_and_irq_gates(); 96 97 if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs()) 98 setup_irq(2, &irq2); 99 100 irq_ctx_init(smp_processor_id()); 101 } 102