1 /* 2 * Common interrupt code for 32 and 64 bit 3 */ 4 #include <linux/cpu.h> 5 #include <linux/interrupt.h> 6 #include <linux/kernel_stat.h> 7 #include <linux/of.h> 8 #include <linux/seq_file.h> 9 #include <linux/smp.h> 10 #include <linux/ftrace.h> 11 12 #include <asm/apic.h> 13 #include <asm/io_apic.h> 14 #include <asm/irq.h> 15 #include <asm/idle.h> 16 #include <asm/mce.h> 17 #include <asm/hw_irq.h> 18 19 atomic_t irq_err_count; 20 21 /* Function pointer for generic interrupt vector handling */ 22 void (*x86_platform_ipi_callback)(void) = NULL; 23 24 /* 25 * 'what should we do if we get a hw irq event on an illegal vector'. 26 * each architecture has to answer this themselves. 27 */ 28 void ack_bad_irq(unsigned int irq) 29 { 30 if (printk_ratelimit()) 31 pr_err("unexpected IRQ trap at vector %02x\n", irq); 32 33 /* 34 * Currently unexpected vectors happen only on SMP and APIC. 35 * We _must_ ack these because every local APIC has only N 36 * irq slots per priority level, and a 'hanging, unacked' IRQ 37 * holds up an irq slot - in excessive cases (when multiple 38 * unexpected vectors occur) that might lock up the APIC 39 * completely. 40 * But only ack when the APIC is enabled -AK 41 */ 42 ack_APIC_irq(); 43 } 44 45 #define irq_stats(x) (&per_cpu(irq_stat, x)) 46 /* 47 * /proc/interrupts printing for arch specific interrupts 48 */ 49 int arch_show_interrupts(struct seq_file *p, int prec) 50 { 51 int j; 52 53 seq_printf(p, "%*s: ", prec, "NMI"); 54 for_each_online_cpu(j) 55 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count); 56 seq_printf(p, " Non-maskable interrupts\n"); 57 #ifdef CONFIG_X86_LOCAL_APIC 58 seq_printf(p, "%*s: ", prec, "LOC"); 59 for_each_online_cpu(j) 60 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs); 61 seq_printf(p, " Local timer interrupts\n"); 62 63 seq_printf(p, "%*s: ", prec, "SPU"); 64 for_each_online_cpu(j) 65 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count); 66 seq_printf(p, " Spurious interrupts\n"); 67 seq_printf(p, "%*s: ", prec, "PMI"); 68 for_each_online_cpu(j) 69 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs); 70 seq_printf(p, " Performance monitoring interrupts\n"); 71 seq_printf(p, "%*s: ", prec, "IWI"); 72 for_each_online_cpu(j) 73 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs); 74 seq_printf(p, " IRQ work interrupts\n"); 75 #endif 76 if (x86_platform_ipi_callback) { 77 seq_printf(p, "%*s: ", prec, "PLT"); 78 for_each_online_cpu(j) 79 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis); 80 seq_printf(p, " Platform interrupts\n"); 81 } 82 #ifdef CONFIG_SMP 83 seq_printf(p, "%*s: ", prec, "RES"); 84 for_each_online_cpu(j) 85 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count); 86 seq_printf(p, " Rescheduling interrupts\n"); 87 seq_printf(p, "%*s: ", prec, "CAL"); 88 for_each_online_cpu(j) 89 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count); 90 seq_printf(p, " Function call interrupts\n"); 91 seq_printf(p, "%*s: ", prec, "TLB"); 92 for_each_online_cpu(j) 93 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count); 94 seq_printf(p, " TLB shootdowns\n"); 95 #endif 96 #ifdef CONFIG_X86_THERMAL_VECTOR 97 seq_printf(p, "%*s: ", prec, "TRM"); 98 for_each_online_cpu(j) 99 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count); 100 seq_printf(p, " Thermal event interrupts\n"); 101 #endif 102 #ifdef CONFIG_X86_MCE_THRESHOLD 103 seq_printf(p, "%*s: ", prec, "THR"); 104 for_each_online_cpu(j) 105 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count); 106 seq_printf(p, " Threshold APIC interrupts\n"); 107 #endif 108 #ifdef CONFIG_X86_MCE 109 seq_printf(p, "%*s: ", prec, "MCE"); 110 for_each_online_cpu(j) 111 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j)); 112 seq_printf(p, " Machine check exceptions\n"); 113 seq_printf(p, "%*s: ", prec, "MCP"); 114 for_each_online_cpu(j) 115 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j)); 116 seq_printf(p, " Machine check polls\n"); 117 #endif 118 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count)); 119 #if defined(CONFIG_X86_IO_APIC) 120 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count)); 121 #endif 122 return 0; 123 } 124 125 /* 126 * /proc/stat helpers 127 */ 128 u64 arch_irq_stat_cpu(unsigned int cpu) 129 { 130 u64 sum = irq_stats(cpu)->__nmi_count; 131 132 #ifdef CONFIG_X86_LOCAL_APIC 133 sum += irq_stats(cpu)->apic_timer_irqs; 134 sum += irq_stats(cpu)->irq_spurious_count; 135 sum += irq_stats(cpu)->apic_perf_irqs; 136 sum += irq_stats(cpu)->apic_irq_work_irqs; 137 #endif 138 if (x86_platform_ipi_callback) 139 sum += irq_stats(cpu)->x86_platform_ipis; 140 #ifdef CONFIG_SMP 141 sum += irq_stats(cpu)->irq_resched_count; 142 sum += irq_stats(cpu)->irq_call_count; 143 sum += irq_stats(cpu)->irq_tlb_count; 144 #endif 145 #ifdef CONFIG_X86_THERMAL_VECTOR 146 sum += irq_stats(cpu)->irq_thermal_count; 147 #endif 148 #ifdef CONFIG_X86_MCE_THRESHOLD 149 sum += irq_stats(cpu)->irq_threshold_count; 150 #endif 151 #ifdef CONFIG_X86_MCE 152 sum += per_cpu(mce_exception_count, cpu); 153 sum += per_cpu(mce_poll_count, cpu); 154 #endif 155 return sum; 156 } 157 158 u64 arch_irq_stat(void) 159 { 160 u64 sum = atomic_read(&irq_err_count); 161 162 #ifdef CONFIG_X86_IO_APIC 163 sum += atomic_read(&irq_mis_count); 164 #endif 165 return sum; 166 } 167 168 169 /* 170 * do_IRQ handles all normal device IRQ's (the special 171 * SMP cross-CPU interrupts have their own specific 172 * handlers). 173 */ 174 unsigned int __irq_entry do_IRQ(struct pt_regs *regs) 175 { 176 struct pt_regs *old_regs = set_irq_regs(regs); 177 178 /* high bit used in ret_from_ code */ 179 unsigned vector = ~regs->orig_ax; 180 unsigned irq; 181 182 exit_idle(); 183 irq_enter(); 184 185 irq = __this_cpu_read(vector_irq[vector]); 186 187 if (!handle_irq(irq, regs)) { 188 ack_APIC_irq(); 189 190 if (printk_ratelimit()) 191 pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n", 192 __func__, smp_processor_id(), vector, irq); 193 } 194 195 irq_exit(); 196 197 set_irq_regs(old_regs); 198 return 1; 199 } 200 201 /* 202 * Handler for X86_PLATFORM_IPI_VECTOR. 203 */ 204 void smp_x86_platform_ipi(struct pt_regs *regs) 205 { 206 struct pt_regs *old_regs = set_irq_regs(regs); 207 208 ack_APIC_irq(); 209 210 exit_idle(); 211 212 irq_enter(); 213 214 inc_irq_stat(x86_platform_ipis); 215 216 if (x86_platform_ipi_callback) 217 x86_platform_ipi_callback(); 218 219 irq_exit(); 220 221 set_irq_regs(old_regs); 222 } 223 224 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq); 225 226 #ifdef CONFIG_HOTPLUG_CPU 227 /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */ 228 void fixup_irqs(void) 229 { 230 unsigned int irq, vector; 231 static int warned; 232 struct irq_desc *desc; 233 struct irq_data *data; 234 struct irq_chip *chip; 235 236 for_each_irq_desc(irq, desc) { 237 int break_affinity = 0; 238 int set_affinity = 1; 239 const struct cpumask *affinity; 240 241 if (!desc) 242 continue; 243 if (irq == 2) 244 continue; 245 246 /* interrupt's are disabled at this point */ 247 raw_spin_lock(&desc->lock); 248 249 data = irq_desc_get_irq_data(desc); 250 affinity = data->affinity; 251 if (!irq_has_action(irq) || 252 cpumask_subset(affinity, cpu_online_mask)) { 253 raw_spin_unlock(&desc->lock); 254 continue; 255 } 256 257 /* 258 * Complete the irq move. This cpu is going down and for 259 * non intr-remapping case, we can't wait till this interrupt 260 * arrives at this cpu before completing the irq move. 261 */ 262 irq_force_complete_move(irq); 263 264 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { 265 break_affinity = 1; 266 affinity = cpu_all_mask; 267 } 268 269 chip = irq_data_get_irq_chip(data); 270 if (!irqd_can_move_in_process_context(data) && chip->irq_mask) 271 chip->irq_mask(data); 272 273 if (chip->irq_set_affinity) 274 chip->irq_set_affinity(data, affinity, true); 275 else if (!(warned++)) 276 set_affinity = 0; 277 278 if (!irqd_can_move_in_process_context(data) && chip->irq_unmask) 279 chip->irq_unmask(data); 280 281 raw_spin_unlock(&desc->lock); 282 283 if (break_affinity && set_affinity) 284 printk("Broke affinity for irq %i\n", irq); 285 else if (!set_affinity) 286 printk("Cannot set affinity for irq %i\n", irq); 287 } 288 289 /* 290 * We can remove mdelay() and then send spuriuous interrupts to 291 * new cpu targets for all the irqs that were handled previously by 292 * this cpu. While it works, I have seen spurious interrupt messages 293 * (nothing wrong but still...). 294 * 295 * So for now, retain mdelay(1) and check the IRR and then send those 296 * interrupts to new targets as this cpu is already offlined... 297 */ 298 mdelay(1); 299 300 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { 301 unsigned int irr; 302 303 if (__this_cpu_read(vector_irq[vector]) < 0) 304 continue; 305 306 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 307 if (irr & (1 << (vector % 32))) { 308 irq = __this_cpu_read(vector_irq[vector]); 309 310 desc = irq_to_desc(irq); 311 data = irq_desc_get_irq_data(desc); 312 chip = irq_data_get_irq_chip(data); 313 raw_spin_lock(&desc->lock); 314 if (chip->irq_retrigger) 315 chip->irq_retrigger(data); 316 raw_spin_unlock(&desc->lock); 317 } 318 } 319 } 320 #endif 321