1 /* 2 * Interrupt descriptor table related code 3 * 4 * This file is licensed under the GPL V2 5 */ 6 #include <linux/interrupt.h> 7 8 #include <asm/traps.h> 9 #include <asm/proto.h> 10 #include <asm/desc.h> 11 #include <asm/hw_irq.h> 12 13 struct idt_data { 14 unsigned int vector; 15 unsigned int segment; 16 struct idt_bits bits; 17 const void *addr; 18 }; 19 20 #define DPL0 0x0 21 #define DPL3 0x3 22 23 #define DEFAULT_STACK 0 24 25 #define G(_vector, _addr, _ist, _type, _dpl, _segment) \ 26 { \ 27 .vector = _vector, \ 28 .bits.ist = _ist, \ 29 .bits.type = _type, \ 30 .bits.dpl = _dpl, \ 31 .bits.p = 1, \ 32 .addr = _addr, \ 33 .segment = _segment, \ 34 } 35 36 /* Interrupt gate */ 37 #define INTG(_vector, _addr) \ 38 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS) 39 40 /* System interrupt gate */ 41 #define SYSG(_vector, _addr) \ 42 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS) 43 44 /* 45 * Interrupt gate with interrupt stack. The _ist index is the index in 46 * the tss.ist[] array, but for the descriptor it needs to start at 1. 47 */ 48 #define ISTG(_vector, _addr, _ist) \ 49 G(_vector, _addr, _ist + 1, GATE_INTERRUPT, DPL0, __KERNEL_CS) 50 51 /* Task gate */ 52 #define TSKG(_vector, _gdt) \ 53 G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3) 54 55 /* 56 * Early traps running on the DEFAULT_STACK because the other interrupt 57 * stacks work only after cpu_init(). 58 */ 59 static const __initconst struct idt_data early_idts[] = { 60 INTG(X86_TRAP_DB, debug), 61 SYSG(X86_TRAP_BP, int3), 62 #ifdef CONFIG_X86_32 63 INTG(X86_TRAP_PF, page_fault), 64 #endif 65 }; 66 67 /* 68 * The default IDT entries which are set up in trap_init() before 69 * cpu_init() is invoked. Interrupt stacks cannot be used at that point and 70 * the traps which use them are reinitialized with IST after cpu_init() has 71 * set up TSS. 72 */ 73 static const __initconst struct idt_data def_idts[] = { 74 INTG(X86_TRAP_DE, divide_error), 75 INTG(X86_TRAP_NMI, nmi), 76 INTG(X86_TRAP_BR, bounds), 77 INTG(X86_TRAP_UD, invalid_op), 78 INTG(X86_TRAP_NM, device_not_available), 79 INTG(X86_TRAP_OLD_MF, coprocessor_segment_overrun), 80 INTG(X86_TRAP_TS, invalid_TSS), 81 INTG(X86_TRAP_NP, segment_not_present), 82 INTG(X86_TRAP_SS, stack_segment), 83 INTG(X86_TRAP_GP, general_protection), 84 INTG(X86_TRAP_SPURIOUS, spurious_interrupt_bug), 85 INTG(X86_TRAP_MF, coprocessor_error), 86 INTG(X86_TRAP_AC, alignment_check), 87 INTG(X86_TRAP_XF, simd_coprocessor_error), 88 89 #ifdef CONFIG_X86_32 90 TSKG(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS), 91 #else 92 INTG(X86_TRAP_DF, double_fault), 93 #endif 94 INTG(X86_TRAP_DB, debug), 95 96 #ifdef CONFIG_X86_MCE 97 INTG(X86_TRAP_MC, &machine_check), 98 #endif 99 100 SYSG(X86_TRAP_OF, overflow), 101 #if defined(CONFIG_IA32_EMULATION) 102 SYSG(IA32_SYSCALL_VECTOR, entry_INT80_compat), 103 #elif defined(CONFIG_X86_32) 104 SYSG(IA32_SYSCALL_VECTOR, entry_INT80_32), 105 #endif 106 }; 107 108 /* 109 * The APIC and SMP idt entries 110 */ 111 static const __initconst struct idt_data apic_idts[] = { 112 #ifdef CONFIG_SMP 113 INTG(RESCHEDULE_VECTOR, reschedule_interrupt), 114 INTG(CALL_FUNCTION_VECTOR, call_function_interrupt), 115 INTG(CALL_FUNCTION_SINGLE_VECTOR, call_function_single_interrupt), 116 INTG(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt), 117 INTG(REBOOT_VECTOR, reboot_interrupt), 118 #endif 119 120 #ifdef CONFIG_X86_THERMAL_VECTOR 121 INTG(THERMAL_APIC_VECTOR, thermal_interrupt), 122 #endif 123 124 #ifdef CONFIG_X86_MCE_THRESHOLD 125 INTG(THRESHOLD_APIC_VECTOR, threshold_interrupt), 126 #endif 127 128 #ifdef CONFIG_X86_MCE_AMD 129 INTG(DEFERRED_ERROR_VECTOR, deferred_error_interrupt), 130 #endif 131 132 #ifdef CONFIG_X86_LOCAL_APIC 133 INTG(LOCAL_TIMER_VECTOR, apic_timer_interrupt), 134 INTG(X86_PLATFORM_IPI_VECTOR, x86_platform_ipi), 135 # ifdef CONFIG_HAVE_KVM 136 INTG(POSTED_INTR_VECTOR, kvm_posted_intr_ipi), 137 INTG(POSTED_INTR_WAKEUP_VECTOR, kvm_posted_intr_wakeup_ipi), 138 INTG(POSTED_INTR_NESTED_VECTOR, kvm_posted_intr_nested_ipi), 139 # endif 140 # ifdef CONFIG_IRQ_WORK 141 INTG(IRQ_WORK_VECTOR, irq_work_interrupt), 142 # endif 143 #ifdef CONFIG_X86_UV 144 INTG(UV_BAU_MESSAGE, uv_bau_message_intr1), 145 #endif 146 INTG(SPURIOUS_APIC_VECTOR, spurious_interrupt), 147 INTG(ERROR_APIC_VECTOR, error_interrupt), 148 #endif 149 }; 150 151 #ifdef CONFIG_X86_64 152 /* 153 * Early traps running on the DEFAULT_STACK because the other interrupt 154 * stacks work only after cpu_init(). 155 */ 156 static const __initconst struct idt_data early_pf_idts[] = { 157 INTG(X86_TRAP_PF, page_fault), 158 }; 159 160 /* 161 * Override for the debug_idt. Same as the default, but with interrupt 162 * stack set to DEFAULT_STACK (0). Required for NMI trap handling. 163 */ 164 static const __initconst struct idt_data dbg_idts[] = { 165 INTG(X86_TRAP_DB, debug), 166 }; 167 #endif 168 169 /* Must be page-aligned because the real IDT is used in a fixmap. */ 170 gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss; 171 172 struct desc_ptr idt_descr __ro_after_init = { 173 .size = (IDT_ENTRIES * 2 * sizeof(unsigned long)) - 1, 174 .address = (unsigned long) idt_table, 175 }; 176 177 #ifdef CONFIG_X86_64 178 /* No need to be aligned, but done to keep all IDTs defined the same way. */ 179 gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss; 180 181 /* 182 * The exceptions which use Interrupt stacks. They are setup after 183 * cpu_init() when the TSS has been initialized. 184 */ 185 static const __initconst struct idt_data ist_idts[] = { 186 ISTG(X86_TRAP_DB, debug, IST_INDEX_DB), 187 ISTG(X86_TRAP_NMI, nmi, IST_INDEX_NMI), 188 ISTG(X86_TRAP_DF, double_fault, IST_INDEX_DF), 189 #ifdef CONFIG_X86_MCE 190 ISTG(X86_TRAP_MC, &machine_check, IST_INDEX_MCE), 191 #endif 192 }; 193 194 /* 195 * Override for the debug_idt. Same as the default, but with interrupt 196 * stack set to DEFAULT_STACK (0). Required for NMI trap handling. 197 */ 198 const struct desc_ptr debug_idt_descr = { 199 .size = IDT_ENTRIES * 16 - 1, 200 .address = (unsigned long) debug_idt_table, 201 }; 202 #endif 203 204 static inline void idt_init_desc(gate_desc *gate, const struct idt_data *d) 205 { 206 unsigned long addr = (unsigned long) d->addr; 207 208 gate->offset_low = (u16) addr; 209 gate->segment = (u16) d->segment; 210 gate->bits = d->bits; 211 gate->offset_middle = (u16) (addr >> 16); 212 #ifdef CONFIG_X86_64 213 gate->offset_high = (u32) (addr >> 32); 214 gate->reserved = 0; 215 #endif 216 } 217 218 static void 219 idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size, bool sys) 220 { 221 gate_desc desc; 222 223 for (; size > 0; t++, size--) { 224 idt_init_desc(&desc, t); 225 write_idt_entry(idt, t->vector, &desc); 226 if (sys) 227 set_bit(t->vector, system_vectors); 228 } 229 } 230 231 static void set_intr_gate(unsigned int n, const void *addr) 232 { 233 struct idt_data data; 234 235 BUG_ON(n > 0xFF); 236 237 memset(&data, 0, sizeof(data)); 238 data.vector = n; 239 data.addr = addr; 240 data.segment = __KERNEL_CS; 241 data.bits.type = GATE_INTERRUPT; 242 data.bits.p = 1; 243 244 idt_setup_from_table(idt_table, &data, 1, false); 245 } 246 247 /** 248 * idt_setup_early_traps - Initialize the idt table with early traps 249 * 250 * On X8664 these traps do not use interrupt stacks as they can't work 251 * before cpu_init() is invoked and sets up TSS. The IST variants are 252 * installed after that. 253 */ 254 void __init idt_setup_early_traps(void) 255 { 256 idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts), 257 true); 258 load_idt(&idt_descr); 259 } 260 261 /** 262 * idt_setup_traps - Initialize the idt table with default traps 263 */ 264 void __init idt_setup_traps(void) 265 { 266 idt_setup_from_table(idt_table, def_idts, ARRAY_SIZE(def_idts), true); 267 } 268 269 #ifdef CONFIG_X86_64 270 /** 271 * idt_setup_early_pf - Initialize the idt table with early pagefault handler 272 * 273 * On X8664 this does not use interrupt stacks as they can't work before 274 * cpu_init() is invoked and sets up TSS. The IST variant is installed 275 * after that. 276 * 277 * FIXME: Why is 32bit and 64bit installing the PF handler at different 278 * places in the early setup code? 279 */ 280 void __init idt_setup_early_pf(void) 281 { 282 idt_setup_from_table(idt_table, early_pf_idts, 283 ARRAY_SIZE(early_pf_idts), true); 284 } 285 286 /** 287 * idt_setup_ist_traps - Initialize the idt table with traps using IST 288 */ 289 void __init idt_setup_ist_traps(void) 290 { 291 idt_setup_from_table(idt_table, ist_idts, ARRAY_SIZE(ist_idts), true); 292 } 293 294 /** 295 * idt_setup_debugidt_traps - Initialize the debug idt table with debug traps 296 */ 297 void __init idt_setup_debugidt_traps(void) 298 { 299 memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16); 300 301 idt_setup_from_table(debug_idt_table, dbg_idts, ARRAY_SIZE(dbg_idts), false); 302 } 303 #endif 304 305 /** 306 * idt_setup_apic_and_irq_gates - Setup APIC/SMP and normal interrupt gates 307 */ 308 void __init idt_setup_apic_and_irq_gates(void) 309 { 310 int i = FIRST_EXTERNAL_VECTOR; 311 void *entry; 312 313 idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true); 314 315 for_each_clear_bit_from(i, system_vectors, FIRST_SYSTEM_VECTOR) { 316 entry = irq_entries_start + 8 * (i - FIRST_EXTERNAL_VECTOR); 317 set_intr_gate(i, entry); 318 } 319 320 #ifdef CONFIG_X86_LOCAL_APIC 321 for_each_clear_bit_from(i, system_vectors, NR_VECTORS) { 322 set_bit(i, system_vectors); 323 set_intr_gate(i, spurious_interrupt); 324 } 325 #endif 326 } 327 328 /** 329 * idt_setup_early_handler - Initializes the idt table with early handlers 330 */ 331 void __init idt_setup_early_handler(void) 332 { 333 int i; 334 335 for (i = 0; i < NUM_EXCEPTION_VECTORS; i++) 336 set_intr_gate(i, early_idt_handler_array[i]); 337 #ifdef CONFIG_X86_32 338 for ( ; i < NR_VECTORS; i++) 339 set_intr_gate(i, early_ignore_irq); 340 #endif 341 load_idt(&idt_descr); 342 } 343 344 /** 345 * idt_invalidate - Invalidate interrupt descriptor table 346 * @addr: The virtual address of the 'invalid' IDT 347 */ 348 void idt_invalidate(void *addr) 349 { 350 struct desc_ptr idt = { .address = (unsigned long) addr, .size = 0 }; 351 352 load_idt(&idt); 353 } 354 355 void __init update_intr_gate(unsigned int n, const void *addr) 356 { 357 if (WARN_ON_ONCE(!test_bit(n, system_vectors))) 358 return; 359 set_intr_gate(n, addr); 360 } 361 362 void alloc_intr_gate(unsigned int n, const void *addr) 363 { 364 BUG_ON(n < FIRST_SYSTEM_VECTOR); 365 if (!test_and_set_bit(n, system_vectors)) 366 set_intr_gate(n, addr); 367 } 368