1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Interrupt descriptor table related code 4 */ 5 #include <linux/interrupt.h> 6 7 #include <asm/cpu_entry_area.h> 8 #include <asm/set_memory.h> 9 #include <asm/traps.h> 10 #include <asm/proto.h> 11 #include <asm/desc.h> 12 #include <asm/hw_irq.h> 13 #include <asm/idtentry.h> 14 15 #define DPL0 0x0 16 #define DPL3 0x3 17 18 #define DEFAULT_STACK 0 19 20 #define G(_vector, _addr, _ist, _type, _dpl, _segment) \ 21 { \ 22 .vector = _vector, \ 23 .bits.ist = _ist, \ 24 .bits.type = _type, \ 25 .bits.dpl = _dpl, \ 26 .bits.p = 1, \ 27 .addr = _addr, \ 28 .segment = _segment, \ 29 } 30 31 /* Interrupt gate */ 32 #define INTG(_vector, _addr) \ 33 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS) 34 35 /* System interrupt gate */ 36 #define SYSG(_vector, _addr) \ 37 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS) 38 39 #ifdef CONFIG_X86_64 40 /* 41 * Interrupt gate with interrupt stack. The _ist index is the index in 42 * the tss.ist[] array, but for the descriptor it needs to start at 1. 43 */ 44 #define ISTG(_vector, _addr, _ist) \ 45 G(_vector, _addr, _ist + 1, GATE_INTERRUPT, DPL0, __KERNEL_CS) 46 #else 47 #define ISTG(_vector, _addr, _ist) INTG(_vector, _addr) 48 #endif 49 50 /* Task gate */ 51 #define TSKG(_vector, _gdt) \ 52 G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3) 53 54 #define IDT_TABLE_SIZE (IDT_ENTRIES * sizeof(gate_desc)) 55 56 static bool idt_setup_done __initdata; 57 58 /* 59 * Early traps running on the DEFAULT_STACK because the other interrupt 60 * stacks work only after cpu_init(). 61 */ 62 static const __initconst struct idt_data early_idts[] = { 63 INTG(X86_TRAP_DB, asm_exc_debug), 64 SYSG(X86_TRAP_BP, asm_exc_int3), 65 66 #ifdef CONFIG_X86_32 67 /* 68 * Not possible on 64-bit. See idt_setup_early_pf() for details. 69 */ 70 INTG(X86_TRAP_PF, asm_exc_page_fault), 71 #endif 72 }; 73 74 /* 75 * The default IDT entries which are set up in trap_init() before 76 * cpu_init() is invoked. Interrupt stacks cannot be used at that point and 77 * the traps which use them are reinitialized with IST after cpu_init() has 78 * set up TSS. 79 */ 80 static const __initconst struct idt_data def_idts[] = { 81 INTG(X86_TRAP_DE, asm_exc_divide_error), 82 ISTG(X86_TRAP_NMI, asm_exc_nmi, IST_INDEX_NMI), 83 INTG(X86_TRAP_BR, asm_exc_bounds), 84 INTG(X86_TRAP_UD, asm_exc_invalid_op), 85 INTG(X86_TRAP_NM, asm_exc_device_not_available), 86 INTG(X86_TRAP_OLD_MF, asm_exc_coproc_segment_overrun), 87 INTG(X86_TRAP_TS, asm_exc_invalid_tss), 88 INTG(X86_TRAP_NP, asm_exc_segment_not_present), 89 INTG(X86_TRAP_SS, asm_exc_stack_segment), 90 INTG(X86_TRAP_GP, asm_exc_general_protection), 91 INTG(X86_TRAP_SPURIOUS, asm_exc_spurious_interrupt_bug), 92 INTG(X86_TRAP_MF, asm_exc_coprocessor_error), 93 INTG(X86_TRAP_AC, asm_exc_alignment_check), 94 INTG(X86_TRAP_XF, asm_exc_simd_coprocessor_error), 95 96 #ifdef CONFIG_X86_32 97 TSKG(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS), 98 #else 99 ISTG(X86_TRAP_DF, asm_exc_double_fault, IST_INDEX_DF), 100 #endif 101 ISTG(X86_TRAP_DB, asm_exc_debug, IST_INDEX_DB), 102 103 #ifdef CONFIG_X86_MCE 104 ISTG(X86_TRAP_MC, asm_exc_machine_check, IST_INDEX_MCE), 105 #endif 106 107 #ifdef CONFIG_X86_KERNEL_IBT 108 INTG(X86_TRAP_CP, asm_exc_control_protection), 109 #endif 110 111 #ifdef CONFIG_AMD_MEM_ENCRYPT 112 ISTG(X86_TRAP_VC, asm_exc_vmm_communication, IST_INDEX_VC), 113 #endif 114 115 SYSG(X86_TRAP_OF, asm_exc_overflow), 116 #if defined(CONFIG_IA32_EMULATION) 117 SYSG(IA32_SYSCALL_VECTOR, entry_INT80_compat), 118 #elif defined(CONFIG_X86_32) 119 SYSG(IA32_SYSCALL_VECTOR, entry_INT80_32), 120 #endif 121 }; 122 123 /* 124 * The APIC and SMP idt entries 125 */ 126 static const __initconst struct idt_data apic_idts[] = { 127 #ifdef CONFIG_SMP 128 INTG(RESCHEDULE_VECTOR, asm_sysvec_reschedule_ipi), 129 INTG(CALL_FUNCTION_VECTOR, asm_sysvec_call_function), 130 INTG(CALL_FUNCTION_SINGLE_VECTOR, asm_sysvec_call_function_single), 131 INTG(IRQ_MOVE_CLEANUP_VECTOR, asm_sysvec_irq_move_cleanup), 132 INTG(REBOOT_VECTOR, asm_sysvec_reboot), 133 #endif 134 135 #ifdef CONFIG_X86_THERMAL_VECTOR 136 INTG(THERMAL_APIC_VECTOR, asm_sysvec_thermal), 137 #endif 138 139 #ifdef CONFIG_X86_MCE_THRESHOLD 140 INTG(THRESHOLD_APIC_VECTOR, asm_sysvec_threshold), 141 #endif 142 143 #ifdef CONFIG_X86_MCE_AMD 144 INTG(DEFERRED_ERROR_VECTOR, asm_sysvec_deferred_error), 145 #endif 146 147 #ifdef CONFIG_X86_LOCAL_APIC 148 INTG(LOCAL_TIMER_VECTOR, asm_sysvec_apic_timer_interrupt), 149 INTG(X86_PLATFORM_IPI_VECTOR, asm_sysvec_x86_platform_ipi), 150 # ifdef CONFIG_HAVE_KVM 151 INTG(POSTED_INTR_VECTOR, asm_sysvec_kvm_posted_intr_ipi), 152 INTG(POSTED_INTR_WAKEUP_VECTOR, asm_sysvec_kvm_posted_intr_wakeup_ipi), 153 INTG(POSTED_INTR_NESTED_VECTOR, asm_sysvec_kvm_posted_intr_nested_ipi), 154 # endif 155 # ifdef CONFIG_IRQ_WORK 156 INTG(IRQ_WORK_VECTOR, asm_sysvec_irq_work), 157 # endif 158 INTG(SPURIOUS_APIC_VECTOR, asm_sysvec_spurious_apic_interrupt), 159 INTG(ERROR_APIC_VECTOR, asm_sysvec_error_interrupt), 160 #endif 161 }; 162 163 /* Must be page-aligned because the real IDT is used in the cpu entry area */ 164 static gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss; 165 166 static struct desc_ptr idt_descr __ro_after_init = { 167 .size = IDT_TABLE_SIZE - 1, 168 .address = (unsigned long) idt_table, 169 }; 170 171 void load_current_idt(void) 172 { 173 lockdep_assert_irqs_disabled(); 174 load_idt(&idt_descr); 175 } 176 177 #ifdef CONFIG_X86_F00F_BUG 178 bool idt_is_f00f_address(unsigned long address) 179 { 180 return ((address - idt_descr.address) >> 3) == 6; 181 } 182 #endif 183 184 static __init void 185 idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size, bool sys) 186 { 187 gate_desc desc; 188 189 for (; size > 0; t++, size--) { 190 idt_init_desc(&desc, t); 191 write_idt_entry(idt, t->vector, &desc); 192 if (sys) 193 set_bit(t->vector, system_vectors); 194 } 195 } 196 197 static __init void set_intr_gate(unsigned int n, const void *addr) 198 { 199 struct idt_data data; 200 201 init_idt_data(&data, n, addr); 202 203 idt_setup_from_table(idt_table, &data, 1, false); 204 } 205 206 /** 207 * idt_setup_early_traps - Initialize the idt table with early traps 208 * 209 * On X8664 these traps do not use interrupt stacks as they can't work 210 * before cpu_init() is invoked and sets up TSS. The IST variants are 211 * installed after that. 212 */ 213 void __init idt_setup_early_traps(void) 214 { 215 idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts), 216 true); 217 load_idt(&idt_descr); 218 } 219 220 /** 221 * idt_setup_traps - Initialize the idt table with default traps 222 */ 223 void __init idt_setup_traps(void) 224 { 225 idt_setup_from_table(idt_table, def_idts, ARRAY_SIZE(def_idts), true); 226 } 227 228 #ifdef CONFIG_X86_64 229 /* 230 * Early traps running on the DEFAULT_STACK because the other interrupt 231 * stacks work only after cpu_init(). 232 */ 233 static const __initconst struct idt_data early_pf_idts[] = { 234 INTG(X86_TRAP_PF, asm_exc_page_fault), 235 }; 236 237 /** 238 * idt_setup_early_pf - Initialize the idt table with early pagefault handler 239 * 240 * On X8664 this does not use interrupt stacks as they can't work before 241 * cpu_init() is invoked and sets up TSS. The IST variant is installed 242 * after that. 243 * 244 * Note, that X86_64 cannot install the real #PF handler in 245 * idt_setup_early_traps() because the memory initialization needs the #PF 246 * handler from the early_idt_handler_array to initialize the early page 247 * tables. 248 */ 249 void __init idt_setup_early_pf(void) 250 { 251 idt_setup_from_table(idt_table, early_pf_idts, 252 ARRAY_SIZE(early_pf_idts), true); 253 } 254 #endif 255 256 static void __init idt_map_in_cea(void) 257 { 258 /* 259 * Set the IDT descriptor to a fixed read-only location in the cpu 260 * entry area, so that the "sidt" instruction will not leak the 261 * location of the kernel, and to defend the IDT against arbitrary 262 * memory write vulnerabilities. 263 */ 264 cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table), 265 PAGE_KERNEL_RO); 266 idt_descr.address = CPU_ENTRY_AREA_RO_IDT; 267 } 268 269 /** 270 * idt_setup_apic_and_irq_gates - Setup APIC/SMP and normal interrupt gates 271 */ 272 void __init idt_setup_apic_and_irq_gates(void) 273 { 274 int i = FIRST_EXTERNAL_VECTOR; 275 void *entry; 276 277 idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true); 278 279 for_each_clear_bit_from(i, system_vectors, FIRST_SYSTEM_VECTOR) { 280 entry = irq_entries_start + IDT_ALIGN * (i - FIRST_EXTERNAL_VECTOR); 281 set_intr_gate(i, entry); 282 } 283 284 #ifdef CONFIG_X86_LOCAL_APIC 285 for_each_clear_bit_from(i, system_vectors, NR_VECTORS) { 286 /* 287 * Don't set the non assigned system vectors in the 288 * system_vectors bitmap. Otherwise they show up in 289 * /proc/interrupts. 290 */ 291 entry = spurious_entries_start + IDT_ALIGN * (i - FIRST_SYSTEM_VECTOR); 292 set_intr_gate(i, entry); 293 } 294 #endif 295 /* Map IDT into CPU entry area and reload it. */ 296 idt_map_in_cea(); 297 load_idt(&idt_descr); 298 299 /* Make the IDT table read only */ 300 set_memory_ro((unsigned long)&idt_table, 1); 301 302 idt_setup_done = true; 303 } 304 305 /** 306 * idt_setup_early_handler - Initializes the idt table with early handlers 307 */ 308 void __init idt_setup_early_handler(void) 309 { 310 int i; 311 312 for (i = 0; i < NUM_EXCEPTION_VECTORS; i++) 313 set_intr_gate(i, early_idt_handler_array[i]); 314 #ifdef CONFIG_X86_32 315 for ( ; i < NR_VECTORS; i++) 316 set_intr_gate(i, early_ignore_irq); 317 #endif 318 load_idt(&idt_descr); 319 } 320 321 /** 322 * idt_invalidate - Invalidate interrupt descriptor table 323 */ 324 void idt_invalidate(void) 325 { 326 static const struct desc_ptr idt = { .address = 0, .size = 0 }; 327 328 load_idt(&idt); 329 } 330 331 void __init alloc_intr_gate(unsigned int n, const void *addr) 332 { 333 if (WARN_ON(n < FIRST_SYSTEM_VECTOR)) 334 return; 335 336 if (WARN_ON(idt_setup_done)) 337 return; 338 339 if (!WARN_ON(test_and_set_bit(n, system_vectors))) 340 set_intr_gate(n, addr); 341 } 342