1 /* 2 * Interrupt descriptor table related code 3 * 4 * This file is licensed under the GPL V2 5 */ 6 #include <linux/interrupt.h> 7 8 #include <asm/traps.h> 9 #include <asm/proto.h> 10 #include <asm/desc.h> 11 12 struct idt_data { 13 unsigned int vector; 14 unsigned int segment; 15 struct idt_bits bits; 16 const void *addr; 17 }; 18 19 #define DPL0 0x0 20 #define DPL3 0x3 21 22 #define DEFAULT_STACK 0 23 24 #define G(_vector, _addr, _ist, _type, _dpl, _segment) \ 25 { \ 26 .vector = _vector, \ 27 .bits.ist = _ist, \ 28 .bits.type = _type, \ 29 .bits.dpl = _dpl, \ 30 .bits.p = 1, \ 31 .addr = _addr, \ 32 .segment = _segment, \ 33 } 34 35 /* Interrupt gate */ 36 #define INTG(_vector, _addr) \ 37 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS) 38 39 /* System interrupt gate */ 40 #define SYSG(_vector, _addr) \ 41 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS) 42 43 /* Interrupt gate with interrupt stack */ 44 #define ISTG(_vector, _addr, _ist) \ 45 G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS) 46 47 /* System interrupt gate with interrupt stack */ 48 #define SISTG(_vector, _addr, _ist) \ 49 G(_vector, _addr, _ist, GATE_INTERRUPT, DPL3, __KERNEL_CS) 50 51 /* Task gate */ 52 #define TSKG(_vector, _gdt) \ 53 G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3) 54 55 /* 56 * Early traps running on the DEFAULT_STACK because the other interrupt 57 * stacks work only after cpu_init(). 58 */ 59 static const __initdata struct idt_data early_idts[] = { 60 INTG(X86_TRAP_DB, debug), 61 SYSG(X86_TRAP_BP, int3), 62 #ifdef CONFIG_X86_32 63 INTG(X86_TRAP_PF, page_fault), 64 #endif 65 }; 66 67 /* 68 * The default IDT entries which are set up in trap_init() before 69 * cpu_init() is invoked. Interrupt stacks cannot be used at that point and 70 * the traps which use them are reinitialized with IST after cpu_init() has 71 * set up TSS. 72 */ 73 static const __initdata struct idt_data def_idts[] = { 74 INTG(X86_TRAP_DE, divide_error), 75 INTG(X86_TRAP_NMI, nmi), 76 INTG(X86_TRAP_BR, bounds), 77 INTG(X86_TRAP_UD, invalid_op), 78 INTG(X86_TRAP_NM, device_not_available), 79 INTG(X86_TRAP_OLD_MF, coprocessor_segment_overrun), 80 INTG(X86_TRAP_TS, invalid_TSS), 81 INTG(X86_TRAP_NP, segment_not_present), 82 INTG(X86_TRAP_SS, stack_segment), 83 INTG(X86_TRAP_GP, general_protection), 84 INTG(X86_TRAP_SPURIOUS, spurious_interrupt_bug), 85 INTG(X86_TRAP_MF, coprocessor_error), 86 INTG(X86_TRAP_AC, alignment_check), 87 INTG(X86_TRAP_XF, simd_coprocessor_error), 88 89 #ifdef CONFIG_X86_32 90 TSKG(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS), 91 #else 92 INTG(X86_TRAP_DF, double_fault), 93 #endif 94 INTG(X86_TRAP_DB, debug), 95 INTG(X86_TRAP_NMI, nmi), 96 INTG(X86_TRAP_BP, int3), 97 98 #ifdef CONFIG_X86_MCE 99 INTG(X86_TRAP_MC, &machine_check), 100 #endif 101 102 SYSG(X86_TRAP_OF, overflow), 103 #if defined(CONFIG_IA32_EMULATION) 104 SYSG(IA32_SYSCALL_VECTOR, entry_INT80_compat), 105 #elif defined(CONFIG_X86_32) 106 SYSG(IA32_SYSCALL_VECTOR, entry_INT80_32), 107 #endif 108 }; 109 110 /* 111 * The APIC and SMP idt entries 112 */ 113 static const __initdata struct idt_data apic_idts[] = { 114 #ifdef CONFIG_SMP 115 INTG(RESCHEDULE_VECTOR, reschedule_interrupt), 116 INTG(CALL_FUNCTION_VECTOR, call_function_interrupt), 117 INTG(CALL_FUNCTION_SINGLE_VECTOR, call_function_single_interrupt), 118 INTG(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt), 119 INTG(REBOOT_VECTOR, reboot_interrupt), 120 #endif 121 122 #ifdef CONFIG_X86_THERMAL_VECTOR 123 INTG(THERMAL_APIC_VECTOR, thermal_interrupt), 124 #endif 125 126 #ifdef CONFIG_X86_MCE_THRESHOLD 127 INTG(THRESHOLD_APIC_VECTOR, threshold_interrupt), 128 #endif 129 130 #ifdef CONFIG_X86_MCE_AMD 131 INTG(DEFERRED_ERROR_VECTOR, deferred_error_interrupt), 132 #endif 133 134 #ifdef CONFIG_X86_LOCAL_APIC 135 INTG(LOCAL_TIMER_VECTOR, apic_timer_interrupt), 136 INTG(X86_PLATFORM_IPI_VECTOR, x86_platform_ipi), 137 # ifdef CONFIG_HAVE_KVM 138 INTG(POSTED_INTR_VECTOR, kvm_posted_intr_ipi), 139 INTG(POSTED_INTR_WAKEUP_VECTOR, kvm_posted_intr_wakeup_ipi), 140 INTG(POSTED_INTR_NESTED_VECTOR, kvm_posted_intr_nested_ipi), 141 # endif 142 # ifdef CONFIG_IRQ_WORK 143 INTG(IRQ_WORK_VECTOR, irq_work_interrupt), 144 # endif 145 INTG(SPURIOUS_APIC_VECTOR, spurious_interrupt), 146 INTG(ERROR_APIC_VECTOR, error_interrupt), 147 #endif 148 }; 149 150 #ifdef CONFIG_X86_64 151 /* 152 * Early traps running on the DEFAULT_STACK because the other interrupt 153 * stacks work only after cpu_init(). 154 */ 155 static const __initdata struct idt_data early_pf_idts[] = { 156 INTG(X86_TRAP_PF, page_fault), 157 }; 158 159 /* 160 * Override for the debug_idt. Same as the default, but with interrupt 161 * stack set to DEFAULT_STACK (0). Required for NMI trap handling. 162 */ 163 static const __initdata struct idt_data dbg_idts[] = { 164 INTG(X86_TRAP_DB, debug), 165 INTG(X86_TRAP_BP, int3), 166 }; 167 #endif 168 169 /* Must be page-aligned because the real IDT is used in a fixmap. */ 170 gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss; 171 172 struct desc_ptr idt_descr __ro_after_init = { 173 .size = (IDT_ENTRIES * 2 * sizeof(unsigned long)) - 1, 174 .address = (unsigned long) idt_table, 175 }; 176 177 #ifdef CONFIG_X86_64 178 /* No need to be aligned, but done to keep all IDTs defined the same way. */ 179 gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss; 180 181 /* 182 * The exceptions which use Interrupt stacks. They are setup after 183 * cpu_init() when the TSS has been initialized. 184 */ 185 static const __initdata struct idt_data ist_idts[] = { 186 ISTG(X86_TRAP_DB, debug, DEBUG_STACK), 187 ISTG(X86_TRAP_NMI, nmi, NMI_STACK), 188 SISTG(X86_TRAP_BP, int3, DEBUG_STACK), 189 ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK), 190 #ifdef CONFIG_X86_MCE 191 ISTG(X86_TRAP_MC, &machine_check, MCE_STACK), 192 #endif 193 }; 194 195 /* 196 * Override for the debug_idt. Same as the default, but with interrupt 197 * stack set to DEFAULT_STACK (0). Required for NMI trap handling. 198 */ 199 const struct desc_ptr debug_idt_descr = { 200 .size = IDT_ENTRIES * 16 - 1, 201 .address = (unsigned long) debug_idt_table, 202 }; 203 #endif 204 205 static inline void idt_init_desc(gate_desc *gate, const struct idt_data *d) 206 { 207 unsigned long addr = (unsigned long) d->addr; 208 209 gate->offset_low = (u16) addr; 210 gate->segment = (u16) d->segment; 211 gate->bits = d->bits; 212 gate->offset_middle = (u16) (addr >> 16); 213 #ifdef CONFIG_X86_64 214 gate->offset_high = (u32) (addr >> 32); 215 gate->reserved = 0; 216 #endif 217 } 218 219 static void 220 idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size, bool sys) 221 { 222 gate_desc desc; 223 224 for (; size > 0; t++, size--) { 225 idt_init_desc(&desc, t); 226 write_idt_entry(idt, t->vector, &desc); 227 if (sys) 228 set_bit(t->vector, used_vectors); 229 } 230 } 231 232 static void set_intr_gate(unsigned int n, const void *addr) 233 { 234 struct idt_data data; 235 236 BUG_ON(n > 0xFF); 237 238 memset(&data, 0, sizeof(data)); 239 data.vector = n; 240 data.addr = addr; 241 data.segment = __KERNEL_CS; 242 data.bits.type = GATE_INTERRUPT; 243 data.bits.p = 1; 244 245 idt_setup_from_table(idt_table, &data, 1, false); 246 } 247 248 /** 249 * idt_setup_early_traps - Initialize the idt table with early traps 250 * 251 * On X8664 these traps do not use interrupt stacks as they can't work 252 * before cpu_init() is invoked and sets up TSS. The IST variants are 253 * installed after that. 254 */ 255 void __init idt_setup_early_traps(void) 256 { 257 idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts), 258 true); 259 load_idt(&idt_descr); 260 } 261 262 /** 263 * idt_setup_traps - Initialize the idt table with default traps 264 */ 265 void __init idt_setup_traps(void) 266 { 267 idt_setup_from_table(idt_table, def_idts, ARRAY_SIZE(def_idts), true); 268 } 269 270 #ifdef CONFIG_X86_64 271 /** 272 * idt_setup_early_pf - Initialize the idt table with early pagefault handler 273 * 274 * On X8664 this does not use interrupt stacks as they can't work before 275 * cpu_init() is invoked and sets up TSS. The IST variant is installed 276 * after that. 277 * 278 * FIXME: Why is 32bit and 64bit installing the PF handler at different 279 * places in the early setup code? 280 */ 281 void __init idt_setup_early_pf(void) 282 { 283 idt_setup_from_table(idt_table, early_pf_idts, 284 ARRAY_SIZE(early_pf_idts), true); 285 } 286 287 /** 288 * idt_setup_ist_traps - Initialize the idt table with traps using IST 289 */ 290 void __init idt_setup_ist_traps(void) 291 { 292 idt_setup_from_table(idt_table, ist_idts, ARRAY_SIZE(ist_idts), true); 293 } 294 295 /** 296 * idt_setup_debugidt_traps - Initialize the debug idt table with debug traps 297 */ 298 void __init idt_setup_debugidt_traps(void) 299 { 300 memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16); 301 302 idt_setup_from_table(debug_idt_table, dbg_idts, ARRAY_SIZE(dbg_idts), false); 303 } 304 #endif 305 306 /** 307 * idt_setup_apic_and_irq_gates - Setup APIC/SMP and normal interrupt gates 308 */ 309 void __init idt_setup_apic_and_irq_gates(void) 310 { 311 int i = FIRST_EXTERNAL_VECTOR; 312 void *entry; 313 314 idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true); 315 316 for_each_clear_bit_from(i, used_vectors, FIRST_SYSTEM_VECTOR) { 317 entry = irq_entries_start + 8 * (i - FIRST_EXTERNAL_VECTOR); 318 set_intr_gate(i, entry); 319 } 320 321 for_each_clear_bit_from(i, used_vectors, NR_VECTORS) { 322 #ifdef CONFIG_X86_LOCAL_APIC 323 set_bit(i, used_vectors); 324 set_intr_gate(i, spurious_interrupt); 325 #else 326 entry = irq_entries_start + 8 * (i - FIRST_EXTERNAL_VECTOR); 327 set_intr_gate(i, entry); 328 #endif 329 } 330 } 331 332 /** 333 * idt_setup_early_handler - Initializes the idt table with early handlers 334 */ 335 void __init idt_setup_early_handler(void) 336 { 337 int i; 338 339 for (i = 0; i < NUM_EXCEPTION_VECTORS; i++) 340 set_intr_gate(i, early_idt_handler_array[i]); 341 #ifdef CONFIG_X86_32 342 for ( ; i < NR_VECTORS; i++) 343 set_intr_gate(i, early_ignore_irq); 344 #endif 345 load_idt(&idt_descr); 346 } 347 348 /** 349 * idt_invalidate - Invalidate interrupt descriptor table 350 * @addr: The virtual address of the 'invalid' IDT 351 */ 352 void idt_invalidate(void *addr) 353 { 354 struct desc_ptr idt = { .address = (unsigned long) addr, .size = 0 }; 355 356 load_idt(&idt); 357 } 358 359 void __init update_intr_gate(unsigned int n, const void *addr) 360 { 361 if (WARN_ON_ONCE(!test_bit(n, used_vectors))) 362 return; 363 set_intr_gate(n, addr); 364 } 365 366 void alloc_intr_gate(unsigned int n, const void *addr) 367 { 368 BUG_ON(n < FIRST_SYSTEM_VECTOR); 369 if (!test_and_set_bit(n, used_vectors)) 370 set_intr_gate(n, addr); 371 } 372