1 #include <linux/linkage.h> 2 #include <linux/errno.h> 3 #include <linux/signal.h> 4 #include <linux/sched.h> 5 #include <linux/ioport.h> 6 #include <linux/interrupt.h> 7 #include <linux/timex.h> 8 #include <linux/random.h> 9 #include <linux/init.h> 10 #include <linux/kernel_stat.h> 11 #include <linux/syscore_ops.h> 12 #include <linux/bitops.h> 13 #include <linux/acpi.h> 14 #include <linux/io.h> 15 #include <linux/delay.h> 16 17 #include <linux/atomic.h> 18 #include <asm/timer.h> 19 #include <asm/hw_irq.h> 20 #include <asm/pgtable.h> 21 #include <asm/desc.h> 22 #include <asm/apic.h> 23 #include <asm/i8259.h> 24 25 /* 26 * This is the 'legacy' 8259A Programmable Interrupt Controller, 27 * present in the majority of PC/AT boxes. 28 * plus some generic x86 specific things if generic specifics makes 29 * any sense at all. 30 */ 31 static void init_8259A(int auto_eoi); 32 33 static int i8259A_auto_eoi; 34 DEFINE_RAW_SPINLOCK(i8259A_lock); 35 36 /* 37 * 8259A PIC functions to handle ISA devices: 38 */ 39 40 /* 41 * This contains the irq mask for both 8259A irq controllers, 42 */ 43 unsigned int cached_irq_mask = 0xffff; 44 45 /* 46 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older) 47 * boards the timer interrupt is not really connected to any IO-APIC pin, 48 * it's fed to the master 8259A's IR0 line only. 49 * 50 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC. 51 * this 'mixed mode' IRQ handling costs nothing because it's only used 52 * at IRQ setup time. 53 */ 54 unsigned long io_apic_irqs; 55 56 static void mask_8259A_irq(unsigned int irq) 57 { 58 unsigned int mask = 1 << irq; 59 unsigned long flags; 60 61 raw_spin_lock_irqsave(&i8259A_lock, flags); 62 cached_irq_mask |= mask; 63 if (irq & 8) 64 outb(cached_slave_mask, PIC_SLAVE_IMR); 65 else 66 outb(cached_master_mask, PIC_MASTER_IMR); 67 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 68 } 69 70 static void disable_8259A_irq(struct irq_data *data) 71 { 72 mask_8259A_irq(data->irq); 73 } 74 75 static void unmask_8259A_irq(unsigned int irq) 76 { 77 unsigned int mask = ~(1 << irq); 78 unsigned long flags; 79 80 raw_spin_lock_irqsave(&i8259A_lock, flags); 81 cached_irq_mask &= mask; 82 if (irq & 8) 83 outb(cached_slave_mask, PIC_SLAVE_IMR); 84 else 85 outb(cached_master_mask, PIC_MASTER_IMR); 86 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 87 } 88 89 static void enable_8259A_irq(struct irq_data *data) 90 { 91 unmask_8259A_irq(data->irq); 92 } 93 94 static int i8259A_irq_pending(unsigned int irq) 95 { 96 unsigned int mask = 1<<irq; 97 unsigned long flags; 98 int ret; 99 100 raw_spin_lock_irqsave(&i8259A_lock, flags); 101 if (irq < 8) 102 ret = inb(PIC_MASTER_CMD) & mask; 103 else 104 ret = inb(PIC_SLAVE_CMD) & (mask >> 8); 105 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 106 107 return ret; 108 } 109 110 static void make_8259A_irq(unsigned int irq) 111 { 112 disable_irq_nosync(irq); 113 io_apic_irqs &= ~(1<<irq); 114 irq_set_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq, 115 i8259A_chip.name); 116 enable_irq(irq); 117 } 118 119 /* 120 * This function assumes to be called rarely. Switching between 121 * 8259A registers is slow. 122 * This has to be protected by the irq controller spinlock 123 * before being called. 124 */ 125 static inline int i8259A_irq_real(unsigned int irq) 126 { 127 int value; 128 int irqmask = 1<<irq; 129 130 if (irq < 8) { 131 outb(0x0B, PIC_MASTER_CMD); /* ISR register */ 132 value = inb(PIC_MASTER_CMD) & irqmask; 133 outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */ 134 return value; 135 } 136 outb(0x0B, PIC_SLAVE_CMD); /* ISR register */ 137 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); 138 outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */ 139 return value; 140 } 141 142 /* 143 * Careful! The 8259A is a fragile beast, it pretty 144 * much _has_ to be done exactly like this (mask it 145 * first, _then_ send the EOI, and the order of EOI 146 * to the two 8259s is important! 147 */ 148 static void mask_and_ack_8259A(struct irq_data *data) 149 { 150 unsigned int irq = data->irq; 151 unsigned int irqmask = 1 << irq; 152 unsigned long flags; 153 154 raw_spin_lock_irqsave(&i8259A_lock, flags); 155 /* 156 * Lightweight spurious IRQ detection. We do not want 157 * to overdo spurious IRQ handling - it's usually a sign 158 * of hardware problems, so we only do the checks we can 159 * do without slowing down good hardware unnecessarily. 160 * 161 * Note that IRQ7 and IRQ15 (the two spurious IRQs 162 * usually resulting from the 8259A-1|2 PICs) occur 163 * even if the IRQ is masked in the 8259A. Thus we 164 * can check spurious 8259A IRQs without doing the 165 * quite slow i8259A_irq_real() call for every IRQ. 166 * This does not cover 100% of spurious interrupts, 167 * but should be enough to warn the user that there 168 * is something bad going on ... 169 */ 170 if (cached_irq_mask & irqmask) 171 goto spurious_8259A_irq; 172 cached_irq_mask |= irqmask; 173 174 handle_real_irq: 175 if (irq & 8) { 176 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */ 177 outb(cached_slave_mask, PIC_SLAVE_IMR); 178 /* 'Specific EOI' to slave */ 179 outb(0x60+(irq&7), PIC_SLAVE_CMD); 180 /* 'Specific EOI' to master-IRQ2 */ 181 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); 182 } else { 183 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */ 184 outb(cached_master_mask, PIC_MASTER_IMR); 185 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */ 186 } 187 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 188 return; 189 190 spurious_8259A_irq: 191 /* 192 * this is the slow path - should happen rarely. 193 */ 194 if (i8259A_irq_real(irq)) 195 /* 196 * oops, the IRQ _is_ in service according to the 197 * 8259A - not spurious, go handle it. 198 */ 199 goto handle_real_irq; 200 201 { 202 static int spurious_irq_mask; 203 /* 204 * At this point we can be sure the IRQ is spurious, 205 * lets ACK and report it. [once per IRQ] 206 */ 207 if (!(spurious_irq_mask & irqmask)) { 208 printk(KERN_DEBUG 209 "spurious 8259A interrupt: IRQ%d.\n", irq); 210 spurious_irq_mask |= irqmask; 211 } 212 atomic_inc(&irq_err_count); 213 /* 214 * Theoretically we do not have to handle this IRQ, 215 * but in Linux this does not cause problems and is 216 * simpler for us. 217 */ 218 goto handle_real_irq; 219 } 220 } 221 222 struct irq_chip i8259A_chip = { 223 .name = "XT-PIC", 224 .irq_mask = disable_8259A_irq, 225 .irq_disable = disable_8259A_irq, 226 .irq_unmask = enable_8259A_irq, 227 .irq_mask_ack = mask_and_ack_8259A, 228 }; 229 230 static char irq_trigger[2]; 231 /** 232 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ 233 */ 234 static void restore_ELCR(char *trigger) 235 { 236 outb(trigger[0], 0x4d0); 237 outb(trigger[1], 0x4d1); 238 } 239 240 static void save_ELCR(char *trigger) 241 { 242 /* IRQ 0,1,2,8,13 are marked as reserved */ 243 trigger[0] = inb(0x4d0) & 0xF8; 244 trigger[1] = inb(0x4d1) & 0xDE; 245 } 246 247 static void i8259A_resume(void) 248 { 249 init_8259A(i8259A_auto_eoi); 250 restore_ELCR(irq_trigger); 251 } 252 253 static int i8259A_suspend(void) 254 { 255 save_ELCR(irq_trigger); 256 return 0; 257 } 258 259 static void i8259A_shutdown(void) 260 { 261 /* Put the i8259A into a quiescent state that 262 * the kernel initialization code can get it 263 * out of. 264 */ 265 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ 266 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ 267 } 268 269 static struct syscore_ops i8259_syscore_ops = { 270 .suspend = i8259A_suspend, 271 .resume = i8259A_resume, 272 .shutdown = i8259A_shutdown, 273 }; 274 275 static void mask_8259A(void) 276 { 277 unsigned long flags; 278 279 raw_spin_lock_irqsave(&i8259A_lock, flags); 280 281 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ 282 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ 283 284 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 285 } 286 287 static void unmask_8259A(void) 288 { 289 unsigned long flags; 290 291 raw_spin_lock_irqsave(&i8259A_lock, flags); 292 293 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */ 294 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */ 295 296 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 297 } 298 299 static void init_8259A(int auto_eoi) 300 { 301 unsigned long flags; 302 303 i8259A_auto_eoi = auto_eoi; 304 305 raw_spin_lock_irqsave(&i8259A_lock, flags); 306 307 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ 308 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ 309 310 /* 311 * outb_pic - this has to work on a wide range of PC hardware. 312 */ 313 outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */ 314 315 /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */ 316 outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR); 317 318 /* 8259A-1 (the master) has a slave on IR2 */ 319 outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); 320 321 if (auto_eoi) /* master does Auto EOI */ 322 outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR); 323 else /* master expects normal EOI */ 324 outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR); 325 326 outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */ 327 328 /* ICW2: 8259A-2 IR0-7 mapped to IRQ8_VECTOR */ 329 outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR); 330 /* 8259A-2 is a slave on master's IR2 */ 331 outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR); 332 /* (slave's support for AEOI in flat mode is to be investigated) */ 333 outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); 334 335 if (auto_eoi) 336 /* 337 * In AEOI mode we just have to mask the interrupt 338 * when acking. 339 */ 340 i8259A_chip.irq_mask_ack = disable_8259A_irq; 341 else 342 i8259A_chip.irq_mask_ack = mask_and_ack_8259A; 343 344 udelay(100); /* wait for 8259A to initialize */ 345 346 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */ 347 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */ 348 349 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 350 } 351 352 /* 353 * make i8259 a driver so that we can select pic functions at run time. the goal 354 * is to make x86 binary compatible among pc compatible and non-pc compatible 355 * platforms, such as x86 MID. 356 */ 357 358 static void legacy_pic_noop(void) { }; 359 static void legacy_pic_uint_noop(unsigned int unused) { }; 360 static void legacy_pic_int_noop(int unused) { }; 361 static int legacy_pic_irq_pending_noop(unsigned int irq) 362 { 363 return 0; 364 } 365 366 struct legacy_pic null_legacy_pic = { 367 .nr_legacy_irqs = 0, 368 .chip = &dummy_irq_chip, 369 .mask = legacy_pic_uint_noop, 370 .unmask = legacy_pic_uint_noop, 371 .mask_all = legacy_pic_noop, 372 .restore_mask = legacy_pic_noop, 373 .init = legacy_pic_int_noop, 374 .irq_pending = legacy_pic_irq_pending_noop, 375 .make_irq = legacy_pic_uint_noop, 376 }; 377 378 struct legacy_pic default_legacy_pic = { 379 .nr_legacy_irqs = NR_IRQS_LEGACY, 380 .chip = &i8259A_chip, 381 .mask = mask_8259A_irq, 382 .unmask = unmask_8259A_irq, 383 .mask_all = mask_8259A, 384 .restore_mask = unmask_8259A, 385 .init = init_8259A, 386 .irq_pending = i8259A_irq_pending, 387 .make_irq = make_8259A_irq, 388 }; 389 390 struct legacy_pic *legacy_pic = &default_legacy_pic; 391 392 static int __init i8259A_init_ops(void) 393 { 394 if (legacy_pic == &default_legacy_pic) 395 register_syscore_ops(&i8259_syscore_ops); 396 397 return 0; 398 } 399 400 device_initcall(i8259A_init_ops); 401