1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License as published by 4 * the Free Software Foundation; either version 2 of the License, or 5 * (at your option) any later version. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program; if not, write to the Free Software 14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 15 * 16 * Copyright (C) 2007 Alan Stern 17 * Copyright (C) 2009 IBM Corporation 18 * Copyright (C) 2009 Frederic Weisbecker <fweisbec@gmail.com> 19 * 20 * Authors: Alan Stern <stern@rowland.harvard.edu> 21 * K.Prasad <prasad@linux.vnet.ibm.com> 22 * Frederic Weisbecker <fweisbec@gmail.com> 23 */ 24 25 /* 26 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility, 27 * using the CPU's debug registers. 28 */ 29 30 #include <linux/perf_event.h> 31 #include <linux/hw_breakpoint.h> 32 #include <linux/irqflags.h> 33 #include <linux/notifier.h> 34 #include <linux/kallsyms.h> 35 #include <linux/kprobes.h> 36 #include <linux/percpu.h> 37 #include <linux/kdebug.h> 38 #include <linux/kernel.h> 39 #include <linux/module.h> 40 #include <linux/sched.h> 41 #include <linux/smp.h> 42 43 #include <asm/hw_breakpoint.h> 44 #include <asm/processor.h> 45 #include <asm/debugreg.h> 46 47 /* Per cpu debug control register value */ 48 DEFINE_PER_CPU(unsigned long, cpu_dr7); 49 EXPORT_PER_CPU_SYMBOL(cpu_dr7); 50 51 /* Per cpu debug address registers values */ 52 static DEFINE_PER_CPU(unsigned long, cpu_debugreg[HBP_NUM]); 53 54 /* 55 * Stores the breakpoints currently in use on each breakpoint address 56 * register for each cpus 57 */ 58 static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM]); 59 60 61 static inline unsigned long 62 __encode_dr7(int drnum, unsigned int len, unsigned int type) 63 { 64 unsigned long bp_info; 65 66 bp_info = (len | type) & 0xf; 67 bp_info <<= (DR_CONTROL_SHIFT + drnum * DR_CONTROL_SIZE); 68 bp_info |= (DR_GLOBAL_ENABLE << (drnum * DR_ENABLE_SIZE)); 69 70 return bp_info; 71 } 72 73 /* 74 * Encode the length, type, Exact, and Enable bits for a particular breakpoint 75 * as stored in debug register 7. 76 */ 77 unsigned long encode_dr7(int drnum, unsigned int len, unsigned int type) 78 { 79 return __encode_dr7(drnum, len, type) | DR_GLOBAL_SLOWDOWN; 80 } 81 82 /* 83 * Decode the length and type bits for a particular breakpoint as 84 * stored in debug register 7. Return the "enabled" status. 85 */ 86 int decode_dr7(unsigned long dr7, int bpnum, unsigned *len, unsigned *type) 87 { 88 int bp_info = dr7 >> (DR_CONTROL_SHIFT + bpnum * DR_CONTROL_SIZE); 89 90 *len = (bp_info & 0xc) | 0x40; 91 *type = (bp_info & 0x3) | 0x80; 92 93 return (dr7 >> (bpnum * DR_ENABLE_SIZE)) & 0x3; 94 } 95 96 /* 97 * Install a perf counter breakpoint. 98 * 99 * We seek a free debug address register and use it for this 100 * breakpoint. Eventually we enable it in the debug control register. 101 * 102 * Atomic: we hold the counter->ctx->lock and we only handle variables 103 * and registers local to this cpu. 104 */ 105 int arch_install_hw_breakpoint(struct perf_event *bp) 106 { 107 struct arch_hw_breakpoint *info = counter_arch_bp(bp); 108 unsigned long *dr7; 109 int i; 110 111 for (i = 0; i < HBP_NUM; i++) { 112 struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]); 113 114 if (!*slot) { 115 *slot = bp; 116 break; 117 } 118 } 119 120 if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot")) 121 return -EBUSY; 122 123 set_debugreg(info->address, i); 124 __this_cpu_write(cpu_debugreg[i], info->address); 125 126 dr7 = this_cpu_ptr(&cpu_dr7); 127 *dr7 |= encode_dr7(i, info->len, info->type); 128 129 set_debugreg(*dr7, 7); 130 if (info->mask) 131 set_dr_addr_mask(info->mask, i); 132 133 return 0; 134 } 135 136 /* 137 * Uninstall the breakpoint contained in the given counter. 138 * 139 * First we search the debug address register it uses and then we disable 140 * it. 141 * 142 * Atomic: we hold the counter->ctx->lock and we only handle variables 143 * and registers local to this cpu. 144 */ 145 void arch_uninstall_hw_breakpoint(struct perf_event *bp) 146 { 147 struct arch_hw_breakpoint *info = counter_arch_bp(bp); 148 unsigned long *dr7; 149 int i; 150 151 for (i = 0; i < HBP_NUM; i++) { 152 struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]); 153 154 if (*slot == bp) { 155 *slot = NULL; 156 break; 157 } 158 } 159 160 if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot")) 161 return; 162 163 dr7 = this_cpu_ptr(&cpu_dr7); 164 *dr7 &= ~__encode_dr7(i, info->len, info->type); 165 166 set_debugreg(*dr7, 7); 167 if (info->mask) 168 set_dr_addr_mask(0, i); 169 } 170 171 /* 172 * Check for virtual address in kernel space. 173 */ 174 int arch_check_bp_in_kernelspace(struct perf_event *bp) 175 { 176 unsigned int len; 177 unsigned long va; 178 struct arch_hw_breakpoint *info = counter_arch_bp(bp); 179 180 va = info->address; 181 len = bp->attr.bp_len; 182 183 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE); 184 } 185 186 int arch_bp_generic_fields(int x86_len, int x86_type, 187 int *gen_len, int *gen_type) 188 { 189 /* Type */ 190 switch (x86_type) { 191 case X86_BREAKPOINT_EXECUTE: 192 if (x86_len != X86_BREAKPOINT_LEN_X) 193 return -EINVAL; 194 195 *gen_type = HW_BREAKPOINT_X; 196 *gen_len = sizeof(long); 197 return 0; 198 case X86_BREAKPOINT_WRITE: 199 *gen_type = HW_BREAKPOINT_W; 200 break; 201 case X86_BREAKPOINT_RW: 202 *gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R; 203 break; 204 default: 205 return -EINVAL; 206 } 207 208 /* Len */ 209 switch (x86_len) { 210 case X86_BREAKPOINT_LEN_1: 211 *gen_len = HW_BREAKPOINT_LEN_1; 212 break; 213 case X86_BREAKPOINT_LEN_2: 214 *gen_len = HW_BREAKPOINT_LEN_2; 215 break; 216 case X86_BREAKPOINT_LEN_4: 217 *gen_len = HW_BREAKPOINT_LEN_4; 218 break; 219 #ifdef CONFIG_X86_64 220 case X86_BREAKPOINT_LEN_8: 221 *gen_len = HW_BREAKPOINT_LEN_8; 222 break; 223 #endif 224 default: 225 return -EINVAL; 226 } 227 228 return 0; 229 } 230 231 232 static int arch_build_bp_info(struct perf_event *bp) 233 { 234 struct arch_hw_breakpoint *info = counter_arch_bp(bp); 235 236 info->address = bp->attr.bp_addr; 237 238 /* Type */ 239 switch (bp->attr.bp_type) { 240 case HW_BREAKPOINT_W: 241 info->type = X86_BREAKPOINT_WRITE; 242 break; 243 case HW_BREAKPOINT_W | HW_BREAKPOINT_R: 244 info->type = X86_BREAKPOINT_RW; 245 break; 246 case HW_BREAKPOINT_X: 247 /* 248 * We don't allow kernel breakpoints in places that are not 249 * acceptable for kprobes. On non-kprobes kernels, we don't 250 * allow kernel breakpoints at all. 251 */ 252 if (bp->attr.bp_addr >= TASK_SIZE_MAX) { 253 #ifdef CONFIG_KPROBES 254 if (within_kprobe_blacklist(bp->attr.bp_addr)) 255 return -EINVAL; 256 #else 257 return -EINVAL; 258 #endif 259 } 260 261 info->type = X86_BREAKPOINT_EXECUTE; 262 /* 263 * x86 inst breakpoints need to have a specific undefined len. 264 * But we still need to check userspace is not trying to setup 265 * an unsupported length, to get a range breakpoint for example. 266 */ 267 if (bp->attr.bp_len == sizeof(long)) { 268 info->len = X86_BREAKPOINT_LEN_X; 269 return 0; 270 } 271 default: 272 return -EINVAL; 273 } 274 275 /* Len */ 276 info->mask = 0; 277 278 switch (bp->attr.bp_len) { 279 case HW_BREAKPOINT_LEN_1: 280 info->len = X86_BREAKPOINT_LEN_1; 281 break; 282 case HW_BREAKPOINT_LEN_2: 283 info->len = X86_BREAKPOINT_LEN_2; 284 break; 285 case HW_BREAKPOINT_LEN_4: 286 info->len = X86_BREAKPOINT_LEN_4; 287 break; 288 #ifdef CONFIG_X86_64 289 case HW_BREAKPOINT_LEN_8: 290 info->len = X86_BREAKPOINT_LEN_8; 291 break; 292 #endif 293 default: 294 if (!is_power_of_2(bp->attr.bp_len)) 295 return -EINVAL; 296 if (!cpu_has_bpext) 297 return -EOPNOTSUPP; 298 info->mask = bp->attr.bp_len - 1; 299 info->len = X86_BREAKPOINT_LEN_1; 300 } 301 302 return 0; 303 } 304 305 /* 306 * Validate the arch-specific HW Breakpoint register settings 307 */ 308 int arch_validate_hwbkpt_settings(struct perf_event *bp) 309 { 310 struct arch_hw_breakpoint *info = counter_arch_bp(bp); 311 unsigned int align; 312 int ret; 313 314 315 ret = arch_build_bp_info(bp); 316 if (ret) 317 return ret; 318 319 switch (info->len) { 320 case X86_BREAKPOINT_LEN_1: 321 align = 0; 322 if (info->mask) 323 align = info->mask; 324 break; 325 case X86_BREAKPOINT_LEN_2: 326 align = 1; 327 break; 328 case X86_BREAKPOINT_LEN_4: 329 align = 3; 330 break; 331 #ifdef CONFIG_X86_64 332 case X86_BREAKPOINT_LEN_8: 333 align = 7; 334 break; 335 #endif 336 default: 337 WARN_ON_ONCE(1); 338 } 339 340 /* 341 * Check that the low-order bits of the address are appropriate 342 * for the alignment implied by len. 343 */ 344 if (info->address & align) 345 return -EINVAL; 346 347 return 0; 348 } 349 350 /* 351 * Dump the debug register contents to the user. 352 * We can't dump our per cpu values because it 353 * may contain cpu wide breakpoint, something that 354 * doesn't belong to the current task. 355 * 356 * TODO: include non-ptrace user breakpoints (perf) 357 */ 358 void aout_dump_debugregs(struct user *dump) 359 { 360 int i; 361 int dr7 = 0; 362 struct perf_event *bp; 363 struct arch_hw_breakpoint *info; 364 struct thread_struct *thread = ¤t->thread; 365 366 for (i = 0; i < HBP_NUM; i++) { 367 bp = thread->ptrace_bps[i]; 368 369 if (bp && !bp->attr.disabled) { 370 dump->u_debugreg[i] = bp->attr.bp_addr; 371 info = counter_arch_bp(bp); 372 dr7 |= encode_dr7(i, info->len, info->type); 373 } else { 374 dump->u_debugreg[i] = 0; 375 } 376 } 377 378 dump->u_debugreg[4] = 0; 379 dump->u_debugreg[5] = 0; 380 dump->u_debugreg[6] = current->thread.debugreg6; 381 382 dump->u_debugreg[7] = dr7; 383 } 384 EXPORT_SYMBOL_GPL(aout_dump_debugregs); 385 386 /* 387 * Release the user breakpoints used by ptrace 388 */ 389 void flush_ptrace_hw_breakpoint(struct task_struct *tsk) 390 { 391 int i; 392 struct thread_struct *t = &tsk->thread; 393 394 for (i = 0; i < HBP_NUM; i++) { 395 unregister_hw_breakpoint(t->ptrace_bps[i]); 396 t->ptrace_bps[i] = NULL; 397 } 398 399 t->debugreg6 = 0; 400 t->ptrace_dr7 = 0; 401 } 402 403 void hw_breakpoint_restore(void) 404 { 405 set_debugreg(__this_cpu_read(cpu_debugreg[0]), 0); 406 set_debugreg(__this_cpu_read(cpu_debugreg[1]), 1); 407 set_debugreg(__this_cpu_read(cpu_debugreg[2]), 2); 408 set_debugreg(__this_cpu_read(cpu_debugreg[3]), 3); 409 set_debugreg(current->thread.debugreg6, 6); 410 set_debugreg(__this_cpu_read(cpu_dr7), 7); 411 } 412 EXPORT_SYMBOL_GPL(hw_breakpoint_restore); 413 414 /* 415 * Handle debug exception notifications. 416 * 417 * Return value is either NOTIFY_STOP or NOTIFY_DONE as explained below. 418 * 419 * NOTIFY_DONE returned if one of the following conditions is true. 420 * i) When the causative address is from user-space and the exception 421 * is a valid one, i.e. not triggered as a result of lazy debug register 422 * switching 423 * ii) When there are more bits than trap<n> set in DR6 register (such 424 * as BD, BS or BT) indicating that more than one debug condition is 425 * met and requires some more action in do_debug(). 426 * 427 * NOTIFY_STOP returned for all other cases 428 * 429 */ 430 static int hw_breakpoint_handler(struct die_args *args) 431 { 432 int i, cpu, rc = NOTIFY_STOP; 433 struct perf_event *bp; 434 unsigned long dr7, dr6; 435 unsigned long *dr6_p; 436 437 /* The DR6 value is pointed by args->err */ 438 dr6_p = (unsigned long *)ERR_PTR(args->err); 439 dr6 = *dr6_p; 440 441 /* If it's a single step, TRAP bits are random */ 442 if (dr6 & DR_STEP) 443 return NOTIFY_DONE; 444 445 /* Do an early return if no trap bits are set in DR6 */ 446 if ((dr6 & DR_TRAP_BITS) == 0) 447 return NOTIFY_DONE; 448 449 get_debugreg(dr7, 7); 450 /* Disable breakpoints during exception handling */ 451 set_debugreg(0UL, 7); 452 /* 453 * Assert that local interrupts are disabled 454 * Reset the DRn bits in the virtualized register value. 455 * The ptrace trigger routine will add in whatever is needed. 456 */ 457 current->thread.debugreg6 &= ~DR_TRAP_BITS; 458 cpu = get_cpu(); 459 460 /* Handle all the breakpoints that were triggered */ 461 for (i = 0; i < HBP_NUM; ++i) { 462 if (likely(!(dr6 & (DR_TRAP0 << i)))) 463 continue; 464 465 /* 466 * The counter may be concurrently released but that can only 467 * occur from a call_rcu() path. We can then safely fetch 468 * the breakpoint, use its callback, touch its counter 469 * while we are in an rcu_read_lock() path. 470 */ 471 rcu_read_lock(); 472 473 bp = per_cpu(bp_per_reg[i], cpu); 474 /* 475 * Reset the 'i'th TRAP bit in dr6 to denote completion of 476 * exception handling 477 */ 478 (*dr6_p) &= ~(DR_TRAP0 << i); 479 /* 480 * bp can be NULL due to lazy debug register switching 481 * or due to concurrent perf counter removing. 482 */ 483 if (!bp) { 484 rcu_read_unlock(); 485 break; 486 } 487 488 perf_bp_event(bp, args->regs); 489 490 /* 491 * Set up resume flag to avoid breakpoint recursion when 492 * returning back to origin. 493 */ 494 if (bp->hw.info.type == X86_BREAKPOINT_EXECUTE) 495 args->regs->flags |= X86_EFLAGS_RF; 496 497 rcu_read_unlock(); 498 } 499 /* 500 * Further processing in do_debug() is needed for a) user-space 501 * breakpoints (to generate signals) and b) when the system has 502 * taken exception due to multiple causes 503 */ 504 if ((current->thread.debugreg6 & DR_TRAP_BITS) || 505 (dr6 & (~DR_TRAP_BITS))) 506 rc = NOTIFY_DONE; 507 508 set_debugreg(dr7, 7); 509 put_cpu(); 510 511 return rc; 512 } 513 514 /* 515 * Handle debug exception notifications. 516 */ 517 int hw_breakpoint_exceptions_notify( 518 struct notifier_block *unused, unsigned long val, void *data) 519 { 520 if (val != DIE_DEBUG) 521 return NOTIFY_DONE; 522 523 return hw_breakpoint_handler(data); 524 } 525 526 void hw_breakpoint_pmu_read(struct perf_event *bp) 527 { 528 /* TODO */ 529 } 530