1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/clockchips.h> 3 #include <linux/interrupt.h> 4 #include <linux/export.h> 5 #include <linux/delay.h> 6 #include <linux/hpet.h> 7 #include <linux/cpu.h> 8 #include <linux/irq.h> 9 10 #include <asm/irq_remapping.h> 11 #include <asm/hpet.h> 12 #include <asm/time.h> 13 14 #undef pr_fmt 15 #define pr_fmt(fmt) "hpet: " fmt 16 17 enum hpet_mode { 18 HPET_MODE_UNUSED, 19 HPET_MODE_LEGACY, 20 HPET_MODE_CLOCKEVT, 21 HPET_MODE_DEVICE, 22 }; 23 24 struct hpet_channel { 25 struct clock_event_device evt; 26 unsigned int num; 27 unsigned int cpu; 28 unsigned int irq; 29 unsigned int in_use; 30 enum hpet_mode mode; 31 unsigned int boot_cfg; 32 char name[10]; 33 }; 34 35 struct hpet_base { 36 unsigned int nr_channels; 37 unsigned int nr_clockevents; 38 unsigned int boot_cfg; 39 struct hpet_channel *channels; 40 }; 41 42 #define HPET_MASK CLOCKSOURCE_MASK(32) 43 44 #define HPET_MIN_CYCLES 128 45 #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1)) 46 47 /* 48 * HPET address is set in acpi/boot.c, when an ACPI entry exists 49 */ 50 unsigned long hpet_address; 51 u8 hpet_blockid; /* OS timer block num */ 52 bool hpet_msi_disable; 53 54 #ifdef CONFIG_GENERIC_MSI_IRQ 55 static DEFINE_PER_CPU(struct hpet_channel *, cpu_hpet_channel); 56 static struct irq_domain *hpet_domain; 57 #endif 58 59 static void __iomem *hpet_virt_address; 60 61 static struct hpet_base hpet_base; 62 63 static bool hpet_legacy_int_enabled; 64 static unsigned long hpet_freq; 65 66 bool boot_hpet_disable; 67 bool hpet_force_user; 68 static bool hpet_verbose; 69 70 static inline 71 struct hpet_channel *clockevent_to_channel(struct clock_event_device *evt) 72 { 73 return container_of(evt, struct hpet_channel, evt); 74 } 75 76 inline unsigned int hpet_readl(unsigned int a) 77 { 78 return readl(hpet_virt_address + a); 79 } 80 81 static inline void hpet_writel(unsigned int d, unsigned int a) 82 { 83 writel(d, hpet_virt_address + a); 84 } 85 86 static inline void hpet_set_mapping(void) 87 { 88 hpet_virt_address = ioremap(hpet_address, HPET_MMAP_SIZE); 89 } 90 91 static inline void hpet_clear_mapping(void) 92 { 93 iounmap(hpet_virt_address); 94 hpet_virt_address = NULL; 95 } 96 97 /* 98 * HPET command line enable / disable 99 */ 100 static int __init hpet_setup(char *str) 101 { 102 while (str) { 103 char *next = strchr(str, ','); 104 105 if (next) 106 *next++ = 0; 107 if (!strncmp("disable", str, 7)) 108 boot_hpet_disable = true; 109 if (!strncmp("force", str, 5)) 110 hpet_force_user = true; 111 if (!strncmp("verbose", str, 7)) 112 hpet_verbose = true; 113 str = next; 114 } 115 return 1; 116 } 117 __setup("hpet=", hpet_setup); 118 119 static int __init disable_hpet(char *str) 120 { 121 boot_hpet_disable = true; 122 return 1; 123 } 124 __setup("nohpet", disable_hpet); 125 126 static inline int is_hpet_capable(void) 127 { 128 return !boot_hpet_disable && hpet_address; 129 } 130 131 /** 132 * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled 133 */ 134 int is_hpet_enabled(void) 135 { 136 return is_hpet_capable() && hpet_legacy_int_enabled; 137 } 138 EXPORT_SYMBOL_GPL(is_hpet_enabled); 139 140 static void _hpet_print_config(const char *function, int line) 141 { 142 u32 i, id, period, cfg, status, channels, l, h; 143 144 pr_info("%s(%d):\n", function, line); 145 146 id = hpet_readl(HPET_ID); 147 period = hpet_readl(HPET_PERIOD); 148 pr_info("ID: 0x%x, PERIOD: 0x%x\n", id, period); 149 150 cfg = hpet_readl(HPET_CFG); 151 status = hpet_readl(HPET_STATUS); 152 pr_info("CFG: 0x%x, STATUS: 0x%x\n", cfg, status); 153 154 l = hpet_readl(HPET_COUNTER); 155 h = hpet_readl(HPET_COUNTER+4); 156 pr_info("COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); 157 158 channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 159 160 for (i = 0; i < channels; i++) { 161 l = hpet_readl(HPET_Tn_CFG(i)); 162 h = hpet_readl(HPET_Tn_CFG(i)+4); 163 pr_info("T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", i, l, h); 164 165 l = hpet_readl(HPET_Tn_CMP(i)); 166 h = hpet_readl(HPET_Tn_CMP(i)+4); 167 pr_info("T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", i, l, h); 168 169 l = hpet_readl(HPET_Tn_ROUTE(i)); 170 h = hpet_readl(HPET_Tn_ROUTE(i)+4); 171 pr_info("T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", i, l, h); 172 } 173 } 174 175 #define hpet_print_config() \ 176 do { \ 177 if (hpet_verbose) \ 178 _hpet_print_config(__func__, __LINE__); \ 179 } while (0) 180 181 /* 182 * When the HPET driver (/dev/hpet) is enabled, we need to reserve 183 * timer 0 and timer 1 in case of RTC emulation. 184 */ 185 #ifdef CONFIG_HPET 186 187 static void __init hpet_reserve_platform_timers(void) 188 { 189 struct hpet_data hd; 190 unsigned int i; 191 192 memset(&hd, 0, sizeof(hd)); 193 hd.hd_phys_address = hpet_address; 194 hd.hd_address = hpet_virt_address; 195 hd.hd_nirqs = hpet_base.nr_channels; 196 197 /* 198 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 199 * is wrong for i8259!) not the output IRQ. Many BIOS writers 200 * don't bother configuring *any* comparator interrupts. 201 */ 202 hd.hd_irq[0] = HPET_LEGACY_8254; 203 hd.hd_irq[1] = HPET_LEGACY_RTC; 204 205 for (i = 0; i < hpet_base.nr_channels; i++) { 206 struct hpet_channel *hc = hpet_base.channels + i; 207 208 if (i >= 2) 209 hd.hd_irq[i] = hc->irq; 210 211 switch (hc->mode) { 212 case HPET_MODE_UNUSED: 213 case HPET_MODE_DEVICE: 214 hc->mode = HPET_MODE_DEVICE; 215 break; 216 case HPET_MODE_CLOCKEVT: 217 case HPET_MODE_LEGACY: 218 hpet_reserve_timer(&hd, hc->num); 219 break; 220 } 221 } 222 223 hpet_alloc(&hd); 224 } 225 226 static void __init hpet_select_device_channel(void) 227 { 228 int i; 229 230 for (i = 0; i < hpet_base.nr_channels; i++) { 231 struct hpet_channel *hc = hpet_base.channels + i; 232 233 /* Associate the first unused channel to /dev/hpet */ 234 if (hc->mode == HPET_MODE_UNUSED) { 235 hc->mode = HPET_MODE_DEVICE; 236 return; 237 } 238 } 239 } 240 241 #else 242 static inline void hpet_reserve_platform_timers(void) { } 243 static inline void hpet_select_device_channel(void) {} 244 #endif 245 246 /* Common HPET functions */ 247 static void hpet_stop_counter(void) 248 { 249 u32 cfg = hpet_readl(HPET_CFG); 250 251 cfg &= ~HPET_CFG_ENABLE; 252 hpet_writel(cfg, HPET_CFG); 253 } 254 255 static void hpet_reset_counter(void) 256 { 257 hpet_writel(0, HPET_COUNTER); 258 hpet_writel(0, HPET_COUNTER + 4); 259 } 260 261 static void hpet_start_counter(void) 262 { 263 unsigned int cfg = hpet_readl(HPET_CFG); 264 265 cfg |= HPET_CFG_ENABLE; 266 hpet_writel(cfg, HPET_CFG); 267 } 268 269 static void hpet_restart_counter(void) 270 { 271 hpet_stop_counter(); 272 hpet_reset_counter(); 273 hpet_start_counter(); 274 } 275 276 static void hpet_resume_device(void) 277 { 278 force_hpet_resume(); 279 } 280 281 static void hpet_resume_counter(struct clocksource *cs) 282 { 283 hpet_resume_device(); 284 hpet_restart_counter(); 285 } 286 287 static void hpet_enable_legacy_int(void) 288 { 289 unsigned int cfg = hpet_readl(HPET_CFG); 290 291 cfg |= HPET_CFG_LEGACY; 292 hpet_writel(cfg, HPET_CFG); 293 hpet_legacy_int_enabled = true; 294 } 295 296 static int hpet_clkevt_set_state_periodic(struct clock_event_device *evt) 297 { 298 unsigned int channel = clockevent_to_channel(evt)->num; 299 unsigned int cfg, cmp, now; 300 uint64_t delta; 301 302 hpet_stop_counter(); 303 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult; 304 delta >>= evt->shift; 305 now = hpet_readl(HPET_COUNTER); 306 cmp = now + (unsigned int)delta; 307 cfg = hpet_readl(HPET_Tn_CFG(channel)); 308 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL | 309 HPET_TN_32BIT; 310 hpet_writel(cfg, HPET_Tn_CFG(channel)); 311 hpet_writel(cmp, HPET_Tn_CMP(channel)); 312 udelay(1); 313 /* 314 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL 315 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL 316 * bit is automatically cleared after the first write. 317 * (See AMD-8111 HyperTransport I/O Hub Data Sheet, 318 * Publication # 24674) 319 */ 320 hpet_writel((unsigned int)delta, HPET_Tn_CMP(channel)); 321 hpet_start_counter(); 322 hpet_print_config(); 323 324 return 0; 325 } 326 327 static int hpet_clkevt_set_state_oneshot(struct clock_event_device *evt) 328 { 329 unsigned int channel = clockevent_to_channel(evt)->num; 330 unsigned int cfg; 331 332 cfg = hpet_readl(HPET_Tn_CFG(channel)); 333 cfg &= ~HPET_TN_PERIODIC; 334 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 335 hpet_writel(cfg, HPET_Tn_CFG(channel)); 336 337 return 0; 338 } 339 340 static int hpet_clkevt_set_state_shutdown(struct clock_event_device *evt) 341 { 342 unsigned int channel = clockevent_to_channel(evt)->num; 343 unsigned int cfg; 344 345 cfg = hpet_readl(HPET_Tn_CFG(channel)); 346 cfg &= ~HPET_TN_ENABLE; 347 hpet_writel(cfg, HPET_Tn_CFG(channel)); 348 349 return 0; 350 } 351 352 static int hpet_clkevt_legacy_resume(struct clock_event_device *evt) 353 { 354 hpet_enable_legacy_int(); 355 hpet_print_config(); 356 return 0; 357 } 358 359 static int 360 hpet_clkevt_set_next_event(unsigned long delta, struct clock_event_device *evt) 361 { 362 unsigned int channel = clockevent_to_channel(evt)->num; 363 u32 cnt; 364 s32 res; 365 366 cnt = hpet_readl(HPET_COUNTER); 367 cnt += (u32) delta; 368 hpet_writel(cnt, HPET_Tn_CMP(channel)); 369 370 /* 371 * HPETs are a complete disaster. The compare register is 372 * based on a equal comparison and neither provides a less 373 * than or equal functionality (which would require to take 374 * the wraparound into account) nor a simple count down event 375 * mode. Further the write to the comparator register is 376 * delayed internally up to two HPET clock cycles in certain 377 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even 378 * longer delays. We worked around that by reading back the 379 * compare register, but that required another workaround for 380 * ICH9,10 chips where the first readout after write can 381 * return the old stale value. We already had a minimum 382 * programming delta of 5us enforced, but a NMI or SMI hitting 383 * between the counter readout and the comparator write can 384 * move us behind that point easily. Now instead of reading 385 * the compare register back several times, we make the ETIME 386 * decision based on the following: Return ETIME if the 387 * counter value after the write is less than HPET_MIN_CYCLES 388 * away from the event or if the counter is already ahead of 389 * the event. The minimum programming delta for the generic 390 * clockevents code is set to 1.5 * HPET_MIN_CYCLES. 391 */ 392 res = (s32)(cnt - hpet_readl(HPET_COUNTER)); 393 394 return res < HPET_MIN_CYCLES ? -ETIME : 0; 395 } 396 397 static void hpet_init_clockevent(struct hpet_channel *hc, unsigned int rating) 398 { 399 struct clock_event_device *evt = &hc->evt; 400 401 evt->rating = rating; 402 evt->irq = hc->irq; 403 evt->name = hc->name; 404 evt->cpumask = cpumask_of(hc->cpu); 405 evt->set_state_oneshot = hpet_clkevt_set_state_oneshot; 406 evt->set_next_event = hpet_clkevt_set_next_event; 407 evt->set_state_shutdown = hpet_clkevt_set_state_shutdown; 408 409 evt->features = CLOCK_EVT_FEAT_ONESHOT; 410 if (hc->boot_cfg & HPET_TN_PERIODIC) { 411 evt->features |= CLOCK_EVT_FEAT_PERIODIC; 412 evt->set_state_periodic = hpet_clkevt_set_state_periodic; 413 } 414 } 415 416 static void __init hpet_legacy_clockevent_register(struct hpet_channel *hc) 417 { 418 /* 419 * Start HPET with the boot CPU's cpumask and make it global after 420 * the IO_APIC has been initialized. 421 */ 422 hc->cpu = boot_cpu_data.cpu_index; 423 strncpy(hc->name, "hpet", sizeof(hc->name)); 424 hpet_init_clockevent(hc, 50); 425 426 hc->evt.tick_resume = hpet_clkevt_legacy_resume; 427 428 /* 429 * Legacy horrors and sins from the past. HPET used periodic mode 430 * unconditionally forever on the legacy channel 0. Removing the 431 * below hack and using the conditional in hpet_init_clockevent() 432 * makes at least Qemu and one hardware machine fail to boot. 433 * There are two issues which cause the boot failure: 434 * 435 * #1 After the timer delivery test in IOAPIC and the IOAPIC setup 436 * the next interrupt is not delivered despite the HPET channel 437 * being programmed correctly. Reprogramming the HPET after 438 * switching to IOAPIC makes it work again. After fixing this, 439 * the next issue surfaces: 440 * 441 * #2 Due to the unconditional periodic mode availability the Local 442 * APIC timer calibration can hijack the global clockevents 443 * event handler without causing damage. Using oneshot at this 444 * stage makes if hang because the HPET does not get 445 * reprogrammed due to the handler hijacking. Duh, stupid me! 446 * 447 * Both issues require major surgery and especially the kick HPET 448 * again after enabling IOAPIC results in really nasty hackery. 449 * This 'assume periodic works' magic has survived since HPET 450 * support got added, so it's questionable whether this should be 451 * fixed. Both Qemu and the failing hardware machine support 452 * periodic mode despite the fact that both don't advertise it in 453 * the configuration register and both need that extra kick after 454 * switching to IOAPIC. Seems to be a feature... 455 */ 456 hc->evt.features |= CLOCK_EVT_FEAT_PERIODIC; 457 hc->evt.set_state_periodic = hpet_clkevt_set_state_periodic; 458 459 /* Start HPET legacy interrupts */ 460 hpet_enable_legacy_int(); 461 462 clockevents_config_and_register(&hc->evt, hpet_freq, 463 HPET_MIN_PROG_DELTA, 0x7FFFFFFF); 464 global_clock_event = &hc->evt; 465 pr_debug("Clockevent registered\n"); 466 } 467 468 /* 469 * HPET MSI Support 470 */ 471 #ifdef CONFIG_GENERIC_MSI_IRQ 472 static void hpet_msi_unmask(struct irq_data *data) 473 { 474 struct hpet_channel *hc = irq_data_get_irq_handler_data(data); 475 unsigned int cfg; 476 477 cfg = hpet_readl(HPET_Tn_CFG(hc->num)); 478 cfg |= HPET_TN_ENABLE | HPET_TN_FSB; 479 hpet_writel(cfg, HPET_Tn_CFG(hc->num)); 480 } 481 482 static void hpet_msi_mask(struct irq_data *data) 483 { 484 struct hpet_channel *hc = irq_data_get_irq_handler_data(data); 485 unsigned int cfg; 486 487 cfg = hpet_readl(HPET_Tn_CFG(hc->num)); 488 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB); 489 hpet_writel(cfg, HPET_Tn_CFG(hc->num)); 490 } 491 492 static void hpet_msi_write(struct hpet_channel *hc, struct msi_msg *msg) 493 { 494 hpet_writel(msg->data, HPET_Tn_ROUTE(hc->num)); 495 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hc->num) + 4); 496 } 497 498 static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg) 499 { 500 hpet_msi_write(irq_data_get_irq_handler_data(data), msg); 501 } 502 503 static struct irq_chip hpet_msi_controller __ro_after_init = { 504 .name = "HPET-MSI", 505 .irq_unmask = hpet_msi_unmask, 506 .irq_mask = hpet_msi_mask, 507 .irq_ack = irq_chip_ack_parent, 508 .irq_set_affinity = msi_domain_set_affinity, 509 .irq_retrigger = irq_chip_retrigger_hierarchy, 510 .irq_write_msi_msg = hpet_msi_write_msg, 511 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_AFFINITY_PRE_STARTUP, 512 }; 513 514 static int hpet_msi_init(struct irq_domain *domain, 515 struct msi_domain_info *info, unsigned int virq, 516 irq_hw_number_t hwirq, msi_alloc_info_t *arg) 517 { 518 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); 519 irq_domain_set_info(domain, virq, arg->hwirq, info->chip, NULL, 520 handle_edge_irq, arg->data, "edge"); 521 522 return 0; 523 } 524 525 static void hpet_msi_free(struct irq_domain *domain, 526 struct msi_domain_info *info, unsigned int virq) 527 { 528 irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT); 529 } 530 531 static struct msi_domain_ops hpet_msi_domain_ops = { 532 .msi_init = hpet_msi_init, 533 .msi_free = hpet_msi_free, 534 }; 535 536 static struct msi_domain_info hpet_msi_domain_info = { 537 .ops = &hpet_msi_domain_ops, 538 .chip = &hpet_msi_controller, 539 .flags = MSI_FLAG_USE_DEF_DOM_OPS, 540 }; 541 542 static struct irq_domain *hpet_create_irq_domain(int hpet_id) 543 { 544 struct msi_domain_info *domain_info; 545 struct irq_domain *parent, *d; 546 struct fwnode_handle *fn; 547 struct irq_fwspec fwspec; 548 549 if (x86_vector_domain == NULL) 550 return NULL; 551 552 domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL); 553 if (!domain_info) 554 return NULL; 555 556 *domain_info = hpet_msi_domain_info; 557 domain_info->data = (void *)(long)hpet_id; 558 559 fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name, 560 hpet_id); 561 if (!fn) { 562 kfree(domain_info); 563 return NULL; 564 } 565 566 fwspec.fwnode = fn; 567 fwspec.param_count = 1; 568 fwspec.param[0] = hpet_id; 569 570 parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_ANY); 571 if (!parent) { 572 irq_domain_free_fwnode(fn); 573 kfree(domain_info); 574 return NULL; 575 } 576 if (parent != x86_vector_domain) 577 hpet_msi_controller.name = "IR-HPET-MSI"; 578 579 d = msi_create_irq_domain(fn, domain_info, parent); 580 if (!d) { 581 irq_domain_free_fwnode(fn); 582 kfree(domain_info); 583 } 584 return d; 585 } 586 587 static inline int hpet_dev_id(struct irq_domain *domain) 588 { 589 struct msi_domain_info *info = msi_get_domain_info(domain); 590 591 return (int)(long)info->data; 592 } 593 594 static int hpet_assign_irq(struct irq_domain *domain, struct hpet_channel *hc, 595 int dev_num) 596 { 597 struct irq_alloc_info info; 598 599 init_irq_alloc_info(&info, NULL); 600 info.type = X86_IRQ_ALLOC_TYPE_HPET; 601 info.data = hc; 602 info.devid = hpet_dev_id(domain); 603 info.hwirq = dev_num; 604 605 return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info); 606 } 607 608 static int hpet_clkevt_msi_resume(struct clock_event_device *evt) 609 { 610 struct hpet_channel *hc = clockevent_to_channel(evt); 611 struct irq_data *data = irq_get_irq_data(hc->irq); 612 struct msi_msg msg; 613 614 /* Restore the MSI msg and unmask the interrupt */ 615 irq_chip_compose_msi_msg(data, &msg); 616 hpet_msi_write(hc, &msg); 617 hpet_msi_unmask(data); 618 return 0; 619 } 620 621 static irqreturn_t hpet_msi_interrupt_handler(int irq, void *data) 622 { 623 struct hpet_channel *hc = data; 624 struct clock_event_device *evt = &hc->evt; 625 626 if (!evt->event_handler) { 627 pr_info("Spurious interrupt HPET channel %d\n", hc->num); 628 return IRQ_HANDLED; 629 } 630 631 evt->event_handler(evt); 632 return IRQ_HANDLED; 633 } 634 635 static int hpet_setup_msi_irq(struct hpet_channel *hc) 636 { 637 if (request_irq(hc->irq, hpet_msi_interrupt_handler, 638 IRQF_TIMER | IRQF_NOBALANCING, 639 hc->name, hc)) 640 return -1; 641 642 disable_irq(hc->irq); 643 irq_set_affinity(hc->irq, cpumask_of(hc->cpu)); 644 enable_irq(hc->irq); 645 646 pr_debug("%s irq %u for MSI\n", hc->name, hc->irq); 647 648 return 0; 649 } 650 651 /* Invoked from the hotplug callback on @cpu */ 652 static void init_one_hpet_msi_clockevent(struct hpet_channel *hc, int cpu) 653 { 654 struct clock_event_device *evt = &hc->evt; 655 656 hc->cpu = cpu; 657 per_cpu(cpu_hpet_channel, cpu) = hc; 658 hpet_setup_msi_irq(hc); 659 660 hpet_init_clockevent(hc, 110); 661 evt->tick_resume = hpet_clkevt_msi_resume; 662 663 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA, 664 0x7FFFFFFF); 665 } 666 667 static struct hpet_channel *hpet_get_unused_clockevent(void) 668 { 669 int i; 670 671 for (i = 0; i < hpet_base.nr_channels; i++) { 672 struct hpet_channel *hc = hpet_base.channels + i; 673 674 if (hc->mode != HPET_MODE_CLOCKEVT || hc->in_use) 675 continue; 676 hc->in_use = 1; 677 return hc; 678 } 679 return NULL; 680 } 681 682 static int hpet_cpuhp_online(unsigned int cpu) 683 { 684 struct hpet_channel *hc = hpet_get_unused_clockevent(); 685 686 if (hc) 687 init_one_hpet_msi_clockevent(hc, cpu); 688 return 0; 689 } 690 691 static int hpet_cpuhp_dead(unsigned int cpu) 692 { 693 struct hpet_channel *hc = per_cpu(cpu_hpet_channel, cpu); 694 695 if (!hc) 696 return 0; 697 free_irq(hc->irq, hc); 698 hc->in_use = 0; 699 per_cpu(cpu_hpet_channel, cpu) = NULL; 700 return 0; 701 } 702 703 static void __init hpet_select_clockevents(void) 704 { 705 unsigned int i; 706 707 hpet_base.nr_clockevents = 0; 708 709 /* No point if MSI is disabled or CPU has an Always Runing APIC Timer */ 710 if (hpet_msi_disable || boot_cpu_has(X86_FEATURE_ARAT)) 711 return; 712 713 hpet_print_config(); 714 715 hpet_domain = hpet_create_irq_domain(hpet_blockid); 716 if (!hpet_domain) 717 return; 718 719 for (i = 0; i < hpet_base.nr_channels; i++) { 720 struct hpet_channel *hc = hpet_base.channels + i; 721 int irq; 722 723 if (hc->mode != HPET_MODE_UNUSED) 724 continue; 725 726 /* Only consider HPET channel with MSI support */ 727 if (!(hc->boot_cfg & HPET_TN_FSB_CAP)) 728 continue; 729 730 sprintf(hc->name, "hpet%d", i); 731 732 irq = hpet_assign_irq(hpet_domain, hc, hc->num); 733 if (irq <= 0) 734 continue; 735 736 hc->irq = irq; 737 hc->mode = HPET_MODE_CLOCKEVT; 738 739 if (++hpet_base.nr_clockevents == num_possible_cpus()) 740 break; 741 } 742 743 pr_info("%d channels of %d reserved for per-cpu timers\n", 744 hpet_base.nr_channels, hpet_base.nr_clockevents); 745 } 746 747 #else 748 749 static inline void hpet_select_clockevents(void) { } 750 751 #define hpet_cpuhp_online NULL 752 #define hpet_cpuhp_dead NULL 753 754 #endif 755 756 /* 757 * Clock source related code 758 */ 759 #if defined(CONFIG_SMP) && defined(CONFIG_64BIT) 760 /* 761 * Reading the HPET counter is a very slow operation. If a large number of 762 * CPUs are trying to access the HPET counter simultaneously, it can cause 763 * massive delays and slow down system performance dramatically. This may 764 * happen when HPET is the default clock source instead of TSC. For a 765 * really large system with hundreds of CPUs, the slowdown may be so 766 * severe, that it can actually crash the system because of a NMI watchdog 767 * soft lockup, for example. 768 * 769 * If multiple CPUs are trying to access the HPET counter at the same time, 770 * we don't actually need to read the counter multiple times. Instead, the 771 * other CPUs can use the counter value read by the first CPU in the group. 772 * 773 * This special feature is only enabled on x86-64 systems. It is unlikely 774 * that 32-bit x86 systems will have enough CPUs to require this feature 775 * with its associated locking overhead. We also need 64-bit atomic read. 776 * 777 * The lock and the HPET value are stored together and can be read in a 778 * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t 779 * is 32 bits in size. 780 */ 781 union hpet_lock { 782 struct { 783 arch_spinlock_t lock; 784 u32 value; 785 }; 786 u64 lockval; 787 }; 788 789 static union hpet_lock hpet __cacheline_aligned = { 790 { .lock = __ARCH_SPIN_LOCK_UNLOCKED, }, 791 }; 792 793 static u64 read_hpet(struct clocksource *cs) 794 { 795 unsigned long flags; 796 union hpet_lock old, new; 797 798 BUILD_BUG_ON(sizeof(union hpet_lock) != 8); 799 800 /* 801 * Read HPET directly if in NMI. 802 */ 803 if (in_nmi()) 804 return (u64)hpet_readl(HPET_COUNTER); 805 806 /* 807 * Read the current state of the lock and HPET value atomically. 808 */ 809 old.lockval = READ_ONCE(hpet.lockval); 810 811 if (arch_spin_is_locked(&old.lock)) 812 goto contended; 813 814 local_irq_save(flags); 815 if (arch_spin_trylock(&hpet.lock)) { 816 new.value = hpet_readl(HPET_COUNTER); 817 /* 818 * Use WRITE_ONCE() to prevent store tearing. 819 */ 820 WRITE_ONCE(hpet.value, new.value); 821 arch_spin_unlock(&hpet.lock); 822 local_irq_restore(flags); 823 return (u64)new.value; 824 } 825 local_irq_restore(flags); 826 827 contended: 828 /* 829 * Contended case 830 * -------------- 831 * Wait until the HPET value change or the lock is free to indicate 832 * its value is up-to-date. 833 * 834 * It is possible that old.value has already contained the latest 835 * HPET value while the lock holder was in the process of releasing 836 * the lock. Checking for lock state change will enable us to return 837 * the value immediately instead of waiting for the next HPET reader 838 * to come along. 839 */ 840 do { 841 cpu_relax(); 842 new.lockval = READ_ONCE(hpet.lockval); 843 } while ((new.value == old.value) && arch_spin_is_locked(&new.lock)); 844 845 return (u64)new.value; 846 } 847 #else 848 /* 849 * For UP or 32-bit. 850 */ 851 static u64 read_hpet(struct clocksource *cs) 852 { 853 return (u64)hpet_readl(HPET_COUNTER); 854 } 855 #endif 856 857 static struct clocksource clocksource_hpet = { 858 .name = "hpet", 859 .rating = 250, 860 .read = read_hpet, 861 .mask = HPET_MASK, 862 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 863 .resume = hpet_resume_counter, 864 }; 865 866 /* 867 * AMD SB700 based systems with spread spectrum enabled use a SMM based 868 * HPET emulation to provide proper frequency setting. 869 * 870 * On such systems the SMM code is initialized with the first HPET register 871 * access and takes some time to complete. During this time the config 872 * register reads 0xffffffff. We check for max 1000 loops whether the 873 * config register reads a non-0xffffffff value to make sure that the 874 * HPET is up and running before we proceed any further. 875 * 876 * A counting loop is safe, as the HPET access takes thousands of CPU cycles. 877 * 878 * On non-SB700 based machines this check is only done once and has no 879 * side effects. 880 */ 881 static bool __init hpet_cfg_working(void) 882 { 883 int i; 884 885 for (i = 0; i < 1000; i++) { 886 if (hpet_readl(HPET_CFG) != 0xFFFFFFFF) 887 return true; 888 } 889 890 pr_warn("Config register invalid. Disabling HPET\n"); 891 return false; 892 } 893 894 static bool __init hpet_counting(void) 895 { 896 u64 start, now, t1; 897 898 hpet_restart_counter(); 899 900 t1 = hpet_readl(HPET_COUNTER); 901 start = rdtsc(); 902 903 /* 904 * We don't know the TSC frequency yet, but waiting for 905 * 200000 TSC cycles is safe: 906 * 4 GHz == 50us 907 * 1 GHz == 200us 908 */ 909 do { 910 if (t1 != hpet_readl(HPET_COUNTER)) 911 return true; 912 now = rdtsc(); 913 } while ((now - start) < 200000UL); 914 915 pr_warn("Counter not counting. HPET disabled\n"); 916 return false; 917 } 918 919 /** 920 * hpet_enable - Try to setup the HPET timer. Returns 1 on success. 921 */ 922 int __init hpet_enable(void) 923 { 924 u32 hpet_period, cfg, id, irq; 925 unsigned int i, channels; 926 struct hpet_channel *hc; 927 u64 freq; 928 929 if (!is_hpet_capable()) 930 return 0; 931 932 hpet_set_mapping(); 933 if (!hpet_virt_address) 934 return 0; 935 936 /* Validate that the config register is working */ 937 if (!hpet_cfg_working()) 938 goto out_nohpet; 939 940 /* 941 * Read the period and check for a sane value: 942 */ 943 hpet_period = hpet_readl(HPET_PERIOD); 944 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) 945 goto out_nohpet; 946 947 /* The period is a femtoseconds value. Convert it to a frequency. */ 948 freq = FSEC_PER_SEC; 949 do_div(freq, hpet_period); 950 hpet_freq = freq; 951 952 /* 953 * Read the HPET ID register to retrieve the IRQ routing 954 * information and the number of channels 955 */ 956 id = hpet_readl(HPET_ID); 957 hpet_print_config(); 958 959 /* This is the HPET channel number which is zero based */ 960 channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 961 962 /* 963 * The legacy routing mode needs at least two channels, tick timer 964 * and the rtc emulation channel. 965 */ 966 if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC) && channels < 2) 967 goto out_nohpet; 968 969 hc = kcalloc(channels, sizeof(*hc), GFP_KERNEL); 970 if (!hc) { 971 pr_warn("Disabling HPET.\n"); 972 goto out_nohpet; 973 } 974 hpet_base.channels = hc; 975 hpet_base.nr_channels = channels; 976 977 /* Read, store and sanitize the global configuration */ 978 cfg = hpet_readl(HPET_CFG); 979 hpet_base.boot_cfg = cfg; 980 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY); 981 hpet_writel(cfg, HPET_CFG); 982 if (cfg) 983 pr_warn("Global config: Unknown bits %#x\n", cfg); 984 985 /* Read, store and sanitize the per channel configuration */ 986 for (i = 0; i < channels; i++, hc++) { 987 hc->num = i; 988 989 cfg = hpet_readl(HPET_Tn_CFG(i)); 990 hc->boot_cfg = cfg; 991 irq = (cfg & Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; 992 hc->irq = irq; 993 994 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB); 995 hpet_writel(cfg, HPET_Tn_CFG(i)); 996 997 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP 998 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE 999 | HPET_TN_FSB | HPET_TN_FSB_CAP); 1000 if (cfg) 1001 pr_warn("Channel #%u config: Unknown bits %#x\n", i, cfg); 1002 } 1003 hpet_print_config(); 1004 1005 /* 1006 * Validate that the counter is counting. This needs to be done 1007 * after sanitizing the config registers to properly deal with 1008 * force enabled HPETs. 1009 */ 1010 if (!hpet_counting()) 1011 goto out_nohpet; 1012 1013 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); 1014 1015 if (id & HPET_ID_LEGSUP) { 1016 hpet_legacy_clockevent_register(&hpet_base.channels[0]); 1017 hpet_base.channels[0].mode = HPET_MODE_LEGACY; 1018 if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC)) 1019 hpet_base.channels[1].mode = HPET_MODE_LEGACY; 1020 return 1; 1021 } 1022 return 0; 1023 1024 out_nohpet: 1025 kfree(hpet_base.channels); 1026 hpet_base.channels = NULL; 1027 hpet_base.nr_channels = 0; 1028 hpet_clear_mapping(); 1029 hpet_address = 0; 1030 return 0; 1031 } 1032 1033 /* 1034 * The late initialization runs after the PCI quirks have been invoked 1035 * which might have detected a system on which the HPET can be enforced. 1036 * 1037 * Also, the MSI machinery is not working yet when the HPET is initialized 1038 * early. 1039 * 1040 * If the HPET is enabled, then: 1041 * 1042 * 1) Reserve one channel for /dev/hpet if CONFIG_HPET=y 1043 * 2) Reserve up to num_possible_cpus() channels as per CPU clockevents 1044 * 3) Setup /dev/hpet if CONFIG_HPET=y 1045 * 4) Register hotplug callbacks when clockevents are available 1046 */ 1047 static __init int hpet_late_init(void) 1048 { 1049 int ret; 1050 1051 if (!hpet_address) { 1052 if (!force_hpet_address) 1053 return -ENODEV; 1054 1055 hpet_address = force_hpet_address; 1056 hpet_enable(); 1057 } 1058 1059 if (!hpet_virt_address) 1060 return -ENODEV; 1061 1062 hpet_select_device_channel(); 1063 hpet_select_clockevents(); 1064 hpet_reserve_platform_timers(); 1065 hpet_print_config(); 1066 1067 if (!hpet_base.nr_clockevents) 1068 return 0; 1069 1070 ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "x86/hpet:online", 1071 hpet_cpuhp_online, NULL); 1072 if (ret) 1073 return ret; 1074 ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "x86/hpet:dead", NULL, 1075 hpet_cpuhp_dead); 1076 if (ret) 1077 goto err_cpuhp; 1078 return 0; 1079 1080 err_cpuhp: 1081 cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE); 1082 return ret; 1083 } 1084 fs_initcall(hpet_late_init); 1085 1086 void hpet_disable(void) 1087 { 1088 unsigned int i; 1089 u32 cfg; 1090 1091 if (!is_hpet_capable() || !hpet_virt_address) 1092 return; 1093 1094 /* Restore boot configuration with the enable bit cleared */ 1095 cfg = hpet_base.boot_cfg; 1096 cfg &= ~HPET_CFG_ENABLE; 1097 hpet_writel(cfg, HPET_CFG); 1098 1099 /* Restore the channel boot configuration */ 1100 for (i = 0; i < hpet_base.nr_channels; i++) 1101 hpet_writel(hpet_base.channels[i].boot_cfg, HPET_Tn_CFG(i)); 1102 1103 /* If the HPET was enabled at boot time, reenable it */ 1104 if (hpet_base.boot_cfg & HPET_CFG_ENABLE) 1105 hpet_writel(hpet_base.boot_cfg, HPET_CFG); 1106 } 1107 1108 #ifdef CONFIG_HPET_EMULATE_RTC 1109 1110 /* 1111 * HPET in LegacyReplacement mode eats up the RTC interrupt line. When HPET 1112 * is enabled, we support RTC interrupt functionality in software. 1113 * 1114 * RTC has 3 kinds of interrupts: 1115 * 1116 * 1) Update Interrupt - generate an interrupt, every second, when the 1117 * RTC clock is updated 1118 * 2) Alarm Interrupt - generate an interrupt at a specific time of day 1119 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies 1120 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all frequencies in powers of 2) 1121 * 1122 * (1) and (2) above are implemented using polling at a frequency of 64 Hz: 1123 * DEFAULT_RTC_INT_FREQ. 1124 * 1125 * The exact frequency is a tradeoff between accuracy and interrupt overhead. 1126 * 1127 * For (3), we use interrupts at 64 Hz, or the user specified periodic frequency, 1128 * if it's higher. 1129 */ 1130 #include <linux/mc146818rtc.h> 1131 #include <linux/rtc.h> 1132 1133 #define DEFAULT_RTC_INT_FREQ 64 1134 #define DEFAULT_RTC_SHIFT 6 1135 #define RTC_NUM_INTS 1 1136 1137 static unsigned long hpet_rtc_flags; 1138 static int hpet_prev_update_sec; 1139 static struct rtc_time hpet_alarm_time; 1140 static unsigned long hpet_pie_count; 1141 static u32 hpet_t1_cmp; 1142 static u32 hpet_default_delta; 1143 static u32 hpet_pie_delta; 1144 static unsigned long hpet_pie_limit; 1145 1146 static rtc_irq_handler irq_handler; 1147 1148 /* 1149 * Check that the HPET counter c1 is ahead of c2 1150 */ 1151 static inline int hpet_cnt_ahead(u32 c1, u32 c2) 1152 { 1153 return (s32)(c2 - c1) < 0; 1154 } 1155 1156 /* 1157 * Registers a IRQ handler. 1158 */ 1159 int hpet_register_irq_handler(rtc_irq_handler handler) 1160 { 1161 if (!is_hpet_enabled()) 1162 return -ENODEV; 1163 if (irq_handler) 1164 return -EBUSY; 1165 1166 irq_handler = handler; 1167 1168 return 0; 1169 } 1170 EXPORT_SYMBOL_GPL(hpet_register_irq_handler); 1171 1172 /* 1173 * Deregisters the IRQ handler registered with hpet_register_irq_handler() 1174 * and does cleanup. 1175 */ 1176 void hpet_unregister_irq_handler(rtc_irq_handler handler) 1177 { 1178 if (!is_hpet_enabled()) 1179 return; 1180 1181 irq_handler = NULL; 1182 hpet_rtc_flags = 0; 1183 } 1184 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); 1185 1186 /* 1187 * Channel 1 for RTC emulation. We use one shot mode, as periodic mode 1188 * is not supported by all HPET implementations for channel 1. 1189 * 1190 * hpet_rtc_timer_init() is called when the rtc is initialized. 1191 */ 1192 int hpet_rtc_timer_init(void) 1193 { 1194 unsigned int cfg, cnt, delta; 1195 unsigned long flags; 1196 1197 if (!is_hpet_enabled()) 1198 return 0; 1199 1200 if (!hpet_default_delta) { 1201 struct clock_event_device *evt = &hpet_base.channels[0].evt; 1202 uint64_t clc; 1203 1204 clc = (uint64_t) evt->mult * NSEC_PER_SEC; 1205 clc >>= evt->shift + DEFAULT_RTC_SHIFT; 1206 hpet_default_delta = clc; 1207 } 1208 1209 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1210 delta = hpet_default_delta; 1211 else 1212 delta = hpet_pie_delta; 1213 1214 local_irq_save(flags); 1215 1216 cnt = delta + hpet_readl(HPET_COUNTER); 1217 hpet_writel(cnt, HPET_T1_CMP); 1218 hpet_t1_cmp = cnt; 1219 1220 cfg = hpet_readl(HPET_T1_CFG); 1221 cfg &= ~HPET_TN_PERIODIC; 1222 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 1223 hpet_writel(cfg, HPET_T1_CFG); 1224 1225 local_irq_restore(flags); 1226 1227 return 1; 1228 } 1229 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); 1230 1231 static void hpet_disable_rtc_channel(void) 1232 { 1233 u32 cfg = hpet_readl(HPET_T1_CFG); 1234 1235 cfg &= ~HPET_TN_ENABLE; 1236 hpet_writel(cfg, HPET_T1_CFG); 1237 } 1238 1239 /* 1240 * The functions below are called from rtc driver. 1241 * Return 0 if HPET is not being used. 1242 * Otherwise do the necessary changes and return 1. 1243 */ 1244 int hpet_mask_rtc_irq_bit(unsigned long bit_mask) 1245 { 1246 if (!is_hpet_enabled()) 1247 return 0; 1248 1249 hpet_rtc_flags &= ~bit_mask; 1250 if (unlikely(!hpet_rtc_flags)) 1251 hpet_disable_rtc_channel(); 1252 1253 return 1; 1254 } 1255 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); 1256 1257 int hpet_set_rtc_irq_bit(unsigned long bit_mask) 1258 { 1259 unsigned long oldbits = hpet_rtc_flags; 1260 1261 if (!is_hpet_enabled()) 1262 return 0; 1263 1264 hpet_rtc_flags |= bit_mask; 1265 1266 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) 1267 hpet_prev_update_sec = -1; 1268 1269 if (!oldbits) 1270 hpet_rtc_timer_init(); 1271 1272 return 1; 1273 } 1274 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); 1275 1276 int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec) 1277 { 1278 if (!is_hpet_enabled()) 1279 return 0; 1280 1281 hpet_alarm_time.tm_hour = hrs; 1282 hpet_alarm_time.tm_min = min; 1283 hpet_alarm_time.tm_sec = sec; 1284 1285 return 1; 1286 } 1287 EXPORT_SYMBOL_GPL(hpet_set_alarm_time); 1288 1289 int hpet_set_periodic_freq(unsigned long freq) 1290 { 1291 uint64_t clc; 1292 1293 if (!is_hpet_enabled()) 1294 return 0; 1295 1296 if (freq <= DEFAULT_RTC_INT_FREQ) { 1297 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; 1298 } else { 1299 struct clock_event_device *evt = &hpet_base.channels[0].evt; 1300 1301 clc = (uint64_t) evt->mult * NSEC_PER_SEC; 1302 do_div(clc, freq); 1303 clc >>= evt->shift; 1304 hpet_pie_delta = clc; 1305 hpet_pie_limit = 0; 1306 } 1307 1308 return 1; 1309 } 1310 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); 1311 1312 int hpet_rtc_dropped_irq(void) 1313 { 1314 return is_hpet_enabled(); 1315 } 1316 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); 1317 1318 static void hpet_rtc_timer_reinit(void) 1319 { 1320 unsigned int delta; 1321 int lost_ints = -1; 1322 1323 if (unlikely(!hpet_rtc_flags)) 1324 hpet_disable_rtc_channel(); 1325 1326 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1327 delta = hpet_default_delta; 1328 else 1329 delta = hpet_pie_delta; 1330 1331 /* 1332 * Increment the comparator value until we are ahead of the 1333 * current count. 1334 */ 1335 do { 1336 hpet_t1_cmp += delta; 1337 hpet_writel(hpet_t1_cmp, HPET_T1_CMP); 1338 lost_ints++; 1339 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); 1340 1341 if (lost_ints) { 1342 if (hpet_rtc_flags & RTC_PIE) 1343 hpet_pie_count += lost_ints; 1344 if (printk_ratelimit()) 1345 pr_warn("Lost %d RTC interrupts\n", lost_ints); 1346 } 1347 } 1348 1349 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) 1350 { 1351 struct rtc_time curr_time; 1352 unsigned long rtc_int_flag = 0; 1353 1354 hpet_rtc_timer_reinit(); 1355 memset(&curr_time, 0, sizeof(struct rtc_time)); 1356 1357 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) 1358 mc146818_get_time(&curr_time); 1359 1360 if (hpet_rtc_flags & RTC_UIE && 1361 curr_time.tm_sec != hpet_prev_update_sec) { 1362 if (hpet_prev_update_sec >= 0) 1363 rtc_int_flag = RTC_UF; 1364 hpet_prev_update_sec = curr_time.tm_sec; 1365 } 1366 1367 if (hpet_rtc_flags & RTC_PIE && ++hpet_pie_count >= hpet_pie_limit) { 1368 rtc_int_flag |= RTC_PF; 1369 hpet_pie_count = 0; 1370 } 1371 1372 if (hpet_rtc_flags & RTC_AIE && 1373 (curr_time.tm_sec == hpet_alarm_time.tm_sec) && 1374 (curr_time.tm_min == hpet_alarm_time.tm_min) && 1375 (curr_time.tm_hour == hpet_alarm_time.tm_hour)) 1376 rtc_int_flag |= RTC_AF; 1377 1378 if (rtc_int_flag) { 1379 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); 1380 if (irq_handler) 1381 irq_handler(rtc_int_flag, dev_id); 1382 } 1383 return IRQ_HANDLED; 1384 } 1385 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); 1386 #endif 1387