1 #include <linux/clocksource.h> 2 #include <linux/clockchips.h> 3 #include <linux/interrupt.h> 4 #include <linux/sysdev.h> 5 #include <linux/delay.h> 6 #include <linux/errno.h> 7 #include <linux/hpet.h> 8 #include <linux/init.h> 9 #include <linux/cpu.h> 10 #include <linux/pm.h> 11 #include <linux/io.h> 12 13 #include <asm/fixmap.h> 14 #include <asm/i8253.h> 15 #include <asm/hpet.h> 16 17 #define HPET_MASK CLOCKSOURCE_MASK(32) 18 #define HPET_SHIFT 22 19 20 /* FSEC = 10^-15 21 NSEC = 10^-9 */ 22 #define FSEC_PER_NSEC 1000000L 23 24 #define HPET_DEV_USED_BIT 2 25 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) 26 #define HPET_DEV_VALID 0x8 27 #define HPET_DEV_FSB_CAP 0x1000 28 #define HPET_DEV_PERI_CAP 0x2000 29 30 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt) 31 32 /* 33 * HPET address is set in acpi/boot.c, when an ACPI entry exists 34 */ 35 unsigned long hpet_address; 36 #ifdef CONFIG_PCI_MSI 37 static unsigned long hpet_num_timers; 38 #endif 39 static void __iomem *hpet_virt_address; 40 41 struct hpet_dev { 42 struct clock_event_device evt; 43 unsigned int num; 44 int cpu; 45 unsigned int irq; 46 unsigned int flags; 47 char name[10]; 48 }; 49 50 unsigned long hpet_readl(unsigned long a) 51 { 52 return readl(hpet_virt_address + a); 53 } 54 55 static inline void hpet_writel(unsigned long d, unsigned long a) 56 { 57 writel(d, hpet_virt_address + a); 58 } 59 60 #ifdef CONFIG_X86_64 61 #include <asm/pgtable.h> 62 #endif 63 64 static inline void hpet_set_mapping(void) 65 { 66 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); 67 #ifdef CONFIG_X86_64 68 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); 69 #endif 70 } 71 72 static inline void hpet_clear_mapping(void) 73 { 74 iounmap(hpet_virt_address); 75 hpet_virt_address = NULL; 76 } 77 78 /* 79 * HPET command line enable / disable 80 */ 81 static int boot_hpet_disable; 82 int hpet_force_user; 83 static int hpet_verbose; 84 85 static int __init hpet_setup(char *str) 86 { 87 if (str) { 88 if (!strncmp("disable", str, 7)) 89 boot_hpet_disable = 1; 90 if (!strncmp("force", str, 5)) 91 hpet_force_user = 1; 92 if (!strncmp("verbose", str, 7)) 93 hpet_verbose = 1; 94 } 95 return 1; 96 } 97 __setup("hpet=", hpet_setup); 98 99 static int __init disable_hpet(char *str) 100 { 101 boot_hpet_disable = 1; 102 return 1; 103 } 104 __setup("nohpet", disable_hpet); 105 106 static inline int is_hpet_capable(void) 107 { 108 return !boot_hpet_disable && hpet_address; 109 } 110 111 /* 112 * HPET timer interrupt enable / disable 113 */ 114 static int hpet_legacy_int_enabled; 115 116 /** 117 * is_hpet_enabled - check whether the hpet timer interrupt is enabled 118 */ 119 int is_hpet_enabled(void) 120 { 121 return is_hpet_capable() && hpet_legacy_int_enabled; 122 } 123 EXPORT_SYMBOL_GPL(is_hpet_enabled); 124 125 static void _hpet_print_config(const char *function, int line) 126 { 127 u32 i, timers, l, h; 128 printk(KERN_INFO "hpet: %s(%d):\n", function, line); 129 l = hpet_readl(HPET_ID); 130 h = hpet_readl(HPET_PERIOD); 131 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 132 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); 133 l = hpet_readl(HPET_CFG); 134 h = hpet_readl(HPET_STATUS); 135 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); 136 l = hpet_readl(HPET_COUNTER); 137 h = hpet_readl(HPET_COUNTER+4); 138 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); 139 140 for (i = 0; i < timers; i++) { 141 l = hpet_readl(HPET_Tn_CFG(i)); 142 h = hpet_readl(HPET_Tn_CFG(i)+4); 143 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", 144 i, l, h); 145 l = hpet_readl(HPET_Tn_CMP(i)); 146 h = hpet_readl(HPET_Tn_CMP(i)+4); 147 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", 148 i, l, h); 149 l = hpet_readl(HPET_Tn_ROUTE(i)); 150 h = hpet_readl(HPET_Tn_ROUTE(i)+4); 151 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", 152 i, l, h); 153 } 154 } 155 156 #define hpet_print_config() \ 157 do { \ 158 if (hpet_verbose) \ 159 _hpet_print_config(__FUNCTION__, __LINE__); \ 160 } while (0) 161 162 /* 163 * When the hpet driver (/dev/hpet) is enabled, we need to reserve 164 * timer 0 and timer 1 in case of RTC emulation. 165 */ 166 #ifdef CONFIG_HPET 167 168 static void hpet_reserve_msi_timers(struct hpet_data *hd); 169 170 static void hpet_reserve_platform_timers(unsigned long id) 171 { 172 struct hpet __iomem *hpet = hpet_virt_address; 173 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; 174 unsigned int nrtimers, i; 175 struct hpet_data hd; 176 177 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 178 179 memset(&hd, 0, sizeof(hd)); 180 hd.hd_phys_address = hpet_address; 181 hd.hd_address = hpet; 182 hd.hd_nirqs = nrtimers; 183 hpet_reserve_timer(&hd, 0); 184 185 #ifdef CONFIG_HPET_EMULATE_RTC 186 hpet_reserve_timer(&hd, 1); 187 #endif 188 189 /* 190 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 191 * is wrong for i8259!) not the output IRQ. Many BIOS writers 192 * don't bother configuring *any* comparator interrupts. 193 */ 194 hd.hd_irq[0] = HPET_LEGACY_8254; 195 hd.hd_irq[1] = HPET_LEGACY_RTC; 196 197 for (i = 2; i < nrtimers; timer++, i++) { 198 hd.hd_irq[i] = (readl(&timer->hpet_config) & 199 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; 200 } 201 202 hpet_reserve_msi_timers(&hd); 203 204 hpet_alloc(&hd); 205 206 } 207 #else 208 static void hpet_reserve_platform_timers(unsigned long id) { } 209 #endif 210 211 /* 212 * Common hpet info 213 */ 214 static unsigned long hpet_period; 215 216 static void hpet_legacy_set_mode(enum clock_event_mode mode, 217 struct clock_event_device *evt); 218 static int hpet_legacy_next_event(unsigned long delta, 219 struct clock_event_device *evt); 220 221 /* 222 * The hpet clock event device 223 */ 224 static struct clock_event_device hpet_clockevent = { 225 .name = "hpet", 226 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 227 .set_mode = hpet_legacy_set_mode, 228 .set_next_event = hpet_legacy_next_event, 229 .shift = 32, 230 .irq = 0, 231 .rating = 50, 232 }; 233 234 static void hpet_stop_counter(void) 235 { 236 unsigned long cfg = hpet_readl(HPET_CFG); 237 cfg &= ~HPET_CFG_ENABLE; 238 hpet_writel(cfg, HPET_CFG); 239 } 240 241 static void hpet_reset_counter(void) 242 { 243 hpet_writel(0, HPET_COUNTER); 244 hpet_writel(0, HPET_COUNTER + 4); 245 } 246 247 static void hpet_start_counter(void) 248 { 249 unsigned long cfg = hpet_readl(HPET_CFG); 250 cfg |= HPET_CFG_ENABLE; 251 hpet_writel(cfg, HPET_CFG); 252 } 253 254 static void hpet_restart_counter(void) 255 { 256 hpet_stop_counter(); 257 hpet_reset_counter(); 258 hpet_start_counter(); 259 } 260 261 static void hpet_resume_device(void) 262 { 263 force_hpet_resume(); 264 } 265 266 static void hpet_resume_counter(void) 267 { 268 hpet_resume_device(); 269 hpet_restart_counter(); 270 } 271 272 static void hpet_enable_legacy_int(void) 273 { 274 unsigned long cfg = hpet_readl(HPET_CFG); 275 276 cfg |= HPET_CFG_LEGACY; 277 hpet_writel(cfg, HPET_CFG); 278 hpet_legacy_int_enabled = 1; 279 } 280 281 static void hpet_legacy_clockevent_register(void) 282 { 283 /* Start HPET legacy interrupts */ 284 hpet_enable_legacy_int(); 285 286 /* 287 * The mult factor is defined as (include/linux/clockchips.h) 288 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h) 289 * hpet_period is in units of femtoseconds (per cycle), so 290 * mult/2^shift = cyc/ns = 10^6/hpet_period 291 * mult = (10^6 * 2^shift)/hpet_period 292 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period 293 */ 294 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC, 295 hpet_period, hpet_clockevent.shift); 296 /* Calculate the min / max delta */ 297 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, 298 &hpet_clockevent); 299 /* 5 usec minimum reprogramming delta. */ 300 hpet_clockevent.min_delta_ns = 5000; 301 302 /* 303 * Start hpet with the boot cpu mask and make it 304 * global after the IO_APIC has been initialized. 305 */ 306 hpet_clockevent.cpumask = cpumask_of(smp_processor_id()); 307 clockevents_register_device(&hpet_clockevent); 308 global_clock_event = &hpet_clockevent; 309 printk(KERN_DEBUG "hpet clockevent registered\n"); 310 } 311 312 static int hpet_setup_msi_irq(unsigned int irq); 313 314 static void hpet_set_mode(enum clock_event_mode mode, 315 struct clock_event_device *evt, int timer) 316 { 317 unsigned long cfg, cmp, now; 318 uint64_t delta; 319 320 switch (mode) { 321 case CLOCK_EVT_MODE_PERIODIC: 322 hpet_stop_counter(); 323 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; 324 delta >>= evt->shift; 325 now = hpet_readl(HPET_COUNTER); 326 cmp = now + (unsigned long) delta; 327 cfg = hpet_readl(HPET_Tn_CFG(timer)); 328 /* Make sure we use edge triggered interrupts */ 329 cfg &= ~HPET_TN_LEVEL; 330 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | 331 HPET_TN_SETVAL | HPET_TN_32BIT; 332 hpet_writel(cfg, HPET_Tn_CFG(timer)); 333 hpet_writel(cmp, HPET_Tn_CMP(timer)); 334 udelay(1); 335 /* 336 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL 337 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL 338 * bit is automatically cleared after the first write. 339 * (See AMD-8111 HyperTransport I/O Hub Data Sheet, 340 * Publication # 24674) 341 */ 342 hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer)); 343 hpet_start_counter(); 344 hpet_print_config(); 345 break; 346 347 case CLOCK_EVT_MODE_ONESHOT: 348 cfg = hpet_readl(HPET_Tn_CFG(timer)); 349 cfg &= ~HPET_TN_PERIODIC; 350 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 351 hpet_writel(cfg, HPET_Tn_CFG(timer)); 352 break; 353 354 case CLOCK_EVT_MODE_UNUSED: 355 case CLOCK_EVT_MODE_SHUTDOWN: 356 cfg = hpet_readl(HPET_Tn_CFG(timer)); 357 cfg &= ~HPET_TN_ENABLE; 358 hpet_writel(cfg, HPET_Tn_CFG(timer)); 359 break; 360 361 case CLOCK_EVT_MODE_RESUME: 362 if (timer == 0) { 363 hpet_enable_legacy_int(); 364 } else { 365 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 366 hpet_setup_msi_irq(hdev->irq); 367 disable_irq(hdev->irq); 368 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); 369 enable_irq(hdev->irq); 370 } 371 hpet_print_config(); 372 break; 373 } 374 } 375 376 static int hpet_next_event(unsigned long delta, 377 struct clock_event_device *evt, int timer) 378 { 379 u32 cnt; 380 381 cnt = hpet_readl(HPET_COUNTER); 382 cnt += (u32) delta; 383 hpet_writel(cnt, HPET_Tn_CMP(timer)); 384 385 /* 386 * We need to read back the CMP register to make sure that 387 * what we wrote hit the chip before we compare it to the 388 * counter. 389 */ 390 WARN_ON_ONCE((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt); 391 392 return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0; 393 } 394 395 static void hpet_legacy_set_mode(enum clock_event_mode mode, 396 struct clock_event_device *evt) 397 { 398 hpet_set_mode(mode, evt, 0); 399 } 400 401 static int hpet_legacy_next_event(unsigned long delta, 402 struct clock_event_device *evt) 403 { 404 return hpet_next_event(delta, evt, 0); 405 } 406 407 /* 408 * HPET MSI Support 409 */ 410 #ifdef CONFIG_PCI_MSI 411 412 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); 413 static struct hpet_dev *hpet_devs; 414 415 void hpet_msi_unmask(unsigned int irq) 416 { 417 struct hpet_dev *hdev = get_irq_data(irq); 418 unsigned long cfg; 419 420 /* unmask it */ 421 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 422 cfg |= HPET_TN_FSB; 423 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 424 } 425 426 void hpet_msi_mask(unsigned int irq) 427 { 428 unsigned long cfg; 429 struct hpet_dev *hdev = get_irq_data(irq); 430 431 /* mask it */ 432 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 433 cfg &= ~HPET_TN_FSB; 434 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 435 } 436 437 void hpet_msi_write(unsigned int irq, struct msi_msg *msg) 438 { 439 struct hpet_dev *hdev = get_irq_data(irq); 440 441 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); 442 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); 443 } 444 445 void hpet_msi_read(unsigned int irq, struct msi_msg *msg) 446 { 447 struct hpet_dev *hdev = get_irq_data(irq); 448 449 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); 450 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); 451 msg->address_hi = 0; 452 } 453 454 static void hpet_msi_set_mode(enum clock_event_mode mode, 455 struct clock_event_device *evt) 456 { 457 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 458 hpet_set_mode(mode, evt, hdev->num); 459 } 460 461 static int hpet_msi_next_event(unsigned long delta, 462 struct clock_event_device *evt) 463 { 464 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 465 return hpet_next_event(delta, evt, hdev->num); 466 } 467 468 static int hpet_setup_msi_irq(unsigned int irq) 469 { 470 if (arch_setup_hpet_msi(irq)) { 471 destroy_irq(irq); 472 return -EINVAL; 473 } 474 return 0; 475 } 476 477 static int hpet_assign_irq(struct hpet_dev *dev) 478 { 479 unsigned int irq; 480 481 irq = create_irq(); 482 if (!irq) 483 return -EINVAL; 484 485 set_irq_data(irq, dev); 486 487 if (hpet_setup_msi_irq(irq)) 488 return -EINVAL; 489 490 dev->irq = irq; 491 return 0; 492 } 493 494 static irqreturn_t hpet_interrupt_handler(int irq, void *data) 495 { 496 struct hpet_dev *dev = (struct hpet_dev *)data; 497 struct clock_event_device *hevt = &dev->evt; 498 499 if (!hevt->event_handler) { 500 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", 501 dev->num); 502 return IRQ_HANDLED; 503 } 504 505 hevt->event_handler(hevt); 506 return IRQ_HANDLED; 507 } 508 509 static int hpet_setup_irq(struct hpet_dev *dev) 510 { 511 512 if (request_irq(dev->irq, hpet_interrupt_handler, 513 IRQF_DISABLED|IRQF_NOBALANCING, dev->name, dev)) 514 return -1; 515 516 disable_irq(dev->irq); 517 irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); 518 enable_irq(dev->irq); 519 520 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", 521 dev->name, dev->irq); 522 523 return 0; 524 } 525 526 /* This should be called in specific @cpu */ 527 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) 528 { 529 struct clock_event_device *evt = &hdev->evt; 530 uint64_t hpet_freq; 531 532 WARN_ON(cpu != smp_processor_id()); 533 if (!(hdev->flags & HPET_DEV_VALID)) 534 return; 535 536 if (hpet_setup_msi_irq(hdev->irq)) 537 return; 538 539 hdev->cpu = cpu; 540 per_cpu(cpu_hpet_dev, cpu) = hdev; 541 evt->name = hdev->name; 542 hpet_setup_irq(hdev); 543 evt->irq = hdev->irq; 544 545 evt->rating = 110; 546 evt->features = CLOCK_EVT_FEAT_ONESHOT; 547 if (hdev->flags & HPET_DEV_PERI_CAP) 548 evt->features |= CLOCK_EVT_FEAT_PERIODIC; 549 550 evt->set_mode = hpet_msi_set_mode; 551 evt->set_next_event = hpet_msi_next_event; 552 evt->shift = 32; 553 554 /* 555 * The period is a femto seconds value. We need to calculate the 556 * scaled math multiplication factor for nanosecond to hpet tick 557 * conversion. 558 */ 559 hpet_freq = 1000000000000000ULL; 560 do_div(hpet_freq, hpet_period); 561 evt->mult = div_sc((unsigned long) hpet_freq, 562 NSEC_PER_SEC, evt->shift); 563 /* Calculate the max delta */ 564 evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt); 565 /* 5 usec minimum reprogramming delta. */ 566 evt->min_delta_ns = 5000; 567 568 evt->cpumask = cpumask_of(hdev->cpu); 569 clockevents_register_device(evt); 570 } 571 572 #ifdef CONFIG_HPET 573 /* Reserve at least one timer for userspace (/dev/hpet) */ 574 #define RESERVE_TIMERS 1 575 #else 576 #define RESERVE_TIMERS 0 577 #endif 578 579 static void hpet_msi_capability_lookup(unsigned int start_timer) 580 { 581 unsigned int id; 582 unsigned int num_timers; 583 unsigned int num_timers_used = 0; 584 int i; 585 586 id = hpet_readl(HPET_ID); 587 588 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); 589 num_timers++; /* Value read out starts from 0 */ 590 hpet_print_config(); 591 592 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); 593 if (!hpet_devs) 594 return; 595 596 hpet_num_timers = num_timers; 597 598 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { 599 struct hpet_dev *hdev = &hpet_devs[num_timers_used]; 600 unsigned long cfg = hpet_readl(HPET_Tn_CFG(i)); 601 602 /* Only consider HPET timer with MSI support */ 603 if (!(cfg & HPET_TN_FSB_CAP)) 604 continue; 605 606 hdev->flags = 0; 607 if (cfg & HPET_TN_PERIODIC_CAP) 608 hdev->flags |= HPET_DEV_PERI_CAP; 609 hdev->num = i; 610 611 sprintf(hdev->name, "hpet%d", i); 612 if (hpet_assign_irq(hdev)) 613 continue; 614 615 hdev->flags |= HPET_DEV_FSB_CAP; 616 hdev->flags |= HPET_DEV_VALID; 617 num_timers_used++; 618 if (num_timers_used == num_possible_cpus()) 619 break; 620 } 621 622 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", 623 num_timers, num_timers_used); 624 } 625 626 #ifdef CONFIG_HPET 627 static void hpet_reserve_msi_timers(struct hpet_data *hd) 628 { 629 int i; 630 631 if (!hpet_devs) 632 return; 633 634 for (i = 0; i < hpet_num_timers; i++) { 635 struct hpet_dev *hdev = &hpet_devs[i]; 636 637 if (!(hdev->flags & HPET_DEV_VALID)) 638 continue; 639 640 hd->hd_irq[hdev->num] = hdev->irq; 641 hpet_reserve_timer(hd, hdev->num); 642 } 643 } 644 #endif 645 646 static struct hpet_dev *hpet_get_unused_timer(void) 647 { 648 int i; 649 650 if (!hpet_devs) 651 return NULL; 652 653 for (i = 0; i < hpet_num_timers; i++) { 654 struct hpet_dev *hdev = &hpet_devs[i]; 655 656 if (!(hdev->flags & HPET_DEV_VALID)) 657 continue; 658 if (test_and_set_bit(HPET_DEV_USED_BIT, 659 (unsigned long *)&hdev->flags)) 660 continue; 661 return hdev; 662 } 663 return NULL; 664 } 665 666 struct hpet_work_struct { 667 struct delayed_work work; 668 struct completion complete; 669 }; 670 671 static void hpet_work(struct work_struct *w) 672 { 673 struct hpet_dev *hdev; 674 int cpu = smp_processor_id(); 675 struct hpet_work_struct *hpet_work; 676 677 hpet_work = container_of(w, struct hpet_work_struct, work.work); 678 679 hdev = hpet_get_unused_timer(); 680 if (hdev) 681 init_one_hpet_msi_clockevent(hdev, cpu); 682 683 complete(&hpet_work->complete); 684 } 685 686 static int hpet_cpuhp_notify(struct notifier_block *n, 687 unsigned long action, void *hcpu) 688 { 689 unsigned long cpu = (unsigned long)hcpu; 690 struct hpet_work_struct work; 691 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); 692 693 switch (action & 0xf) { 694 case CPU_ONLINE: 695 INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work); 696 init_completion(&work.complete); 697 /* FIXME: add schedule_work_on() */ 698 schedule_delayed_work_on(cpu, &work.work, 0); 699 wait_for_completion(&work.complete); 700 destroy_timer_on_stack(&work.work.timer); 701 break; 702 case CPU_DEAD: 703 if (hdev) { 704 free_irq(hdev->irq, hdev); 705 hdev->flags &= ~HPET_DEV_USED; 706 per_cpu(cpu_hpet_dev, cpu) = NULL; 707 } 708 break; 709 } 710 return NOTIFY_OK; 711 } 712 #else 713 714 static int hpet_setup_msi_irq(unsigned int irq) 715 { 716 return 0; 717 } 718 static void hpet_msi_capability_lookup(unsigned int start_timer) 719 { 720 return; 721 } 722 723 #ifdef CONFIG_HPET 724 static void hpet_reserve_msi_timers(struct hpet_data *hd) 725 { 726 return; 727 } 728 #endif 729 730 static int hpet_cpuhp_notify(struct notifier_block *n, 731 unsigned long action, void *hcpu) 732 { 733 return NOTIFY_OK; 734 } 735 736 #endif 737 738 /* 739 * Clock source related code 740 */ 741 static cycle_t read_hpet(struct clocksource *cs) 742 { 743 return (cycle_t)hpet_readl(HPET_COUNTER); 744 } 745 746 #ifdef CONFIG_X86_64 747 static cycle_t __vsyscall_fn vread_hpet(void) 748 { 749 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0); 750 } 751 #endif 752 753 static struct clocksource clocksource_hpet = { 754 .name = "hpet", 755 .rating = 250, 756 .read = read_hpet, 757 .mask = HPET_MASK, 758 .shift = HPET_SHIFT, 759 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 760 .resume = hpet_resume_counter, 761 #ifdef CONFIG_X86_64 762 .vread = vread_hpet, 763 #endif 764 }; 765 766 static int hpet_clocksource_register(void) 767 { 768 u64 start, now; 769 cycle_t t1; 770 771 /* Start the counter */ 772 hpet_restart_counter(); 773 774 /* Verify whether hpet counter works */ 775 t1 = hpet_readl(HPET_COUNTER); 776 rdtscll(start); 777 778 /* 779 * We don't know the TSC frequency yet, but waiting for 780 * 200000 TSC cycles is safe: 781 * 4 GHz == 50us 782 * 1 GHz == 200us 783 */ 784 do { 785 rep_nop(); 786 rdtscll(now); 787 } while ((now - start) < 200000UL); 788 789 if (t1 == hpet_readl(HPET_COUNTER)) { 790 printk(KERN_WARNING 791 "HPET counter not counting. HPET disabled\n"); 792 return -ENODEV; 793 } 794 795 /* 796 * The definition of mult is (include/linux/clocksource.h) 797 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc 798 * so we first need to convert hpet_period to ns/cyc units: 799 * mult/2^shift = ns/cyc = hpet_period/10^6 800 * mult = (hpet_period * 2^shift)/10^6 801 * mult = (hpet_period << shift)/FSEC_PER_NSEC 802 */ 803 clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT); 804 805 clocksource_register(&clocksource_hpet); 806 807 return 0; 808 } 809 810 /** 811 * hpet_enable - Try to setup the HPET timer. Returns 1 on success. 812 */ 813 int __init hpet_enable(void) 814 { 815 unsigned long id; 816 int i; 817 818 if (!is_hpet_capable()) 819 return 0; 820 821 hpet_set_mapping(); 822 823 /* 824 * Read the period and check for a sane value: 825 */ 826 hpet_period = hpet_readl(HPET_PERIOD); 827 828 /* 829 * AMD SB700 based systems with spread spectrum enabled use a 830 * SMM based HPET emulation to provide proper frequency 831 * setting. The SMM code is initialized with the first HPET 832 * register access and takes some time to complete. During 833 * this time the config register reads 0xffffffff. We check 834 * for max. 1000 loops whether the config register reads a non 835 * 0xffffffff value to make sure that HPET is up and running 836 * before we go further. A counting loop is safe, as the HPET 837 * access takes thousands of CPU cycles. On non SB700 based 838 * machines this check is only done once and has no side 839 * effects. 840 */ 841 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { 842 if (i == 1000) { 843 printk(KERN_WARNING 844 "HPET config register value = 0xFFFFFFFF. " 845 "Disabling HPET\n"); 846 goto out_nohpet; 847 } 848 } 849 850 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) 851 goto out_nohpet; 852 853 /* 854 * Read the HPET ID register to retrieve the IRQ routing 855 * information and the number of channels 856 */ 857 id = hpet_readl(HPET_ID); 858 hpet_print_config(); 859 860 #ifdef CONFIG_HPET_EMULATE_RTC 861 /* 862 * The legacy routing mode needs at least two channels, tick timer 863 * and the rtc emulation channel. 864 */ 865 if (!(id & HPET_ID_NUMBER)) 866 goto out_nohpet; 867 #endif 868 869 if (hpet_clocksource_register()) 870 goto out_nohpet; 871 872 if (id & HPET_ID_LEGSUP) { 873 hpet_legacy_clockevent_register(); 874 hpet_msi_capability_lookup(2); 875 return 1; 876 } 877 hpet_msi_capability_lookup(0); 878 return 0; 879 880 out_nohpet: 881 hpet_clear_mapping(); 882 hpet_address = 0; 883 return 0; 884 } 885 886 /* 887 * Needs to be late, as the reserve_timer code calls kalloc ! 888 * 889 * Not a problem on i386 as hpet_enable is called from late_time_init, 890 * but on x86_64 it is necessary ! 891 */ 892 static __init int hpet_late_init(void) 893 { 894 int cpu; 895 896 if (boot_hpet_disable) 897 return -ENODEV; 898 899 if (!hpet_address) { 900 if (!force_hpet_address) 901 return -ENODEV; 902 903 hpet_address = force_hpet_address; 904 hpet_enable(); 905 } 906 907 if (!hpet_virt_address) 908 return -ENODEV; 909 910 hpet_reserve_platform_timers(hpet_readl(HPET_ID)); 911 hpet_print_config(); 912 913 for_each_online_cpu(cpu) { 914 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); 915 } 916 917 /* This notifier should be called after workqueue is ready */ 918 hotcpu_notifier(hpet_cpuhp_notify, -20); 919 920 return 0; 921 } 922 fs_initcall(hpet_late_init); 923 924 void hpet_disable(void) 925 { 926 if (is_hpet_capable()) { 927 unsigned long cfg = hpet_readl(HPET_CFG); 928 929 if (hpet_legacy_int_enabled) { 930 cfg &= ~HPET_CFG_LEGACY; 931 hpet_legacy_int_enabled = 0; 932 } 933 cfg &= ~HPET_CFG_ENABLE; 934 hpet_writel(cfg, HPET_CFG); 935 } 936 } 937 938 #ifdef CONFIG_HPET_EMULATE_RTC 939 940 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET 941 * is enabled, we support RTC interrupt functionality in software. 942 * RTC has 3 kinds of interrupts: 943 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock 944 * is updated 945 * 2) Alarm Interrupt - generate an interrupt at a specific time of day 946 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies 947 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) 948 * (1) and (2) above are implemented using polling at a frequency of 949 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt 950 * overhead. (DEFAULT_RTC_INT_FREQ) 951 * For (3), we use interrupts at 64Hz or user specified periodic 952 * frequency, whichever is higher. 953 */ 954 #include <linux/mc146818rtc.h> 955 #include <linux/rtc.h> 956 #include <asm/rtc.h> 957 958 #define DEFAULT_RTC_INT_FREQ 64 959 #define DEFAULT_RTC_SHIFT 6 960 #define RTC_NUM_INTS 1 961 962 static unsigned long hpet_rtc_flags; 963 static int hpet_prev_update_sec; 964 static struct rtc_time hpet_alarm_time; 965 static unsigned long hpet_pie_count; 966 static u32 hpet_t1_cmp; 967 static unsigned long hpet_default_delta; 968 static unsigned long hpet_pie_delta; 969 static unsigned long hpet_pie_limit; 970 971 static rtc_irq_handler irq_handler; 972 973 /* 974 * Check that the hpet counter c1 is ahead of the c2 975 */ 976 static inline int hpet_cnt_ahead(u32 c1, u32 c2) 977 { 978 return (s32)(c2 - c1) < 0; 979 } 980 981 /* 982 * Registers a IRQ handler. 983 */ 984 int hpet_register_irq_handler(rtc_irq_handler handler) 985 { 986 if (!is_hpet_enabled()) 987 return -ENODEV; 988 if (irq_handler) 989 return -EBUSY; 990 991 irq_handler = handler; 992 993 return 0; 994 } 995 EXPORT_SYMBOL_GPL(hpet_register_irq_handler); 996 997 /* 998 * Deregisters the IRQ handler registered with hpet_register_irq_handler() 999 * and does cleanup. 1000 */ 1001 void hpet_unregister_irq_handler(rtc_irq_handler handler) 1002 { 1003 if (!is_hpet_enabled()) 1004 return; 1005 1006 irq_handler = NULL; 1007 hpet_rtc_flags = 0; 1008 } 1009 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); 1010 1011 /* 1012 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode 1013 * is not supported by all HPET implementations for timer 1. 1014 * 1015 * hpet_rtc_timer_init() is called when the rtc is initialized. 1016 */ 1017 int hpet_rtc_timer_init(void) 1018 { 1019 unsigned long cfg, cnt, delta, flags; 1020 1021 if (!is_hpet_enabled()) 1022 return 0; 1023 1024 if (!hpet_default_delta) { 1025 uint64_t clc; 1026 1027 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1028 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; 1029 hpet_default_delta = (unsigned long) clc; 1030 } 1031 1032 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1033 delta = hpet_default_delta; 1034 else 1035 delta = hpet_pie_delta; 1036 1037 local_irq_save(flags); 1038 1039 cnt = delta + hpet_readl(HPET_COUNTER); 1040 hpet_writel(cnt, HPET_T1_CMP); 1041 hpet_t1_cmp = cnt; 1042 1043 cfg = hpet_readl(HPET_T1_CFG); 1044 cfg &= ~HPET_TN_PERIODIC; 1045 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 1046 hpet_writel(cfg, HPET_T1_CFG); 1047 1048 local_irq_restore(flags); 1049 1050 return 1; 1051 } 1052 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); 1053 1054 /* 1055 * The functions below are called from rtc driver. 1056 * Return 0 if HPET is not being used. 1057 * Otherwise do the necessary changes and return 1. 1058 */ 1059 int hpet_mask_rtc_irq_bit(unsigned long bit_mask) 1060 { 1061 if (!is_hpet_enabled()) 1062 return 0; 1063 1064 hpet_rtc_flags &= ~bit_mask; 1065 return 1; 1066 } 1067 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); 1068 1069 int hpet_set_rtc_irq_bit(unsigned long bit_mask) 1070 { 1071 unsigned long oldbits = hpet_rtc_flags; 1072 1073 if (!is_hpet_enabled()) 1074 return 0; 1075 1076 hpet_rtc_flags |= bit_mask; 1077 1078 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) 1079 hpet_prev_update_sec = -1; 1080 1081 if (!oldbits) 1082 hpet_rtc_timer_init(); 1083 1084 return 1; 1085 } 1086 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); 1087 1088 int hpet_set_alarm_time(unsigned char hrs, unsigned char min, 1089 unsigned char sec) 1090 { 1091 if (!is_hpet_enabled()) 1092 return 0; 1093 1094 hpet_alarm_time.tm_hour = hrs; 1095 hpet_alarm_time.tm_min = min; 1096 hpet_alarm_time.tm_sec = sec; 1097 1098 return 1; 1099 } 1100 EXPORT_SYMBOL_GPL(hpet_set_alarm_time); 1101 1102 int hpet_set_periodic_freq(unsigned long freq) 1103 { 1104 uint64_t clc; 1105 1106 if (!is_hpet_enabled()) 1107 return 0; 1108 1109 if (freq <= DEFAULT_RTC_INT_FREQ) 1110 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; 1111 else { 1112 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1113 do_div(clc, freq); 1114 clc >>= hpet_clockevent.shift; 1115 hpet_pie_delta = (unsigned long) clc; 1116 } 1117 return 1; 1118 } 1119 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); 1120 1121 int hpet_rtc_dropped_irq(void) 1122 { 1123 return is_hpet_enabled(); 1124 } 1125 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); 1126 1127 static void hpet_rtc_timer_reinit(void) 1128 { 1129 unsigned long cfg, delta; 1130 int lost_ints = -1; 1131 1132 if (unlikely(!hpet_rtc_flags)) { 1133 cfg = hpet_readl(HPET_T1_CFG); 1134 cfg &= ~HPET_TN_ENABLE; 1135 hpet_writel(cfg, HPET_T1_CFG); 1136 return; 1137 } 1138 1139 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1140 delta = hpet_default_delta; 1141 else 1142 delta = hpet_pie_delta; 1143 1144 /* 1145 * Increment the comparator value until we are ahead of the 1146 * current count. 1147 */ 1148 do { 1149 hpet_t1_cmp += delta; 1150 hpet_writel(hpet_t1_cmp, HPET_T1_CMP); 1151 lost_ints++; 1152 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); 1153 1154 if (lost_ints) { 1155 if (hpet_rtc_flags & RTC_PIE) 1156 hpet_pie_count += lost_ints; 1157 if (printk_ratelimit()) 1158 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", 1159 lost_ints); 1160 } 1161 } 1162 1163 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) 1164 { 1165 struct rtc_time curr_time; 1166 unsigned long rtc_int_flag = 0; 1167 1168 hpet_rtc_timer_reinit(); 1169 memset(&curr_time, 0, sizeof(struct rtc_time)); 1170 1171 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) 1172 get_rtc_time(&curr_time); 1173 1174 if (hpet_rtc_flags & RTC_UIE && 1175 curr_time.tm_sec != hpet_prev_update_sec) { 1176 if (hpet_prev_update_sec >= 0) 1177 rtc_int_flag = RTC_UF; 1178 hpet_prev_update_sec = curr_time.tm_sec; 1179 } 1180 1181 if (hpet_rtc_flags & RTC_PIE && 1182 ++hpet_pie_count >= hpet_pie_limit) { 1183 rtc_int_flag |= RTC_PF; 1184 hpet_pie_count = 0; 1185 } 1186 1187 if (hpet_rtc_flags & RTC_AIE && 1188 (curr_time.tm_sec == hpet_alarm_time.tm_sec) && 1189 (curr_time.tm_min == hpet_alarm_time.tm_min) && 1190 (curr_time.tm_hour == hpet_alarm_time.tm_hour)) 1191 rtc_int_flag |= RTC_AF; 1192 1193 if (rtc_int_flag) { 1194 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); 1195 if (irq_handler) 1196 irq_handler(rtc_int_flag, dev_id); 1197 } 1198 return IRQ_HANDLED; 1199 } 1200 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); 1201 #endif 1202