1 #include <linux/clocksource.h> 2 #include <linux/clockchips.h> 3 #include <linux/interrupt.h> 4 #include <linux/irq.h> 5 #include <linux/export.h> 6 #include <linux/delay.h> 7 #include <linux/errno.h> 8 #include <linux/i8253.h> 9 #include <linux/slab.h> 10 #include <linux/hpet.h> 11 #include <linux/init.h> 12 #include <linux/cpu.h> 13 #include <linux/pm.h> 14 #include <linux/io.h> 15 16 #include <asm/cpufeature.h> 17 #include <asm/irqdomain.h> 18 #include <asm/fixmap.h> 19 #include <asm/hpet.h> 20 #include <asm/time.h> 21 22 #define HPET_MASK CLOCKSOURCE_MASK(32) 23 24 /* FSEC = 10^-15 25 NSEC = 10^-9 */ 26 #define FSEC_PER_NSEC 1000000L 27 28 #define HPET_DEV_USED_BIT 2 29 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) 30 #define HPET_DEV_VALID 0x8 31 #define HPET_DEV_FSB_CAP 0x1000 32 #define HPET_DEV_PERI_CAP 0x2000 33 34 #define HPET_MIN_CYCLES 128 35 #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1)) 36 37 /* 38 * HPET address is set in acpi/boot.c, when an ACPI entry exists 39 */ 40 unsigned long hpet_address; 41 u8 hpet_blockid; /* OS timer block num */ 42 bool hpet_msi_disable; 43 44 #ifdef CONFIG_PCI_MSI 45 static unsigned int hpet_num_timers; 46 #endif 47 static void __iomem *hpet_virt_address; 48 49 struct hpet_dev { 50 struct clock_event_device evt; 51 unsigned int num; 52 int cpu; 53 unsigned int irq; 54 unsigned int flags; 55 char name[10]; 56 }; 57 58 static inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev) 59 { 60 return container_of(evtdev, struct hpet_dev, evt); 61 } 62 63 inline unsigned int hpet_readl(unsigned int a) 64 { 65 return readl(hpet_virt_address + a); 66 } 67 68 static inline void hpet_writel(unsigned int d, unsigned int a) 69 { 70 writel(d, hpet_virt_address + a); 71 } 72 73 #ifdef CONFIG_X86_64 74 #include <asm/pgtable.h> 75 #endif 76 77 static inline void hpet_set_mapping(void) 78 { 79 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); 80 } 81 82 static inline void hpet_clear_mapping(void) 83 { 84 iounmap(hpet_virt_address); 85 hpet_virt_address = NULL; 86 } 87 88 /* 89 * HPET command line enable / disable 90 */ 91 bool boot_hpet_disable; 92 bool hpet_force_user; 93 static bool hpet_verbose; 94 95 static int __init hpet_setup(char *str) 96 { 97 while (str) { 98 char *next = strchr(str, ','); 99 100 if (next) 101 *next++ = 0; 102 if (!strncmp("disable", str, 7)) 103 boot_hpet_disable = true; 104 if (!strncmp("force", str, 5)) 105 hpet_force_user = true; 106 if (!strncmp("verbose", str, 7)) 107 hpet_verbose = true; 108 str = next; 109 } 110 return 1; 111 } 112 __setup("hpet=", hpet_setup); 113 114 static int __init disable_hpet(char *str) 115 { 116 boot_hpet_disable = true; 117 return 1; 118 } 119 __setup("nohpet", disable_hpet); 120 121 static inline int is_hpet_capable(void) 122 { 123 return !boot_hpet_disable && hpet_address; 124 } 125 126 /* 127 * HPET timer interrupt enable / disable 128 */ 129 static bool hpet_legacy_int_enabled; 130 131 /** 132 * is_hpet_enabled - check whether the hpet timer interrupt is enabled 133 */ 134 int is_hpet_enabled(void) 135 { 136 return is_hpet_capable() && hpet_legacy_int_enabled; 137 } 138 EXPORT_SYMBOL_GPL(is_hpet_enabled); 139 140 static void _hpet_print_config(const char *function, int line) 141 { 142 u32 i, timers, l, h; 143 printk(KERN_INFO "hpet: %s(%d):\n", function, line); 144 l = hpet_readl(HPET_ID); 145 h = hpet_readl(HPET_PERIOD); 146 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 147 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); 148 l = hpet_readl(HPET_CFG); 149 h = hpet_readl(HPET_STATUS); 150 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); 151 l = hpet_readl(HPET_COUNTER); 152 h = hpet_readl(HPET_COUNTER+4); 153 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); 154 155 for (i = 0; i < timers; i++) { 156 l = hpet_readl(HPET_Tn_CFG(i)); 157 h = hpet_readl(HPET_Tn_CFG(i)+4); 158 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", 159 i, l, h); 160 l = hpet_readl(HPET_Tn_CMP(i)); 161 h = hpet_readl(HPET_Tn_CMP(i)+4); 162 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", 163 i, l, h); 164 l = hpet_readl(HPET_Tn_ROUTE(i)); 165 h = hpet_readl(HPET_Tn_ROUTE(i)+4); 166 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", 167 i, l, h); 168 } 169 } 170 171 #define hpet_print_config() \ 172 do { \ 173 if (hpet_verbose) \ 174 _hpet_print_config(__func__, __LINE__); \ 175 } while (0) 176 177 /* 178 * When the hpet driver (/dev/hpet) is enabled, we need to reserve 179 * timer 0 and timer 1 in case of RTC emulation. 180 */ 181 #ifdef CONFIG_HPET 182 183 static void hpet_reserve_msi_timers(struct hpet_data *hd); 184 185 static void hpet_reserve_platform_timers(unsigned int id) 186 { 187 struct hpet __iomem *hpet = hpet_virt_address; 188 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; 189 unsigned int nrtimers, i; 190 struct hpet_data hd; 191 192 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; 193 194 memset(&hd, 0, sizeof(hd)); 195 hd.hd_phys_address = hpet_address; 196 hd.hd_address = hpet; 197 hd.hd_nirqs = nrtimers; 198 hpet_reserve_timer(&hd, 0); 199 200 #ifdef CONFIG_HPET_EMULATE_RTC 201 hpet_reserve_timer(&hd, 1); 202 #endif 203 204 /* 205 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 206 * is wrong for i8259!) not the output IRQ. Many BIOS writers 207 * don't bother configuring *any* comparator interrupts. 208 */ 209 hd.hd_irq[0] = HPET_LEGACY_8254; 210 hd.hd_irq[1] = HPET_LEGACY_RTC; 211 212 for (i = 2; i < nrtimers; timer++, i++) { 213 hd.hd_irq[i] = (readl(&timer->hpet_config) & 214 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; 215 } 216 217 hpet_reserve_msi_timers(&hd); 218 219 hpet_alloc(&hd); 220 221 } 222 #else 223 static void hpet_reserve_platform_timers(unsigned int id) { } 224 #endif 225 226 /* 227 * Common hpet info 228 */ 229 static unsigned long hpet_freq; 230 231 static struct clock_event_device hpet_clockevent; 232 233 static void hpet_stop_counter(void) 234 { 235 u32 cfg = hpet_readl(HPET_CFG); 236 cfg &= ~HPET_CFG_ENABLE; 237 hpet_writel(cfg, HPET_CFG); 238 } 239 240 static void hpet_reset_counter(void) 241 { 242 hpet_writel(0, HPET_COUNTER); 243 hpet_writel(0, HPET_COUNTER + 4); 244 } 245 246 static void hpet_start_counter(void) 247 { 248 unsigned int cfg = hpet_readl(HPET_CFG); 249 cfg |= HPET_CFG_ENABLE; 250 hpet_writel(cfg, HPET_CFG); 251 } 252 253 static void hpet_restart_counter(void) 254 { 255 hpet_stop_counter(); 256 hpet_reset_counter(); 257 hpet_start_counter(); 258 } 259 260 static void hpet_resume_device(void) 261 { 262 force_hpet_resume(); 263 } 264 265 static void hpet_resume_counter(struct clocksource *cs) 266 { 267 hpet_resume_device(); 268 hpet_restart_counter(); 269 } 270 271 static void hpet_enable_legacy_int(void) 272 { 273 unsigned int cfg = hpet_readl(HPET_CFG); 274 275 cfg |= HPET_CFG_LEGACY; 276 hpet_writel(cfg, HPET_CFG); 277 hpet_legacy_int_enabled = true; 278 } 279 280 static void hpet_legacy_clockevent_register(void) 281 { 282 /* Start HPET legacy interrupts */ 283 hpet_enable_legacy_int(); 284 285 /* 286 * Start hpet with the boot cpu mask and make it 287 * global after the IO_APIC has been initialized. 288 */ 289 hpet_clockevent.cpumask = cpumask_of(boot_cpu_data.cpu_index); 290 clockevents_config_and_register(&hpet_clockevent, hpet_freq, 291 HPET_MIN_PROG_DELTA, 0x7FFFFFFF); 292 global_clock_event = &hpet_clockevent; 293 printk(KERN_DEBUG "hpet clockevent registered\n"); 294 } 295 296 static int hpet_set_periodic(struct clock_event_device *evt, int timer) 297 { 298 unsigned int cfg, cmp, now; 299 uint64_t delta; 300 301 hpet_stop_counter(); 302 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult; 303 delta >>= evt->shift; 304 now = hpet_readl(HPET_COUNTER); 305 cmp = now + (unsigned int)delta; 306 cfg = hpet_readl(HPET_Tn_CFG(timer)); 307 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL | 308 HPET_TN_32BIT; 309 hpet_writel(cfg, HPET_Tn_CFG(timer)); 310 hpet_writel(cmp, HPET_Tn_CMP(timer)); 311 udelay(1); 312 /* 313 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL 314 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL 315 * bit is automatically cleared after the first write. 316 * (See AMD-8111 HyperTransport I/O Hub Data Sheet, 317 * Publication # 24674) 318 */ 319 hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer)); 320 hpet_start_counter(); 321 hpet_print_config(); 322 323 return 0; 324 } 325 326 static int hpet_set_oneshot(struct clock_event_device *evt, int timer) 327 { 328 unsigned int cfg; 329 330 cfg = hpet_readl(HPET_Tn_CFG(timer)); 331 cfg &= ~HPET_TN_PERIODIC; 332 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 333 hpet_writel(cfg, HPET_Tn_CFG(timer)); 334 335 return 0; 336 } 337 338 static int hpet_shutdown(struct clock_event_device *evt, int timer) 339 { 340 unsigned int cfg; 341 342 cfg = hpet_readl(HPET_Tn_CFG(timer)); 343 cfg &= ~HPET_TN_ENABLE; 344 hpet_writel(cfg, HPET_Tn_CFG(timer)); 345 346 return 0; 347 } 348 349 static int hpet_resume(struct clock_event_device *evt) 350 { 351 hpet_enable_legacy_int(); 352 hpet_print_config(); 353 return 0; 354 } 355 356 static int hpet_next_event(unsigned long delta, 357 struct clock_event_device *evt, int timer) 358 { 359 u32 cnt; 360 s32 res; 361 362 cnt = hpet_readl(HPET_COUNTER); 363 cnt += (u32) delta; 364 hpet_writel(cnt, HPET_Tn_CMP(timer)); 365 366 /* 367 * HPETs are a complete disaster. The compare register is 368 * based on a equal comparison and neither provides a less 369 * than or equal functionality (which would require to take 370 * the wraparound into account) nor a simple count down event 371 * mode. Further the write to the comparator register is 372 * delayed internally up to two HPET clock cycles in certain 373 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even 374 * longer delays. We worked around that by reading back the 375 * compare register, but that required another workaround for 376 * ICH9,10 chips where the first readout after write can 377 * return the old stale value. We already had a minimum 378 * programming delta of 5us enforced, but a NMI or SMI hitting 379 * between the counter readout and the comparator write can 380 * move us behind that point easily. Now instead of reading 381 * the compare register back several times, we make the ETIME 382 * decision based on the following: Return ETIME if the 383 * counter value after the write is less than HPET_MIN_CYCLES 384 * away from the event or if the counter is already ahead of 385 * the event. The minimum programming delta for the generic 386 * clockevents code is set to 1.5 * HPET_MIN_CYCLES. 387 */ 388 res = (s32)(cnt - hpet_readl(HPET_COUNTER)); 389 390 return res < HPET_MIN_CYCLES ? -ETIME : 0; 391 } 392 393 static int hpet_legacy_shutdown(struct clock_event_device *evt) 394 { 395 return hpet_shutdown(evt, 0); 396 } 397 398 static int hpet_legacy_set_oneshot(struct clock_event_device *evt) 399 { 400 return hpet_set_oneshot(evt, 0); 401 } 402 403 static int hpet_legacy_set_periodic(struct clock_event_device *evt) 404 { 405 return hpet_set_periodic(evt, 0); 406 } 407 408 static int hpet_legacy_resume(struct clock_event_device *evt) 409 { 410 return hpet_resume(evt); 411 } 412 413 static int hpet_legacy_next_event(unsigned long delta, 414 struct clock_event_device *evt) 415 { 416 return hpet_next_event(delta, evt, 0); 417 } 418 419 /* 420 * The hpet clock event device 421 */ 422 static struct clock_event_device hpet_clockevent = { 423 .name = "hpet", 424 .features = CLOCK_EVT_FEAT_PERIODIC | 425 CLOCK_EVT_FEAT_ONESHOT, 426 .set_state_periodic = hpet_legacy_set_periodic, 427 .set_state_oneshot = hpet_legacy_set_oneshot, 428 .set_state_shutdown = hpet_legacy_shutdown, 429 .tick_resume = hpet_legacy_resume, 430 .set_next_event = hpet_legacy_next_event, 431 .irq = 0, 432 .rating = 50, 433 }; 434 435 /* 436 * HPET MSI Support 437 */ 438 #ifdef CONFIG_PCI_MSI 439 440 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); 441 static struct hpet_dev *hpet_devs; 442 static struct irq_domain *hpet_domain; 443 444 void hpet_msi_unmask(struct irq_data *data) 445 { 446 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data); 447 unsigned int cfg; 448 449 /* unmask it */ 450 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 451 cfg |= HPET_TN_ENABLE | HPET_TN_FSB; 452 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 453 } 454 455 void hpet_msi_mask(struct irq_data *data) 456 { 457 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data); 458 unsigned int cfg; 459 460 /* mask it */ 461 cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); 462 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB); 463 hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); 464 } 465 466 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg) 467 { 468 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); 469 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); 470 } 471 472 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg) 473 { 474 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); 475 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); 476 msg->address_hi = 0; 477 } 478 479 static int hpet_msi_shutdown(struct clock_event_device *evt) 480 { 481 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 482 483 return hpet_shutdown(evt, hdev->num); 484 } 485 486 static int hpet_msi_set_oneshot(struct clock_event_device *evt) 487 { 488 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 489 490 return hpet_set_oneshot(evt, hdev->num); 491 } 492 493 static int hpet_msi_set_periodic(struct clock_event_device *evt) 494 { 495 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 496 497 return hpet_set_periodic(evt, hdev->num); 498 } 499 500 static int hpet_msi_resume(struct clock_event_device *evt) 501 { 502 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 503 struct irq_data *data = irq_get_irq_data(hdev->irq); 504 struct msi_msg msg; 505 506 /* Restore the MSI msg and unmask the interrupt */ 507 irq_chip_compose_msi_msg(data, &msg); 508 hpet_msi_write(hdev, &msg); 509 hpet_msi_unmask(data); 510 return 0; 511 } 512 513 static int hpet_msi_next_event(unsigned long delta, 514 struct clock_event_device *evt) 515 { 516 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); 517 return hpet_next_event(delta, evt, hdev->num); 518 } 519 520 static irqreturn_t hpet_interrupt_handler(int irq, void *data) 521 { 522 struct hpet_dev *dev = (struct hpet_dev *)data; 523 struct clock_event_device *hevt = &dev->evt; 524 525 if (!hevt->event_handler) { 526 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", 527 dev->num); 528 return IRQ_HANDLED; 529 } 530 531 hevt->event_handler(hevt); 532 return IRQ_HANDLED; 533 } 534 535 static int hpet_setup_irq(struct hpet_dev *dev) 536 { 537 538 if (request_irq(dev->irq, hpet_interrupt_handler, 539 IRQF_TIMER | IRQF_NOBALANCING, 540 dev->name, dev)) 541 return -1; 542 543 disable_irq(dev->irq); 544 irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); 545 enable_irq(dev->irq); 546 547 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", 548 dev->name, dev->irq); 549 550 return 0; 551 } 552 553 /* This should be called in specific @cpu */ 554 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) 555 { 556 struct clock_event_device *evt = &hdev->evt; 557 558 WARN_ON(cpu != smp_processor_id()); 559 if (!(hdev->flags & HPET_DEV_VALID)) 560 return; 561 562 hdev->cpu = cpu; 563 per_cpu(cpu_hpet_dev, cpu) = hdev; 564 evt->name = hdev->name; 565 hpet_setup_irq(hdev); 566 evt->irq = hdev->irq; 567 568 evt->rating = 110; 569 evt->features = CLOCK_EVT_FEAT_ONESHOT; 570 if (hdev->flags & HPET_DEV_PERI_CAP) { 571 evt->features |= CLOCK_EVT_FEAT_PERIODIC; 572 evt->set_state_periodic = hpet_msi_set_periodic; 573 } 574 575 evt->set_state_shutdown = hpet_msi_shutdown; 576 evt->set_state_oneshot = hpet_msi_set_oneshot; 577 evt->tick_resume = hpet_msi_resume; 578 evt->set_next_event = hpet_msi_next_event; 579 evt->cpumask = cpumask_of(hdev->cpu); 580 581 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA, 582 0x7FFFFFFF); 583 } 584 585 #ifdef CONFIG_HPET 586 /* Reserve at least one timer for userspace (/dev/hpet) */ 587 #define RESERVE_TIMERS 1 588 #else 589 #define RESERVE_TIMERS 0 590 #endif 591 592 static void hpet_msi_capability_lookup(unsigned int start_timer) 593 { 594 unsigned int id; 595 unsigned int num_timers; 596 unsigned int num_timers_used = 0; 597 int i, irq; 598 599 if (hpet_msi_disable) 600 return; 601 602 if (boot_cpu_has(X86_FEATURE_ARAT)) 603 return; 604 id = hpet_readl(HPET_ID); 605 606 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); 607 num_timers++; /* Value read out starts from 0 */ 608 hpet_print_config(); 609 610 hpet_domain = hpet_create_irq_domain(hpet_blockid); 611 if (!hpet_domain) 612 return; 613 614 hpet_devs = kcalloc(num_timers, sizeof(struct hpet_dev), GFP_KERNEL); 615 if (!hpet_devs) 616 return; 617 618 hpet_num_timers = num_timers; 619 620 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { 621 struct hpet_dev *hdev = &hpet_devs[num_timers_used]; 622 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); 623 624 /* Only consider HPET timer with MSI support */ 625 if (!(cfg & HPET_TN_FSB_CAP)) 626 continue; 627 628 hdev->flags = 0; 629 if (cfg & HPET_TN_PERIODIC_CAP) 630 hdev->flags |= HPET_DEV_PERI_CAP; 631 sprintf(hdev->name, "hpet%d", i); 632 hdev->num = i; 633 634 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num); 635 if (irq <= 0) 636 continue; 637 638 hdev->irq = irq; 639 hdev->flags |= HPET_DEV_FSB_CAP; 640 hdev->flags |= HPET_DEV_VALID; 641 num_timers_used++; 642 if (num_timers_used == num_possible_cpus()) 643 break; 644 } 645 646 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", 647 num_timers, num_timers_used); 648 } 649 650 #ifdef CONFIG_HPET 651 static void hpet_reserve_msi_timers(struct hpet_data *hd) 652 { 653 int i; 654 655 if (!hpet_devs) 656 return; 657 658 for (i = 0; i < hpet_num_timers; i++) { 659 struct hpet_dev *hdev = &hpet_devs[i]; 660 661 if (!(hdev->flags & HPET_DEV_VALID)) 662 continue; 663 664 hd->hd_irq[hdev->num] = hdev->irq; 665 hpet_reserve_timer(hd, hdev->num); 666 } 667 } 668 #endif 669 670 static struct hpet_dev *hpet_get_unused_timer(void) 671 { 672 int i; 673 674 if (!hpet_devs) 675 return NULL; 676 677 for (i = 0; i < hpet_num_timers; i++) { 678 struct hpet_dev *hdev = &hpet_devs[i]; 679 680 if (!(hdev->flags & HPET_DEV_VALID)) 681 continue; 682 if (test_and_set_bit(HPET_DEV_USED_BIT, 683 (unsigned long *)&hdev->flags)) 684 continue; 685 return hdev; 686 } 687 return NULL; 688 } 689 690 struct hpet_work_struct { 691 struct delayed_work work; 692 struct completion complete; 693 }; 694 695 static void hpet_work(struct work_struct *w) 696 { 697 struct hpet_dev *hdev; 698 int cpu = smp_processor_id(); 699 struct hpet_work_struct *hpet_work; 700 701 hpet_work = container_of(w, struct hpet_work_struct, work.work); 702 703 hdev = hpet_get_unused_timer(); 704 if (hdev) 705 init_one_hpet_msi_clockevent(hdev, cpu); 706 707 complete(&hpet_work->complete); 708 } 709 710 static int hpet_cpuhp_online(unsigned int cpu) 711 { 712 struct hpet_work_struct work; 713 714 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work); 715 init_completion(&work.complete); 716 /* FIXME: add schedule_work_on() */ 717 schedule_delayed_work_on(cpu, &work.work, 0); 718 wait_for_completion(&work.complete); 719 destroy_delayed_work_on_stack(&work.work); 720 return 0; 721 } 722 723 static int hpet_cpuhp_dead(unsigned int cpu) 724 { 725 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); 726 727 if (!hdev) 728 return 0; 729 free_irq(hdev->irq, hdev); 730 hdev->flags &= ~HPET_DEV_USED; 731 per_cpu(cpu_hpet_dev, cpu) = NULL; 732 return 0; 733 } 734 #else 735 736 static void hpet_msi_capability_lookup(unsigned int start_timer) 737 { 738 return; 739 } 740 741 #ifdef CONFIG_HPET 742 static void hpet_reserve_msi_timers(struct hpet_data *hd) 743 { 744 return; 745 } 746 #endif 747 748 #define hpet_cpuhp_online NULL 749 #define hpet_cpuhp_dead NULL 750 751 #endif 752 753 /* 754 * Clock source related code 755 */ 756 #if defined(CONFIG_SMP) && defined(CONFIG_64BIT) 757 /* 758 * Reading the HPET counter is a very slow operation. If a large number of 759 * CPUs are trying to access the HPET counter simultaneously, it can cause 760 * massive delay and slow down system performance dramatically. This may 761 * happen when HPET is the default clock source instead of TSC. For a 762 * really large system with hundreds of CPUs, the slowdown may be so 763 * severe that it may actually crash the system because of a NMI watchdog 764 * soft lockup, for example. 765 * 766 * If multiple CPUs are trying to access the HPET counter at the same time, 767 * we don't actually need to read the counter multiple times. Instead, the 768 * other CPUs can use the counter value read by the first CPU in the group. 769 * 770 * This special feature is only enabled on x86-64 systems. It is unlikely 771 * that 32-bit x86 systems will have enough CPUs to require this feature 772 * with its associated locking overhead. And we also need 64-bit atomic 773 * read. 774 * 775 * The lock and the hpet value are stored together and can be read in a 776 * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t 777 * is 32 bits in size. 778 */ 779 union hpet_lock { 780 struct { 781 arch_spinlock_t lock; 782 u32 value; 783 }; 784 u64 lockval; 785 }; 786 787 static union hpet_lock hpet __cacheline_aligned = { 788 { .lock = __ARCH_SPIN_LOCK_UNLOCKED, }, 789 }; 790 791 static u64 read_hpet(struct clocksource *cs) 792 { 793 unsigned long flags; 794 union hpet_lock old, new; 795 796 BUILD_BUG_ON(sizeof(union hpet_lock) != 8); 797 798 /* 799 * Read HPET directly if in NMI. 800 */ 801 if (in_nmi()) 802 return (u64)hpet_readl(HPET_COUNTER); 803 804 /* 805 * Read the current state of the lock and HPET value atomically. 806 */ 807 old.lockval = READ_ONCE(hpet.lockval); 808 809 if (arch_spin_is_locked(&old.lock)) 810 goto contended; 811 812 local_irq_save(flags); 813 if (arch_spin_trylock(&hpet.lock)) { 814 new.value = hpet_readl(HPET_COUNTER); 815 /* 816 * Use WRITE_ONCE() to prevent store tearing. 817 */ 818 WRITE_ONCE(hpet.value, new.value); 819 arch_spin_unlock(&hpet.lock); 820 local_irq_restore(flags); 821 return (u64)new.value; 822 } 823 local_irq_restore(flags); 824 825 contended: 826 /* 827 * Contended case 828 * -------------- 829 * Wait until the HPET value change or the lock is free to indicate 830 * its value is up-to-date. 831 * 832 * It is possible that old.value has already contained the latest 833 * HPET value while the lock holder was in the process of releasing 834 * the lock. Checking for lock state change will enable us to return 835 * the value immediately instead of waiting for the next HPET reader 836 * to come along. 837 */ 838 do { 839 cpu_relax(); 840 new.lockval = READ_ONCE(hpet.lockval); 841 } while ((new.value == old.value) && arch_spin_is_locked(&new.lock)); 842 843 return (u64)new.value; 844 } 845 #else 846 /* 847 * For UP or 32-bit. 848 */ 849 static u64 read_hpet(struct clocksource *cs) 850 { 851 return (u64)hpet_readl(HPET_COUNTER); 852 } 853 #endif 854 855 static struct clocksource clocksource_hpet = { 856 .name = "hpet", 857 .rating = 250, 858 .read = read_hpet, 859 .mask = HPET_MASK, 860 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 861 .resume = hpet_resume_counter, 862 }; 863 864 static int hpet_clocksource_register(void) 865 { 866 u64 start, now; 867 u64 t1; 868 869 /* Start the counter */ 870 hpet_restart_counter(); 871 872 /* Verify whether hpet counter works */ 873 t1 = hpet_readl(HPET_COUNTER); 874 start = rdtsc(); 875 876 /* 877 * We don't know the TSC frequency yet, but waiting for 878 * 200000 TSC cycles is safe: 879 * 4 GHz == 50us 880 * 1 GHz == 200us 881 */ 882 do { 883 rep_nop(); 884 now = rdtsc(); 885 } while ((now - start) < 200000UL); 886 887 if (t1 == hpet_readl(HPET_COUNTER)) { 888 printk(KERN_WARNING 889 "HPET counter not counting. HPET disabled\n"); 890 return -ENODEV; 891 } 892 893 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); 894 return 0; 895 } 896 897 static u32 *hpet_boot_cfg; 898 899 /** 900 * hpet_enable - Try to setup the HPET timer. Returns 1 on success. 901 */ 902 int __init hpet_enable(void) 903 { 904 u32 hpet_period, cfg, id; 905 u64 freq; 906 unsigned int i, last; 907 908 if (!is_hpet_capable()) 909 return 0; 910 911 hpet_set_mapping(); 912 913 /* 914 * Read the period and check for a sane value: 915 */ 916 hpet_period = hpet_readl(HPET_PERIOD); 917 918 /* 919 * AMD SB700 based systems with spread spectrum enabled use a 920 * SMM based HPET emulation to provide proper frequency 921 * setting. The SMM code is initialized with the first HPET 922 * register access and takes some time to complete. During 923 * this time the config register reads 0xffffffff. We check 924 * for max. 1000 loops whether the config register reads a non 925 * 0xffffffff value to make sure that HPET is up and running 926 * before we go further. A counting loop is safe, as the HPET 927 * access takes thousands of CPU cycles. On non SB700 based 928 * machines this check is only done once and has no side 929 * effects. 930 */ 931 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { 932 if (i == 1000) { 933 printk(KERN_WARNING 934 "HPET config register value = 0xFFFFFFFF. " 935 "Disabling HPET\n"); 936 goto out_nohpet; 937 } 938 } 939 940 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) 941 goto out_nohpet; 942 943 /* 944 * The period is a femto seconds value. Convert it to a 945 * frequency. 946 */ 947 freq = FSEC_PER_SEC; 948 do_div(freq, hpet_period); 949 hpet_freq = freq; 950 951 /* 952 * Read the HPET ID register to retrieve the IRQ routing 953 * information and the number of channels 954 */ 955 id = hpet_readl(HPET_ID); 956 hpet_print_config(); 957 958 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT; 959 960 #ifdef CONFIG_HPET_EMULATE_RTC 961 /* 962 * The legacy routing mode needs at least two channels, tick timer 963 * and the rtc emulation channel. 964 */ 965 if (!last) 966 goto out_nohpet; 967 #endif 968 969 cfg = hpet_readl(HPET_CFG); 970 hpet_boot_cfg = kmalloc_array(last + 2, sizeof(*hpet_boot_cfg), 971 GFP_KERNEL); 972 if (hpet_boot_cfg) 973 *hpet_boot_cfg = cfg; 974 else 975 pr_warn("HPET initial state will not be saved\n"); 976 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY); 977 hpet_writel(cfg, HPET_CFG); 978 if (cfg) 979 pr_warn("Unrecognized bits %#x set in global cfg\n", cfg); 980 981 for (i = 0; i <= last; ++i) { 982 cfg = hpet_readl(HPET_Tn_CFG(i)); 983 if (hpet_boot_cfg) 984 hpet_boot_cfg[i + 1] = cfg; 985 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB); 986 hpet_writel(cfg, HPET_Tn_CFG(i)); 987 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP 988 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE 989 | HPET_TN_FSB | HPET_TN_FSB_CAP); 990 if (cfg) 991 pr_warn("Unrecognized bits %#x set in cfg#%u\n", 992 cfg, i); 993 } 994 hpet_print_config(); 995 996 if (hpet_clocksource_register()) 997 goto out_nohpet; 998 999 if (id & HPET_ID_LEGSUP) { 1000 hpet_legacy_clockevent_register(); 1001 return 1; 1002 } 1003 return 0; 1004 1005 out_nohpet: 1006 hpet_clear_mapping(); 1007 hpet_address = 0; 1008 return 0; 1009 } 1010 1011 /* 1012 * Needs to be late, as the reserve_timer code calls kalloc ! 1013 * 1014 * Not a problem on i386 as hpet_enable is called from late_time_init, 1015 * but on x86_64 it is necessary ! 1016 */ 1017 static __init int hpet_late_init(void) 1018 { 1019 int ret; 1020 1021 if (boot_hpet_disable) 1022 return -ENODEV; 1023 1024 if (!hpet_address) { 1025 if (!force_hpet_address) 1026 return -ENODEV; 1027 1028 hpet_address = force_hpet_address; 1029 hpet_enable(); 1030 } 1031 1032 if (!hpet_virt_address) 1033 return -ENODEV; 1034 1035 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP) 1036 hpet_msi_capability_lookup(2); 1037 else 1038 hpet_msi_capability_lookup(0); 1039 1040 hpet_reserve_platform_timers(hpet_readl(HPET_ID)); 1041 hpet_print_config(); 1042 1043 if (hpet_msi_disable) 1044 return 0; 1045 1046 if (boot_cpu_has(X86_FEATURE_ARAT)) 1047 return 0; 1048 1049 /* This notifier should be called after workqueue is ready */ 1050 ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "x86/hpet:online", 1051 hpet_cpuhp_online, NULL); 1052 if (ret) 1053 return ret; 1054 ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "x86/hpet:dead", NULL, 1055 hpet_cpuhp_dead); 1056 if (ret) 1057 goto err_cpuhp; 1058 return 0; 1059 1060 err_cpuhp: 1061 cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE); 1062 return ret; 1063 } 1064 fs_initcall(hpet_late_init); 1065 1066 void hpet_disable(void) 1067 { 1068 if (is_hpet_capable() && hpet_virt_address) { 1069 unsigned int cfg = hpet_readl(HPET_CFG), id, last; 1070 1071 if (hpet_boot_cfg) 1072 cfg = *hpet_boot_cfg; 1073 else if (hpet_legacy_int_enabled) { 1074 cfg &= ~HPET_CFG_LEGACY; 1075 hpet_legacy_int_enabled = false; 1076 } 1077 cfg &= ~HPET_CFG_ENABLE; 1078 hpet_writel(cfg, HPET_CFG); 1079 1080 if (!hpet_boot_cfg) 1081 return; 1082 1083 id = hpet_readl(HPET_ID); 1084 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); 1085 1086 for (id = 0; id <= last; ++id) 1087 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id)); 1088 1089 if (*hpet_boot_cfg & HPET_CFG_ENABLE) 1090 hpet_writel(*hpet_boot_cfg, HPET_CFG); 1091 } 1092 } 1093 1094 #ifdef CONFIG_HPET_EMULATE_RTC 1095 1096 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET 1097 * is enabled, we support RTC interrupt functionality in software. 1098 * RTC has 3 kinds of interrupts: 1099 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock 1100 * is updated 1101 * 2) Alarm Interrupt - generate an interrupt at a specific time of day 1102 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies 1103 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) 1104 * (1) and (2) above are implemented using polling at a frequency of 1105 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt 1106 * overhead. (DEFAULT_RTC_INT_FREQ) 1107 * For (3), we use interrupts at 64Hz or user specified periodic 1108 * frequency, whichever is higher. 1109 */ 1110 #include <linux/mc146818rtc.h> 1111 #include <linux/rtc.h> 1112 1113 #define DEFAULT_RTC_INT_FREQ 64 1114 #define DEFAULT_RTC_SHIFT 6 1115 #define RTC_NUM_INTS 1 1116 1117 static unsigned long hpet_rtc_flags; 1118 static int hpet_prev_update_sec; 1119 static struct rtc_time hpet_alarm_time; 1120 static unsigned long hpet_pie_count; 1121 static u32 hpet_t1_cmp; 1122 static u32 hpet_default_delta; 1123 static u32 hpet_pie_delta; 1124 static unsigned long hpet_pie_limit; 1125 1126 static rtc_irq_handler irq_handler; 1127 1128 /* 1129 * Check that the hpet counter c1 is ahead of the c2 1130 */ 1131 static inline int hpet_cnt_ahead(u32 c1, u32 c2) 1132 { 1133 return (s32)(c2 - c1) < 0; 1134 } 1135 1136 /* 1137 * Registers a IRQ handler. 1138 */ 1139 int hpet_register_irq_handler(rtc_irq_handler handler) 1140 { 1141 if (!is_hpet_enabled()) 1142 return -ENODEV; 1143 if (irq_handler) 1144 return -EBUSY; 1145 1146 irq_handler = handler; 1147 1148 return 0; 1149 } 1150 EXPORT_SYMBOL_GPL(hpet_register_irq_handler); 1151 1152 /* 1153 * Deregisters the IRQ handler registered with hpet_register_irq_handler() 1154 * and does cleanup. 1155 */ 1156 void hpet_unregister_irq_handler(rtc_irq_handler handler) 1157 { 1158 if (!is_hpet_enabled()) 1159 return; 1160 1161 irq_handler = NULL; 1162 hpet_rtc_flags = 0; 1163 } 1164 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); 1165 1166 /* 1167 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode 1168 * is not supported by all HPET implementations for timer 1. 1169 * 1170 * hpet_rtc_timer_init() is called when the rtc is initialized. 1171 */ 1172 int hpet_rtc_timer_init(void) 1173 { 1174 unsigned int cfg, cnt, delta; 1175 unsigned long flags; 1176 1177 if (!is_hpet_enabled()) 1178 return 0; 1179 1180 if (!hpet_default_delta) { 1181 uint64_t clc; 1182 1183 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1184 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; 1185 hpet_default_delta = clc; 1186 } 1187 1188 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1189 delta = hpet_default_delta; 1190 else 1191 delta = hpet_pie_delta; 1192 1193 local_irq_save(flags); 1194 1195 cnt = delta + hpet_readl(HPET_COUNTER); 1196 hpet_writel(cnt, HPET_T1_CMP); 1197 hpet_t1_cmp = cnt; 1198 1199 cfg = hpet_readl(HPET_T1_CFG); 1200 cfg &= ~HPET_TN_PERIODIC; 1201 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; 1202 hpet_writel(cfg, HPET_T1_CFG); 1203 1204 local_irq_restore(flags); 1205 1206 return 1; 1207 } 1208 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); 1209 1210 static void hpet_disable_rtc_channel(void) 1211 { 1212 u32 cfg = hpet_readl(HPET_T1_CFG); 1213 cfg &= ~HPET_TN_ENABLE; 1214 hpet_writel(cfg, HPET_T1_CFG); 1215 } 1216 1217 /* 1218 * The functions below are called from rtc driver. 1219 * Return 0 if HPET is not being used. 1220 * Otherwise do the necessary changes and return 1. 1221 */ 1222 int hpet_mask_rtc_irq_bit(unsigned long bit_mask) 1223 { 1224 if (!is_hpet_enabled()) 1225 return 0; 1226 1227 hpet_rtc_flags &= ~bit_mask; 1228 if (unlikely(!hpet_rtc_flags)) 1229 hpet_disable_rtc_channel(); 1230 1231 return 1; 1232 } 1233 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); 1234 1235 int hpet_set_rtc_irq_bit(unsigned long bit_mask) 1236 { 1237 unsigned long oldbits = hpet_rtc_flags; 1238 1239 if (!is_hpet_enabled()) 1240 return 0; 1241 1242 hpet_rtc_flags |= bit_mask; 1243 1244 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) 1245 hpet_prev_update_sec = -1; 1246 1247 if (!oldbits) 1248 hpet_rtc_timer_init(); 1249 1250 return 1; 1251 } 1252 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); 1253 1254 int hpet_set_alarm_time(unsigned char hrs, unsigned char min, 1255 unsigned char sec) 1256 { 1257 if (!is_hpet_enabled()) 1258 return 0; 1259 1260 hpet_alarm_time.tm_hour = hrs; 1261 hpet_alarm_time.tm_min = min; 1262 hpet_alarm_time.tm_sec = sec; 1263 1264 return 1; 1265 } 1266 EXPORT_SYMBOL_GPL(hpet_set_alarm_time); 1267 1268 int hpet_set_periodic_freq(unsigned long freq) 1269 { 1270 uint64_t clc; 1271 1272 if (!is_hpet_enabled()) 1273 return 0; 1274 1275 if (freq <= DEFAULT_RTC_INT_FREQ) 1276 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; 1277 else { 1278 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; 1279 do_div(clc, freq); 1280 clc >>= hpet_clockevent.shift; 1281 hpet_pie_delta = clc; 1282 hpet_pie_limit = 0; 1283 } 1284 return 1; 1285 } 1286 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); 1287 1288 int hpet_rtc_dropped_irq(void) 1289 { 1290 return is_hpet_enabled(); 1291 } 1292 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); 1293 1294 static void hpet_rtc_timer_reinit(void) 1295 { 1296 unsigned int delta; 1297 int lost_ints = -1; 1298 1299 if (unlikely(!hpet_rtc_flags)) 1300 hpet_disable_rtc_channel(); 1301 1302 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) 1303 delta = hpet_default_delta; 1304 else 1305 delta = hpet_pie_delta; 1306 1307 /* 1308 * Increment the comparator value until we are ahead of the 1309 * current count. 1310 */ 1311 do { 1312 hpet_t1_cmp += delta; 1313 hpet_writel(hpet_t1_cmp, HPET_T1_CMP); 1314 lost_ints++; 1315 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); 1316 1317 if (lost_ints) { 1318 if (hpet_rtc_flags & RTC_PIE) 1319 hpet_pie_count += lost_ints; 1320 if (printk_ratelimit()) 1321 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", 1322 lost_ints); 1323 } 1324 } 1325 1326 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) 1327 { 1328 struct rtc_time curr_time; 1329 unsigned long rtc_int_flag = 0; 1330 1331 hpet_rtc_timer_reinit(); 1332 memset(&curr_time, 0, sizeof(struct rtc_time)); 1333 1334 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) 1335 mc146818_get_time(&curr_time); 1336 1337 if (hpet_rtc_flags & RTC_UIE && 1338 curr_time.tm_sec != hpet_prev_update_sec) { 1339 if (hpet_prev_update_sec >= 0) 1340 rtc_int_flag = RTC_UF; 1341 hpet_prev_update_sec = curr_time.tm_sec; 1342 } 1343 1344 if (hpet_rtc_flags & RTC_PIE && 1345 ++hpet_pie_count >= hpet_pie_limit) { 1346 rtc_int_flag |= RTC_PF; 1347 hpet_pie_count = 0; 1348 } 1349 1350 if (hpet_rtc_flags & RTC_AIE && 1351 (curr_time.tm_sec == hpet_alarm_time.tm_sec) && 1352 (curr_time.tm_min == hpet_alarm_time.tm_min) && 1353 (curr_time.tm_hour == hpet_alarm_time.tm_hour)) 1354 rtc_int_flag |= RTC_AF; 1355 1356 if (rtc_int_flag) { 1357 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); 1358 if (irq_handler) 1359 irq_handler(rtc_int_flag, dev_id); 1360 } 1361 return IRQ_HANDLED; 1362 } 1363 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); 1364 #endif 1365