1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 4 * 5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 10 */ 11 12 13#include <linux/linkage.h> 14#include <linux/threads.h> 15#include <linux/init.h> 16#include <linux/pgtable.h> 17#include <asm/segment.h> 18#include <asm/page.h> 19#include <asm/msr.h> 20#include <asm/cache.h> 21#include <asm/processor-flags.h> 22#include <asm/percpu.h> 23#include <asm/nops.h> 24#include "../entry/calling.h" 25#include <asm/export.h> 26#include <asm/nospec-branch.h> 27#include <asm/fixmap.h> 28 29#ifdef CONFIG_PARAVIRT_XXL 30#include <asm/asm-offsets.h> 31#include <asm/paravirt.h> 32#define GET_CR2_INTO(reg) GET_CR2_INTO_AX ; _ASM_MOV %_ASM_AX, reg 33#else 34#define INTERRUPT_RETURN iretq 35#define GET_CR2_INTO(reg) _ASM_MOV %cr2, reg 36#endif 37 38/* 39 * We are not able to switch in one step to the final KERNEL ADDRESS SPACE 40 * because we need identity-mapped pages. 41 */ 42#define l4_index(x) (((x) >> 39) & 511) 43#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 44 45L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4) 46L4_START_KERNEL = l4_index(__START_KERNEL_map) 47 48L3_START_KERNEL = pud_index(__START_KERNEL_map) 49 50 .text 51 __HEAD 52 .code64 53SYM_CODE_START_NOALIGN(startup_64) 54 UNWIND_HINT_EMPTY 55 /* 56 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 57 * and someone has loaded an identity mapped page table 58 * for us. These identity mapped page tables map all of the 59 * kernel pages and possibly all of memory. 60 * 61 * %rsi holds a physical pointer to real_mode_data. 62 * 63 * We come here either directly from a 64bit bootloader, or from 64 * arch/x86/boot/compressed/head_64.S. 65 * 66 * We only come here initially at boot nothing else comes here. 67 * 68 * Since we may be loaded at an address different from what we were 69 * compiled to run at we first fixup the physical addresses in our page 70 * tables and then reload them. 71 */ 72 73 /* Set up the stack for verify_cpu(), similar to initial_stack below */ 74 leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp 75 76 leaq _text(%rip), %rdi 77 pushq %rsi 78 call startup_64_setup_env 79 popq %rsi 80 81 /* Now switch to __KERNEL_CS so IRET works reliably */ 82 pushq $__KERNEL_CS 83 leaq .Lon_kernel_cs(%rip), %rax 84 pushq %rax 85 lretq 86 87.Lon_kernel_cs: 88 UNWIND_HINT_EMPTY 89 90 /* Sanitize CPU configuration */ 91 call verify_cpu 92 93 /* 94 * Perform pagetable fixups. Additionally, if SME is active, encrypt 95 * the kernel and retrieve the modifier (SME encryption mask if SME 96 * is active) to be added to the initial pgdir entry that will be 97 * programmed into CR3. 98 */ 99 leaq _text(%rip), %rdi 100 pushq %rsi 101 call __startup_64 102 popq %rsi 103 104 /* Form the CR3 value being sure to include the CR3 modifier */ 105 addq $(early_top_pgt - __START_KERNEL_map), %rax 106 jmp 1f 107SYM_CODE_END(startup_64) 108 109SYM_CODE_START(secondary_startup_64) 110 UNWIND_HINT_EMPTY 111 /* 112 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 113 * and someone has loaded a mapped page table. 114 * 115 * %rsi holds a physical pointer to real_mode_data. 116 * 117 * We come here either from startup_64 (using physical addresses) 118 * or from trampoline.S (using virtual addresses). 119 * 120 * Using virtual addresses from trampoline.S removes the need 121 * to have any identity mapped pages in the kernel page table 122 * after the boot processor executes this code. 123 */ 124 125 /* Sanitize CPU configuration */ 126 call verify_cpu 127 128 /* 129 * The secondary_startup_64_no_verify entry point is only used by 130 * SEV-ES guests. In those guests the call to verify_cpu() would cause 131 * #VC exceptions which can not be handled at this stage of secondary 132 * CPU bringup. 133 * 134 * All non SEV-ES systems, especially Intel systems, need to execute 135 * verify_cpu() above to make sure NX is enabled. 136 */ 137SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) 138 UNWIND_HINT_EMPTY 139 140 /* 141 * Retrieve the modifier (SME encryption mask if SME is active) to be 142 * added to the initial pgdir entry that will be programmed into CR3. 143 */ 144 pushq %rsi 145 call __startup_secondary_64 146 popq %rsi 147 148 /* Form the CR3 value being sure to include the CR3 modifier */ 149 addq $(init_top_pgt - __START_KERNEL_map), %rax 1501: 151 152 /* Enable PAE mode, PGE and LA57 */ 153 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx 154#ifdef CONFIG_X86_5LEVEL 155 testl $1, __pgtable_l5_enabled(%rip) 156 jz 1f 157 orl $X86_CR4_LA57, %ecx 1581: 159#endif 160 movq %rcx, %cr4 161 162 /* Setup early boot stage 4-/5-level pagetables. */ 163 addq phys_base(%rip), %rax 164 165 /* 166 * For SEV guests: Verify that the C-bit is correct. A malicious 167 * hypervisor could lie about the C-bit position to perform a ROP 168 * attack on the guest by writing to the unencrypted stack and wait for 169 * the next RET instruction. 170 * %rsi carries pointer to realmode data and is callee-clobbered. Save 171 * and restore it. 172 */ 173 pushq %rsi 174 movq %rax, %rdi 175 call sev_verify_cbit 176 popq %rsi 177 178 /* Switch to new page-table */ 179 movq %rax, %cr3 180 181 /* Ensure I am executing from virtual addresses */ 182 movq $1f, %rax 183 ANNOTATE_RETPOLINE_SAFE 184 jmp *%rax 1851: 186 UNWIND_HINT_EMPTY 187 188 /* 189 * We must switch to a new descriptor in kernel space for the GDT 190 * because soon the kernel won't have access anymore to the userspace 191 * addresses where we're currently running on. We have to do that here 192 * because in 32bit we couldn't load a 64bit linear address. 193 */ 194 lgdt early_gdt_descr(%rip) 195 196 /* set up data segments */ 197 xorl %eax,%eax 198 movl %eax,%ds 199 movl %eax,%ss 200 movl %eax,%es 201 202 /* 203 * We don't really need to load %fs or %gs, but load them anyway 204 * to kill any stale realmode selectors. This allows execution 205 * under VT hardware. 206 */ 207 movl %eax,%fs 208 movl %eax,%gs 209 210 /* Set up %gs. 211 * 212 * The base of %gs always points to fixed_percpu_data. If the 213 * stack protector canary is enabled, it is located at %gs:40. 214 * Note that, on SMP, the boot cpu uses init data section until 215 * the per cpu areas are set up. 216 */ 217 movl $MSR_GS_BASE,%ecx 218 movl initial_gs(%rip),%eax 219 movl initial_gs+4(%rip),%edx 220 wrmsr 221 222 /* 223 * Setup a boot time stack - Any secondary CPU will have lost its stack 224 * by now because the cr3-switch above unmaps the real-mode stack 225 */ 226 movq initial_stack(%rip), %rsp 227 228 /* Setup and Load IDT */ 229 pushq %rsi 230 call early_setup_idt 231 popq %rsi 232 233 /* Check if nx is implemented */ 234 movl $0x80000001, %eax 235 cpuid 236 movl %edx,%edi 237 238 /* Setup EFER (Extended Feature Enable Register) */ 239 movl $MSR_EFER, %ecx 240 rdmsr 241 btsl $_EFER_SCE, %eax /* Enable System Call */ 242 btl $20,%edi /* No Execute supported? */ 243 jnc 1f 244 btsl $_EFER_NX, %eax 245 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 2461: wrmsr /* Make changes effective */ 247 248 /* Setup cr0 */ 249 movl $CR0_STATE, %eax 250 /* Make changes effective */ 251 movq %rax, %cr0 252 253 /* zero EFLAGS after setting rsp */ 254 pushq $0 255 popfq 256 257 /* rsi is pointer to real mode structure with interesting info. 258 pass it to C */ 259 movq %rsi, %rdi 260 261.Ljump_to_C_code: 262 /* 263 * Jump to run C code and to be on a real kernel address. 264 * Since we are running on identity-mapped space we have to jump 265 * to the full 64bit address, this is only possible as indirect 266 * jump. In addition we need to ensure %cs is set so we make this 267 * a far return. 268 * 269 * Note: do not change to far jump indirect with 64bit offset. 270 * 271 * AMD does not support far jump indirect with 64bit offset. 272 * AMD64 Architecture Programmer's Manual, Volume 3: states only 273 * JMP FAR mem16:16 FF /5 Far jump indirect, 274 * with the target specified by a far pointer in memory. 275 * JMP FAR mem16:32 FF /5 Far jump indirect, 276 * with the target specified by a far pointer in memory. 277 * 278 * Intel64 does support 64bit offset. 279 * Software Developer Manual Vol 2: states: 280 * FF /5 JMP m16:16 Jump far, absolute indirect, 281 * address given in m16:16 282 * FF /5 JMP m16:32 Jump far, absolute indirect, 283 * address given in m16:32. 284 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, 285 * address given in m16:64. 286 */ 287 pushq $.Lafter_lret # put return address on stack for unwinder 288 xorl %ebp, %ebp # clear frame pointer 289 movq initial_code(%rip), %rax 290 pushq $__KERNEL_CS # set correct cs 291 pushq %rax # target address in negative space 292 lretq 293.Lafter_lret: 294SYM_CODE_END(secondary_startup_64) 295 296#include "verify_cpu.S" 297#include "sev_verify_cbit.S" 298 299#ifdef CONFIG_HOTPLUG_CPU 300/* 301 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set 302 * up already except stack. We just set up stack here. Then call 303 * start_secondary() via .Ljump_to_C_code. 304 */ 305SYM_CODE_START(start_cpu0) 306 UNWIND_HINT_EMPTY 307 movq initial_stack(%rip), %rsp 308 jmp .Ljump_to_C_code 309SYM_CODE_END(start_cpu0) 310#endif 311 312#ifdef CONFIG_AMD_MEM_ENCRYPT 313/* 314 * VC Exception handler used during early boot when running on kernel 315 * addresses, but before the switch to the idt_table can be made. 316 * The early_idt_handler_array can't be used here because it calls into a lot 317 * of __init code and this handler is also used during CPU offlining/onlining. 318 * Therefore this handler ends up in the .text section so that it stays around 319 * when .init.text is freed. 320 */ 321SYM_CODE_START_NOALIGN(vc_boot_ghcb) 322 UNWIND_HINT_IRET_REGS offset=8 323 324 /* Build pt_regs */ 325 PUSH_AND_CLEAR_REGS 326 327 /* Call C handler */ 328 movq %rsp, %rdi 329 movq ORIG_RAX(%rsp), %rsi 330 movq initial_vc_handler(%rip), %rax 331 ANNOTATE_RETPOLINE_SAFE 332 call *%rax 333 334 /* Unwind pt_regs */ 335 POP_REGS 336 337 /* Remove Error Code */ 338 addq $8, %rsp 339 340 /* Pure iret required here - don't use INTERRUPT_RETURN */ 341 iretq 342SYM_CODE_END(vc_boot_ghcb) 343#endif 344 345 /* Both SMP bootup and ACPI suspend change these variables */ 346 __REFDATA 347 .balign 8 348SYM_DATA(initial_code, .quad x86_64_start_kernel) 349SYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data)) 350#ifdef CONFIG_AMD_MEM_ENCRYPT 351SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb) 352#endif 353 354/* 355 * The SIZEOF_PTREGS gap is a convention which helps the in-kernel unwinder 356 * reliably detect the end of the stack. 357 */ 358SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS) 359 __FINITDATA 360 361 __INIT 362SYM_CODE_START(early_idt_handler_array) 363 i = 0 364 .rept NUM_EXCEPTION_VECTORS 365 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 366 UNWIND_HINT_IRET_REGS 367 pushq $0 # Dummy error code, to make stack frame uniform 368 .else 369 UNWIND_HINT_IRET_REGS offset=8 370 .endif 371 pushq $i # 72(%rsp) Vector number 372 jmp early_idt_handler_common 373 UNWIND_HINT_IRET_REGS 374 i = i + 1 375 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc 376 .endr 377 UNWIND_HINT_IRET_REGS offset=16 378SYM_CODE_END(early_idt_handler_array) 379 380SYM_CODE_START_LOCAL(early_idt_handler_common) 381 /* 382 * The stack is the hardware frame, an error code or zero, and the 383 * vector number. 384 */ 385 cld 386 387 incl early_recursion_flag(%rip) 388 389 /* The vector number is currently in the pt_regs->di slot. */ 390 pushq %rsi /* pt_regs->si */ 391 movq 8(%rsp), %rsi /* RSI = vector number */ 392 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ 393 pushq %rdx /* pt_regs->dx */ 394 pushq %rcx /* pt_regs->cx */ 395 pushq %rax /* pt_regs->ax */ 396 pushq %r8 /* pt_regs->r8 */ 397 pushq %r9 /* pt_regs->r9 */ 398 pushq %r10 /* pt_regs->r10 */ 399 pushq %r11 /* pt_regs->r11 */ 400 pushq %rbx /* pt_regs->bx */ 401 pushq %rbp /* pt_regs->bp */ 402 pushq %r12 /* pt_regs->r12 */ 403 pushq %r13 /* pt_regs->r13 */ 404 pushq %r14 /* pt_regs->r14 */ 405 pushq %r15 /* pt_regs->r15 */ 406 UNWIND_HINT_REGS 407 408 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ 409 call do_early_exception 410 411 decl early_recursion_flag(%rip) 412 jmp restore_regs_and_return_to_kernel 413SYM_CODE_END(early_idt_handler_common) 414 415#ifdef CONFIG_AMD_MEM_ENCRYPT 416/* 417 * VC Exception handler used during very early boot. The 418 * early_idt_handler_array can't be used because it returns via the 419 * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early. 420 * 421 * This handler will end up in the .init.text section and not be 422 * available to boot secondary CPUs. 423 */ 424SYM_CODE_START_NOALIGN(vc_no_ghcb) 425 UNWIND_HINT_IRET_REGS offset=8 426 427 /* Build pt_regs */ 428 PUSH_AND_CLEAR_REGS 429 430 /* Call C handler */ 431 movq %rsp, %rdi 432 movq ORIG_RAX(%rsp), %rsi 433 call do_vc_no_ghcb 434 435 /* Unwind pt_regs */ 436 POP_REGS 437 438 /* Remove Error Code */ 439 addq $8, %rsp 440 441 /* Pure iret required here - don't use INTERRUPT_RETURN */ 442 iretq 443SYM_CODE_END(vc_no_ghcb) 444#endif 445 446#define SYM_DATA_START_PAGE_ALIGNED(name) \ 447 SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE) 448 449#ifdef CONFIG_PAGE_TABLE_ISOLATION 450/* 451 * Each PGD needs to be 8k long and 8k aligned. We do not 452 * ever go out to userspace with these, so we do not 453 * strictly *need* the second page, but this allows us to 454 * have a single set_pgd() implementation that does not 455 * need to worry about whether it has 4k or 8k to work 456 * with. 457 * 458 * This ensures PGDs are 8k long: 459 */ 460#define PTI_USER_PGD_FILL 512 461/* This ensures they are 8k-aligned: */ 462#define SYM_DATA_START_PTI_ALIGNED(name) \ 463 SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE) 464#else 465#define SYM_DATA_START_PTI_ALIGNED(name) \ 466 SYM_DATA_START_PAGE_ALIGNED(name) 467#define PTI_USER_PGD_FILL 0 468#endif 469 470/* Automate the creation of 1 to 1 mapping pmd entries */ 471#define PMDS(START, PERM, COUNT) \ 472 i = 0 ; \ 473 .rept (COUNT) ; \ 474 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 475 i = i + 1 ; \ 476 .endr 477 478 __INITDATA 479 .balign 4 480 481SYM_DATA_START_PTI_ALIGNED(early_top_pgt) 482 .fill 512,8,0 483 .fill PTI_USER_PGD_FILL,8,0 484SYM_DATA_END(early_top_pgt) 485 486SYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts) 487 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 488SYM_DATA_END(early_dynamic_pgts) 489 490SYM_DATA(early_recursion_flag, .long 0) 491 492 .data 493 494#if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH) 495SYM_DATA_START_PTI_ALIGNED(init_top_pgt) 496 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 497 .org init_top_pgt + L4_PAGE_OFFSET*8, 0 498 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 499 .org init_top_pgt + L4_START_KERNEL*8, 0 500 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 501 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 502 .fill PTI_USER_PGD_FILL,8,0 503SYM_DATA_END(init_top_pgt) 504 505SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt) 506 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 507 .fill 511, 8, 0 508SYM_DATA_END(level3_ident_pgt) 509SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt) 510 /* 511 * Since I easily can, map the first 1G. 512 * Don't set NX because code runs from these pages. 513 * 514 * Note: This sets _PAGE_GLOBAL despite whether 515 * the CPU supports it or it is enabled. But, 516 * the CPU should ignore the bit. 517 */ 518 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 519SYM_DATA_END(level2_ident_pgt) 520#else 521SYM_DATA_START_PTI_ALIGNED(init_top_pgt) 522 .fill 512,8,0 523 .fill PTI_USER_PGD_FILL,8,0 524SYM_DATA_END(init_top_pgt) 525#endif 526 527#ifdef CONFIG_X86_5LEVEL 528SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt) 529 .fill 511,8,0 530 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 531SYM_DATA_END(level4_kernel_pgt) 532#endif 533 534SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt) 535 .fill L3_START_KERNEL,8,0 536 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 537 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 538 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 539SYM_DATA_END(level3_kernel_pgt) 540 541SYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt) 542 /* 543 * 512 MB kernel mapping. We spend a full page on this pagetable 544 * anyway. 545 * 546 * The kernel code+data+bss must not be bigger than that. 547 * 548 * (NOTE: at +512MB starts the module area, see MODULES_VADDR. 549 * If you want to increase this then increase MODULES_VADDR 550 * too.) 551 * 552 * This table is eventually used by the kernel during normal 553 * runtime. Care must be taken to clear out undesired bits 554 * later, like _PAGE_RW or _PAGE_GLOBAL in some cases. 555 */ 556 PMDS(0, __PAGE_KERNEL_LARGE_EXEC, 557 KERNEL_IMAGE_SIZE/PMD_SIZE) 558SYM_DATA_END(level2_kernel_pgt) 559 560SYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt) 561 .fill (512 - 4 - FIXMAP_PMD_NUM),8,0 562 pgtno = 0 563 .rept (FIXMAP_PMD_NUM) 564 .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \ 565 + _PAGE_TABLE_NOENC; 566 pgtno = pgtno + 1 567 .endr 568 /* 6 MB reserved space + a 2MB hole */ 569 .fill 4,8,0 570SYM_DATA_END(level2_fixmap_pgt) 571 572SYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt) 573 .rept (FIXMAP_PMD_NUM) 574 .fill 512,8,0 575 .endr 576SYM_DATA_END(level1_fixmap_pgt) 577 578#undef PMDS 579 580 .data 581 .align 16 582 583SYM_DATA(early_gdt_descr, .word GDT_ENTRIES*8-1) 584SYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page)) 585 586 .align 16 587/* This must match the first entry in level2_kernel_pgt */ 588SYM_DATA(phys_base, .quad 0x0) 589EXPORT_SYMBOL(phys_base) 590 591#include "../../x86/xen/xen-head.S" 592 593 __PAGE_ALIGNED_BSS 594SYM_DATA_START_PAGE_ALIGNED(empty_zero_page) 595 .skip PAGE_SIZE 596SYM_DATA_END(empty_zero_page) 597EXPORT_SYMBOL(empty_zero_page) 598 599