1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * prepare to run common code 4 * 5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 6 */ 7 8 #define DISABLE_BRANCH_PROFILING 9 10 /* cpu_feature_enabled() cannot be used this early */ 11 #define USE_EARLY_PGTABLE_L5 12 13 #include <linux/init.h> 14 #include <linux/linkage.h> 15 #include <linux/types.h> 16 #include <linux/kernel.h> 17 #include <linux/string.h> 18 #include <linux/percpu.h> 19 #include <linux/start_kernel.h> 20 #include <linux/io.h> 21 #include <linux/memblock.h> 22 #include <linux/cc_platform.h> 23 #include <linux/pgtable.h> 24 25 #include <asm/processor.h> 26 #include <asm/proto.h> 27 #include <asm/smp.h> 28 #include <asm/setup.h> 29 #include <asm/desc.h> 30 #include <asm/tlbflush.h> 31 #include <asm/sections.h> 32 #include <asm/kdebug.h> 33 #include <asm/e820/api.h> 34 #include <asm/bios_ebda.h> 35 #include <asm/bootparam_utils.h> 36 #include <asm/microcode.h> 37 #include <asm/kasan.h> 38 #include <asm/fixmap.h> 39 #include <asm/realmode.h> 40 #include <asm/extable.h> 41 #include <asm/trapnr.h> 42 #include <asm/sev.h> 43 44 /* 45 * Manage page tables very early on. 46 */ 47 extern pmd_t early_dynamic_pgts[EARLY_DYNAMIC_PAGE_TABLES][PTRS_PER_PMD]; 48 static unsigned int __initdata next_early_pgt; 49 pmdval_t early_pmd_flags = __PAGE_KERNEL_LARGE & ~(_PAGE_GLOBAL | _PAGE_NX); 50 51 #ifdef CONFIG_X86_5LEVEL 52 unsigned int __pgtable_l5_enabled __ro_after_init; 53 unsigned int pgdir_shift __ro_after_init = 39; 54 EXPORT_SYMBOL(pgdir_shift); 55 unsigned int ptrs_per_p4d __ro_after_init = 1; 56 EXPORT_SYMBOL(ptrs_per_p4d); 57 #endif 58 59 #ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT 60 unsigned long page_offset_base __ro_after_init = __PAGE_OFFSET_BASE_L4; 61 EXPORT_SYMBOL(page_offset_base); 62 unsigned long vmalloc_base __ro_after_init = __VMALLOC_BASE_L4; 63 EXPORT_SYMBOL(vmalloc_base); 64 unsigned long vmemmap_base __ro_after_init = __VMEMMAP_BASE_L4; 65 EXPORT_SYMBOL(vmemmap_base); 66 #endif 67 68 /* 69 * GDT used on the boot CPU before switching to virtual addresses. 70 */ 71 static struct desc_struct startup_gdt[GDT_ENTRIES] = { 72 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), 73 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), 74 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), 75 }; 76 77 /* 78 * Address needs to be set at runtime because it references the startup_gdt 79 * while the kernel still uses a direct mapping. 80 */ 81 static struct desc_ptr startup_gdt_descr = { 82 .size = sizeof(startup_gdt), 83 .address = 0, 84 }; 85 86 #define __head __section(".head.text") 87 88 static void __head *fixup_pointer(void *ptr, unsigned long physaddr) 89 { 90 return ptr - (void *)_text + (void *)physaddr; 91 } 92 93 static unsigned long __head *fixup_long(void *ptr, unsigned long physaddr) 94 { 95 return fixup_pointer(ptr, physaddr); 96 } 97 98 #ifdef CONFIG_X86_5LEVEL 99 static unsigned int __head *fixup_int(void *ptr, unsigned long physaddr) 100 { 101 return fixup_pointer(ptr, physaddr); 102 } 103 104 static bool __head check_la57_support(unsigned long physaddr) 105 { 106 /* 107 * 5-level paging is detected and enabled at kernel decompression 108 * stage. Only check if it has been enabled there. 109 */ 110 if (!(native_read_cr4() & X86_CR4_LA57)) 111 return false; 112 113 *fixup_int(&__pgtable_l5_enabled, physaddr) = 1; 114 *fixup_int(&pgdir_shift, physaddr) = 48; 115 *fixup_int(&ptrs_per_p4d, physaddr) = 512; 116 *fixup_long(&page_offset_base, physaddr) = __PAGE_OFFSET_BASE_L5; 117 *fixup_long(&vmalloc_base, physaddr) = __VMALLOC_BASE_L5; 118 *fixup_long(&vmemmap_base, physaddr) = __VMEMMAP_BASE_L5; 119 120 return true; 121 } 122 #else 123 static bool __head check_la57_support(unsigned long physaddr) 124 { 125 return false; 126 } 127 #endif 128 129 static unsigned long __head sme_postprocess_startup(struct boot_params *bp, pmdval_t *pmd) 130 { 131 unsigned long vaddr, vaddr_end; 132 int i; 133 134 /* Encrypt the kernel and related (if SME is active) */ 135 sme_encrypt_kernel(bp); 136 137 /* 138 * Clear the memory encryption mask from the .bss..decrypted section. 139 * The bss section will be memset to zero later in the initialization so 140 * there is no need to zero it after changing the memory encryption 141 * attribute. 142 */ 143 if (sme_get_me_mask()) { 144 vaddr = (unsigned long)__start_bss_decrypted; 145 vaddr_end = (unsigned long)__end_bss_decrypted; 146 for (; vaddr < vaddr_end; vaddr += PMD_SIZE) { 147 i = pmd_index(vaddr); 148 pmd[i] -= sme_get_me_mask(); 149 } 150 } 151 152 /* 153 * Return the SME encryption mask (if SME is active) to be used as a 154 * modifier for the initial pgdir entry programmed into CR3. 155 */ 156 return sme_get_me_mask(); 157 } 158 159 /* Code in __startup_64() can be relocated during execution, but the compiler 160 * doesn't have to generate PC-relative relocations when accessing globals from 161 * that function. Clang actually does not generate them, which leads to 162 * boot-time crashes. To work around this problem, every global pointer must 163 * be adjusted using fixup_pointer(). 164 */ 165 unsigned long __head __startup_64(unsigned long physaddr, 166 struct boot_params *bp) 167 { 168 unsigned long load_delta, *p; 169 unsigned long pgtable_flags; 170 pgdval_t *pgd; 171 p4dval_t *p4d; 172 pudval_t *pud; 173 pmdval_t *pmd, pmd_entry; 174 pteval_t *mask_ptr; 175 bool la57; 176 int i; 177 unsigned int *next_pgt_ptr; 178 179 la57 = check_la57_support(physaddr); 180 181 /* Is the address too large? */ 182 if (physaddr >> MAX_PHYSMEM_BITS) 183 for (;;); 184 185 /* 186 * Compute the delta between the address I am compiled to run at 187 * and the address I am actually running at. 188 */ 189 load_delta = physaddr - (unsigned long)(_text - __START_KERNEL_map); 190 191 /* Is the address not 2M aligned? */ 192 if (load_delta & ~PMD_PAGE_MASK) 193 for (;;); 194 195 /* Include the SME encryption mask in the fixup value */ 196 load_delta += sme_get_me_mask(); 197 198 /* Fixup the physical addresses in the page table */ 199 200 pgd = fixup_pointer(&early_top_pgt, physaddr); 201 p = pgd + pgd_index(__START_KERNEL_map); 202 if (la57) 203 *p = (unsigned long)level4_kernel_pgt; 204 else 205 *p = (unsigned long)level3_kernel_pgt; 206 *p += _PAGE_TABLE_NOENC - __START_KERNEL_map + load_delta; 207 208 if (la57) { 209 p4d = fixup_pointer(&level4_kernel_pgt, physaddr); 210 p4d[511] += load_delta; 211 } 212 213 pud = fixup_pointer(&level3_kernel_pgt, physaddr); 214 pud[510] += load_delta; 215 pud[511] += load_delta; 216 217 pmd = fixup_pointer(level2_fixmap_pgt, physaddr); 218 for (i = FIXMAP_PMD_TOP; i > FIXMAP_PMD_TOP - FIXMAP_PMD_NUM; i--) 219 pmd[i] += load_delta; 220 221 /* 222 * Set up the identity mapping for the switchover. These 223 * entries should *NOT* have the global bit set! This also 224 * creates a bunch of nonsense entries but that is fine -- 225 * it avoids problems around wraparound. 226 */ 227 228 next_pgt_ptr = fixup_pointer(&next_early_pgt, physaddr); 229 pud = fixup_pointer(early_dynamic_pgts[(*next_pgt_ptr)++], physaddr); 230 pmd = fixup_pointer(early_dynamic_pgts[(*next_pgt_ptr)++], physaddr); 231 232 pgtable_flags = _KERNPG_TABLE_NOENC + sme_get_me_mask(); 233 234 if (la57) { 235 p4d = fixup_pointer(early_dynamic_pgts[(*next_pgt_ptr)++], 236 physaddr); 237 238 i = (physaddr >> PGDIR_SHIFT) % PTRS_PER_PGD; 239 pgd[i + 0] = (pgdval_t)p4d + pgtable_flags; 240 pgd[i + 1] = (pgdval_t)p4d + pgtable_flags; 241 242 i = physaddr >> P4D_SHIFT; 243 p4d[(i + 0) % PTRS_PER_P4D] = (pgdval_t)pud + pgtable_flags; 244 p4d[(i + 1) % PTRS_PER_P4D] = (pgdval_t)pud + pgtable_flags; 245 } else { 246 i = (physaddr >> PGDIR_SHIFT) % PTRS_PER_PGD; 247 pgd[i + 0] = (pgdval_t)pud + pgtable_flags; 248 pgd[i + 1] = (pgdval_t)pud + pgtable_flags; 249 } 250 251 i = physaddr >> PUD_SHIFT; 252 pud[(i + 0) % PTRS_PER_PUD] = (pudval_t)pmd + pgtable_flags; 253 pud[(i + 1) % PTRS_PER_PUD] = (pudval_t)pmd + pgtable_flags; 254 255 pmd_entry = __PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL; 256 /* Filter out unsupported __PAGE_KERNEL_* bits: */ 257 mask_ptr = fixup_pointer(&__supported_pte_mask, physaddr); 258 pmd_entry &= *mask_ptr; 259 pmd_entry += sme_get_me_mask(); 260 pmd_entry += physaddr; 261 262 for (i = 0; i < DIV_ROUND_UP(_end - _text, PMD_SIZE); i++) { 263 int idx = i + (physaddr >> PMD_SHIFT); 264 265 pmd[idx % PTRS_PER_PMD] = pmd_entry + i * PMD_SIZE; 266 } 267 268 /* 269 * Fixup the kernel text+data virtual addresses. Note that 270 * we might write invalid pmds, when the kernel is relocated 271 * cleanup_highmap() fixes this up along with the mappings 272 * beyond _end. 273 * 274 * Only the region occupied by the kernel image has so far 275 * been checked against the table of usable memory regions 276 * provided by the firmware, so invalidate pages outside that 277 * region. A page table entry that maps to a reserved area of 278 * memory would allow processor speculation into that area, 279 * and on some hardware (particularly the UV platform) even 280 * speculative access to some reserved areas is caught as an 281 * error, causing the BIOS to halt the system. 282 */ 283 284 pmd = fixup_pointer(level2_kernel_pgt, physaddr); 285 286 /* invalidate pages before the kernel image */ 287 for (i = 0; i < pmd_index((unsigned long)_text); i++) 288 pmd[i] &= ~_PAGE_PRESENT; 289 290 /* fixup pages that are part of the kernel image */ 291 for (; i <= pmd_index((unsigned long)_end); i++) 292 if (pmd[i] & _PAGE_PRESENT) 293 pmd[i] += load_delta; 294 295 /* invalidate pages after the kernel image */ 296 for (; i < PTRS_PER_PMD; i++) 297 pmd[i] &= ~_PAGE_PRESENT; 298 299 /* 300 * Fixup phys_base - remove the memory encryption mask to obtain 301 * the true physical address. 302 */ 303 *fixup_long(&phys_base, physaddr) += load_delta - sme_get_me_mask(); 304 305 return sme_postprocess_startup(bp, pmd); 306 } 307 308 unsigned long __startup_secondary_64(void) 309 { 310 /* 311 * Return the SME encryption mask (if SME is active) to be used as a 312 * modifier for the initial pgdir entry programmed into CR3. 313 */ 314 return sme_get_me_mask(); 315 } 316 317 /* Wipe all early page tables except for the kernel symbol map */ 318 static void __init reset_early_page_tables(void) 319 { 320 memset(early_top_pgt, 0, sizeof(pgd_t)*(PTRS_PER_PGD-1)); 321 next_early_pgt = 0; 322 write_cr3(__sme_pa_nodebug(early_top_pgt)); 323 } 324 325 /* Create a new PMD entry */ 326 bool __init __early_make_pgtable(unsigned long address, pmdval_t pmd) 327 { 328 unsigned long physaddr = address - __PAGE_OFFSET; 329 pgdval_t pgd, *pgd_p; 330 p4dval_t p4d, *p4d_p; 331 pudval_t pud, *pud_p; 332 pmdval_t *pmd_p; 333 334 /* Invalid address or early pgt is done ? */ 335 if (physaddr >= MAXMEM || read_cr3_pa() != __pa_nodebug(early_top_pgt)) 336 return false; 337 338 again: 339 pgd_p = &early_top_pgt[pgd_index(address)].pgd; 340 pgd = *pgd_p; 341 342 /* 343 * The use of __START_KERNEL_map rather than __PAGE_OFFSET here is 344 * critical -- __PAGE_OFFSET would point us back into the dynamic 345 * range and we might end up looping forever... 346 */ 347 if (!pgtable_l5_enabled()) 348 p4d_p = pgd_p; 349 else if (pgd) 350 p4d_p = (p4dval_t *)((pgd & PTE_PFN_MASK) + __START_KERNEL_map - phys_base); 351 else { 352 if (next_early_pgt >= EARLY_DYNAMIC_PAGE_TABLES) { 353 reset_early_page_tables(); 354 goto again; 355 } 356 357 p4d_p = (p4dval_t *)early_dynamic_pgts[next_early_pgt++]; 358 memset(p4d_p, 0, sizeof(*p4d_p) * PTRS_PER_P4D); 359 *pgd_p = (pgdval_t)p4d_p - __START_KERNEL_map + phys_base + _KERNPG_TABLE; 360 } 361 p4d_p += p4d_index(address); 362 p4d = *p4d_p; 363 364 if (p4d) 365 pud_p = (pudval_t *)((p4d & PTE_PFN_MASK) + __START_KERNEL_map - phys_base); 366 else { 367 if (next_early_pgt >= EARLY_DYNAMIC_PAGE_TABLES) { 368 reset_early_page_tables(); 369 goto again; 370 } 371 372 pud_p = (pudval_t *)early_dynamic_pgts[next_early_pgt++]; 373 memset(pud_p, 0, sizeof(*pud_p) * PTRS_PER_PUD); 374 *p4d_p = (p4dval_t)pud_p - __START_KERNEL_map + phys_base + _KERNPG_TABLE; 375 } 376 pud_p += pud_index(address); 377 pud = *pud_p; 378 379 if (pud) 380 pmd_p = (pmdval_t *)((pud & PTE_PFN_MASK) + __START_KERNEL_map - phys_base); 381 else { 382 if (next_early_pgt >= EARLY_DYNAMIC_PAGE_TABLES) { 383 reset_early_page_tables(); 384 goto again; 385 } 386 387 pmd_p = (pmdval_t *)early_dynamic_pgts[next_early_pgt++]; 388 memset(pmd_p, 0, sizeof(*pmd_p) * PTRS_PER_PMD); 389 *pud_p = (pudval_t)pmd_p - __START_KERNEL_map + phys_base + _KERNPG_TABLE; 390 } 391 pmd_p[pmd_index(address)] = pmd; 392 393 return true; 394 } 395 396 static bool __init early_make_pgtable(unsigned long address) 397 { 398 unsigned long physaddr = address - __PAGE_OFFSET; 399 pmdval_t pmd; 400 401 pmd = (physaddr & PMD_MASK) + early_pmd_flags; 402 403 return __early_make_pgtable(address, pmd); 404 } 405 406 void __init do_early_exception(struct pt_regs *regs, int trapnr) 407 { 408 if (trapnr == X86_TRAP_PF && 409 early_make_pgtable(native_read_cr2())) 410 return; 411 412 if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT) && 413 trapnr == X86_TRAP_VC && handle_vc_boot_ghcb(regs)) 414 return; 415 416 early_fixup_exception(regs, trapnr); 417 } 418 419 /* Don't add a printk in there. printk relies on the PDA which is not initialized 420 yet. */ 421 static void __init clear_bss(void) 422 { 423 memset(__bss_start, 0, 424 (unsigned long) __bss_stop - (unsigned long) __bss_start); 425 } 426 427 static unsigned long get_cmd_line_ptr(void) 428 { 429 unsigned long cmd_line_ptr = boot_params.hdr.cmd_line_ptr; 430 431 cmd_line_ptr |= (u64)boot_params.ext_cmd_line_ptr << 32; 432 433 return cmd_line_ptr; 434 } 435 436 static void __init copy_bootdata(char *real_mode_data) 437 { 438 char * command_line; 439 unsigned long cmd_line_ptr; 440 441 /* 442 * If SME is active, this will create decrypted mappings of the 443 * boot data in advance of the copy operations. 444 */ 445 sme_map_bootdata(real_mode_data); 446 447 memcpy(&boot_params, real_mode_data, sizeof(boot_params)); 448 sanitize_boot_params(&boot_params); 449 cmd_line_ptr = get_cmd_line_ptr(); 450 if (cmd_line_ptr) { 451 command_line = __va(cmd_line_ptr); 452 memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); 453 } 454 455 /* 456 * The old boot data is no longer needed and won't be reserved, 457 * freeing up that memory for use by the system. If SME is active, 458 * we need to remove the mappings that were created so that the 459 * memory doesn't remain mapped as decrypted. 460 */ 461 sme_unmap_bootdata(real_mode_data); 462 } 463 464 asmlinkage __visible void __init x86_64_start_kernel(char * real_mode_data) 465 { 466 /* 467 * Build-time sanity checks on the kernel image and module 468 * area mappings. (these are purely build-time and produce no code) 469 */ 470 BUILD_BUG_ON(MODULES_VADDR < __START_KERNEL_map); 471 BUILD_BUG_ON(MODULES_VADDR - __START_KERNEL_map < KERNEL_IMAGE_SIZE); 472 BUILD_BUG_ON(MODULES_LEN + KERNEL_IMAGE_SIZE > 2*PUD_SIZE); 473 BUILD_BUG_ON((__START_KERNEL_map & ~PMD_MASK) != 0); 474 BUILD_BUG_ON((MODULES_VADDR & ~PMD_MASK) != 0); 475 BUILD_BUG_ON(!(MODULES_VADDR > __START_KERNEL)); 476 MAYBE_BUILD_BUG_ON(!(((MODULES_END - 1) & PGDIR_MASK) == 477 (__START_KERNEL & PGDIR_MASK))); 478 BUILD_BUG_ON(__fix_to_virt(__end_of_fixed_addresses) <= MODULES_END); 479 480 cr4_init_shadow(); 481 482 /* Kill off the identity-map trampoline */ 483 reset_early_page_tables(); 484 485 clear_bss(); 486 487 /* 488 * This needs to happen *before* kasan_early_init() because latter maps stuff 489 * into that page. 490 */ 491 clear_page(init_top_pgt); 492 493 /* 494 * SME support may update early_pmd_flags to include the memory 495 * encryption mask, so it needs to be called before anything 496 * that may generate a page fault. 497 */ 498 sme_early_init(); 499 500 kasan_early_init(); 501 502 /* 503 * Flush global TLB entries which could be left over from the trampoline page 504 * table. 505 * 506 * This needs to happen *after* kasan_early_init() as KASAN-enabled .configs 507 * instrument native_write_cr4() so KASAN must be initialized for that 508 * instrumentation to work. 509 */ 510 __native_tlb_flush_global(this_cpu_read(cpu_tlbstate.cr4)); 511 512 idt_setup_early_handler(); 513 514 copy_bootdata(__va(real_mode_data)); 515 516 /* 517 * Load microcode early on BSP. 518 */ 519 load_ucode_bsp(); 520 521 /* set init_top_pgt kernel high mapping*/ 522 init_top_pgt[511] = early_top_pgt[511]; 523 524 x86_64_start_reservations(real_mode_data); 525 } 526 527 void __init x86_64_start_reservations(char *real_mode_data) 528 { 529 /* version is always not zero if it is copied */ 530 if (!boot_params.hdr.version) 531 copy_bootdata(__va(real_mode_data)); 532 533 x86_early_init_platform_quirks(); 534 535 switch (boot_params.hdr.hardware_subarch) { 536 case X86_SUBARCH_INTEL_MID: 537 x86_intel_mid_early_setup(); 538 break; 539 default: 540 break; 541 } 542 543 start_kernel(); 544 } 545 546 /* 547 * Data structures and code used for IDT setup in head_64.S. The bringup-IDT is 548 * used until the idt_table takes over. On the boot CPU this happens in 549 * x86_64_start_kernel(), on secondary CPUs in start_secondary(). In both cases 550 * this happens in the functions called from head_64.S. 551 * 552 * The idt_table can't be used that early because all the code modifying it is 553 * in idt.c and can be instrumented by tracing or KASAN, which both don't work 554 * during early CPU bringup. Also the idt_table has the runtime vectors 555 * configured which require certain CPU state to be setup already (like TSS), 556 * which also hasn't happened yet in early CPU bringup. 557 */ 558 static gate_desc bringup_idt_table[NUM_EXCEPTION_VECTORS] __page_aligned_data; 559 560 static struct desc_ptr bringup_idt_descr = { 561 .size = (NUM_EXCEPTION_VECTORS * sizeof(gate_desc)) - 1, 562 .address = 0, /* Set at runtime */ 563 }; 564 565 static void set_bringup_idt_handler(gate_desc *idt, int n, void *handler) 566 { 567 #ifdef CONFIG_AMD_MEM_ENCRYPT 568 struct idt_data data; 569 gate_desc desc; 570 571 init_idt_data(&data, n, handler); 572 idt_init_desc(&desc, &data); 573 native_write_idt_entry(idt, n, &desc); 574 #endif 575 } 576 577 /* This runs while still in the direct mapping */ 578 static void startup_64_load_idt(unsigned long physbase) 579 { 580 struct desc_ptr *desc = fixup_pointer(&bringup_idt_descr, physbase); 581 gate_desc *idt = fixup_pointer(bringup_idt_table, physbase); 582 583 584 if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) { 585 void *handler; 586 587 /* VMM Communication Exception */ 588 handler = fixup_pointer(vc_no_ghcb, physbase); 589 set_bringup_idt_handler(idt, X86_TRAP_VC, handler); 590 } 591 592 desc->address = (unsigned long)idt; 593 native_load_idt(desc); 594 } 595 596 /* This is used when running on kernel addresses */ 597 void early_setup_idt(void) 598 { 599 /* VMM Communication Exception */ 600 if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) 601 set_bringup_idt_handler(bringup_idt_table, X86_TRAP_VC, vc_boot_ghcb); 602 603 bringup_idt_descr.address = (unsigned long)bringup_idt_table; 604 native_load_idt(&bringup_idt_descr); 605 } 606 607 /* 608 * Setup boot CPU state needed before kernel switches to virtual addresses. 609 */ 610 void __head startup_64_setup_env(unsigned long physbase) 611 { 612 /* Load GDT */ 613 startup_gdt_descr.address = (unsigned long)fixup_pointer(startup_gdt, physbase); 614 native_load_gdt(&startup_gdt_descr); 615 616 /* New GDT is live - reload data segment registers */ 617 asm volatile("movl %%eax, %%ds\n" 618 "movl %%eax, %%ss\n" 619 "movl %%eax, %%es\n" : : "a"(__KERNEL_DS) : "memory"); 620 621 startup_64_load_idt(physbase); 622 } 623