1b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
20c306bcfSIngo Molnar /*
30c306bcfSIngo Molnar * FPU register's regset abstraction, for ptrace, core dumps, etc.
40c306bcfSIngo Molnar */
543be46e8SThomas Gleixner #include <linux/sched/task_stack.h>
643be46e8SThomas Gleixner #include <linux/vmalloc.h>
743be46e8SThomas Gleixner
8b56d2795SThomas Gleixner #include <asm/fpu/api.h>
90c306bcfSIngo Molnar #include <asm/fpu/signal.h>
100c306bcfSIngo Molnar #include <asm/fpu/regset.h>
11*2fab02b2SRick Edgecombe #include <asm/prctl.h>
120c306bcfSIngo Molnar
139848fb96SThomas Gleixner #include "context.h"
14d06241f5SThomas Gleixner #include "internal.h"
15d9d005f3SThomas Gleixner #include "legacy.h"
1649e4eb41SThomas Gleixner #include "xstate.h"
17d06241f5SThomas Gleixner
180c306bcfSIngo Molnar /*
190c306bcfSIngo Molnar * The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
200c306bcfSIngo Molnar * as the "regset->n" for the xstate regset will be updated based on the feature
216a6256f9SAdam Buchbinder * capabilities supported by the xsave.
220c306bcfSIngo Molnar */
regset_fpregs_active(struct task_struct * target,const struct user_regset * regset)230c306bcfSIngo Molnar int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
240c306bcfSIngo Molnar {
252722146eSSebastian Andrzej Siewior return regset->n;
260c306bcfSIngo Molnar }
270c306bcfSIngo Molnar
regset_xregset_fpregs_active(struct task_struct * target,const struct user_regset * regset)280c306bcfSIngo Molnar int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
290c306bcfSIngo Molnar {
302722146eSSebastian Andrzej Siewior if (boot_cpu_has(X86_FEATURE_FXSR))
3101f8fd73SBorislav Petkov return regset->n;
3201f8fd73SBorislav Petkov else
3301f8fd73SBorislav Petkov return 0;
340c306bcfSIngo Molnar }
350c306bcfSIngo Molnar
365a32fac8SThomas Gleixner /*
375a32fac8SThomas Gleixner * The regset get() functions are invoked from:
385a32fac8SThomas Gleixner *
395a32fac8SThomas Gleixner * - coredump to dump the current task's fpstate. If the current task
405a32fac8SThomas Gleixner * owns the FPU then the memory state has to be synchronized and the
415a32fac8SThomas Gleixner * FPU register state preserved. Otherwise fpstate is already in sync.
425a32fac8SThomas Gleixner *
435a32fac8SThomas Gleixner * - ptrace to dump fpstate of a stopped task, in which case the registers
445a32fac8SThomas Gleixner * have already been saved to fpstate on context switch.
455a32fac8SThomas Gleixner */
sync_fpstate(struct fpu * fpu)465a32fac8SThomas Gleixner static void sync_fpstate(struct fpu *fpu)
475a32fac8SThomas Gleixner {
485a32fac8SThomas Gleixner if (fpu == ¤t->thread.fpu)
49b2681e79SThomas Gleixner fpu_sync_fpstate(fpu);
505a32fac8SThomas Gleixner }
515a32fac8SThomas Gleixner
52dbb60ac7SThomas Gleixner /*
53dbb60ac7SThomas Gleixner * Invalidate cached FPU registers before modifying the stopped target
54dbb60ac7SThomas Gleixner * task's fpstate.
55dbb60ac7SThomas Gleixner *
56dbb60ac7SThomas Gleixner * This forces the target task on resume to restore the FPU registers from
57dbb60ac7SThomas Gleixner * modified fpstate. Otherwise the task might skip the restore and operate
58dbb60ac7SThomas Gleixner * with the cached FPU registers which discards the modifications.
59dbb60ac7SThomas Gleixner */
fpu_force_restore(struct fpu * fpu)60dbb60ac7SThomas Gleixner static void fpu_force_restore(struct fpu *fpu)
61dbb60ac7SThomas Gleixner {
62dbb60ac7SThomas Gleixner /*
63dbb60ac7SThomas Gleixner * Only stopped child tasks can be used to modify the FPU
64dbb60ac7SThomas Gleixner * state in the fpstate buffer:
65dbb60ac7SThomas Gleixner */
66dbb60ac7SThomas Gleixner WARN_ON_FPU(fpu == ¤t->thread.fpu);
67dbb60ac7SThomas Gleixner
68dbb60ac7SThomas Gleixner __fpu_invalidate_fpregs_state(fpu);
69dbb60ac7SThomas Gleixner }
70dbb60ac7SThomas Gleixner
xfpregs_get(struct task_struct * target,const struct user_regset * regset,struct membuf to)710c306bcfSIngo Molnar int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
720557d64dSAl Viro struct membuf to)
730c306bcfSIngo Molnar {
740c306bcfSIngo Molnar struct fpu *fpu = &target->thread.fpu;
750c306bcfSIngo Molnar
76adc997b3SThomas Gleixner if (!cpu_feature_enabled(X86_FEATURE_FXSR))
770c306bcfSIngo Molnar return -ENODEV;
780c306bcfSIngo Molnar
795a32fac8SThomas Gleixner sync_fpstate(fpu);
800c306bcfSIngo Molnar
81adc997b3SThomas Gleixner if (!use_xsave()) {
82caee31a3SThomas Gleixner return membuf_write(&to, &fpu->fpstate->regs.fxsave,
83caee31a3SThomas Gleixner sizeof(fpu->fpstate->regs.fxsave));
84adc997b3SThomas Gleixner }
85adc997b3SThomas Gleixner
86e84ba47eSDave Hansen copy_xstate_to_uabi_buf(to, target, XSTATE_COPY_FX);
87adc997b3SThomas Gleixner return 0;
880c306bcfSIngo Molnar }
890c306bcfSIngo Molnar
xfpregs_set(struct task_struct * target,const struct user_regset * regset,unsigned int pos,unsigned int count,const void * kbuf,const void __user * ubuf)900c306bcfSIngo Molnar int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
910c306bcfSIngo Molnar unsigned int pos, unsigned int count,
920c306bcfSIngo Molnar const void *kbuf, const void __user *ubuf)
930c306bcfSIngo Molnar {
940c306bcfSIngo Molnar struct fpu *fpu = &target->thread.fpu;
9544cad52cSAndy Lutomirski struct fxregs_state newstate;
960c306bcfSIngo Molnar int ret;
970c306bcfSIngo Molnar
986164331dSAndy Lutomirski if (!cpu_feature_enabled(X86_FEATURE_FXSR))
990c306bcfSIngo Molnar return -ENODEV;
1000c306bcfSIngo Molnar
1016164331dSAndy Lutomirski /* No funny business with partial or oversized writes is permitted. */
1026164331dSAndy Lutomirski if (pos != 0 || count != sizeof(newstate))
1036164331dSAndy Lutomirski return -EINVAL;
1046164331dSAndy Lutomirski
1056164331dSAndy Lutomirski ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newstate, 0, -1);
1066164331dSAndy Lutomirski if (ret)
1076164331dSAndy Lutomirski return ret;
1086164331dSAndy Lutomirski
109145e9e0dSAndy Lutomirski /* Do not allow an invalid MXCSR value. */
110145e9e0dSAndy Lutomirski if (newstate.mxcsr & ~mxcsr_feature_mask)
111145e9e0dSAndy Lutomirski return -EINVAL;
1126164331dSAndy Lutomirski
113dbb60ac7SThomas Gleixner fpu_force_restore(fpu);
1140c306bcfSIngo Molnar
1156164331dSAndy Lutomirski /* Copy the state */
116caee31a3SThomas Gleixner memcpy(&fpu->fpstate->regs.fxsave, &newstate, sizeof(newstate));
1170c306bcfSIngo Molnar
11844cad52cSAndy Lutomirski /* Clear xmm8..15 for 32-bit callers */
119caee31a3SThomas Gleixner BUILD_BUG_ON(sizeof(fpu->__fpstate.regs.fxsave.xmm_space) != 16 * 16);
12044cad52cSAndy Lutomirski if (in_ia32_syscall())
12144cad52cSAndy Lutomirski memset(&fpu->fpstate->regs.fxsave.xmm_space[8*4], 0, 8 * 16);
1220c306bcfSIngo Molnar
1236164331dSAndy Lutomirski /* Mark FP and SSE as in use when XSAVE is enabled */
1246164331dSAndy Lutomirski if (use_xsave())
125caee31a3SThomas Gleixner fpu->fpstate->regs.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
1260c306bcfSIngo Molnar
1276164331dSAndy Lutomirski return 0;
1280c306bcfSIngo Molnar }
1290c306bcfSIngo Molnar
xstateregs_get(struct task_struct * target,const struct user_regset * regset,struct membuf to)1300c306bcfSIngo Molnar int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
1310557d64dSAl Viro struct membuf to)
1320c306bcfSIngo Molnar {
1333a335112SDave Hansen if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
1340c306bcfSIngo Molnar return -ENODEV;
1350c306bcfSIngo Molnar
136e84ba47eSDave Hansen sync_fpstate(&target->thread.fpu);
13791c3dba7SYu-cheng Yu
138e84ba47eSDave Hansen copy_xstate_to_uabi_buf(to, target, XSTATE_COPY_XSAVE);
1390557d64dSAl Viro return 0;
1400c306bcfSIngo Molnar }
1410c306bcfSIngo Molnar
xstateregs_set(struct task_struct * target,const struct user_regset * regset,unsigned int pos,unsigned int count,const void * kbuf,const void __user * ubuf)1420c306bcfSIngo Molnar int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
1430c306bcfSIngo Molnar unsigned int pos, unsigned int count,
1440c306bcfSIngo Molnar const void *kbuf, const void __user *ubuf)
1450c306bcfSIngo Molnar {
1460c306bcfSIngo Molnar struct fpu *fpu = &target->thread.fpu;
14743be46e8SThomas Gleixner struct xregs_state *tmpbuf = NULL;
1480c306bcfSIngo Molnar int ret;
1490c306bcfSIngo Molnar
15043be46e8SThomas Gleixner if (!cpu_feature_enabled(X86_FEATURE_XSAVE))
1510c306bcfSIngo Molnar return -ENODEV;
1520c306bcfSIngo Molnar
15391c3dba7SYu-cheng Yu /*
15491c3dba7SYu-cheng Yu * A whole standard-format XSAVE buffer is needed:
15591c3dba7SYu-cheng Yu */
1562bd264bcSThomas Gleixner if (pos != 0 || count != fpu_user_cfg.max_size)
15791c3dba7SYu-cheng Yu return -EFAULT;
1580c306bcfSIngo Molnar
15943be46e8SThomas Gleixner if (!kbuf) {
16043be46e8SThomas Gleixner tmpbuf = vmalloc(count);
16143be46e8SThomas Gleixner if (!tmpbuf)
16243be46e8SThomas Gleixner return -ENOMEM;
1630c306bcfSIngo Molnar
16443be46e8SThomas Gleixner if (copy_from_user(tmpbuf, ubuf, count)) {
16543be46e8SThomas Gleixner ret = -EFAULT;
16643be46e8SThomas Gleixner goto out;
16743be46e8SThomas Gleixner }
16879fecc2bSIngo Molnar }
16991c3dba7SYu-cheng Yu
170dbb60ac7SThomas Gleixner fpu_force_restore(fpu);
1711c813ce0SKyle Huey ret = copy_uabi_from_kernel_to_xstate(fpu->fpstate, kbuf ?: tmpbuf, &target->thread.pkru);
172cf9df81bSEric Biggers
17343be46e8SThomas Gleixner out:
17443be46e8SThomas Gleixner vfree(tmpbuf);
1750c306bcfSIngo Molnar return ret;
1760c306bcfSIngo Molnar }
1770c306bcfSIngo Molnar
178*2fab02b2SRick Edgecombe #ifdef CONFIG_X86_USER_SHADOW_STACK
ssp_active(struct task_struct * target,const struct user_regset * regset)179*2fab02b2SRick Edgecombe int ssp_active(struct task_struct *target, const struct user_regset *regset)
180*2fab02b2SRick Edgecombe {
181*2fab02b2SRick Edgecombe if (target->thread.features & ARCH_SHSTK_SHSTK)
182*2fab02b2SRick Edgecombe return regset->n;
183*2fab02b2SRick Edgecombe
184*2fab02b2SRick Edgecombe return 0;
185*2fab02b2SRick Edgecombe }
186*2fab02b2SRick Edgecombe
ssp_get(struct task_struct * target,const struct user_regset * regset,struct membuf to)187*2fab02b2SRick Edgecombe int ssp_get(struct task_struct *target, const struct user_regset *regset,
188*2fab02b2SRick Edgecombe struct membuf to)
189*2fab02b2SRick Edgecombe {
190*2fab02b2SRick Edgecombe struct fpu *fpu = &target->thread.fpu;
191*2fab02b2SRick Edgecombe struct cet_user_state *cetregs;
192*2fab02b2SRick Edgecombe
193*2fab02b2SRick Edgecombe if (!cpu_feature_enabled(X86_FEATURE_USER_SHSTK))
194*2fab02b2SRick Edgecombe return -ENODEV;
195*2fab02b2SRick Edgecombe
196*2fab02b2SRick Edgecombe sync_fpstate(fpu);
197*2fab02b2SRick Edgecombe cetregs = get_xsave_addr(&fpu->fpstate->regs.xsave, XFEATURE_CET_USER);
198*2fab02b2SRick Edgecombe if (WARN_ON(!cetregs)) {
199*2fab02b2SRick Edgecombe /*
200*2fab02b2SRick Edgecombe * This shouldn't ever be NULL because shadow stack was
201*2fab02b2SRick Edgecombe * verified to be enabled above. This means
202*2fab02b2SRick Edgecombe * MSR_IA32_U_CET.CET_SHSTK_EN should be 1 and so
203*2fab02b2SRick Edgecombe * XFEATURE_CET_USER should not be in the init state.
204*2fab02b2SRick Edgecombe */
205*2fab02b2SRick Edgecombe return -ENODEV;
206*2fab02b2SRick Edgecombe }
207*2fab02b2SRick Edgecombe
208*2fab02b2SRick Edgecombe return membuf_write(&to, (unsigned long *)&cetregs->user_ssp,
209*2fab02b2SRick Edgecombe sizeof(cetregs->user_ssp));
210*2fab02b2SRick Edgecombe }
211*2fab02b2SRick Edgecombe
ssp_set(struct task_struct * target,const struct user_regset * regset,unsigned int pos,unsigned int count,const void * kbuf,const void __user * ubuf)212*2fab02b2SRick Edgecombe int ssp_set(struct task_struct *target, const struct user_regset *regset,
213*2fab02b2SRick Edgecombe unsigned int pos, unsigned int count,
214*2fab02b2SRick Edgecombe const void *kbuf, const void __user *ubuf)
215*2fab02b2SRick Edgecombe {
216*2fab02b2SRick Edgecombe struct fpu *fpu = &target->thread.fpu;
217*2fab02b2SRick Edgecombe struct xregs_state *xsave = &fpu->fpstate->regs.xsave;
218*2fab02b2SRick Edgecombe struct cet_user_state *cetregs;
219*2fab02b2SRick Edgecombe unsigned long user_ssp;
220*2fab02b2SRick Edgecombe int r;
221*2fab02b2SRick Edgecombe
222*2fab02b2SRick Edgecombe if (!cpu_feature_enabled(X86_FEATURE_USER_SHSTK) ||
223*2fab02b2SRick Edgecombe !ssp_active(target, regset))
224*2fab02b2SRick Edgecombe return -ENODEV;
225*2fab02b2SRick Edgecombe
226*2fab02b2SRick Edgecombe if (pos != 0 || count != sizeof(user_ssp))
227*2fab02b2SRick Edgecombe return -EINVAL;
228*2fab02b2SRick Edgecombe
229*2fab02b2SRick Edgecombe r = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &user_ssp, 0, -1);
230*2fab02b2SRick Edgecombe if (r)
231*2fab02b2SRick Edgecombe return r;
232*2fab02b2SRick Edgecombe
233*2fab02b2SRick Edgecombe /*
234*2fab02b2SRick Edgecombe * Some kernel instructions (IRET, etc) can cause exceptions in the case
235*2fab02b2SRick Edgecombe * of disallowed CET register values. Just prevent invalid values.
236*2fab02b2SRick Edgecombe */
237*2fab02b2SRick Edgecombe if (user_ssp >= TASK_SIZE_MAX || !IS_ALIGNED(user_ssp, 8))
238*2fab02b2SRick Edgecombe return -EINVAL;
239*2fab02b2SRick Edgecombe
240*2fab02b2SRick Edgecombe fpu_force_restore(fpu);
241*2fab02b2SRick Edgecombe
242*2fab02b2SRick Edgecombe cetregs = get_xsave_addr(xsave, XFEATURE_CET_USER);
243*2fab02b2SRick Edgecombe if (WARN_ON(!cetregs)) {
244*2fab02b2SRick Edgecombe /*
245*2fab02b2SRick Edgecombe * This shouldn't ever be NULL because shadow stack was
246*2fab02b2SRick Edgecombe * verified to be enabled above. This means
247*2fab02b2SRick Edgecombe * MSR_IA32_U_CET.CET_SHSTK_EN should be 1 and so
248*2fab02b2SRick Edgecombe * XFEATURE_CET_USER should not be in the init state.
249*2fab02b2SRick Edgecombe */
250*2fab02b2SRick Edgecombe return -ENODEV;
251*2fab02b2SRick Edgecombe }
252*2fab02b2SRick Edgecombe
253*2fab02b2SRick Edgecombe cetregs->user_ssp = user_ssp;
254*2fab02b2SRick Edgecombe return 0;
255*2fab02b2SRick Edgecombe }
256*2fab02b2SRick Edgecombe #endif /* CONFIG_X86_USER_SHADOW_STACK */
257*2fab02b2SRick Edgecombe
2580c306bcfSIngo Molnar #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
2590c306bcfSIngo Molnar
2600c306bcfSIngo Molnar /*
2610c306bcfSIngo Molnar * FPU tag word conversions.
2620c306bcfSIngo Molnar */
2630c306bcfSIngo Molnar
twd_i387_to_fxsr(unsigned short twd)2640c306bcfSIngo Molnar static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
2650c306bcfSIngo Molnar {
2660c306bcfSIngo Molnar unsigned int tmp; /* to avoid 16 bit prefixes in the code */
2670c306bcfSIngo Molnar
2680c306bcfSIngo Molnar /* Transform each pair of bits into 01 (valid) or 00 (empty) */
2690c306bcfSIngo Molnar tmp = ~twd;
2700c306bcfSIngo Molnar tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
2710c306bcfSIngo Molnar /* and move the valid bits to the lower byte. */
2720c306bcfSIngo Molnar tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
2730c306bcfSIngo Molnar tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
2740c306bcfSIngo Molnar tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
2750c306bcfSIngo Molnar
2760c306bcfSIngo Molnar return tmp;
2770c306bcfSIngo Molnar }
2780c306bcfSIngo Molnar
2790c306bcfSIngo Molnar #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16)
2800c306bcfSIngo Molnar #define FP_EXP_TAG_VALID 0
2810c306bcfSIngo Molnar #define FP_EXP_TAG_ZERO 1
2820c306bcfSIngo Molnar #define FP_EXP_TAG_SPECIAL 2
2830c306bcfSIngo Molnar #define FP_EXP_TAG_EMPTY 3
2840c306bcfSIngo Molnar
twd_fxsr_to_i387(struct fxregs_state * fxsave)285c47ada30SIngo Molnar static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave)
2860c306bcfSIngo Molnar {
2870c306bcfSIngo Molnar struct _fpxreg *st;
2880c306bcfSIngo Molnar u32 tos = (fxsave->swd >> 11) & 7;
2890c306bcfSIngo Molnar u32 twd = (unsigned long) fxsave->twd;
2900c306bcfSIngo Molnar u32 tag;
2910c306bcfSIngo Molnar u32 ret = 0xffff0000u;
2920c306bcfSIngo Molnar int i;
2930c306bcfSIngo Molnar
2940c306bcfSIngo Molnar for (i = 0; i < 8; i++, twd >>= 1) {
2950c306bcfSIngo Molnar if (twd & 0x1) {
2960c306bcfSIngo Molnar st = FPREG_ADDR(fxsave, (i - tos) & 7);
2970c306bcfSIngo Molnar
2980c306bcfSIngo Molnar switch (st->exponent & 0x7fff) {
2990c306bcfSIngo Molnar case 0x7fff:
3000c306bcfSIngo Molnar tag = FP_EXP_TAG_SPECIAL;
3010c306bcfSIngo Molnar break;
3020c306bcfSIngo Molnar case 0x0000:
3030c306bcfSIngo Molnar if (!st->significand[0] &&
3040c306bcfSIngo Molnar !st->significand[1] &&
3050c306bcfSIngo Molnar !st->significand[2] &&
3060c306bcfSIngo Molnar !st->significand[3])
3070c306bcfSIngo Molnar tag = FP_EXP_TAG_ZERO;
3080c306bcfSIngo Molnar else
3090c306bcfSIngo Molnar tag = FP_EXP_TAG_SPECIAL;
3100c306bcfSIngo Molnar break;
3110c306bcfSIngo Molnar default:
3120c306bcfSIngo Molnar if (st->significand[3] & 0x8000)
3130c306bcfSIngo Molnar tag = FP_EXP_TAG_VALID;
3140c306bcfSIngo Molnar else
3150c306bcfSIngo Molnar tag = FP_EXP_TAG_SPECIAL;
3160c306bcfSIngo Molnar break;
3170c306bcfSIngo Molnar }
3180c306bcfSIngo Molnar } else {
3190c306bcfSIngo Molnar tag = FP_EXP_TAG_EMPTY;
3200c306bcfSIngo Molnar }
3210c306bcfSIngo Molnar ret |= tag << (2 * i);
3220c306bcfSIngo Molnar }
3230c306bcfSIngo Molnar return ret;
3240c306bcfSIngo Molnar }
3250c306bcfSIngo Molnar
3260c306bcfSIngo Molnar /*
3270c306bcfSIngo Molnar * FXSR floating point environment conversions.
3280c306bcfSIngo Molnar */
3290c306bcfSIngo Molnar
__convert_from_fxsr(struct user_i387_ia32_struct * env,struct task_struct * tsk,struct fxregs_state * fxsave)3303f7f7563SThomas Gleixner static void __convert_from_fxsr(struct user_i387_ia32_struct *env,
3313f7f7563SThomas Gleixner struct task_struct *tsk,
3323f7f7563SThomas Gleixner struct fxregs_state *fxsave)
3330c306bcfSIngo Molnar {
3340c306bcfSIngo Molnar struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
3350c306bcfSIngo Molnar struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
3360c306bcfSIngo Molnar int i;
3370c306bcfSIngo Molnar
3380c306bcfSIngo Molnar env->cwd = fxsave->cwd | 0xffff0000u;
3390c306bcfSIngo Molnar env->swd = fxsave->swd | 0xffff0000u;
3400c306bcfSIngo Molnar env->twd = twd_fxsr_to_i387(fxsave);
3410c306bcfSIngo Molnar
3420c306bcfSIngo Molnar #ifdef CONFIG_X86_64
3430c306bcfSIngo Molnar env->fip = fxsave->rip;
3440c306bcfSIngo Molnar env->foo = fxsave->rdp;
3450c306bcfSIngo Molnar /*
3460c306bcfSIngo Molnar * should be actually ds/cs at fpu exception time, but
3470c306bcfSIngo Molnar * that information is not available in 64bit mode.
3480c306bcfSIngo Molnar */
3490c306bcfSIngo Molnar env->fcs = task_pt_regs(tsk)->cs;
3500c306bcfSIngo Molnar if (tsk == current) {
3510c306bcfSIngo Molnar savesegment(ds, env->fos);
3520c306bcfSIngo Molnar } else {
3530c306bcfSIngo Molnar env->fos = tsk->thread.ds;
3540c306bcfSIngo Molnar }
3550c306bcfSIngo Molnar env->fos |= 0xffff0000;
3560c306bcfSIngo Molnar #else
3570c306bcfSIngo Molnar env->fip = fxsave->fip;
3580c306bcfSIngo Molnar env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
3590c306bcfSIngo Molnar env->foo = fxsave->foo;
3600c306bcfSIngo Molnar env->fos = fxsave->fos;
3610c306bcfSIngo Molnar #endif
3620c306bcfSIngo Molnar
3630c306bcfSIngo Molnar for (i = 0; i < 8; ++i)
3640c306bcfSIngo Molnar memcpy(&to[i], &from[i], sizeof(to[0]));
3650c306bcfSIngo Molnar }
3660c306bcfSIngo Molnar
3673f7f7563SThomas Gleixner void
convert_from_fxsr(struct user_i387_ia32_struct * env,struct task_struct * tsk)3683f7f7563SThomas Gleixner convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
3693f7f7563SThomas Gleixner {
370caee31a3SThomas Gleixner __convert_from_fxsr(env, tsk, &tsk->thread.fpu.fpstate->regs.fxsave);
3713f7f7563SThomas Gleixner }
3723f7f7563SThomas Gleixner
convert_to_fxsr(struct fxregs_state * fxsave,const struct user_i387_ia32_struct * env)37339ea9bafSSebastian Andrzej Siewior void convert_to_fxsr(struct fxregs_state *fxsave,
3740c306bcfSIngo Molnar const struct user_i387_ia32_struct *env)
3750c306bcfSIngo Molnar
3760c306bcfSIngo Molnar {
3770c306bcfSIngo Molnar struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
3780c306bcfSIngo Molnar struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
3790c306bcfSIngo Molnar int i;
3800c306bcfSIngo Molnar
3810c306bcfSIngo Molnar fxsave->cwd = env->cwd;
3820c306bcfSIngo Molnar fxsave->swd = env->swd;
3830c306bcfSIngo Molnar fxsave->twd = twd_i387_to_fxsr(env->twd);
3840c306bcfSIngo Molnar fxsave->fop = (u16) ((u32) env->fcs >> 16);
3850c306bcfSIngo Molnar #ifdef CONFIG_X86_64
3860c306bcfSIngo Molnar fxsave->rip = env->fip;
3870c306bcfSIngo Molnar fxsave->rdp = env->foo;
3880c306bcfSIngo Molnar /* cs and ds ignored */
3890c306bcfSIngo Molnar #else
3900c306bcfSIngo Molnar fxsave->fip = env->fip;
3910c306bcfSIngo Molnar fxsave->fcs = (env->fcs & 0xffff);
3920c306bcfSIngo Molnar fxsave->foo = env->foo;
3930c306bcfSIngo Molnar fxsave->fos = env->fos;
3940c306bcfSIngo Molnar #endif
3950c306bcfSIngo Molnar
3960c306bcfSIngo Molnar for (i = 0; i < 8; ++i)
3970c306bcfSIngo Molnar memcpy(&to[i], &from[i], sizeof(from[0]));
3980c306bcfSIngo Molnar }
3990c306bcfSIngo Molnar
fpregs_get(struct task_struct * target,const struct user_regset * regset,struct membuf to)4000c306bcfSIngo Molnar int fpregs_get(struct task_struct *target, const struct user_regset *regset,
4010557d64dSAl Viro struct membuf to)
4020c306bcfSIngo Molnar {
4030c306bcfSIngo Molnar struct fpu *fpu = &target->thread.fpu;
4040c306bcfSIngo Molnar struct user_i387_ia32_struct env;
4053f7f7563SThomas Gleixner struct fxregs_state fxsave, *fx;
4060c306bcfSIngo Molnar
4075a32fac8SThomas Gleixner sync_fpstate(fpu);
4080c306bcfSIngo Molnar
4093f7f7563SThomas Gleixner if (!cpu_feature_enabled(X86_FEATURE_FPU))
4100557d64dSAl Viro return fpregs_soft_get(target, regset, to);
4110c306bcfSIngo Molnar
4123f7f7563SThomas Gleixner if (!cpu_feature_enabled(X86_FEATURE_FXSR)) {
413caee31a3SThomas Gleixner return membuf_write(&to, &fpu->fpstate->regs.fsave,
4140557d64dSAl Viro sizeof(struct fregs_state));
4150557d64dSAl Viro }
4160c306bcfSIngo Molnar
4173f7f7563SThomas Gleixner if (use_xsave()) {
4183f7f7563SThomas Gleixner struct membuf mb = { .p = &fxsave, .left = sizeof(fxsave) };
4190c306bcfSIngo Molnar
4203f7f7563SThomas Gleixner /* Handle init state optimized xstate correctly */
421e84ba47eSDave Hansen copy_xstate_to_uabi_buf(mb, target, XSTATE_COPY_FP);
4223f7f7563SThomas Gleixner fx = &fxsave;
4233f7f7563SThomas Gleixner } else {
424caee31a3SThomas Gleixner fx = &fpu->fpstate->regs.fxsave;
4250c306bcfSIngo Molnar }
4260c306bcfSIngo Molnar
4273f7f7563SThomas Gleixner __convert_from_fxsr(&env, target, fx);
4280557d64dSAl Viro return membuf_write(&to, &env, sizeof(env));
4290c306bcfSIngo Molnar }
4300c306bcfSIngo Molnar
fpregs_set(struct task_struct * target,const struct user_regset * regset,unsigned int pos,unsigned int count,const void * kbuf,const void __user * ubuf)4310c306bcfSIngo Molnar int fpregs_set(struct task_struct *target, const struct user_regset *regset,
4320c306bcfSIngo Molnar unsigned int pos, unsigned int count,
4330c306bcfSIngo Molnar const void *kbuf, const void __user *ubuf)
4340c306bcfSIngo Molnar {
4350c306bcfSIngo Molnar struct fpu *fpu = &target->thread.fpu;
4360c306bcfSIngo Molnar struct user_i387_ia32_struct env;
4370c306bcfSIngo Molnar int ret;
4380c306bcfSIngo Molnar
439da53f60bSAndy Lutomirski /* No funny business with partial or oversized writes is permitted. */
440da53f60bSAndy Lutomirski if (pos != 0 || count != sizeof(struct user_i387_ia32_struct))
441da53f60bSAndy Lutomirski return -EINVAL;
4420c306bcfSIngo Molnar
443da53f60bSAndy Lutomirski if (!cpu_feature_enabled(X86_FEATURE_FPU))
4440c306bcfSIngo Molnar return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
4450c306bcfSIngo Molnar
4460c306bcfSIngo Molnar ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
447da53f60bSAndy Lutomirski if (ret)
448da53f60bSAndy Lutomirski return ret;
449da53f60bSAndy Lutomirski
450dbb60ac7SThomas Gleixner fpu_force_restore(fpu);
451da53f60bSAndy Lutomirski
452da53f60bSAndy Lutomirski if (cpu_feature_enabled(X86_FEATURE_FXSR))
453caee31a3SThomas Gleixner convert_to_fxsr(&fpu->fpstate->regs.fxsave, &env);
454da53f60bSAndy Lutomirski else
455caee31a3SThomas Gleixner memcpy(&fpu->fpstate->regs.fsave, &env, sizeof(env));
4560c306bcfSIngo Molnar
4570c306bcfSIngo Molnar /*
458da53f60bSAndy Lutomirski * Update the header bit in the xsave header, indicating the
4590c306bcfSIngo Molnar * presence of FP.
4600c306bcfSIngo Molnar */
461da53f60bSAndy Lutomirski if (cpu_feature_enabled(X86_FEATURE_XSAVE))
462caee31a3SThomas Gleixner fpu->fpstate->regs.xsave.header.xfeatures |= XFEATURE_MASK_FP;
463da53f60bSAndy Lutomirski
464da53f60bSAndy Lutomirski return 0;
4650c306bcfSIngo Molnar }
4660c306bcfSIngo Molnar
4670c306bcfSIngo Molnar #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */
468