1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 1994 Linus Torvalds 4 * 5 * Pentium III FXSR, SSE support 6 * General FPU state handling cleanups 7 * Gareth Hughes <gareth@valinux.com>, May 2000 8 */ 9 #include <asm/fpu/internal.h> 10 #include <asm/fpu/regset.h> 11 #include <asm/fpu/signal.h> 12 #include <asm/fpu/types.h> 13 #include <asm/traps.h> 14 #include <asm/irq_regs.h> 15 16 #include <linux/hardirq.h> 17 #include <linux/pkeys.h> 18 19 #define CREATE_TRACE_POINTS 20 #include <asm/trace/fpu.h> 21 22 /* 23 * Represents the initial FPU state. It's mostly (but not completely) zeroes, 24 * depending on the FPU hardware format: 25 */ 26 union fpregs_state init_fpstate __read_mostly; 27 28 /* 29 * Track whether the kernel is using the FPU state 30 * currently. 31 * 32 * This flag is used: 33 * 34 * - by IRQ context code to potentially use the FPU 35 * if it's unused. 36 * 37 * - to debug kernel_fpu_begin()/end() correctness 38 */ 39 static DEFINE_PER_CPU(bool, in_kernel_fpu); 40 41 /* 42 * Track which context is using the FPU on the CPU: 43 */ 44 DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx); 45 46 static void kernel_fpu_disable(void) 47 { 48 WARN_ON_FPU(this_cpu_read(in_kernel_fpu)); 49 this_cpu_write(in_kernel_fpu, true); 50 } 51 52 static void kernel_fpu_enable(void) 53 { 54 WARN_ON_FPU(!this_cpu_read(in_kernel_fpu)); 55 this_cpu_write(in_kernel_fpu, false); 56 } 57 58 static bool kernel_fpu_disabled(void) 59 { 60 return this_cpu_read(in_kernel_fpu); 61 } 62 63 static bool interrupted_kernel_fpu_idle(void) 64 { 65 return !kernel_fpu_disabled(); 66 } 67 68 /* 69 * Were we in user mode (or vm86 mode) when we were 70 * interrupted? 71 * 72 * Doing kernel_fpu_begin/end() is ok if we are running 73 * in an interrupt context from user mode - we'll just 74 * save the FPU state as required. 75 */ 76 static bool interrupted_user_mode(void) 77 { 78 struct pt_regs *regs = get_irq_regs(); 79 return regs && user_mode(regs); 80 } 81 82 /* 83 * Can we use the FPU in kernel mode with the 84 * whole "kernel_fpu_begin/end()" sequence? 85 * 86 * It's always ok in process context (ie "not interrupt") 87 * but it is sometimes ok even from an irq. 88 */ 89 bool irq_fpu_usable(void) 90 { 91 return !in_interrupt() || 92 interrupted_user_mode() || 93 interrupted_kernel_fpu_idle(); 94 } 95 EXPORT_SYMBOL(irq_fpu_usable); 96 97 static void __kernel_fpu_begin(void) 98 { 99 struct fpu *fpu = ¤t->thread.fpu; 100 101 WARN_ON_FPU(!irq_fpu_usable()); 102 103 kernel_fpu_disable(); 104 105 if (current->mm) { 106 if (!test_thread_flag(TIF_NEED_FPU_LOAD)) { 107 set_thread_flag(TIF_NEED_FPU_LOAD); 108 /* 109 * Ignore return value -- we don't care if reg state 110 * is clobbered. 111 */ 112 copy_fpregs_to_fpstate(fpu); 113 } 114 } 115 __cpu_invalidate_fpregs_state(); 116 } 117 118 static void __kernel_fpu_end(void) 119 { 120 kernel_fpu_enable(); 121 } 122 123 void kernel_fpu_begin(void) 124 { 125 preempt_disable(); 126 __kernel_fpu_begin(); 127 } 128 EXPORT_SYMBOL_GPL(kernel_fpu_begin); 129 130 void kernel_fpu_end(void) 131 { 132 __kernel_fpu_end(); 133 preempt_enable(); 134 } 135 EXPORT_SYMBOL_GPL(kernel_fpu_end); 136 137 /* 138 * Save the FPU state (mark it for reload if necessary): 139 * 140 * This only ever gets called for the current task. 141 */ 142 void fpu__save(struct fpu *fpu) 143 { 144 WARN_ON_FPU(fpu != ¤t->thread.fpu); 145 146 fpregs_lock(); 147 trace_x86_fpu_before_save(fpu); 148 149 if (!test_thread_flag(TIF_NEED_FPU_LOAD)) { 150 if (!copy_fpregs_to_fpstate(fpu)) { 151 copy_kernel_to_fpregs(&fpu->state); 152 } 153 } 154 155 trace_x86_fpu_after_save(fpu); 156 fpregs_unlock(); 157 } 158 EXPORT_SYMBOL_GPL(fpu__save); 159 160 /* 161 * Legacy x87 fpstate state init: 162 */ 163 static inline void fpstate_init_fstate(struct fregs_state *fp) 164 { 165 fp->cwd = 0xffff037fu; 166 fp->swd = 0xffff0000u; 167 fp->twd = 0xffffffffu; 168 fp->fos = 0xffff0000u; 169 } 170 171 void fpstate_init(union fpregs_state *state) 172 { 173 if (!static_cpu_has(X86_FEATURE_FPU)) { 174 fpstate_init_soft(&state->soft); 175 return; 176 } 177 178 memset(state, 0, fpu_kernel_xstate_size); 179 180 if (static_cpu_has(X86_FEATURE_XSAVES)) 181 fpstate_init_xstate(&state->xsave); 182 if (static_cpu_has(X86_FEATURE_FXSR)) 183 fpstate_init_fxstate(&state->fxsave); 184 else 185 fpstate_init_fstate(&state->fsave); 186 } 187 EXPORT_SYMBOL_GPL(fpstate_init); 188 189 int fpu__copy(struct task_struct *dst, struct task_struct *src) 190 { 191 struct fpu *dst_fpu = &dst->thread.fpu; 192 struct fpu *src_fpu = &src->thread.fpu; 193 194 dst_fpu->last_cpu = -1; 195 196 if (!static_cpu_has(X86_FEATURE_FPU)) 197 return 0; 198 199 WARN_ON_FPU(src_fpu != ¤t->thread.fpu); 200 201 /* 202 * Don't let 'init optimized' areas of the XSAVE area 203 * leak into the child task: 204 */ 205 memset(&dst_fpu->state.xsave, 0, fpu_kernel_xstate_size); 206 207 /* 208 * If the FPU registers are not current just memcpy() the state. 209 * Otherwise save current FPU registers directly into the child's FPU 210 * context, without any memory-to-memory copying. 211 * 212 * ( The function 'fails' in the FNSAVE case, which destroys 213 * register contents so we have to load them back. ) 214 */ 215 fpregs_lock(); 216 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 217 memcpy(&dst_fpu->state, &src_fpu->state, fpu_kernel_xstate_size); 218 219 else if (!copy_fpregs_to_fpstate(dst_fpu)) 220 copy_kernel_to_fpregs(&dst_fpu->state); 221 222 fpregs_unlock(); 223 224 set_tsk_thread_flag(dst, TIF_NEED_FPU_LOAD); 225 226 trace_x86_fpu_copy_src(src_fpu); 227 trace_x86_fpu_copy_dst(dst_fpu); 228 229 return 0; 230 } 231 232 /* 233 * Activate the current task's in-memory FPU context, 234 * if it has not been used before: 235 */ 236 static void fpu__initialize(struct fpu *fpu) 237 { 238 WARN_ON_FPU(fpu != ¤t->thread.fpu); 239 240 set_thread_flag(TIF_NEED_FPU_LOAD); 241 fpstate_init(&fpu->state); 242 trace_x86_fpu_init_state(fpu); 243 } 244 245 /* 246 * This function must be called before we read a task's fpstate. 247 * 248 * There's two cases where this gets called: 249 * 250 * - for the current task (when coredumping), in which case we have 251 * to save the latest FPU registers into the fpstate, 252 * 253 * - or it's called for stopped tasks (ptrace), in which case the 254 * registers were already saved by the context-switch code when 255 * the task scheduled out. 256 * 257 * If the task has used the FPU before then save it. 258 */ 259 void fpu__prepare_read(struct fpu *fpu) 260 { 261 if (fpu == ¤t->thread.fpu) 262 fpu__save(fpu); 263 } 264 265 /* 266 * This function must be called before we write a task's fpstate. 267 * 268 * Invalidate any cached FPU registers. 269 * 270 * After this function call, after registers in the fpstate are 271 * modified and the child task has woken up, the child task will 272 * restore the modified FPU state from the modified context. If we 273 * didn't clear its cached status here then the cached in-registers 274 * state pending on its former CPU could be restored, corrupting 275 * the modifications. 276 */ 277 void fpu__prepare_write(struct fpu *fpu) 278 { 279 /* 280 * Only stopped child tasks can be used to modify the FPU 281 * state in the fpstate buffer: 282 */ 283 WARN_ON_FPU(fpu == ¤t->thread.fpu); 284 285 /* Invalidate any cached state: */ 286 __fpu_invalidate_fpregs_state(fpu); 287 } 288 289 /* 290 * Drops current FPU state: deactivates the fpregs and 291 * the fpstate. NOTE: it still leaves previous contents 292 * in the fpregs in the eager-FPU case. 293 * 294 * This function can be used in cases where we know that 295 * a state-restore is coming: either an explicit one, 296 * or a reschedule. 297 */ 298 void fpu__drop(struct fpu *fpu) 299 { 300 preempt_disable(); 301 302 if (fpu == ¤t->thread.fpu) { 303 /* Ignore delayed exceptions from user space */ 304 asm volatile("1: fwait\n" 305 "2:\n" 306 _ASM_EXTABLE(1b, 2b)); 307 fpregs_deactivate(fpu); 308 } 309 310 trace_x86_fpu_dropped(fpu); 311 312 preempt_enable(); 313 } 314 315 /* 316 * Clear FPU registers by setting them up from 317 * the init fpstate: 318 */ 319 static inline void copy_init_fpstate_to_fpregs(void) 320 { 321 fpregs_lock(); 322 323 if (use_xsave()) 324 copy_kernel_to_xregs(&init_fpstate.xsave, -1); 325 else if (static_cpu_has(X86_FEATURE_FXSR)) 326 copy_kernel_to_fxregs(&init_fpstate.fxsave); 327 else 328 copy_kernel_to_fregs(&init_fpstate.fsave); 329 330 if (boot_cpu_has(X86_FEATURE_OSPKE)) 331 copy_init_pkru_to_fpregs(); 332 333 fpregs_mark_activate(); 334 fpregs_unlock(); 335 } 336 337 /* 338 * Clear the FPU state back to init state. 339 * 340 * Called by sys_execve(), by the signal handler code and by various 341 * error paths. 342 */ 343 void fpu__clear(struct fpu *fpu) 344 { 345 WARN_ON_FPU(fpu != ¤t->thread.fpu); /* Almost certainly an anomaly */ 346 347 fpu__drop(fpu); 348 349 /* 350 * Make sure fpstate is cleared and initialized. 351 */ 352 fpu__initialize(fpu); 353 if (static_cpu_has(X86_FEATURE_FPU)) 354 copy_init_fpstate_to_fpregs(); 355 } 356 357 /* 358 * Load FPU context before returning to userspace. 359 */ 360 void switch_fpu_return(void) 361 { 362 if (!static_cpu_has(X86_FEATURE_FPU)) 363 return; 364 365 __fpregs_load_activate(); 366 } 367 EXPORT_SYMBOL_GPL(switch_fpu_return); 368 369 #ifdef CONFIG_X86_DEBUG_FPU 370 /* 371 * If current FPU state according to its tracking (loaded FPU context on this 372 * CPU) is not valid then we must have TIF_NEED_FPU_LOAD set so the context is 373 * loaded on return to userland. 374 */ 375 void fpregs_assert_state_consistent(void) 376 { 377 struct fpu *fpu = ¤t->thread.fpu; 378 379 if (test_thread_flag(TIF_NEED_FPU_LOAD)) 380 return; 381 382 WARN_ON_FPU(!fpregs_state_valid(fpu, smp_processor_id())); 383 } 384 EXPORT_SYMBOL_GPL(fpregs_assert_state_consistent); 385 #endif 386 387 void fpregs_mark_activate(void) 388 { 389 struct fpu *fpu = ¤t->thread.fpu; 390 391 fpregs_activate(fpu); 392 fpu->last_cpu = smp_processor_id(); 393 clear_thread_flag(TIF_NEED_FPU_LOAD); 394 } 395 EXPORT_SYMBOL_GPL(fpregs_mark_activate); 396 397 /* 398 * x87 math exception handling: 399 */ 400 401 int fpu__exception_code(struct fpu *fpu, int trap_nr) 402 { 403 int err; 404 405 if (trap_nr == X86_TRAP_MF) { 406 unsigned short cwd, swd; 407 /* 408 * (~cwd & swd) will mask out exceptions that are not set to unmasked 409 * status. 0x3f is the exception bits in these regs, 0x200 is the 410 * C1 reg you need in case of a stack fault, 0x040 is the stack 411 * fault bit. We should only be taking one exception at a time, 412 * so if this combination doesn't produce any single exception, 413 * then we have a bad program that isn't synchronizing its FPU usage 414 * and it will suffer the consequences since we won't be able to 415 * fully reproduce the context of the exception. 416 */ 417 if (boot_cpu_has(X86_FEATURE_FXSR)) { 418 cwd = fpu->state.fxsave.cwd; 419 swd = fpu->state.fxsave.swd; 420 } else { 421 cwd = (unsigned short)fpu->state.fsave.cwd; 422 swd = (unsigned short)fpu->state.fsave.swd; 423 } 424 425 err = swd & ~cwd; 426 } else { 427 /* 428 * The SIMD FPU exceptions are handled a little differently, as there 429 * is only a single status/control register. Thus, to determine which 430 * unmasked exception was caught we must mask the exception mask bits 431 * at 0x1f80, and then use these to mask the exception bits at 0x3f. 432 */ 433 unsigned short mxcsr = MXCSR_DEFAULT; 434 435 if (boot_cpu_has(X86_FEATURE_XMM)) 436 mxcsr = fpu->state.fxsave.mxcsr; 437 438 err = ~(mxcsr >> 7) & mxcsr; 439 } 440 441 if (err & 0x001) { /* Invalid op */ 442 /* 443 * swd & 0x240 == 0x040: Stack Underflow 444 * swd & 0x240 == 0x240: Stack Overflow 445 * User must clear the SF bit (0x40) if set 446 */ 447 return FPE_FLTINV; 448 } else if (err & 0x004) { /* Divide by Zero */ 449 return FPE_FLTDIV; 450 } else if (err & 0x008) { /* Overflow */ 451 return FPE_FLTOVF; 452 } else if (err & 0x012) { /* Denormal, Underflow */ 453 return FPE_FLTUND; 454 } else if (err & 0x020) { /* Precision */ 455 return FPE_FLTRES; 456 } 457 458 /* 459 * If we're using IRQ 13, or supposedly even some trap 460 * X86_TRAP_MF implementations, it's possible 461 * we get a spurious trap, which is not an error. 462 */ 463 return 0; 464 } 465