1 // SPDX-License-Identifier: GPL-2.0 2 /* Various workarounds for chipset bugs. 3 This code runs very early and can't use the regular PCI subsystem 4 The entries are keyed to PCI bridges which usually identify chipsets 5 uniquely. 6 This is only for whole classes of chipsets with specific problems which 7 need early invasive action (e.g. before the timers are initialized). 8 Most PCI device specific workarounds can be done later and should be 9 in standard PCI quirks 10 Mainboard specific bugs should be handled by DMI entries. 11 CPU specific bugs in setup.c */ 12 13 #include <linux/pci.h> 14 #include <linux/acpi.h> 15 #include <linux/delay.h> 16 #include <linux/pci_ids.h> 17 #include <linux/bcma/bcma.h> 18 #include <linux/bcma/bcma_regs.h> 19 #include <linux/platform_data/x86/apple.h> 20 #include <drm/i915_drm.h> 21 #include <asm/pci-direct.h> 22 #include <asm/dma.h> 23 #include <asm/io_apic.h> 24 #include <asm/apic.h> 25 #include <asm/hpet.h> 26 #include <asm/iommu.h> 27 #include <asm/gart.h> 28 #include <asm/irq_remapping.h> 29 #include <asm/early_ioremap.h> 30 31 static void __init fix_hypertransport_config(int num, int slot, int func) 32 { 33 u32 htcfg; 34 /* 35 * we found a hypertransport bus 36 * make sure that we are broadcasting 37 * interrupts to all cpus on the ht bus 38 * if we're using extended apic ids 39 */ 40 htcfg = read_pci_config(num, slot, func, 0x68); 41 if (htcfg & (1 << 18)) { 42 printk(KERN_INFO "Detected use of extended apic ids " 43 "on hypertransport bus\n"); 44 if ((htcfg & (1 << 17)) == 0) { 45 printk(KERN_INFO "Enabling hypertransport extended " 46 "apic interrupt broadcast\n"); 47 printk(KERN_INFO "Note this is a bios bug, " 48 "please contact your hw vendor\n"); 49 htcfg |= (1 << 17); 50 write_pci_config(num, slot, func, 0x68, htcfg); 51 } 52 } 53 54 55 } 56 57 static void __init via_bugs(int num, int slot, int func) 58 { 59 #ifdef CONFIG_GART_IOMMU 60 if ((max_pfn > MAX_DMA32_PFN || force_iommu) && 61 !gart_iommu_aperture_allowed) { 62 printk(KERN_INFO 63 "Looks like a VIA chipset. Disabling IOMMU." 64 " Override with iommu=allowed\n"); 65 gart_iommu_aperture_disabled = 1; 66 } 67 #endif 68 } 69 70 #ifdef CONFIG_ACPI 71 #ifdef CONFIG_X86_IO_APIC 72 73 static int __init nvidia_hpet_check(struct acpi_table_header *header) 74 { 75 return 0; 76 } 77 #endif /* CONFIG_X86_IO_APIC */ 78 #endif /* CONFIG_ACPI */ 79 80 static void __init nvidia_bugs(int num, int slot, int func) 81 { 82 #ifdef CONFIG_ACPI 83 #ifdef CONFIG_X86_IO_APIC 84 /* 85 * Only applies to Nvidia root ports (bus 0) and not to 86 * Nvidia graphics cards with PCI ports on secondary buses. 87 */ 88 if (num) 89 return; 90 91 /* 92 * All timer overrides on Nvidia are 93 * wrong unless HPET is enabled. 94 * Unfortunately that's not true on many Asus boards. 95 * We don't know yet how to detect this automatically, but 96 * at least allow a command line override. 97 */ 98 if (acpi_use_timer_override) 99 return; 100 101 if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) { 102 acpi_skip_timer_override = 1; 103 printk(KERN_INFO "Nvidia board " 104 "detected. Ignoring ACPI " 105 "timer override.\n"); 106 printk(KERN_INFO "If you got timer trouble " 107 "try acpi_use_timer_override\n"); 108 } 109 #endif 110 #endif 111 /* RED-PEN skip them on mptables too? */ 112 113 } 114 115 #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC) 116 static u32 __init ati_ixp4x0_rev(int num, int slot, int func) 117 { 118 u32 d; 119 u8 b; 120 121 b = read_pci_config_byte(num, slot, func, 0xac); 122 b &= ~(1<<5); 123 write_pci_config_byte(num, slot, func, 0xac, b); 124 125 d = read_pci_config(num, slot, func, 0x70); 126 d |= 1<<8; 127 write_pci_config(num, slot, func, 0x70, d); 128 129 d = read_pci_config(num, slot, func, 0x8); 130 d &= 0xff; 131 return d; 132 } 133 134 static void __init ati_bugs(int num, int slot, int func) 135 { 136 u32 d; 137 u8 b; 138 139 if (acpi_use_timer_override) 140 return; 141 142 d = ati_ixp4x0_rev(num, slot, func); 143 if (d < 0x82) 144 acpi_skip_timer_override = 1; 145 else { 146 /* check for IRQ0 interrupt swap */ 147 outb(0x72, 0xcd6); b = inb(0xcd7); 148 if (!(b & 0x2)) 149 acpi_skip_timer_override = 1; 150 } 151 152 if (acpi_skip_timer_override) { 153 printk(KERN_INFO "SB4X0 revision 0x%x\n", d); 154 printk(KERN_INFO "Ignoring ACPI timer override.\n"); 155 printk(KERN_INFO "If you got timer trouble " 156 "try acpi_use_timer_override\n"); 157 } 158 } 159 160 static u32 __init ati_sbx00_rev(int num, int slot, int func) 161 { 162 u32 d; 163 164 d = read_pci_config(num, slot, func, 0x8); 165 d &= 0xff; 166 167 return d; 168 } 169 170 static void __init ati_bugs_contd(int num, int slot, int func) 171 { 172 u32 d, rev; 173 174 rev = ati_sbx00_rev(num, slot, func); 175 if (rev >= 0x40) 176 acpi_fix_pin2_polarity = 1; 177 178 /* 179 * SB600: revisions 0x11, 0x12, 0x13, 0x14, ... 180 * SB700: revisions 0x39, 0x3a, ... 181 * SB800: revisions 0x40, 0x41, ... 182 */ 183 if (rev >= 0x39) 184 return; 185 186 if (acpi_use_timer_override) 187 return; 188 189 /* check for IRQ0 interrupt swap */ 190 d = read_pci_config(num, slot, func, 0x64); 191 if (!(d & (1<<14))) 192 acpi_skip_timer_override = 1; 193 194 if (acpi_skip_timer_override) { 195 printk(KERN_INFO "SB600 revision 0x%x\n", rev); 196 printk(KERN_INFO "Ignoring ACPI timer override.\n"); 197 printk(KERN_INFO "If you got timer trouble " 198 "try acpi_use_timer_override\n"); 199 } 200 } 201 #else 202 static void __init ati_bugs(int num, int slot, int func) 203 { 204 } 205 206 static void __init ati_bugs_contd(int num, int slot, int func) 207 { 208 } 209 #endif 210 211 static void __init intel_remapping_check(int num, int slot, int func) 212 { 213 u8 revision; 214 u16 device; 215 216 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID); 217 revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID); 218 219 /* 220 * Revision <= 13 of all triggering devices id in this quirk 221 * have a problem draining interrupts when irq remapping is 222 * enabled, and should be flagged as broken. Additionally 223 * revision 0x22 of device id 0x3405 has this problem. 224 */ 225 if (revision <= 0x13) 226 set_irq_remapping_broken(); 227 else if (device == 0x3405 && revision == 0x22) 228 set_irq_remapping_broken(); 229 } 230 231 /* 232 * Systems with Intel graphics controllers set aside memory exclusively 233 * for gfx driver use. This memory is not marked in the E820 as reserved 234 * or as RAM, and so is subject to overlap from E820 manipulation later 235 * in the boot process. On some systems, MMIO space is allocated on top, 236 * despite the efforts of the "RAM buffer" approach, which simply rounds 237 * memory boundaries up to 64M to try to catch space that may decode 238 * as RAM and so is not suitable for MMIO. 239 */ 240 241 #define KB(x) ((x) * 1024UL) 242 #define MB(x) (KB (KB (x))) 243 244 static resource_size_t __init i830_tseg_size(void) 245 { 246 u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC); 247 248 if (!(esmramc & TSEG_ENABLE)) 249 return 0; 250 251 if (esmramc & I830_TSEG_SIZE_1M) 252 return MB(1); 253 else 254 return KB(512); 255 } 256 257 static resource_size_t __init i845_tseg_size(void) 258 { 259 u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC); 260 u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK; 261 262 if (!(esmramc & TSEG_ENABLE)) 263 return 0; 264 265 switch (tseg_size) { 266 case I845_TSEG_SIZE_512K: return KB(512); 267 case I845_TSEG_SIZE_1M: return MB(1); 268 default: 269 WARN(1, "Unknown ESMRAMC value: %x!\n", esmramc); 270 } 271 return 0; 272 } 273 274 static resource_size_t __init i85x_tseg_size(void) 275 { 276 u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC); 277 278 if (!(esmramc & TSEG_ENABLE)) 279 return 0; 280 281 return MB(1); 282 } 283 284 static resource_size_t __init i830_mem_size(void) 285 { 286 return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32); 287 } 288 289 static resource_size_t __init i85x_mem_size(void) 290 { 291 return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32); 292 } 293 294 /* 295 * On 830/845/85x the stolen memory base isn't available in any 296 * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size. 297 */ 298 static resource_size_t __init i830_stolen_base(int num, int slot, int func, 299 resource_size_t stolen_size) 300 { 301 return i830_mem_size() - i830_tseg_size() - stolen_size; 302 } 303 304 static resource_size_t __init i845_stolen_base(int num, int slot, int func, 305 resource_size_t stolen_size) 306 { 307 return i830_mem_size() - i845_tseg_size() - stolen_size; 308 } 309 310 static resource_size_t __init i85x_stolen_base(int num, int slot, int func, 311 resource_size_t stolen_size) 312 { 313 return i85x_mem_size() - i85x_tseg_size() - stolen_size; 314 } 315 316 static resource_size_t __init i865_stolen_base(int num, int slot, int func, 317 resource_size_t stolen_size) 318 { 319 u16 toud = 0; 320 321 toud = read_pci_config_16(0, 0, 0, I865_TOUD); 322 323 return toud * KB(64) + i845_tseg_size(); 324 } 325 326 static resource_size_t __init gen3_stolen_base(int num, int slot, int func, 327 resource_size_t stolen_size) 328 { 329 u32 bsm; 330 331 /* Almost universally we can find the Graphics Base of Stolen Memory 332 * at register BSM (0x5c) in the igfx configuration space. On a few 333 * (desktop) machines this is also mirrored in the bridge device at 334 * different locations, or in the MCHBAR. 335 */ 336 bsm = read_pci_config(num, slot, func, INTEL_BSM); 337 338 return bsm & INTEL_BSM_MASK; 339 } 340 341 static resource_size_t __init i830_stolen_size(int num, int slot, int func) 342 { 343 u16 gmch_ctrl; 344 u16 gms; 345 346 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL); 347 gms = gmch_ctrl & I830_GMCH_GMS_MASK; 348 349 switch (gms) { 350 case I830_GMCH_GMS_STOLEN_512: return KB(512); 351 case I830_GMCH_GMS_STOLEN_1024: return MB(1); 352 case I830_GMCH_GMS_STOLEN_8192: return MB(8); 353 /* local memory isn't part of the normal address space */ 354 case I830_GMCH_GMS_LOCAL: return 0; 355 default: 356 WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl); 357 } 358 359 return 0; 360 } 361 362 static resource_size_t __init gen3_stolen_size(int num, int slot, int func) 363 { 364 u16 gmch_ctrl; 365 u16 gms; 366 367 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL); 368 gms = gmch_ctrl & I855_GMCH_GMS_MASK; 369 370 switch (gms) { 371 case I855_GMCH_GMS_STOLEN_1M: return MB(1); 372 case I855_GMCH_GMS_STOLEN_4M: return MB(4); 373 case I855_GMCH_GMS_STOLEN_8M: return MB(8); 374 case I855_GMCH_GMS_STOLEN_16M: return MB(16); 375 case I855_GMCH_GMS_STOLEN_32M: return MB(32); 376 case I915_GMCH_GMS_STOLEN_48M: return MB(48); 377 case I915_GMCH_GMS_STOLEN_64M: return MB(64); 378 case G33_GMCH_GMS_STOLEN_128M: return MB(128); 379 case G33_GMCH_GMS_STOLEN_256M: return MB(256); 380 case INTEL_GMCH_GMS_STOLEN_96M: return MB(96); 381 case INTEL_GMCH_GMS_STOLEN_160M:return MB(160); 382 case INTEL_GMCH_GMS_STOLEN_224M:return MB(224); 383 case INTEL_GMCH_GMS_STOLEN_352M:return MB(352); 384 default: 385 WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl); 386 } 387 388 return 0; 389 } 390 391 static resource_size_t __init gen6_stolen_size(int num, int slot, int func) 392 { 393 u16 gmch_ctrl; 394 u16 gms; 395 396 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL); 397 gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK; 398 399 return gms * MB(32); 400 } 401 402 static resource_size_t __init gen8_stolen_size(int num, int slot, int func) 403 { 404 u16 gmch_ctrl; 405 u16 gms; 406 407 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL); 408 gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK; 409 410 return gms * MB(32); 411 } 412 413 static resource_size_t __init chv_stolen_size(int num, int slot, int func) 414 { 415 u16 gmch_ctrl; 416 u16 gms; 417 418 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL); 419 gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK; 420 421 /* 422 * 0x0 to 0x10: 32MB increments starting at 0MB 423 * 0x11 to 0x16: 4MB increments starting at 8MB 424 * 0x17 to 0x1d: 4MB increments start at 36MB 425 */ 426 if (gms < 0x11) 427 return gms * MB(32); 428 else if (gms < 0x17) 429 return (gms - 0x11) * MB(4) + MB(8); 430 else 431 return (gms - 0x17) * MB(4) + MB(36); 432 } 433 434 static resource_size_t __init gen9_stolen_size(int num, int slot, int func) 435 { 436 u16 gmch_ctrl; 437 u16 gms; 438 439 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL); 440 gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK; 441 442 /* 0x0 to 0xef: 32MB increments starting at 0MB */ 443 /* 0xf0 to 0xfe: 4MB increments starting at 4MB */ 444 if (gms < 0xf0) 445 return gms * MB(32); 446 else 447 return (gms - 0xf0) * MB(4) + MB(4); 448 } 449 450 struct intel_early_ops { 451 resource_size_t (*stolen_size)(int num, int slot, int func); 452 resource_size_t (*stolen_base)(int num, int slot, int func, 453 resource_size_t size); 454 }; 455 456 static const struct intel_early_ops i830_early_ops __initconst = { 457 .stolen_base = i830_stolen_base, 458 .stolen_size = i830_stolen_size, 459 }; 460 461 static const struct intel_early_ops i845_early_ops __initconst = { 462 .stolen_base = i845_stolen_base, 463 .stolen_size = i830_stolen_size, 464 }; 465 466 static const struct intel_early_ops i85x_early_ops __initconst = { 467 .stolen_base = i85x_stolen_base, 468 .stolen_size = gen3_stolen_size, 469 }; 470 471 static const struct intel_early_ops i865_early_ops __initconst = { 472 .stolen_base = i865_stolen_base, 473 .stolen_size = gen3_stolen_size, 474 }; 475 476 static const struct intel_early_ops gen3_early_ops __initconst = { 477 .stolen_base = gen3_stolen_base, 478 .stolen_size = gen3_stolen_size, 479 }; 480 481 static const struct intel_early_ops gen6_early_ops __initconst = { 482 .stolen_base = gen3_stolen_base, 483 .stolen_size = gen6_stolen_size, 484 }; 485 486 static const struct intel_early_ops gen8_early_ops __initconst = { 487 .stolen_base = gen3_stolen_base, 488 .stolen_size = gen8_stolen_size, 489 }; 490 491 static const struct intel_early_ops gen9_early_ops __initconst = { 492 .stolen_base = gen3_stolen_base, 493 .stolen_size = gen9_stolen_size, 494 }; 495 496 static const struct intel_early_ops chv_early_ops __initconst = { 497 .stolen_base = gen3_stolen_base, 498 .stolen_size = chv_stolen_size, 499 }; 500 501 static const struct pci_device_id intel_early_ids[] __initconst = { 502 INTEL_I830_IDS(&i830_early_ops), 503 INTEL_I845G_IDS(&i845_early_ops), 504 INTEL_I85X_IDS(&i85x_early_ops), 505 INTEL_I865G_IDS(&i865_early_ops), 506 INTEL_I915G_IDS(&gen3_early_ops), 507 INTEL_I915GM_IDS(&gen3_early_ops), 508 INTEL_I945G_IDS(&gen3_early_ops), 509 INTEL_I945GM_IDS(&gen3_early_ops), 510 INTEL_VLV_IDS(&gen6_early_ops), 511 INTEL_PINEVIEW_IDS(&gen3_early_ops), 512 INTEL_I965G_IDS(&gen3_early_ops), 513 INTEL_G33_IDS(&gen3_early_ops), 514 INTEL_I965GM_IDS(&gen3_early_ops), 515 INTEL_GM45_IDS(&gen3_early_ops), 516 INTEL_G45_IDS(&gen3_early_ops), 517 INTEL_IRONLAKE_D_IDS(&gen3_early_ops), 518 INTEL_IRONLAKE_M_IDS(&gen3_early_ops), 519 INTEL_SNB_D_IDS(&gen6_early_ops), 520 INTEL_SNB_M_IDS(&gen6_early_ops), 521 INTEL_IVB_M_IDS(&gen6_early_ops), 522 INTEL_IVB_D_IDS(&gen6_early_ops), 523 INTEL_HSW_IDS(&gen6_early_ops), 524 INTEL_BDW_IDS(&gen8_early_ops), 525 INTEL_CHV_IDS(&chv_early_ops), 526 INTEL_SKL_IDS(&gen9_early_ops), 527 INTEL_BXT_IDS(&gen9_early_ops), 528 INTEL_KBL_IDS(&gen9_early_ops), 529 INTEL_CFL_IDS(&gen9_early_ops), 530 INTEL_GLK_IDS(&gen9_early_ops), 531 INTEL_CNL_IDS(&gen9_early_ops), 532 }; 533 534 struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0); 535 EXPORT_SYMBOL(intel_graphics_stolen_res); 536 537 static void __init 538 intel_graphics_stolen(int num, int slot, int func, 539 const struct intel_early_ops *early_ops) 540 { 541 resource_size_t base, size; 542 resource_size_t end; 543 544 size = early_ops->stolen_size(num, slot, func); 545 base = early_ops->stolen_base(num, slot, func, size); 546 547 if (!size || !base) 548 return; 549 550 end = base + size - 1; 551 552 intel_graphics_stolen_res.start = base; 553 intel_graphics_stolen_res.end = end; 554 555 printk(KERN_INFO "Reserving Intel graphics memory at %pR\n", 556 &intel_graphics_stolen_res); 557 558 /* Mark this space as reserved */ 559 e820__range_add(base, size, E820_TYPE_RESERVED); 560 e820__update_table(e820_table); 561 } 562 563 static void __init intel_graphics_quirks(int num, int slot, int func) 564 { 565 const struct intel_early_ops *early_ops; 566 u16 device; 567 int i; 568 569 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID); 570 571 for (i = 0; i < ARRAY_SIZE(intel_early_ids); i++) { 572 kernel_ulong_t driver_data = intel_early_ids[i].driver_data; 573 574 if (intel_early_ids[i].device != device) 575 continue; 576 577 early_ops = (typeof(early_ops))driver_data; 578 579 intel_graphics_stolen(num, slot, func, early_ops); 580 581 return; 582 } 583 } 584 585 static void __init force_disable_hpet(int num, int slot, int func) 586 { 587 #ifdef CONFIG_HPET_TIMER 588 boot_hpet_disable = true; 589 pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n"); 590 #endif 591 } 592 593 #define BCM4331_MMIO_SIZE 16384 594 #define BCM4331_PM_CAP 0x40 595 #define bcma_aread32(reg) ioread32(mmio + 1 * BCMA_CORE_SIZE + reg) 596 #define bcma_awrite32(reg, val) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg) 597 598 static void __init apple_airport_reset(int bus, int slot, int func) 599 { 600 void __iomem *mmio; 601 u16 pmcsr; 602 u64 addr; 603 int i; 604 605 if (!x86_apple_machine) 606 return; 607 608 /* Card may have been put into PCI_D3hot by grub quirk */ 609 pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL); 610 611 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) { 612 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 613 write_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL, pmcsr); 614 mdelay(10); 615 616 pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL); 617 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) { 618 pr_err("pci 0000:%02x:%02x.%d: Cannot power up Apple AirPort card\n", 619 bus, slot, func); 620 return; 621 } 622 } 623 624 addr = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0); 625 addr |= (u64)read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_1) << 32; 626 addr &= PCI_BASE_ADDRESS_MEM_MASK; 627 628 mmio = early_ioremap(addr, BCM4331_MMIO_SIZE); 629 if (!mmio) { 630 pr_err("pci 0000:%02x:%02x.%d: Cannot iomap Apple AirPort card\n", 631 bus, slot, func); 632 return; 633 } 634 635 pr_info("Resetting Apple AirPort card (left enabled by EFI)\n"); 636 637 for (i = 0; bcma_aread32(BCMA_RESET_ST) && i < 30; i++) 638 udelay(10); 639 640 bcma_awrite32(BCMA_RESET_CTL, BCMA_RESET_CTL_RESET); 641 bcma_aread32(BCMA_RESET_CTL); 642 udelay(1); 643 644 bcma_awrite32(BCMA_RESET_CTL, 0); 645 bcma_aread32(BCMA_RESET_CTL); 646 udelay(10); 647 648 early_iounmap(mmio, BCM4331_MMIO_SIZE); 649 } 650 651 #define QFLAG_APPLY_ONCE 0x1 652 #define QFLAG_APPLIED 0x2 653 #define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED) 654 struct chipset { 655 u32 vendor; 656 u32 device; 657 u32 class; 658 u32 class_mask; 659 u32 flags; 660 void (*f)(int num, int slot, int func); 661 }; 662 663 static struct chipset early_qrk[] __initdata = { 664 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 665 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs }, 666 { PCI_VENDOR_ID_VIA, PCI_ANY_ID, 667 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs }, 668 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB, 669 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config }, 670 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS, 671 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs }, 672 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 673 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd }, 674 { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST, 675 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check }, 676 { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST, 677 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check }, 678 { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST, 679 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check }, 680 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID, 681 QFLAG_APPLY_ONCE, intel_graphics_quirks }, 682 /* 683 * HPET on the current version of the Baytrail platform has accuracy 684 * problems: it will halt in deep idle state - so we disable it. 685 * 686 * More details can be found in section 18.10.1.3 of the datasheet: 687 * 688 * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf 689 */ 690 { PCI_VENDOR_ID_INTEL, 0x0f00, 691 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, 692 { PCI_VENDOR_ID_BROADCOM, 0x4331, 693 PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset}, 694 {} 695 }; 696 697 static void __init early_pci_scan_bus(int bus); 698 699 /** 700 * check_dev_quirk - apply early quirks to a given PCI device 701 * @num: bus number 702 * @slot: slot number 703 * @func: PCI function 704 * 705 * Check the vendor & device ID against the early quirks table. 706 * 707 * If the device is single function, let early_pci_scan_bus() know so we don't 708 * poke at this device again. 709 */ 710 static int __init check_dev_quirk(int num, int slot, int func) 711 { 712 u16 class; 713 u16 vendor; 714 u16 device; 715 u8 type; 716 u8 sec; 717 int i; 718 719 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE); 720 721 if (class == 0xffff) 722 return -1; /* no class, treat as single function */ 723 724 vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID); 725 726 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID); 727 728 for (i = 0; early_qrk[i].f != NULL; i++) { 729 if (((early_qrk[i].vendor == PCI_ANY_ID) || 730 (early_qrk[i].vendor == vendor)) && 731 ((early_qrk[i].device == PCI_ANY_ID) || 732 (early_qrk[i].device == device)) && 733 (!((early_qrk[i].class ^ class) & 734 early_qrk[i].class_mask))) { 735 if ((early_qrk[i].flags & 736 QFLAG_DONE) != QFLAG_DONE) 737 early_qrk[i].f(num, slot, func); 738 early_qrk[i].flags |= QFLAG_APPLIED; 739 } 740 } 741 742 type = read_pci_config_byte(num, slot, func, 743 PCI_HEADER_TYPE); 744 745 if ((type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { 746 sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS); 747 if (sec > num) 748 early_pci_scan_bus(sec); 749 } 750 751 if (!(type & 0x80)) 752 return -1; 753 754 return 0; 755 } 756 757 static void __init early_pci_scan_bus(int bus) 758 { 759 int slot, func; 760 761 /* Poor man's PCI discovery */ 762 for (slot = 0; slot < 32; slot++) 763 for (func = 0; func < 8; func++) { 764 /* Only probe function 0 on single fn devices */ 765 if (check_dev_quirk(bus, slot, func)) 766 break; 767 } 768 } 769 770 void __init early_quirks(void) 771 { 772 if (!early_pci_allowed()) 773 return; 774 775 early_pci_scan_bus(0); 776 } 777