1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Resource Director Technology(RDT) 4 * - Cache Allocation code. 5 * 6 * Copyright (C) 2016 Intel Corporation 7 * 8 * Authors: 9 * Fenghua Yu <fenghua.yu@intel.com> 10 * Tony Luck <tony.luck@intel.com> 11 * Vikas Shivappa <vikas.shivappa@intel.com> 12 * 13 * More information about RDT be found in the Intel (R) x86 Architecture 14 * Software Developer Manual June 2016, volume 3, section 17.17. 15 */ 16 17 #define pr_fmt(fmt) "resctrl: " fmt 18 19 #include <linux/slab.h> 20 #include <linux/err.h> 21 #include <linux/cacheinfo.h> 22 #include <linux/cpuhotplug.h> 23 24 #include <asm/intel-family.h> 25 #include <asm/resctrl.h> 26 #include "internal.h" 27 28 /* Mutex to protect rdtgroup access. */ 29 DEFINE_MUTEX(rdtgroup_mutex); 30 31 /* 32 * The cached resctrl_pqr_state is strictly per CPU and can never be 33 * updated from a remote CPU. Functions which modify the state 34 * are called with interrupts disabled and no preemption, which 35 * is sufficient for the protection. 36 */ 37 DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state); 38 39 /* 40 * Used to store the max resource name width and max resource data width 41 * to display the schemata in a tabular format 42 */ 43 int max_name_width, max_data_width; 44 45 /* 46 * Global boolean for rdt_alloc which is true if any 47 * resource allocation is enabled. 48 */ 49 bool rdt_alloc_capable; 50 51 static void 52 mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m, 53 struct rdt_resource *r); 54 static void 55 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r); 56 static void 57 mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, 58 struct rdt_resource *r); 59 60 #define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.domains) 61 62 struct rdt_hw_resource rdt_resources_all[] = { 63 [RDT_RESOURCE_L3] = 64 { 65 .r_resctrl = { 66 .rid = RDT_RESOURCE_L3, 67 .name = "L3", 68 .cache_level = 3, 69 .cache = { 70 .min_cbm_bits = 1, 71 }, 72 .domains = domain_init(RDT_RESOURCE_L3), 73 .parse_ctrlval = parse_cbm, 74 .format_str = "%d=%0*x", 75 .fflags = RFTYPE_RES_CACHE, 76 }, 77 .msr_base = MSR_IA32_L3_CBM_BASE, 78 .msr_update = cat_wrmsr, 79 }, 80 [RDT_RESOURCE_L2] = 81 { 82 .r_resctrl = { 83 .rid = RDT_RESOURCE_L2, 84 .name = "L2", 85 .cache_level = 2, 86 .cache = { 87 .min_cbm_bits = 1, 88 }, 89 .domains = domain_init(RDT_RESOURCE_L2), 90 .parse_ctrlval = parse_cbm, 91 .format_str = "%d=%0*x", 92 .fflags = RFTYPE_RES_CACHE, 93 }, 94 .msr_base = MSR_IA32_L2_CBM_BASE, 95 .msr_update = cat_wrmsr, 96 }, 97 [RDT_RESOURCE_MBA] = 98 { 99 .r_resctrl = { 100 .rid = RDT_RESOURCE_MBA, 101 .name = "MB", 102 .cache_level = 3, 103 .domains = domain_init(RDT_RESOURCE_MBA), 104 .parse_ctrlval = parse_bw, 105 .format_str = "%d=%*u", 106 .fflags = RFTYPE_RES_MB, 107 }, 108 }, 109 }; 110 111 /* 112 * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs 113 * as they do not have CPUID enumeration support for Cache allocation. 114 * The check for Vendor/Family/Model is not enough to guarantee that 115 * the MSRs won't #GP fault because only the following SKUs support 116 * CAT: 117 * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz 118 * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz 119 * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz 120 * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz 121 * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz 122 * Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz 123 * 124 * Probe by trying to write the first of the L3 cache mask registers 125 * and checking that the bits stick. Max CLOSids is always 4 and max cbm length 126 * is always 20 on hsw server parts. The minimum cache bitmask length 127 * allowed for HSW server is always 2 bits. Hardcode all of them. 128 */ 129 static inline void cache_alloc_hsw_probe(void) 130 { 131 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3]; 132 struct rdt_resource *r = &hw_res->r_resctrl; 133 u32 l, h, max_cbm = BIT_MASK(20) - 1; 134 135 if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0)) 136 return; 137 138 rdmsr(MSR_IA32_L3_CBM_BASE, l, h); 139 140 /* If all the bits were set in MSR, return success */ 141 if (l != max_cbm) 142 return; 143 144 hw_res->num_closid = 4; 145 r->default_ctrl = max_cbm; 146 r->cache.cbm_len = 20; 147 r->cache.shareable_bits = 0xc0000; 148 r->cache.min_cbm_bits = 2; 149 r->alloc_capable = true; 150 151 rdt_alloc_capable = true; 152 } 153 154 bool is_mba_sc(struct rdt_resource *r) 155 { 156 if (!r) 157 return rdt_resources_all[RDT_RESOURCE_MBA].r_resctrl.membw.mba_sc; 158 159 return r->membw.mba_sc; 160 } 161 162 /* 163 * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values 164 * exposed to user interface and the h/w understandable delay values. 165 * 166 * The non-linear delay values have the granularity of power of two 167 * and also the h/w does not guarantee a curve for configured delay 168 * values vs. actual b/w enforced. 169 * Hence we need a mapping that is pre calibrated so the user can 170 * express the memory b/w as a percentage value. 171 */ 172 static inline bool rdt_get_mb_table(struct rdt_resource *r) 173 { 174 /* 175 * There are no Intel SKUs as of now to support non-linear delay. 176 */ 177 pr_info("MBA b/w map not implemented for cpu:%d, model:%d", 178 boot_cpu_data.x86, boot_cpu_data.x86_model); 179 180 return false; 181 } 182 183 static bool __get_mem_config_intel(struct rdt_resource *r) 184 { 185 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 186 union cpuid_0x10_3_eax eax; 187 union cpuid_0x10_x_edx edx; 188 u32 ebx, ecx, max_delay; 189 190 cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full); 191 hw_res->num_closid = edx.split.cos_max + 1; 192 max_delay = eax.split.max_delay + 1; 193 r->default_ctrl = MAX_MBA_BW; 194 r->membw.arch_needs_linear = true; 195 if (ecx & MBA_IS_LINEAR) { 196 r->membw.delay_linear = true; 197 r->membw.min_bw = MAX_MBA_BW - max_delay; 198 r->membw.bw_gran = MAX_MBA_BW - max_delay; 199 } else { 200 if (!rdt_get_mb_table(r)) 201 return false; 202 r->membw.arch_needs_linear = false; 203 } 204 r->data_width = 3; 205 206 if (boot_cpu_has(X86_FEATURE_PER_THREAD_MBA)) 207 r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD; 208 else 209 r->membw.throttle_mode = THREAD_THROTTLE_MAX; 210 thread_throttle_mode_init(); 211 212 r->alloc_capable = true; 213 214 return true; 215 } 216 217 static bool __rdt_get_mem_config_amd(struct rdt_resource *r) 218 { 219 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 220 union cpuid_0x10_3_eax eax; 221 union cpuid_0x10_x_edx edx; 222 u32 ebx, ecx; 223 224 cpuid_count(0x80000020, 1, &eax.full, &ebx, &ecx, &edx.full); 225 hw_res->num_closid = edx.split.cos_max + 1; 226 r->default_ctrl = MAX_MBA_BW_AMD; 227 228 /* AMD does not use delay */ 229 r->membw.delay_linear = false; 230 r->membw.arch_needs_linear = false; 231 232 /* 233 * AMD does not use memory delay throttle model to control 234 * the allocation like Intel does. 235 */ 236 r->membw.throttle_mode = THREAD_THROTTLE_UNDEFINED; 237 r->membw.min_bw = 0; 238 r->membw.bw_gran = 1; 239 /* Max value is 2048, Data width should be 4 in decimal */ 240 r->data_width = 4; 241 242 r->alloc_capable = true; 243 244 return true; 245 } 246 247 static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) 248 { 249 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 250 union cpuid_0x10_1_eax eax; 251 union cpuid_0x10_x_edx edx; 252 u32 ebx, ecx; 253 254 cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full); 255 hw_res->num_closid = edx.split.cos_max + 1; 256 r->cache.cbm_len = eax.split.cbm_len + 1; 257 r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1; 258 r->cache.shareable_bits = ebx & r->default_ctrl; 259 r->data_width = (r->cache.cbm_len + 3) / 4; 260 r->alloc_capable = true; 261 } 262 263 static void rdt_get_cdp_config(int level) 264 { 265 /* 266 * By default, CDP is disabled. CDP can be enabled by mount parameter 267 * "cdp" during resctrl file system mount time. 268 */ 269 rdt_resources_all[level].cdp_enabled = false; 270 rdt_resources_all[level].r_resctrl.cdp_capable = true; 271 } 272 273 static void rdt_get_cdp_l3_config(void) 274 { 275 rdt_get_cdp_config(RDT_RESOURCE_L3); 276 } 277 278 static void rdt_get_cdp_l2_config(void) 279 { 280 rdt_get_cdp_config(RDT_RESOURCE_L2); 281 } 282 283 static void 284 mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r) 285 { 286 unsigned int i; 287 struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); 288 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 289 290 for (i = m->low; i < m->high; i++) 291 wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]); 292 } 293 294 /* 295 * Map the memory b/w percentage value to delay values 296 * that can be written to QOS_MSRs. 297 * There are currently no SKUs which support non linear delay values. 298 */ 299 u32 delay_bw_map(unsigned long bw, struct rdt_resource *r) 300 { 301 if (r->membw.delay_linear) 302 return MAX_MBA_BW - bw; 303 304 pr_warn_once("Non Linear delay-bw map not supported but queried\n"); 305 return r->default_ctrl; 306 } 307 308 static void 309 mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m, 310 struct rdt_resource *r) 311 { 312 unsigned int i; 313 struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); 314 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 315 316 /* Write the delay values for mba. */ 317 for (i = m->low; i < m->high; i++) 318 wrmsrl(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], r)); 319 } 320 321 static void 322 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r) 323 { 324 unsigned int i; 325 struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); 326 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 327 328 for (i = m->low; i < m->high; i++) 329 wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]); 330 } 331 332 struct rdt_domain *get_domain_from_cpu(int cpu, struct rdt_resource *r) 333 { 334 struct rdt_domain *d; 335 336 list_for_each_entry(d, &r->domains, list) { 337 /* Find the domain that contains this CPU */ 338 if (cpumask_test_cpu(cpu, &d->cpu_mask)) 339 return d; 340 } 341 342 return NULL; 343 } 344 345 u32 resctrl_arch_get_num_closid(struct rdt_resource *r) 346 { 347 return resctrl_to_arch_res(r)->num_closid; 348 } 349 350 void rdt_ctrl_update(void *arg) 351 { 352 struct msr_param *m = arg; 353 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(m->res); 354 struct rdt_resource *r = m->res; 355 int cpu = smp_processor_id(); 356 struct rdt_domain *d; 357 358 d = get_domain_from_cpu(cpu, r); 359 if (d) { 360 hw_res->msr_update(d, m, r); 361 return; 362 } 363 pr_warn_once("cpu %d not found in any domain for resource %s\n", 364 cpu, r->name); 365 } 366 367 /* 368 * rdt_find_domain - Find a domain in a resource that matches input resource id 369 * 370 * Search resource r's domain list to find the resource id. If the resource 371 * id is found in a domain, return the domain. Otherwise, if requested by 372 * caller, return the first domain whose id is bigger than the input id. 373 * The domain list is sorted by id in ascending order. 374 */ 375 struct rdt_domain *rdt_find_domain(struct rdt_resource *r, int id, 376 struct list_head **pos) 377 { 378 struct rdt_domain *d; 379 struct list_head *l; 380 381 if (id < 0) 382 return ERR_PTR(-ENODEV); 383 384 list_for_each(l, &r->domains) { 385 d = list_entry(l, struct rdt_domain, list); 386 /* When id is found, return its domain. */ 387 if (id == d->id) 388 return d; 389 /* Stop searching when finding id's position in sorted list. */ 390 if (id < d->id) 391 break; 392 } 393 394 if (pos) 395 *pos = l; 396 397 return NULL; 398 } 399 400 void setup_default_ctrlval(struct rdt_resource *r, u32 *dc, u32 *dm) 401 { 402 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 403 int i; 404 405 /* 406 * Initialize the Control MSRs to having no control. 407 * For Cache Allocation: Set all bits in cbm 408 * For Memory Allocation: Set b/w requested to 100% 409 * and the bandwidth in MBps to U32_MAX 410 */ 411 for (i = 0; i < hw_res->num_closid; i++, dc++, dm++) { 412 *dc = r->default_ctrl; 413 *dm = MBA_MAX_MBPS; 414 } 415 } 416 417 static void domain_free(struct rdt_hw_domain *hw_dom) 418 { 419 kfree(hw_dom->ctrl_val); 420 kfree(hw_dom->mbps_val); 421 kfree(hw_dom); 422 } 423 424 static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain *d) 425 { 426 struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); 427 struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); 428 struct msr_param m; 429 u32 *dc, *dm; 430 431 dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val), 432 GFP_KERNEL); 433 if (!dc) 434 return -ENOMEM; 435 436 dm = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->mbps_val), 437 GFP_KERNEL); 438 if (!dm) { 439 kfree(dc); 440 return -ENOMEM; 441 } 442 443 hw_dom->ctrl_val = dc; 444 hw_dom->mbps_val = dm; 445 setup_default_ctrlval(r, dc, dm); 446 447 m.low = 0; 448 m.high = hw_res->num_closid; 449 hw_res->msr_update(d, &m, r); 450 return 0; 451 } 452 453 /* 454 * domain_add_cpu - Add a cpu to a resource's domain list. 455 * 456 * If an existing domain in the resource r's domain list matches the cpu's 457 * resource id, add the cpu in the domain. 458 * 459 * Otherwise, a new domain is allocated and inserted into the right position 460 * in the domain list sorted by id in ascending order. 461 * 462 * The order in the domain list is visible to users when we print entries 463 * in the schemata file and schemata input is validated to have the same order 464 * as this list. 465 */ 466 static void domain_add_cpu(int cpu, struct rdt_resource *r) 467 { 468 int id = get_cpu_cacheinfo_id(cpu, r->cache_level); 469 struct list_head *add_pos = NULL; 470 struct rdt_hw_domain *hw_dom; 471 struct rdt_domain *d; 472 int err; 473 474 d = rdt_find_domain(r, id, &add_pos); 475 if (IS_ERR(d)) { 476 pr_warn("Couldn't find cache id for CPU %d\n", cpu); 477 return; 478 } 479 480 if (d) { 481 cpumask_set_cpu(cpu, &d->cpu_mask); 482 if (r->cache.arch_has_per_cpu_cfg) 483 rdt_domain_reconfigure_cdp(r); 484 return; 485 } 486 487 hw_dom = kzalloc_node(sizeof(*hw_dom), GFP_KERNEL, cpu_to_node(cpu)); 488 if (!hw_dom) 489 return; 490 491 d = &hw_dom->d_resctrl; 492 d->id = id; 493 cpumask_set_cpu(cpu, &d->cpu_mask); 494 495 rdt_domain_reconfigure_cdp(r); 496 497 if (r->alloc_capable && domain_setup_ctrlval(r, d)) { 498 domain_free(hw_dom); 499 return; 500 } 501 502 list_add_tail(&d->list, add_pos); 503 504 err = resctrl_online_domain(r, d); 505 if (err) { 506 list_del(&d->list); 507 domain_free(hw_dom); 508 } 509 } 510 511 static void domain_remove_cpu(int cpu, struct rdt_resource *r) 512 { 513 int id = get_cpu_cacheinfo_id(cpu, r->cache_level); 514 struct rdt_hw_domain *hw_dom; 515 struct rdt_domain *d; 516 517 d = rdt_find_domain(r, id, NULL); 518 if (IS_ERR_OR_NULL(d)) { 519 pr_warn("Couldn't find cache id for CPU %d\n", cpu); 520 return; 521 } 522 hw_dom = resctrl_to_arch_dom(d); 523 524 cpumask_clear_cpu(cpu, &d->cpu_mask); 525 if (cpumask_empty(&d->cpu_mask)) { 526 /* 527 * If resctrl is mounted, remove all the 528 * per domain monitor data directories. 529 */ 530 if (static_branch_unlikely(&rdt_mon_enable_key)) 531 rmdir_mondata_subdir_allrdtgrp(r, d->id); 532 list_del(&d->list); 533 if (r->mon_capable && is_mbm_enabled()) 534 cancel_delayed_work(&d->mbm_over); 535 if (is_llc_occupancy_enabled() && has_busy_rmid(r, d)) { 536 /* 537 * When a package is going down, forcefully 538 * decrement rmid->ebusy. There is no way to know 539 * that the L3 was flushed and hence may lead to 540 * incorrect counts in rare scenarios, but leaving 541 * the RMID as busy creates RMID leaks if the 542 * package never comes back. 543 */ 544 __check_limbo(d, true); 545 cancel_delayed_work(&d->cqm_limbo); 546 } 547 548 /* 549 * rdt_domain "d" is going to be freed below, so clear 550 * its pointer from pseudo_lock_region struct. 551 */ 552 if (d->plr) 553 d->plr->d = NULL; 554 555 bitmap_free(d->rmid_busy_llc); 556 kfree(d->mbm_total); 557 kfree(d->mbm_local); 558 domain_free(hw_dom); 559 return; 560 } 561 562 if (r == &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl) { 563 if (is_mbm_enabled() && cpu == d->mbm_work_cpu) { 564 cancel_delayed_work(&d->mbm_over); 565 mbm_setup_overflow_handler(d, 0); 566 } 567 if (is_llc_occupancy_enabled() && cpu == d->cqm_work_cpu && 568 has_busy_rmid(r, d)) { 569 cancel_delayed_work(&d->cqm_limbo); 570 cqm_setup_limbo_handler(d, 0); 571 } 572 } 573 } 574 575 static void clear_closid_rmid(int cpu) 576 { 577 struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state); 578 579 state->default_closid = 0; 580 state->default_rmid = 0; 581 state->cur_closid = 0; 582 state->cur_rmid = 0; 583 wrmsr(IA32_PQR_ASSOC, 0, 0); 584 } 585 586 static int resctrl_online_cpu(unsigned int cpu) 587 { 588 struct rdt_resource *r; 589 590 mutex_lock(&rdtgroup_mutex); 591 for_each_capable_rdt_resource(r) 592 domain_add_cpu(cpu, r); 593 /* The cpu is set in default rdtgroup after online. */ 594 cpumask_set_cpu(cpu, &rdtgroup_default.cpu_mask); 595 clear_closid_rmid(cpu); 596 mutex_unlock(&rdtgroup_mutex); 597 598 return 0; 599 } 600 601 static void clear_childcpus(struct rdtgroup *r, unsigned int cpu) 602 { 603 struct rdtgroup *cr; 604 605 list_for_each_entry(cr, &r->mon.crdtgrp_list, mon.crdtgrp_list) { 606 if (cpumask_test_and_clear_cpu(cpu, &cr->cpu_mask)) { 607 break; 608 } 609 } 610 } 611 612 static int resctrl_offline_cpu(unsigned int cpu) 613 { 614 struct rdtgroup *rdtgrp; 615 struct rdt_resource *r; 616 617 mutex_lock(&rdtgroup_mutex); 618 for_each_capable_rdt_resource(r) 619 domain_remove_cpu(cpu, r); 620 list_for_each_entry(rdtgrp, &rdt_all_groups, rdtgroup_list) { 621 if (cpumask_test_and_clear_cpu(cpu, &rdtgrp->cpu_mask)) { 622 clear_childcpus(rdtgrp, cpu); 623 break; 624 } 625 } 626 clear_closid_rmid(cpu); 627 mutex_unlock(&rdtgroup_mutex); 628 629 return 0; 630 } 631 632 /* 633 * Choose a width for the resource name and resource data based on the 634 * resource that has widest name and cbm. 635 */ 636 static __init void rdt_init_padding(void) 637 { 638 struct rdt_resource *r; 639 640 for_each_alloc_capable_rdt_resource(r) { 641 if (r->data_width > max_data_width) 642 max_data_width = r->data_width; 643 } 644 } 645 646 enum { 647 RDT_FLAG_CMT, 648 RDT_FLAG_MBM_TOTAL, 649 RDT_FLAG_MBM_LOCAL, 650 RDT_FLAG_L3_CAT, 651 RDT_FLAG_L3_CDP, 652 RDT_FLAG_L2_CAT, 653 RDT_FLAG_L2_CDP, 654 RDT_FLAG_MBA, 655 }; 656 657 #define RDT_OPT(idx, n, f) \ 658 [idx] = { \ 659 .name = n, \ 660 .flag = f \ 661 } 662 663 struct rdt_options { 664 char *name; 665 int flag; 666 bool force_off, force_on; 667 }; 668 669 static struct rdt_options rdt_options[] __initdata = { 670 RDT_OPT(RDT_FLAG_CMT, "cmt", X86_FEATURE_CQM_OCCUP_LLC), 671 RDT_OPT(RDT_FLAG_MBM_TOTAL, "mbmtotal", X86_FEATURE_CQM_MBM_TOTAL), 672 RDT_OPT(RDT_FLAG_MBM_LOCAL, "mbmlocal", X86_FEATURE_CQM_MBM_LOCAL), 673 RDT_OPT(RDT_FLAG_L3_CAT, "l3cat", X86_FEATURE_CAT_L3), 674 RDT_OPT(RDT_FLAG_L3_CDP, "l3cdp", X86_FEATURE_CDP_L3), 675 RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2), 676 RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2), 677 RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA), 678 }; 679 #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options) 680 681 static int __init set_rdt_options(char *str) 682 { 683 struct rdt_options *o; 684 bool force_off; 685 char *tok; 686 687 if (*str == '=') 688 str++; 689 while ((tok = strsep(&str, ",")) != NULL) { 690 force_off = *tok == '!'; 691 if (force_off) 692 tok++; 693 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) { 694 if (strcmp(tok, o->name) == 0) { 695 if (force_off) 696 o->force_off = true; 697 else 698 o->force_on = true; 699 break; 700 } 701 } 702 } 703 return 1; 704 } 705 __setup("rdt", set_rdt_options); 706 707 static bool __init rdt_cpu_has(int flag) 708 { 709 bool ret = boot_cpu_has(flag); 710 struct rdt_options *o; 711 712 if (!ret) 713 return ret; 714 715 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) { 716 if (flag == o->flag) { 717 if (o->force_off) 718 ret = false; 719 if (o->force_on) 720 ret = true; 721 break; 722 } 723 } 724 return ret; 725 } 726 727 static __init bool get_mem_config(void) 728 { 729 struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_MBA]; 730 731 if (!rdt_cpu_has(X86_FEATURE_MBA)) 732 return false; 733 734 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 735 return __get_mem_config_intel(&hw_res->r_resctrl); 736 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 737 return __rdt_get_mem_config_amd(&hw_res->r_resctrl); 738 739 return false; 740 } 741 742 static __init bool get_rdt_alloc_resources(void) 743 { 744 struct rdt_resource *r; 745 bool ret = false; 746 747 if (rdt_alloc_capable) 748 return true; 749 750 if (!boot_cpu_has(X86_FEATURE_RDT_A)) 751 return false; 752 753 if (rdt_cpu_has(X86_FEATURE_CAT_L3)) { 754 r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; 755 rdt_get_cache_alloc_cfg(1, r); 756 if (rdt_cpu_has(X86_FEATURE_CDP_L3)) 757 rdt_get_cdp_l3_config(); 758 ret = true; 759 } 760 if (rdt_cpu_has(X86_FEATURE_CAT_L2)) { 761 /* CPUID 0x10.2 fields are same format at 0x10.1 */ 762 r = &rdt_resources_all[RDT_RESOURCE_L2].r_resctrl; 763 rdt_get_cache_alloc_cfg(2, r); 764 if (rdt_cpu_has(X86_FEATURE_CDP_L2)) 765 rdt_get_cdp_l2_config(); 766 ret = true; 767 } 768 769 if (get_mem_config()) 770 ret = true; 771 772 return ret; 773 } 774 775 static __init bool get_rdt_mon_resources(void) 776 { 777 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; 778 779 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) 780 rdt_mon_features |= (1 << QOS_L3_OCCUP_EVENT_ID); 781 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) 782 rdt_mon_features |= (1 << QOS_L3_MBM_TOTAL_EVENT_ID); 783 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL)) 784 rdt_mon_features |= (1 << QOS_L3_MBM_LOCAL_EVENT_ID); 785 786 if (!rdt_mon_features) 787 return false; 788 789 return !rdt_get_mon_l3_config(r); 790 } 791 792 static __init void __check_quirks_intel(void) 793 { 794 switch (boot_cpu_data.x86_model) { 795 case INTEL_FAM6_HASWELL_X: 796 if (!rdt_options[RDT_FLAG_L3_CAT].force_off) 797 cache_alloc_hsw_probe(); 798 break; 799 case INTEL_FAM6_SKYLAKE_X: 800 if (boot_cpu_data.x86_stepping <= 4) 801 set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat"); 802 else 803 set_rdt_options("!l3cat"); 804 fallthrough; 805 case INTEL_FAM6_BROADWELL_X: 806 intel_rdt_mbm_apply_quirk(); 807 break; 808 } 809 } 810 811 static __init void check_quirks(void) 812 { 813 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 814 __check_quirks_intel(); 815 } 816 817 static __init bool get_rdt_resources(void) 818 { 819 rdt_alloc_capable = get_rdt_alloc_resources(); 820 rdt_mon_capable = get_rdt_mon_resources(); 821 822 return (rdt_mon_capable || rdt_alloc_capable); 823 } 824 825 static __init void rdt_init_res_defs_intel(void) 826 { 827 struct rdt_hw_resource *hw_res; 828 struct rdt_resource *r; 829 830 for_each_rdt_resource(r) { 831 hw_res = resctrl_to_arch_res(r); 832 833 if (r->rid == RDT_RESOURCE_L3 || 834 r->rid == RDT_RESOURCE_L2) { 835 r->cache.arch_has_sparse_bitmaps = false; 836 r->cache.arch_has_empty_bitmaps = false; 837 r->cache.arch_has_per_cpu_cfg = false; 838 } else if (r->rid == RDT_RESOURCE_MBA) { 839 hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE; 840 hw_res->msr_update = mba_wrmsr_intel; 841 } 842 } 843 } 844 845 static __init void rdt_init_res_defs_amd(void) 846 { 847 struct rdt_hw_resource *hw_res; 848 struct rdt_resource *r; 849 850 for_each_rdt_resource(r) { 851 hw_res = resctrl_to_arch_res(r); 852 853 if (r->rid == RDT_RESOURCE_L3 || 854 r->rid == RDT_RESOURCE_L2) { 855 r->cache.arch_has_sparse_bitmaps = true; 856 r->cache.arch_has_empty_bitmaps = true; 857 r->cache.arch_has_per_cpu_cfg = true; 858 } else if (r->rid == RDT_RESOURCE_MBA) { 859 hw_res->msr_base = MSR_IA32_MBA_BW_BASE; 860 hw_res->msr_update = mba_wrmsr_amd; 861 } 862 } 863 } 864 865 static __init void rdt_init_res_defs(void) 866 { 867 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 868 rdt_init_res_defs_intel(); 869 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 870 rdt_init_res_defs_amd(); 871 } 872 873 static enum cpuhp_state rdt_online; 874 875 /* Runs once on the BSP during boot. */ 876 void resctrl_cpu_detect(struct cpuinfo_x86 *c) 877 { 878 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { 879 c->x86_cache_max_rmid = -1; 880 c->x86_cache_occ_scale = -1; 881 c->x86_cache_mbm_width_offset = -1; 882 return; 883 } 884 885 /* will be overridden if occupancy monitoring exists */ 886 c->x86_cache_max_rmid = cpuid_ebx(0xf); 887 888 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || 889 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || 890 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { 891 u32 eax, ebx, ecx, edx; 892 893 /* QoS sub-leaf, EAX=0Fh, ECX=1 */ 894 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); 895 896 c->x86_cache_max_rmid = ecx; 897 c->x86_cache_occ_scale = ebx; 898 c->x86_cache_mbm_width_offset = eax & 0xff; 899 900 if (c->x86_vendor == X86_VENDOR_AMD && !c->x86_cache_mbm_width_offset) 901 c->x86_cache_mbm_width_offset = MBM_CNTR_WIDTH_OFFSET_AMD; 902 } 903 } 904 905 static int __init resctrl_late_init(void) 906 { 907 struct rdt_resource *r; 908 int state, ret; 909 910 /* 911 * Initialize functions(or definitions) that are different 912 * between vendors here. 913 */ 914 rdt_init_res_defs(); 915 916 check_quirks(); 917 918 if (!get_rdt_resources()) 919 return -ENODEV; 920 921 rdt_init_padding(); 922 923 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 924 "x86/resctrl/cat:online:", 925 resctrl_online_cpu, resctrl_offline_cpu); 926 if (state < 0) 927 return state; 928 929 ret = rdtgroup_init(); 930 if (ret) { 931 cpuhp_remove_state(state); 932 return ret; 933 } 934 rdt_online = state; 935 936 for_each_alloc_capable_rdt_resource(r) 937 pr_info("%s allocation detected\n", r->name); 938 939 for_each_mon_capable_rdt_resource(r) 940 pr_info("%s monitoring detected\n", r->name); 941 942 return 0; 943 } 944 945 late_initcall(resctrl_late_init); 946 947 static void __exit resctrl_exit(void) 948 { 949 cpuhp_remove_state(rdt_online); 950 rdtgroup_exit(); 951 } 952 953 __exitcall(resctrl_exit); 954