1 /* 2 * Resource Director Technology(RDT) 3 * - Cache Allocation code. 4 * 5 * Copyright (C) 2016 Intel Corporation 6 * 7 * Authors: 8 * Fenghua Yu <fenghua.yu@intel.com> 9 * Tony Luck <tony.luck@intel.com> 10 * Vikas Shivappa <vikas.shivappa@intel.com> 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms and conditions of the GNU General Public License, 14 * version 2, as published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * More information about RDT be found in the Intel (R) x86 Architecture 22 * Software Developer Manual June 2016, volume 3, section 17.17. 23 */ 24 25 #define pr_fmt(fmt) "resctrl: " fmt 26 27 #include <linux/slab.h> 28 #include <linux/err.h> 29 #include <linux/cacheinfo.h> 30 #include <linux/cpuhotplug.h> 31 32 #include <asm/intel-family.h> 33 #include <asm/resctrl_sched.h> 34 #include "internal.h" 35 36 /* Mutex to protect rdtgroup access. */ 37 DEFINE_MUTEX(rdtgroup_mutex); 38 39 /* 40 * The cached resctrl_pqr_state is strictly per CPU and can never be 41 * updated from a remote CPU. Functions which modify the state 42 * are called with interrupts disabled and no preemption, which 43 * is sufficient for the protection. 44 */ 45 DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state); 46 47 /* 48 * Used to store the max resource name width and max resource data width 49 * to display the schemata in a tabular format 50 */ 51 int max_name_width, max_data_width; 52 53 /* 54 * Global boolean for rdt_alloc which is true if any 55 * resource allocation is enabled. 56 */ 57 bool rdt_alloc_capable; 58 59 static void 60 mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m, 61 struct rdt_resource *r); 62 static void 63 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r); 64 static void 65 mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, 66 struct rdt_resource *r); 67 68 #define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].domains) 69 70 struct rdt_resource rdt_resources_all[] = { 71 [RDT_RESOURCE_L3] = 72 { 73 .rid = RDT_RESOURCE_L3, 74 .name = "L3", 75 .domains = domain_init(RDT_RESOURCE_L3), 76 .msr_base = MSR_IA32_L3_CBM_BASE, 77 .msr_update = cat_wrmsr, 78 .cache_level = 3, 79 .cache = { 80 .min_cbm_bits = 1, 81 .cbm_idx_mult = 1, 82 .cbm_idx_offset = 0, 83 }, 84 .parse_ctrlval = parse_cbm, 85 .format_str = "%d=%0*x", 86 .fflags = RFTYPE_RES_CACHE, 87 }, 88 [RDT_RESOURCE_L3DATA] = 89 { 90 .rid = RDT_RESOURCE_L3DATA, 91 .name = "L3DATA", 92 .domains = domain_init(RDT_RESOURCE_L3DATA), 93 .msr_base = MSR_IA32_L3_CBM_BASE, 94 .msr_update = cat_wrmsr, 95 .cache_level = 3, 96 .cache = { 97 .min_cbm_bits = 1, 98 .cbm_idx_mult = 2, 99 .cbm_idx_offset = 0, 100 }, 101 .parse_ctrlval = parse_cbm, 102 .format_str = "%d=%0*x", 103 .fflags = RFTYPE_RES_CACHE, 104 }, 105 [RDT_RESOURCE_L3CODE] = 106 { 107 .rid = RDT_RESOURCE_L3CODE, 108 .name = "L3CODE", 109 .domains = domain_init(RDT_RESOURCE_L3CODE), 110 .msr_base = MSR_IA32_L3_CBM_BASE, 111 .msr_update = cat_wrmsr, 112 .cache_level = 3, 113 .cache = { 114 .min_cbm_bits = 1, 115 .cbm_idx_mult = 2, 116 .cbm_idx_offset = 1, 117 }, 118 .parse_ctrlval = parse_cbm, 119 .format_str = "%d=%0*x", 120 .fflags = RFTYPE_RES_CACHE, 121 }, 122 [RDT_RESOURCE_L2] = 123 { 124 .rid = RDT_RESOURCE_L2, 125 .name = "L2", 126 .domains = domain_init(RDT_RESOURCE_L2), 127 .msr_base = MSR_IA32_L2_CBM_BASE, 128 .msr_update = cat_wrmsr, 129 .cache_level = 2, 130 .cache = { 131 .min_cbm_bits = 1, 132 .cbm_idx_mult = 1, 133 .cbm_idx_offset = 0, 134 }, 135 .parse_ctrlval = parse_cbm, 136 .format_str = "%d=%0*x", 137 .fflags = RFTYPE_RES_CACHE, 138 }, 139 [RDT_RESOURCE_L2DATA] = 140 { 141 .rid = RDT_RESOURCE_L2DATA, 142 .name = "L2DATA", 143 .domains = domain_init(RDT_RESOURCE_L2DATA), 144 .msr_base = MSR_IA32_L2_CBM_BASE, 145 .msr_update = cat_wrmsr, 146 .cache_level = 2, 147 .cache = { 148 .min_cbm_bits = 1, 149 .cbm_idx_mult = 2, 150 .cbm_idx_offset = 0, 151 }, 152 .parse_ctrlval = parse_cbm, 153 .format_str = "%d=%0*x", 154 .fflags = RFTYPE_RES_CACHE, 155 }, 156 [RDT_RESOURCE_L2CODE] = 157 { 158 .rid = RDT_RESOURCE_L2CODE, 159 .name = "L2CODE", 160 .domains = domain_init(RDT_RESOURCE_L2CODE), 161 .msr_base = MSR_IA32_L2_CBM_BASE, 162 .msr_update = cat_wrmsr, 163 .cache_level = 2, 164 .cache = { 165 .min_cbm_bits = 1, 166 .cbm_idx_mult = 2, 167 .cbm_idx_offset = 1, 168 }, 169 .parse_ctrlval = parse_cbm, 170 .format_str = "%d=%0*x", 171 .fflags = RFTYPE_RES_CACHE, 172 }, 173 [RDT_RESOURCE_MBA] = 174 { 175 .rid = RDT_RESOURCE_MBA, 176 .name = "MB", 177 .domains = domain_init(RDT_RESOURCE_MBA), 178 .cache_level = 3, 179 .format_str = "%d=%*u", 180 .fflags = RFTYPE_RES_MB, 181 }, 182 }; 183 184 static unsigned int cbm_idx(struct rdt_resource *r, unsigned int closid) 185 { 186 return closid * r->cache.cbm_idx_mult + r->cache.cbm_idx_offset; 187 } 188 189 /* 190 * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs 191 * as they do not have CPUID enumeration support for Cache allocation. 192 * The check for Vendor/Family/Model is not enough to guarantee that 193 * the MSRs won't #GP fault because only the following SKUs support 194 * CAT: 195 * Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz 196 * Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz 197 * Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz 198 * Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz 199 * Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz 200 * Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz 201 * 202 * Probe by trying to write the first of the L3 cach mask registers 203 * and checking that the bits stick. Max CLOSids is always 4 and max cbm length 204 * is always 20 on hsw server parts. The minimum cache bitmask length 205 * allowed for HSW server is always 2 bits. Hardcode all of them. 206 */ 207 static inline void cache_alloc_hsw_probe(void) 208 { 209 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3]; 210 u32 l, h, max_cbm = BIT_MASK(20) - 1; 211 212 if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0)) 213 return; 214 215 rdmsr(MSR_IA32_L3_CBM_BASE, l, h); 216 217 /* If all the bits were set in MSR, return success */ 218 if (l != max_cbm) 219 return; 220 221 r->num_closid = 4; 222 r->default_ctrl = max_cbm; 223 r->cache.cbm_len = 20; 224 r->cache.shareable_bits = 0xc0000; 225 r->cache.min_cbm_bits = 2; 226 r->alloc_capable = true; 227 r->alloc_enabled = true; 228 229 rdt_alloc_capable = true; 230 } 231 232 bool is_mba_sc(struct rdt_resource *r) 233 { 234 if (!r) 235 return rdt_resources_all[RDT_RESOURCE_MBA].membw.mba_sc; 236 237 return r->membw.mba_sc; 238 } 239 240 /* 241 * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values 242 * exposed to user interface and the h/w understandable delay values. 243 * 244 * The non-linear delay values have the granularity of power of two 245 * and also the h/w does not guarantee a curve for configured delay 246 * values vs. actual b/w enforced. 247 * Hence we need a mapping that is pre calibrated so the user can 248 * express the memory b/w as a percentage value. 249 */ 250 static inline bool rdt_get_mb_table(struct rdt_resource *r) 251 { 252 /* 253 * There are no Intel SKUs as of now to support non-linear delay. 254 */ 255 pr_info("MBA b/w map not implemented for cpu:%d, model:%d", 256 boot_cpu_data.x86, boot_cpu_data.x86_model); 257 258 return false; 259 } 260 261 static bool __get_mem_config_intel(struct rdt_resource *r) 262 { 263 union cpuid_0x10_3_eax eax; 264 union cpuid_0x10_x_edx edx; 265 u32 ebx, ecx; 266 267 cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full); 268 r->num_closid = edx.split.cos_max + 1; 269 r->membw.max_delay = eax.split.max_delay + 1; 270 r->default_ctrl = MAX_MBA_BW; 271 if (ecx & MBA_IS_LINEAR) { 272 r->membw.delay_linear = true; 273 r->membw.min_bw = MAX_MBA_BW - r->membw.max_delay; 274 r->membw.bw_gran = MAX_MBA_BW - r->membw.max_delay; 275 } else { 276 if (!rdt_get_mb_table(r)) 277 return false; 278 } 279 r->data_width = 3; 280 281 r->alloc_capable = true; 282 r->alloc_enabled = true; 283 284 return true; 285 } 286 287 static bool __rdt_get_mem_config_amd(struct rdt_resource *r) 288 { 289 union cpuid_0x10_3_eax eax; 290 union cpuid_0x10_x_edx edx; 291 u32 ebx, ecx; 292 293 cpuid_count(0x80000020, 1, &eax.full, &ebx, &ecx, &edx.full); 294 r->num_closid = edx.split.cos_max + 1; 295 r->default_ctrl = MAX_MBA_BW_AMD; 296 297 /* AMD does not use delay */ 298 r->membw.delay_linear = false; 299 300 r->membw.min_bw = 0; 301 r->membw.bw_gran = 1; 302 /* Max value is 2048, Data width should be 4 in decimal */ 303 r->data_width = 4; 304 305 r->alloc_capable = true; 306 r->alloc_enabled = true; 307 308 return true; 309 } 310 311 static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) 312 { 313 union cpuid_0x10_1_eax eax; 314 union cpuid_0x10_x_edx edx; 315 u32 ebx, ecx; 316 317 cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full); 318 r->num_closid = edx.split.cos_max + 1; 319 r->cache.cbm_len = eax.split.cbm_len + 1; 320 r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1; 321 r->cache.shareable_bits = ebx & r->default_ctrl; 322 r->data_width = (r->cache.cbm_len + 3) / 4; 323 r->alloc_capable = true; 324 r->alloc_enabled = true; 325 } 326 327 static void rdt_get_cdp_config(int level, int type) 328 { 329 struct rdt_resource *r_l = &rdt_resources_all[level]; 330 struct rdt_resource *r = &rdt_resources_all[type]; 331 332 r->num_closid = r_l->num_closid / 2; 333 r->cache.cbm_len = r_l->cache.cbm_len; 334 r->default_ctrl = r_l->default_ctrl; 335 r->cache.shareable_bits = r_l->cache.shareable_bits; 336 r->data_width = (r->cache.cbm_len + 3) / 4; 337 r->alloc_capable = true; 338 /* 339 * By default, CDP is disabled. CDP can be enabled by mount parameter 340 * "cdp" during resctrl file system mount time. 341 */ 342 r->alloc_enabled = false; 343 } 344 345 static void rdt_get_cdp_l3_config(void) 346 { 347 rdt_get_cdp_config(RDT_RESOURCE_L3, RDT_RESOURCE_L3DATA); 348 rdt_get_cdp_config(RDT_RESOURCE_L3, RDT_RESOURCE_L3CODE); 349 } 350 351 static void rdt_get_cdp_l2_config(void) 352 { 353 rdt_get_cdp_config(RDT_RESOURCE_L2, RDT_RESOURCE_L2DATA); 354 rdt_get_cdp_config(RDT_RESOURCE_L2, RDT_RESOURCE_L2CODE); 355 } 356 357 static int get_cache_id(int cpu, int level) 358 { 359 struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu); 360 int i; 361 362 for (i = 0; i < ci->num_leaves; i++) { 363 if (ci->info_list[i].level == level) 364 return ci->info_list[i].id; 365 } 366 367 return -1; 368 } 369 370 static void 371 mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r) 372 { 373 unsigned int i; 374 375 for (i = m->low; i < m->high; i++) 376 wrmsrl(r->msr_base + i, d->ctrl_val[i]); 377 } 378 379 /* 380 * Map the memory b/w percentage value to delay values 381 * that can be written to QOS_MSRs. 382 * There are currently no SKUs which support non linear delay values. 383 */ 384 u32 delay_bw_map(unsigned long bw, struct rdt_resource *r) 385 { 386 if (r->membw.delay_linear) 387 return MAX_MBA_BW - bw; 388 389 pr_warn_once("Non Linear delay-bw map not supported but queried\n"); 390 return r->default_ctrl; 391 } 392 393 static void 394 mba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m, 395 struct rdt_resource *r) 396 { 397 unsigned int i; 398 399 /* Write the delay values for mba. */ 400 for (i = m->low; i < m->high; i++) 401 wrmsrl(r->msr_base + i, delay_bw_map(d->ctrl_val[i], r)); 402 } 403 404 static void 405 cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r) 406 { 407 unsigned int i; 408 409 for (i = m->low; i < m->high; i++) 410 wrmsrl(r->msr_base + cbm_idx(r, i), d->ctrl_val[i]); 411 } 412 413 struct rdt_domain *get_domain_from_cpu(int cpu, struct rdt_resource *r) 414 { 415 struct rdt_domain *d; 416 417 list_for_each_entry(d, &r->domains, list) { 418 /* Find the domain that contains this CPU */ 419 if (cpumask_test_cpu(cpu, &d->cpu_mask)) 420 return d; 421 } 422 423 return NULL; 424 } 425 426 void rdt_ctrl_update(void *arg) 427 { 428 struct msr_param *m = arg; 429 struct rdt_resource *r = m->res; 430 int cpu = smp_processor_id(); 431 struct rdt_domain *d; 432 433 d = get_domain_from_cpu(cpu, r); 434 if (d) { 435 r->msr_update(d, m, r); 436 return; 437 } 438 pr_warn_once("cpu %d not found in any domain for resource %s\n", 439 cpu, r->name); 440 } 441 442 /* 443 * rdt_find_domain - Find a domain in a resource that matches input resource id 444 * 445 * Search resource r's domain list to find the resource id. If the resource 446 * id is found in a domain, return the domain. Otherwise, if requested by 447 * caller, return the first domain whose id is bigger than the input id. 448 * The domain list is sorted by id in ascending order. 449 */ 450 struct rdt_domain *rdt_find_domain(struct rdt_resource *r, int id, 451 struct list_head **pos) 452 { 453 struct rdt_domain *d; 454 struct list_head *l; 455 456 if (id < 0) 457 return ERR_PTR(-ENODEV); 458 459 list_for_each(l, &r->domains) { 460 d = list_entry(l, struct rdt_domain, list); 461 /* When id is found, return its domain. */ 462 if (id == d->id) 463 return d; 464 /* Stop searching when finding id's position in sorted list. */ 465 if (id < d->id) 466 break; 467 } 468 469 if (pos) 470 *pos = l; 471 472 return NULL; 473 } 474 475 void setup_default_ctrlval(struct rdt_resource *r, u32 *dc, u32 *dm) 476 { 477 int i; 478 479 /* 480 * Initialize the Control MSRs to having no control. 481 * For Cache Allocation: Set all bits in cbm 482 * For Memory Allocation: Set b/w requested to 100% 483 * and the bandwidth in MBps to U32_MAX 484 */ 485 for (i = 0; i < r->num_closid; i++, dc++, dm++) { 486 *dc = r->default_ctrl; 487 *dm = MBA_MAX_MBPS; 488 } 489 } 490 491 static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain *d) 492 { 493 struct msr_param m; 494 u32 *dc, *dm; 495 496 dc = kmalloc_array(r->num_closid, sizeof(*d->ctrl_val), GFP_KERNEL); 497 if (!dc) 498 return -ENOMEM; 499 500 dm = kmalloc_array(r->num_closid, sizeof(*d->mbps_val), GFP_KERNEL); 501 if (!dm) { 502 kfree(dc); 503 return -ENOMEM; 504 } 505 506 d->ctrl_val = dc; 507 d->mbps_val = dm; 508 setup_default_ctrlval(r, dc, dm); 509 510 m.low = 0; 511 m.high = r->num_closid; 512 r->msr_update(d, &m, r); 513 return 0; 514 } 515 516 static int domain_setup_mon_state(struct rdt_resource *r, struct rdt_domain *d) 517 { 518 size_t tsize; 519 520 if (is_llc_occupancy_enabled()) { 521 d->rmid_busy_llc = bitmap_zalloc(r->num_rmid, GFP_KERNEL); 522 if (!d->rmid_busy_llc) 523 return -ENOMEM; 524 INIT_DELAYED_WORK(&d->cqm_limbo, cqm_handle_limbo); 525 } 526 if (is_mbm_total_enabled()) { 527 tsize = sizeof(*d->mbm_total); 528 d->mbm_total = kcalloc(r->num_rmid, tsize, GFP_KERNEL); 529 if (!d->mbm_total) { 530 bitmap_free(d->rmid_busy_llc); 531 return -ENOMEM; 532 } 533 } 534 if (is_mbm_local_enabled()) { 535 tsize = sizeof(*d->mbm_local); 536 d->mbm_local = kcalloc(r->num_rmid, tsize, GFP_KERNEL); 537 if (!d->mbm_local) { 538 bitmap_free(d->rmid_busy_llc); 539 kfree(d->mbm_total); 540 return -ENOMEM; 541 } 542 } 543 544 if (is_mbm_enabled()) { 545 INIT_DELAYED_WORK(&d->mbm_over, mbm_handle_overflow); 546 mbm_setup_overflow_handler(d, MBM_OVERFLOW_INTERVAL); 547 } 548 549 return 0; 550 } 551 552 /* 553 * domain_add_cpu - Add a cpu to a resource's domain list. 554 * 555 * If an existing domain in the resource r's domain list matches the cpu's 556 * resource id, add the cpu in the domain. 557 * 558 * Otherwise, a new domain is allocated and inserted into the right position 559 * in the domain list sorted by id in ascending order. 560 * 561 * The order in the domain list is visible to users when we print entries 562 * in the schemata file and schemata input is validated to have the same order 563 * as this list. 564 */ 565 static void domain_add_cpu(int cpu, struct rdt_resource *r) 566 { 567 int id = get_cache_id(cpu, r->cache_level); 568 struct list_head *add_pos = NULL; 569 struct rdt_domain *d; 570 571 d = rdt_find_domain(r, id, &add_pos); 572 if (IS_ERR(d)) { 573 pr_warn("Could't find cache id for cpu %d\n", cpu); 574 return; 575 } 576 577 if (d) { 578 cpumask_set_cpu(cpu, &d->cpu_mask); 579 return; 580 } 581 582 d = kzalloc_node(sizeof(*d), GFP_KERNEL, cpu_to_node(cpu)); 583 if (!d) 584 return; 585 586 d->id = id; 587 cpumask_set_cpu(cpu, &d->cpu_mask); 588 589 if (r->alloc_capable && domain_setup_ctrlval(r, d)) { 590 kfree(d); 591 return; 592 } 593 594 if (r->mon_capable && domain_setup_mon_state(r, d)) { 595 kfree(d); 596 return; 597 } 598 599 list_add_tail(&d->list, add_pos); 600 601 /* 602 * If resctrl is mounted, add 603 * per domain monitor data directories. 604 */ 605 if (static_branch_unlikely(&rdt_mon_enable_key)) 606 mkdir_mondata_subdir_allrdtgrp(r, d); 607 } 608 609 static void domain_remove_cpu(int cpu, struct rdt_resource *r) 610 { 611 int id = get_cache_id(cpu, r->cache_level); 612 struct rdt_domain *d; 613 614 d = rdt_find_domain(r, id, NULL); 615 if (IS_ERR_OR_NULL(d)) { 616 pr_warn("Could't find cache id for cpu %d\n", cpu); 617 return; 618 } 619 620 cpumask_clear_cpu(cpu, &d->cpu_mask); 621 if (cpumask_empty(&d->cpu_mask)) { 622 /* 623 * If resctrl is mounted, remove all the 624 * per domain monitor data directories. 625 */ 626 if (static_branch_unlikely(&rdt_mon_enable_key)) 627 rmdir_mondata_subdir_allrdtgrp(r, d->id); 628 list_del(&d->list); 629 if (is_mbm_enabled()) 630 cancel_delayed_work(&d->mbm_over); 631 if (is_llc_occupancy_enabled() && has_busy_rmid(r, d)) { 632 /* 633 * When a package is going down, forcefully 634 * decrement rmid->ebusy. There is no way to know 635 * that the L3 was flushed and hence may lead to 636 * incorrect counts in rare scenarios, but leaving 637 * the RMID as busy creates RMID leaks if the 638 * package never comes back. 639 */ 640 __check_limbo(d, true); 641 cancel_delayed_work(&d->cqm_limbo); 642 } 643 644 /* 645 * rdt_domain "d" is going to be freed below, so clear 646 * its pointer from pseudo_lock_region struct. 647 */ 648 if (d->plr) 649 d->plr->d = NULL; 650 651 kfree(d->ctrl_val); 652 kfree(d->mbps_val); 653 bitmap_free(d->rmid_busy_llc); 654 kfree(d->mbm_total); 655 kfree(d->mbm_local); 656 kfree(d); 657 return; 658 } 659 660 if (r == &rdt_resources_all[RDT_RESOURCE_L3]) { 661 if (is_mbm_enabled() && cpu == d->mbm_work_cpu) { 662 cancel_delayed_work(&d->mbm_over); 663 mbm_setup_overflow_handler(d, 0); 664 } 665 if (is_llc_occupancy_enabled() && cpu == d->cqm_work_cpu && 666 has_busy_rmid(r, d)) { 667 cancel_delayed_work(&d->cqm_limbo); 668 cqm_setup_limbo_handler(d, 0); 669 } 670 } 671 } 672 673 static void clear_closid_rmid(int cpu) 674 { 675 struct resctrl_pqr_state *state = this_cpu_ptr(&pqr_state); 676 677 state->default_closid = 0; 678 state->default_rmid = 0; 679 state->cur_closid = 0; 680 state->cur_rmid = 0; 681 wrmsr(IA32_PQR_ASSOC, 0, 0); 682 } 683 684 static int resctrl_online_cpu(unsigned int cpu) 685 { 686 struct rdt_resource *r; 687 688 mutex_lock(&rdtgroup_mutex); 689 for_each_capable_rdt_resource(r) 690 domain_add_cpu(cpu, r); 691 /* The cpu is set in default rdtgroup after online. */ 692 cpumask_set_cpu(cpu, &rdtgroup_default.cpu_mask); 693 clear_closid_rmid(cpu); 694 mutex_unlock(&rdtgroup_mutex); 695 696 return 0; 697 } 698 699 static void clear_childcpus(struct rdtgroup *r, unsigned int cpu) 700 { 701 struct rdtgroup *cr; 702 703 list_for_each_entry(cr, &r->mon.crdtgrp_list, mon.crdtgrp_list) { 704 if (cpumask_test_and_clear_cpu(cpu, &cr->cpu_mask)) { 705 break; 706 } 707 } 708 } 709 710 static int resctrl_offline_cpu(unsigned int cpu) 711 { 712 struct rdtgroup *rdtgrp; 713 struct rdt_resource *r; 714 715 mutex_lock(&rdtgroup_mutex); 716 for_each_capable_rdt_resource(r) 717 domain_remove_cpu(cpu, r); 718 list_for_each_entry(rdtgrp, &rdt_all_groups, rdtgroup_list) { 719 if (cpumask_test_and_clear_cpu(cpu, &rdtgrp->cpu_mask)) { 720 clear_childcpus(rdtgrp, cpu); 721 break; 722 } 723 } 724 clear_closid_rmid(cpu); 725 mutex_unlock(&rdtgroup_mutex); 726 727 return 0; 728 } 729 730 /* 731 * Choose a width for the resource name and resource data based on the 732 * resource that has widest name and cbm. 733 */ 734 static __init void rdt_init_padding(void) 735 { 736 struct rdt_resource *r; 737 int cl; 738 739 for_each_alloc_capable_rdt_resource(r) { 740 cl = strlen(r->name); 741 if (cl > max_name_width) 742 max_name_width = cl; 743 744 if (r->data_width > max_data_width) 745 max_data_width = r->data_width; 746 } 747 } 748 749 enum { 750 RDT_FLAG_CMT, 751 RDT_FLAG_MBM_TOTAL, 752 RDT_FLAG_MBM_LOCAL, 753 RDT_FLAG_L3_CAT, 754 RDT_FLAG_L3_CDP, 755 RDT_FLAG_L2_CAT, 756 RDT_FLAG_L2_CDP, 757 RDT_FLAG_MBA, 758 }; 759 760 #define RDT_OPT(idx, n, f) \ 761 [idx] = { \ 762 .name = n, \ 763 .flag = f \ 764 } 765 766 struct rdt_options { 767 char *name; 768 int flag; 769 bool force_off, force_on; 770 }; 771 772 static struct rdt_options rdt_options[] __initdata = { 773 RDT_OPT(RDT_FLAG_CMT, "cmt", X86_FEATURE_CQM_OCCUP_LLC), 774 RDT_OPT(RDT_FLAG_MBM_TOTAL, "mbmtotal", X86_FEATURE_CQM_MBM_TOTAL), 775 RDT_OPT(RDT_FLAG_MBM_LOCAL, "mbmlocal", X86_FEATURE_CQM_MBM_LOCAL), 776 RDT_OPT(RDT_FLAG_L3_CAT, "l3cat", X86_FEATURE_CAT_L3), 777 RDT_OPT(RDT_FLAG_L3_CDP, "l3cdp", X86_FEATURE_CDP_L3), 778 RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2), 779 RDT_OPT(RDT_FLAG_L2_CDP, "l2cdp", X86_FEATURE_CDP_L2), 780 RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA), 781 }; 782 #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options) 783 784 static int __init set_rdt_options(char *str) 785 { 786 struct rdt_options *o; 787 bool force_off; 788 char *tok; 789 790 if (*str == '=') 791 str++; 792 while ((tok = strsep(&str, ",")) != NULL) { 793 force_off = *tok == '!'; 794 if (force_off) 795 tok++; 796 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) { 797 if (strcmp(tok, o->name) == 0) { 798 if (force_off) 799 o->force_off = true; 800 else 801 o->force_on = true; 802 break; 803 } 804 } 805 } 806 return 1; 807 } 808 __setup("rdt", set_rdt_options); 809 810 static bool __init rdt_cpu_has(int flag) 811 { 812 bool ret = boot_cpu_has(flag); 813 struct rdt_options *o; 814 815 if (!ret) 816 return ret; 817 818 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) { 819 if (flag == o->flag) { 820 if (o->force_off) 821 ret = false; 822 if (o->force_on) 823 ret = true; 824 break; 825 } 826 } 827 return ret; 828 } 829 830 static __init bool get_mem_config(void) 831 { 832 if (!rdt_cpu_has(X86_FEATURE_MBA)) 833 return false; 834 835 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 836 return __get_mem_config_intel(&rdt_resources_all[RDT_RESOURCE_MBA]); 837 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 838 return __rdt_get_mem_config_amd(&rdt_resources_all[RDT_RESOURCE_MBA]); 839 840 return false; 841 } 842 843 static __init bool get_rdt_alloc_resources(void) 844 { 845 bool ret = false; 846 847 if (rdt_alloc_capable) 848 return true; 849 850 if (!boot_cpu_has(X86_FEATURE_RDT_A)) 851 return false; 852 853 if (rdt_cpu_has(X86_FEATURE_CAT_L3)) { 854 rdt_get_cache_alloc_cfg(1, &rdt_resources_all[RDT_RESOURCE_L3]); 855 if (rdt_cpu_has(X86_FEATURE_CDP_L3)) 856 rdt_get_cdp_l3_config(); 857 ret = true; 858 } 859 if (rdt_cpu_has(X86_FEATURE_CAT_L2)) { 860 /* CPUID 0x10.2 fields are same format at 0x10.1 */ 861 rdt_get_cache_alloc_cfg(2, &rdt_resources_all[RDT_RESOURCE_L2]); 862 if (rdt_cpu_has(X86_FEATURE_CDP_L2)) 863 rdt_get_cdp_l2_config(); 864 ret = true; 865 } 866 867 if (get_mem_config()) 868 ret = true; 869 870 return ret; 871 } 872 873 static __init bool get_rdt_mon_resources(void) 874 { 875 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) 876 rdt_mon_features |= (1 << QOS_L3_OCCUP_EVENT_ID); 877 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) 878 rdt_mon_features |= (1 << QOS_L3_MBM_TOTAL_EVENT_ID); 879 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL)) 880 rdt_mon_features |= (1 << QOS_L3_MBM_LOCAL_EVENT_ID); 881 882 if (!rdt_mon_features) 883 return false; 884 885 return !rdt_get_mon_l3_config(&rdt_resources_all[RDT_RESOURCE_L3]); 886 } 887 888 static __init void __check_quirks_intel(void) 889 { 890 switch (boot_cpu_data.x86_model) { 891 case INTEL_FAM6_HASWELL_X: 892 if (!rdt_options[RDT_FLAG_L3_CAT].force_off) 893 cache_alloc_hsw_probe(); 894 break; 895 case INTEL_FAM6_SKYLAKE_X: 896 if (boot_cpu_data.x86_stepping <= 4) 897 set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat"); 898 else 899 set_rdt_options("!l3cat"); 900 } 901 } 902 903 static __init void check_quirks(void) 904 { 905 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 906 __check_quirks_intel(); 907 } 908 909 static __init bool get_rdt_resources(void) 910 { 911 rdt_alloc_capable = get_rdt_alloc_resources(); 912 rdt_mon_capable = get_rdt_mon_resources(); 913 914 return (rdt_mon_capable || rdt_alloc_capable); 915 } 916 917 static __init void rdt_init_res_defs_intel(void) 918 { 919 struct rdt_resource *r; 920 921 for_each_rdt_resource(r) { 922 if (r->rid == RDT_RESOURCE_L3 || 923 r->rid == RDT_RESOURCE_L3DATA || 924 r->rid == RDT_RESOURCE_L3CODE || 925 r->rid == RDT_RESOURCE_L2 || 926 r->rid == RDT_RESOURCE_L2DATA || 927 r->rid == RDT_RESOURCE_L2CODE) 928 r->cbm_validate = cbm_validate_intel; 929 else if (r->rid == RDT_RESOURCE_MBA) { 930 r->msr_base = MSR_IA32_MBA_THRTL_BASE; 931 r->msr_update = mba_wrmsr_intel; 932 r->parse_ctrlval = parse_bw_intel; 933 } 934 } 935 } 936 937 static __init void rdt_init_res_defs_amd(void) 938 { 939 struct rdt_resource *r; 940 941 for_each_rdt_resource(r) { 942 if (r->rid == RDT_RESOURCE_L3 || 943 r->rid == RDT_RESOURCE_L3DATA || 944 r->rid == RDT_RESOURCE_L3CODE || 945 r->rid == RDT_RESOURCE_L2 || 946 r->rid == RDT_RESOURCE_L2DATA || 947 r->rid == RDT_RESOURCE_L2CODE) 948 r->cbm_validate = cbm_validate_amd; 949 else if (r->rid == RDT_RESOURCE_MBA) { 950 r->msr_base = MSR_IA32_MBA_BW_BASE; 951 r->msr_update = mba_wrmsr_amd; 952 r->parse_ctrlval = parse_bw_amd; 953 } 954 } 955 } 956 957 static __init void rdt_init_res_defs(void) 958 { 959 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 960 rdt_init_res_defs_intel(); 961 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 962 rdt_init_res_defs_amd(); 963 } 964 965 static enum cpuhp_state rdt_online; 966 967 static int __init resctrl_late_init(void) 968 { 969 struct rdt_resource *r; 970 int state, ret; 971 972 /* 973 * Initialize functions(or definitions) that are different 974 * between vendors here. 975 */ 976 rdt_init_res_defs(); 977 978 check_quirks(); 979 980 if (!get_rdt_resources()) 981 return -ENODEV; 982 983 rdt_init_padding(); 984 985 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 986 "x86/resctrl/cat:online:", 987 resctrl_online_cpu, resctrl_offline_cpu); 988 if (state < 0) 989 return state; 990 991 ret = rdtgroup_init(); 992 if (ret) { 993 cpuhp_remove_state(state); 994 return ret; 995 } 996 rdt_online = state; 997 998 for_each_alloc_capable_rdt_resource(r) 999 pr_info("%s allocation detected\n", r->name); 1000 1001 for_each_mon_capable_rdt_resource(r) 1002 pr_info("%s monitoring detected\n", r->name); 1003 1004 return 0; 1005 } 1006 1007 late_initcall(resctrl_late_init); 1008 1009 static void __exit resctrl_exit(void) 1010 { 1011 cpuhp_remove_state(rdt_online); 1012 rdtgroup_exit(); 1013 } 1014 1015 __exitcall(resctrl_exit); 1016