1 /* 2 * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong 3 * because MTRRs can span up to 40 bits (36bits on most modern x86) 4 */ 5 #define DEBUG 6 7 #include <linux/module.h> 8 #include <linux/init.h> 9 #include <linux/io.h> 10 #include <linux/mm.h> 11 12 #include <asm/processor-flags.h> 13 #include <asm/cpufeature.h> 14 #include <asm/tlbflush.h> 15 #include <asm/mtrr.h> 16 #include <asm/msr.h> 17 #include <asm/pat.h> 18 19 #include "mtrr.h" 20 21 struct fixed_range_block { 22 int base_msr; /* start address of an MTRR block */ 23 int ranges; /* number of MTRRs in this block */ 24 }; 25 26 static struct fixed_range_block fixed_range_blocks[] = { 27 { MSR_MTRRfix64K_00000, 1 }, /* one 64k MTRR */ 28 { MSR_MTRRfix16K_80000, 2 }, /* two 16k MTRRs */ 29 { MSR_MTRRfix4K_C0000, 8 }, /* eight 4k MTRRs */ 30 {} 31 }; 32 33 static unsigned long smp_changes_mask; 34 static int mtrr_state_set; 35 u64 mtrr_tom2; 36 37 struct mtrr_state_type mtrr_state; 38 EXPORT_SYMBOL_GPL(mtrr_state); 39 40 /* 41 * BIOS is expected to clear MtrrFixDramModEn bit, see for example 42 * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD 43 * Opteron Processors" (26094 Rev. 3.30 February 2006), section 44 * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set 45 * to 1 during BIOS initalization of the fixed MTRRs, then cleared to 46 * 0 for operation." 47 */ 48 static inline void k8_check_syscfg_dram_mod_en(void) 49 { 50 u32 lo, hi; 51 52 if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && 53 (boot_cpu_data.x86 >= 0x0f))) 54 return; 55 56 rdmsr(MSR_K8_SYSCFG, lo, hi); 57 if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) { 58 printk(KERN_ERR FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]" 59 " not cleared by BIOS, clearing this bit\n", 60 smp_processor_id()); 61 lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY; 62 mtrr_wrmsr(MSR_K8_SYSCFG, lo, hi); 63 } 64 } 65 66 /* Get the size of contiguous MTRR range */ 67 static u64 get_mtrr_size(u64 mask) 68 { 69 u64 size; 70 71 mask >>= PAGE_SHIFT; 72 mask |= size_or_mask; 73 size = -mask; 74 size <<= PAGE_SHIFT; 75 return size; 76 } 77 78 /* 79 * Check and return the effective type for MTRR-MTRR type overlap. 80 * Returns 1 if the effective type is UNCACHEABLE, else returns 0 81 */ 82 static int check_type_overlap(u8 *prev, u8 *curr) 83 { 84 if (*prev == MTRR_TYPE_UNCACHABLE || *curr == MTRR_TYPE_UNCACHABLE) { 85 *prev = MTRR_TYPE_UNCACHABLE; 86 *curr = MTRR_TYPE_UNCACHABLE; 87 return 1; 88 } 89 90 if ((*prev == MTRR_TYPE_WRBACK && *curr == MTRR_TYPE_WRTHROUGH) || 91 (*prev == MTRR_TYPE_WRTHROUGH && *curr == MTRR_TYPE_WRBACK)) { 92 *prev = MTRR_TYPE_WRTHROUGH; 93 *curr = MTRR_TYPE_WRTHROUGH; 94 } 95 96 if (*prev != *curr) { 97 *prev = MTRR_TYPE_UNCACHABLE; 98 *curr = MTRR_TYPE_UNCACHABLE; 99 return 1; 100 } 101 102 return 0; 103 } 104 105 /** 106 * mtrr_type_lookup_fixed - look up memory type in MTRR fixed entries 107 * 108 * Return the MTRR fixed memory type of 'start'. 109 * 110 * MTRR fixed entries are divided into the following ways: 111 * 0x00000 - 0x7FFFF : This range is divided into eight 64KB sub-ranges 112 * 0x80000 - 0xBFFFF : This range is divided into sixteen 16KB sub-ranges 113 * 0xC0000 - 0xFFFFF : This range is divided into sixty-four 4KB sub-ranges 114 * 115 * Return Values: 116 * MTRR_TYPE_(type) - Matched memory type 117 * MTRR_TYPE_INVALID - Unmatched 118 */ 119 static u8 mtrr_type_lookup_fixed(u64 start, u64 end) 120 { 121 int idx; 122 123 if (start >= 0x100000) 124 return MTRR_TYPE_INVALID; 125 126 /* 0x0 - 0x7FFFF */ 127 if (start < 0x80000) { 128 idx = 0; 129 idx += (start >> 16); 130 return mtrr_state.fixed_ranges[idx]; 131 /* 0x80000 - 0xBFFFF */ 132 } else if (start < 0xC0000) { 133 idx = 1 * 8; 134 idx += ((start - 0x80000) >> 14); 135 return mtrr_state.fixed_ranges[idx]; 136 } 137 138 /* 0xC0000 - 0xFFFFF */ 139 idx = 3 * 8; 140 idx += ((start - 0xC0000) >> 12); 141 return mtrr_state.fixed_ranges[idx]; 142 } 143 144 /** 145 * mtrr_type_lookup_variable - look up memory type in MTRR variable entries 146 * 147 * Return Value: 148 * MTRR_TYPE_(type) - Matched memory type or default memory type (unmatched) 149 * 150 * Output Arguments: 151 * repeat - Set to 1 when [start:end] spanned across MTRR range and type 152 * returned corresponds only to [start:*partial_end]. Caller has 153 * to lookup again for [*partial_end:end]. 154 * 155 * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the 156 * region is fully covered by a single MTRR entry or the default 157 * type. 158 */ 159 static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, 160 int *repeat, u8 *uniform) 161 { 162 int i; 163 u64 base, mask; 164 u8 prev_match, curr_match; 165 166 *repeat = 0; 167 *uniform = 1; 168 169 /* Make end inclusive instead of exclusive */ 170 end--; 171 172 prev_match = MTRR_TYPE_INVALID; 173 for (i = 0; i < num_var_ranges; ++i) { 174 unsigned short start_state, end_state, inclusive; 175 176 if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11))) 177 continue; 178 179 base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + 180 (mtrr_state.var_ranges[i].base_lo & PAGE_MASK); 181 mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) + 182 (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK); 183 184 start_state = ((start & mask) == (base & mask)); 185 end_state = ((end & mask) == (base & mask)); 186 inclusive = ((start < base) && (end > base)); 187 188 if ((start_state != end_state) || inclusive) { 189 /* 190 * We have start:end spanning across an MTRR. 191 * We split the region into either 192 * 193 * - start_state:1 194 * (start:mtrr_end)(mtrr_end:end) 195 * - end_state:1 196 * (start:mtrr_start)(mtrr_start:end) 197 * - inclusive:1 198 * (start:mtrr_start)(mtrr_start:mtrr_end)(mtrr_end:end) 199 * 200 * depending on kind of overlap. 201 * 202 * Return the type of the first region and a pointer 203 * to the start of next region so that caller will be 204 * advised to lookup again after having adjusted start 205 * and end. 206 * 207 * Note: This way we handle overlaps with multiple 208 * entries and the default type properly. 209 */ 210 if (start_state) 211 *partial_end = base + get_mtrr_size(mask); 212 else 213 *partial_end = base; 214 215 if (unlikely(*partial_end <= start)) { 216 WARN_ON(1); 217 *partial_end = start + PAGE_SIZE; 218 } 219 220 end = *partial_end - 1; /* end is inclusive */ 221 *repeat = 1; 222 *uniform = 0; 223 } 224 225 if ((start & mask) != (base & mask)) 226 continue; 227 228 curr_match = mtrr_state.var_ranges[i].base_lo & 0xff; 229 if (prev_match == MTRR_TYPE_INVALID) { 230 prev_match = curr_match; 231 continue; 232 } 233 234 *uniform = 0; 235 if (check_type_overlap(&prev_match, &curr_match)) 236 return curr_match; 237 } 238 239 if (prev_match != MTRR_TYPE_INVALID) 240 return prev_match; 241 242 return mtrr_state.def_type; 243 } 244 245 /** 246 * mtrr_type_lookup - look up memory type in MTRR 247 * 248 * Return Values: 249 * MTRR_TYPE_(type) - The effective MTRR type for the region 250 * MTRR_TYPE_INVALID - MTRR is disabled 251 * 252 * Output Argument: 253 * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the 254 * region is fully covered by a single MTRR entry or the default 255 * type. 256 */ 257 u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) 258 { 259 u8 type, prev_type, is_uniform = 1, dummy; 260 int repeat; 261 u64 partial_end; 262 263 if (!mtrr_state_set) 264 return MTRR_TYPE_INVALID; 265 266 if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)) 267 return MTRR_TYPE_INVALID; 268 269 /* 270 * Look up the fixed ranges first, which take priority over 271 * the variable ranges. 272 */ 273 if ((start < 0x100000) && 274 (mtrr_state.have_fixed) && 275 (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) { 276 is_uniform = 0; 277 type = mtrr_type_lookup_fixed(start, end); 278 goto out; 279 } 280 281 /* 282 * Look up the variable ranges. Look of multiple ranges matching 283 * this address and pick type as per MTRR precedence. 284 */ 285 type = mtrr_type_lookup_variable(start, end, &partial_end, 286 &repeat, &is_uniform); 287 288 /* 289 * Common path is with repeat = 0. 290 * However, we can have cases where [start:end] spans across some 291 * MTRR ranges and/or the default type. Do repeated lookups for 292 * that case here. 293 */ 294 while (repeat) { 295 prev_type = type; 296 start = partial_end; 297 is_uniform = 0; 298 type = mtrr_type_lookup_variable(start, end, &partial_end, 299 &repeat, &dummy); 300 301 if (check_type_overlap(&prev_type, &type)) 302 goto out; 303 } 304 305 if (mtrr_tom2 && (start >= (1ULL<<32)) && (end < mtrr_tom2)) 306 type = MTRR_TYPE_WRBACK; 307 308 out: 309 *uniform = is_uniform; 310 return type; 311 } 312 313 /* Get the MSR pair relating to a var range */ 314 static void 315 get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr) 316 { 317 rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); 318 rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); 319 } 320 321 /* Fill the MSR pair relating to a var range */ 322 void fill_mtrr_var_range(unsigned int index, 323 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi) 324 { 325 struct mtrr_var_range *vr; 326 327 vr = mtrr_state.var_ranges; 328 329 vr[index].base_lo = base_lo; 330 vr[index].base_hi = base_hi; 331 vr[index].mask_lo = mask_lo; 332 vr[index].mask_hi = mask_hi; 333 } 334 335 static void get_fixed_ranges(mtrr_type *frs) 336 { 337 unsigned int *p = (unsigned int *)frs; 338 int i; 339 340 k8_check_syscfg_dram_mod_en(); 341 342 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]); 343 344 for (i = 0; i < 2; i++) 345 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]); 346 for (i = 0; i < 8; i++) 347 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]); 348 } 349 350 void mtrr_save_fixed_ranges(void *info) 351 { 352 if (cpu_has_mtrr) 353 get_fixed_ranges(mtrr_state.fixed_ranges); 354 } 355 356 static unsigned __initdata last_fixed_start; 357 static unsigned __initdata last_fixed_end; 358 static mtrr_type __initdata last_fixed_type; 359 360 static void __init print_fixed_last(void) 361 { 362 if (!last_fixed_end) 363 return; 364 365 pr_debug(" %05X-%05X %s\n", last_fixed_start, 366 last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type)); 367 368 last_fixed_end = 0; 369 } 370 371 static void __init update_fixed_last(unsigned base, unsigned end, 372 mtrr_type type) 373 { 374 last_fixed_start = base; 375 last_fixed_end = end; 376 last_fixed_type = type; 377 } 378 379 static void __init 380 print_fixed(unsigned base, unsigned step, const mtrr_type *types) 381 { 382 unsigned i; 383 384 for (i = 0; i < 8; ++i, ++types, base += step) { 385 if (last_fixed_end == 0) { 386 update_fixed_last(base, base + step, *types); 387 continue; 388 } 389 if (last_fixed_end == base && last_fixed_type == *types) { 390 last_fixed_end = base + step; 391 continue; 392 } 393 /* new segments: gap or different type */ 394 print_fixed_last(); 395 update_fixed_last(base, base + step, *types); 396 } 397 } 398 399 static void prepare_set(void); 400 static void post_set(void); 401 402 static void __init print_mtrr_state(void) 403 { 404 unsigned int i; 405 int high_width; 406 407 pr_debug("MTRR default type: %s\n", 408 mtrr_attrib_to_str(mtrr_state.def_type)); 409 if (mtrr_state.have_fixed) { 410 pr_debug("MTRR fixed ranges %sabled:\n", 411 ((mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED) && 412 (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) ? 413 "en" : "dis"); 414 print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0); 415 for (i = 0; i < 2; ++i) 416 print_fixed(0x80000 + i * 0x20000, 0x04000, 417 mtrr_state.fixed_ranges + (i + 1) * 8); 418 for (i = 0; i < 8; ++i) 419 print_fixed(0xC0000 + i * 0x08000, 0x01000, 420 mtrr_state.fixed_ranges + (i + 3) * 8); 421 422 /* tail */ 423 print_fixed_last(); 424 } 425 pr_debug("MTRR variable ranges %sabled:\n", 426 mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis"); 427 high_width = (__ffs64(size_or_mask) - (32 - PAGE_SHIFT) + 3) / 4; 428 429 for (i = 0; i < num_var_ranges; ++i) { 430 if (mtrr_state.var_ranges[i].mask_lo & (1 << 11)) 431 pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", 432 i, 433 high_width, 434 mtrr_state.var_ranges[i].base_hi, 435 mtrr_state.var_ranges[i].base_lo >> 12, 436 high_width, 437 mtrr_state.var_ranges[i].mask_hi, 438 mtrr_state.var_ranges[i].mask_lo >> 12, 439 mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff)); 440 else 441 pr_debug(" %u disabled\n", i); 442 } 443 if (mtrr_tom2) 444 pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20); 445 } 446 447 /* Grab all of the MTRR state for this CPU into *state */ 448 bool __init get_mtrr_state(void) 449 { 450 struct mtrr_var_range *vrs; 451 unsigned long flags; 452 unsigned lo, dummy; 453 unsigned int i; 454 455 vrs = mtrr_state.var_ranges; 456 457 rdmsr(MSR_MTRRcap, lo, dummy); 458 mtrr_state.have_fixed = (lo >> 8) & 1; 459 460 for (i = 0; i < num_var_ranges; i++) 461 get_mtrr_var_range(i, &vrs[i]); 462 if (mtrr_state.have_fixed) 463 get_fixed_ranges(mtrr_state.fixed_ranges); 464 465 rdmsr(MSR_MTRRdefType, lo, dummy); 466 mtrr_state.def_type = (lo & 0xff); 467 mtrr_state.enabled = (lo & 0xc00) >> 10; 468 469 if (amd_special_default_mtrr()) { 470 unsigned low, high; 471 472 /* TOP_MEM2 */ 473 rdmsr(MSR_K8_TOP_MEM2, low, high); 474 mtrr_tom2 = high; 475 mtrr_tom2 <<= 32; 476 mtrr_tom2 |= low; 477 mtrr_tom2 &= 0xffffff800000ULL; 478 } 479 480 print_mtrr_state(); 481 482 mtrr_state_set = 1; 483 484 /* PAT setup for BP. We need to go through sync steps here */ 485 local_irq_save(flags); 486 prepare_set(); 487 488 pat_init(); 489 490 post_set(); 491 local_irq_restore(flags); 492 493 return !!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED); 494 } 495 496 /* Some BIOS's are messed up and don't set all MTRRs the same! */ 497 void __init mtrr_state_warn(void) 498 { 499 unsigned long mask = smp_changes_mask; 500 501 if (!mask) 502 return; 503 if (mask & MTRR_CHANGE_MASK_FIXED) 504 pr_warning("mtrr: your CPUs had inconsistent fixed MTRR settings\n"); 505 if (mask & MTRR_CHANGE_MASK_VARIABLE) 506 pr_warning("mtrr: your CPUs had inconsistent variable MTRR settings\n"); 507 if (mask & MTRR_CHANGE_MASK_DEFTYPE) 508 pr_warning("mtrr: your CPUs had inconsistent MTRRdefType settings\n"); 509 510 printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n"); 511 printk(KERN_INFO "mtrr: corrected configuration.\n"); 512 } 513 514 /* 515 * Doesn't attempt to pass an error out to MTRR users 516 * because it's quite complicated in some cases and probably not 517 * worth it because the best error handling is to ignore it. 518 */ 519 void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b) 520 { 521 if (wrmsr_safe(msr, a, b) < 0) { 522 printk(KERN_ERR 523 "MTRR: CPU %u: Writing MSR %x to %x:%x failed\n", 524 smp_processor_id(), msr, a, b); 525 } 526 } 527 528 /** 529 * set_fixed_range - checks & updates a fixed-range MTRR if it 530 * differs from the value it should have 531 * @msr: MSR address of the MTTR which should be checked and updated 532 * @changed: pointer which indicates whether the MTRR needed to be changed 533 * @msrwords: pointer to the MSR values which the MSR should have 534 */ 535 static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords) 536 { 537 unsigned lo, hi; 538 539 rdmsr(msr, lo, hi); 540 541 if (lo != msrwords[0] || hi != msrwords[1]) { 542 mtrr_wrmsr(msr, msrwords[0], msrwords[1]); 543 *changed = true; 544 } 545 } 546 547 /** 548 * generic_get_free_region - Get a free MTRR. 549 * @base: The starting (base) address of the region. 550 * @size: The size (in bytes) of the region. 551 * @replace_reg: mtrr index to be replaced; set to invalid value if none. 552 * 553 * Returns: The index of the region on success, else negative on error. 554 */ 555 int 556 generic_get_free_region(unsigned long base, unsigned long size, int replace_reg) 557 { 558 unsigned long lbase, lsize; 559 mtrr_type ltype; 560 int i, max; 561 562 max = num_var_ranges; 563 if (replace_reg >= 0 && replace_reg < max) 564 return replace_reg; 565 566 for (i = 0; i < max; ++i) { 567 mtrr_if->get(i, &lbase, &lsize, <ype); 568 if (lsize == 0) 569 return i; 570 } 571 572 return -ENOSPC; 573 } 574 575 static void generic_get_mtrr(unsigned int reg, unsigned long *base, 576 unsigned long *size, mtrr_type *type) 577 { 578 u32 mask_lo, mask_hi, base_lo, base_hi; 579 unsigned int hi; 580 u64 tmp, mask; 581 582 /* 583 * get_mtrr doesn't need to update mtrr_state, also it could be called 584 * from any cpu, so try to print it out directly. 585 */ 586 get_cpu(); 587 588 rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); 589 590 if ((mask_lo & 0x800) == 0) { 591 /* Invalid (i.e. free) range */ 592 *base = 0; 593 *size = 0; 594 *type = 0; 595 goto out_put_cpu; 596 } 597 598 rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi); 599 600 /* Work out the shifted address mask: */ 601 tmp = (u64)mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT; 602 mask = size_or_mask | tmp; 603 604 /* Expand tmp with high bits to all 1s: */ 605 hi = fls64(tmp); 606 if (hi > 0) { 607 tmp |= ~((1ULL<<(hi - 1)) - 1); 608 609 if (tmp != mask) { 610 printk(KERN_WARNING "mtrr: your BIOS has configured an incorrect mask, fixing it.\n"); 611 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); 612 mask = tmp; 613 } 614 } 615 616 /* 617 * This works correctly if size is a power of two, i.e. a 618 * contiguous range: 619 */ 620 *size = -mask; 621 *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT; 622 *type = base_lo & 0xff; 623 624 out_put_cpu: 625 put_cpu(); 626 } 627 628 /** 629 * set_fixed_ranges - checks & updates the fixed-range MTRRs if they 630 * differ from the saved set 631 * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges() 632 */ 633 static int set_fixed_ranges(mtrr_type *frs) 634 { 635 unsigned long long *saved = (unsigned long long *)frs; 636 bool changed = false; 637 int block = -1, range; 638 639 k8_check_syscfg_dram_mod_en(); 640 641 while (fixed_range_blocks[++block].ranges) { 642 for (range = 0; range < fixed_range_blocks[block].ranges; range++) 643 set_fixed_range(fixed_range_blocks[block].base_msr + range, 644 &changed, (unsigned int *)saved++); 645 } 646 647 return changed; 648 } 649 650 /* 651 * Set the MSR pair relating to a var range. 652 * Returns true if changes are made. 653 */ 654 static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr) 655 { 656 unsigned int lo, hi; 657 bool changed = false; 658 659 rdmsr(MTRRphysBase_MSR(index), lo, hi); 660 if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL) 661 || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) != 662 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { 663 664 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); 665 changed = true; 666 } 667 668 rdmsr(MTRRphysMask_MSR(index), lo, hi); 669 670 if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL) 671 || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) != 672 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { 673 mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); 674 changed = true; 675 } 676 return changed; 677 } 678 679 static u32 deftype_lo, deftype_hi; 680 681 /** 682 * set_mtrr_state - Set the MTRR state for this CPU. 683 * 684 * NOTE: The CPU must already be in a safe state for MTRR changes. 685 * RETURNS: 0 if no changes made, else a mask indicating what was changed. 686 */ 687 static unsigned long set_mtrr_state(void) 688 { 689 unsigned long change_mask = 0; 690 unsigned int i; 691 692 for (i = 0; i < num_var_ranges; i++) { 693 if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i])) 694 change_mask |= MTRR_CHANGE_MASK_VARIABLE; 695 } 696 697 if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges)) 698 change_mask |= MTRR_CHANGE_MASK_FIXED; 699 700 /* 701 * Set_mtrr_restore restores the old value of MTRRdefType, 702 * so to set it we fiddle with the saved value: 703 */ 704 if ((deftype_lo & 0xff) != mtrr_state.def_type 705 || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) { 706 707 deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type | 708 (mtrr_state.enabled << 10); 709 change_mask |= MTRR_CHANGE_MASK_DEFTYPE; 710 } 711 712 return change_mask; 713 } 714 715 716 static unsigned long cr4; 717 static DEFINE_RAW_SPINLOCK(set_atomicity_lock); 718 719 /* 720 * Since we are disabling the cache don't allow any interrupts, 721 * they would run extremely slow and would only increase the pain. 722 * 723 * The caller must ensure that local interrupts are disabled and 724 * are reenabled after post_set() has been called. 725 */ 726 static void prepare_set(void) __acquires(set_atomicity_lock) 727 { 728 unsigned long cr0; 729 730 /* 731 * Note that this is not ideal 732 * since the cache is only flushed/disabled for this CPU while the 733 * MTRRs are changed, but changing this requires more invasive 734 * changes to the way the kernel boots 735 */ 736 737 raw_spin_lock(&set_atomicity_lock); 738 739 /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */ 740 cr0 = read_cr0() | X86_CR0_CD; 741 write_cr0(cr0); 742 wbinvd(); 743 744 /* Save value of CR4 and clear Page Global Enable (bit 7) */ 745 if (cpu_has_pge) { 746 cr4 = __read_cr4(); 747 __write_cr4(cr4 & ~X86_CR4_PGE); 748 } 749 750 /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */ 751 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); 752 __flush_tlb(); 753 754 /* Save MTRR state */ 755 rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); 756 757 /* Disable MTRRs, and set the default type to uncached */ 758 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi); 759 wbinvd(); 760 } 761 762 static void post_set(void) __releases(set_atomicity_lock) 763 { 764 /* Flush TLBs (no need to flush caches - they are disabled) */ 765 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); 766 __flush_tlb(); 767 768 /* Intel (P6) standard MTRRs */ 769 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); 770 771 /* Enable caches */ 772 write_cr0(read_cr0() & ~X86_CR0_CD); 773 774 /* Restore value of CR4 */ 775 if (cpu_has_pge) 776 __write_cr4(cr4); 777 raw_spin_unlock(&set_atomicity_lock); 778 } 779 780 static void generic_set_all(void) 781 { 782 unsigned long mask, count; 783 unsigned long flags; 784 785 local_irq_save(flags); 786 prepare_set(); 787 788 /* Actually set the state */ 789 mask = set_mtrr_state(); 790 791 /* also set PAT */ 792 pat_init(); 793 794 post_set(); 795 local_irq_restore(flags); 796 797 /* Use the atomic bitops to update the global mask */ 798 for (count = 0; count < sizeof mask * 8; ++count) { 799 if (mask & 0x01) 800 set_bit(count, &smp_changes_mask); 801 mask >>= 1; 802 } 803 804 } 805 806 /** 807 * generic_set_mtrr - set variable MTRR register on the local CPU. 808 * 809 * @reg: The register to set. 810 * @base: The base address of the region. 811 * @size: The size of the region. If this is 0 the region is disabled. 812 * @type: The type of the region. 813 * 814 * Returns nothing. 815 */ 816 static void generic_set_mtrr(unsigned int reg, unsigned long base, 817 unsigned long size, mtrr_type type) 818 { 819 unsigned long flags; 820 struct mtrr_var_range *vr; 821 822 vr = &mtrr_state.var_ranges[reg]; 823 824 local_irq_save(flags); 825 prepare_set(); 826 827 if (size == 0) { 828 /* 829 * The invalid bit is kept in the mask, so we simply 830 * clear the relevant mask register to disable a range. 831 */ 832 mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0); 833 memset(vr, 0, sizeof(struct mtrr_var_range)); 834 } else { 835 vr->base_lo = base << PAGE_SHIFT | type; 836 vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT); 837 vr->mask_lo = -size << PAGE_SHIFT | 0x800; 838 vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT); 839 840 mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); 841 mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi); 842 } 843 844 post_set(); 845 local_irq_restore(flags); 846 } 847 848 int generic_validate_add_page(unsigned long base, unsigned long size, 849 unsigned int type) 850 { 851 unsigned long lbase, last; 852 853 /* 854 * For Intel PPro stepping <= 7 855 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF 856 */ 857 if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 && 858 boot_cpu_data.x86_model == 1 && 859 boot_cpu_data.x86_mask <= 7) { 860 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) { 861 pr_warning("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base); 862 return -EINVAL; 863 } 864 if (!(base + size < 0x70000 || base > 0x7003F) && 865 (type == MTRR_TYPE_WRCOMB 866 || type == MTRR_TYPE_WRBACK)) { 867 pr_warning("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n"); 868 return -EINVAL; 869 } 870 } 871 872 /* 873 * Check upper bits of base and last are equal and lower bits are 0 874 * for base and 1 for last 875 */ 876 last = base + size - 1; 877 for (lbase = base; !(lbase & 1) && (last & 1); 878 lbase = lbase >> 1, last = last >> 1) 879 ; 880 if (lbase != last) { 881 pr_warning("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size); 882 return -EINVAL; 883 } 884 return 0; 885 } 886 887 static int generic_have_wrcomb(void) 888 { 889 unsigned long config, dummy; 890 rdmsr(MSR_MTRRcap, config, dummy); 891 return config & (1 << 10); 892 } 893 894 int positive_have_wrcomb(void) 895 { 896 return 1; 897 } 898 899 /* 900 * Generic structure... 901 */ 902 const struct mtrr_ops generic_mtrr_ops = { 903 .use_intel_if = 1, 904 .set_all = generic_set_all, 905 .get = generic_get_mtrr, 906 .get_free_region = generic_get_free_region, 907 .set = generic_set_mtrr, 908 .validate_add_page = generic_validate_add_page, 909 .have_wrcomb = generic_have_wrcomb, 910 }; 911