1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HyperV Detection code. 4 * 5 * Copyright (C) 2010, Novell, Inc. 6 * Author : K. Y. Srinivasan <ksrinivasan@novell.com> 7 */ 8 9 #include <linux/types.h> 10 #include <linux/time.h> 11 #include <linux/clocksource.h> 12 #include <linux/init.h> 13 #include <linux/export.h> 14 #include <linux/hardirq.h> 15 #include <linux/efi.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/kexec.h> 19 #include <linux/i8253.h> 20 #include <linux/random.h> 21 #include <linux/swiotlb.h> 22 #include <asm/processor.h> 23 #include <asm/hypervisor.h> 24 #include <asm/hyperv-tlfs.h> 25 #include <asm/mshyperv.h> 26 #include <asm/desc.h> 27 #include <asm/idtentry.h> 28 #include <asm/irq_regs.h> 29 #include <asm/i8259.h> 30 #include <asm/apic.h> 31 #include <asm/timer.h> 32 #include <asm/reboot.h> 33 #include <asm/nmi.h> 34 #include <clocksource/hyperv_timer.h> 35 #include <asm/numa.h> 36 #include <asm/coco.h> 37 38 /* Is Linux running as the root partition? */ 39 bool hv_root_partition; 40 /* Is Linux running on nested Microsoft Hypervisor */ 41 bool hv_nested; 42 struct ms_hyperv_info ms_hyperv; 43 44 #if IS_ENABLED(CONFIG_HYPERV) 45 static inline unsigned int hv_get_nested_reg(unsigned int reg) 46 { 47 if (hv_is_sint_reg(reg)) 48 return reg - HV_REGISTER_SINT0 + HV_REGISTER_NESTED_SINT0; 49 50 switch (reg) { 51 case HV_REGISTER_SIMP: 52 return HV_REGISTER_NESTED_SIMP; 53 case HV_REGISTER_SIEFP: 54 return HV_REGISTER_NESTED_SIEFP; 55 case HV_REGISTER_SVERSION: 56 return HV_REGISTER_NESTED_SVERSION; 57 case HV_REGISTER_SCONTROL: 58 return HV_REGISTER_NESTED_SCONTROL; 59 case HV_REGISTER_EOM: 60 return HV_REGISTER_NESTED_EOM; 61 default: 62 return reg; 63 } 64 } 65 66 u64 hv_get_non_nested_register(unsigned int reg) 67 { 68 u64 value; 69 70 if (hv_is_synic_reg(reg) && hv_isolation_type_snp()) 71 hv_ghcb_msr_read(reg, &value); 72 else 73 rdmsrl(reg, value); 74 return value; 75 } 76 EXPORT_SYMBOL_GPL(hv_get_non_nested_register); 77 78 void hv_set_non_nested_register(unsigned int reg, u64 value) 79 { 80 if (hv_is_synic_reg(reg) && hv_isolation_type_snp()) { 81 hv_ghcb_msr_write(reg, value); 82 83 /* Write proxy bit via wrmsl instruction */ 84 if (hv_is_sint_reg(reg)) 85 wrmsrl(reg, value | 1 << 20); 86 } else { 87 wrmsrl(reg, value); 88 } 89 } 90 EXPORT_SYMBOL_GPL(hv_set_non_nested_register); 91 92 u64 hv_get_register(unsigned int reg) 93 { 94 if (hv_nested) 95 reg = hv_get_nested_reg(reg); 96 97 return hv_get_non_nested_register(reg); 98 } 99 EXPORT_SYMBOL_GPL(hv_get_register); 100 101 void hv_set_register(unsigned int reg, u64 value) 102 { 103 if (hv_nested) 104 reg = hv_get_nested_reg(reg); 105 106 hv_set_non_nested_register(reg, value); 107 } 108 EXPORT_SYMBOL_GPL(hv_set_register); 109 110 static void (*vmbus_handler)(void); 111 static void (*hv_stimer0_handler)(void); 112 static void (*hv_kexec_handler)(void); 113 static void (*hv_crash_handler)(struct pt_regs *regs); 114 115 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback) 116 { 117 struct pt_regs *old_regs = set_irq_regs(regs); 118 119 inc_irq_stat(irq_hv_callback_count); 120 if (vmbus_handler) 121 vmbus_handler(); 122 123 if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED) 124 ack_APIC_irq(); 125 126 set_irq_regs(old_regs); 127 } 128 129 void hv_setup_vmbus_handler(void (*handler)(void)) 130 { 131 vmbus_handler = handler; 132 } 133 134 void hv_remove_vmbus_handler(void) 135 { 136 /* We have no way to deallocate the interrupt gate */ 137 vmbus_handler = NULL; 138 } 139 140 /* 141 * Routines to do per-architecture handling of stimer0 142 * interrupts when in Direct Mode 143 */ 144 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0) 145 { 146 struct pt_regs *old_regs = set_irq_regs(regs); 147 148 inc_irq_stat(hyperv_stimer0_count); 149 if (hv_stimer0_handler) 150 hv_stimer0_handler(); 151 add_interrupt_randomness(HYPERV_STIMER0_VECTOR); 152 ack_APIC_irq(); 153 154 set_irq_regs(old_regs); 155 } 156 157 /* For x86/x64, override weak placeholders in hyperv_timer.c */ 158 void hv_setup_stimer0_handler(void (*handler)(void)) 159 { 160 hv_stimer0_handler = handler; 161 } 162 163 void hv_remove_stimer0_handler(void) 164 { 165 /* We have no way to deallocate the interrupt gate */ 166 hv_stimer0_handler = NULL; 167 } 168 169 void hv_setup_kexec_handler(void (*handler)(void)) 170 { 171 hv_kexec_handler = handler; 172 } 173 174 void hv_remove_kexec_handler(void) 175 { 176 hv_kexec_handler = NULL; 177 } 178 179 void hv_setup_crash_handler(void (*handler)(struct pt_regs *regs)) 180 { 181 hv_crash_handler = handler; 182 } 183 184 void hv_remove_crash_handler(void) 185 { 186 hv_crash_handler = NULL; 187 } 188 189 #ifdef CONFIG_KEXEC_CORE 190 static void hv_machine_shutdown(void) 191 { 192 if (kexec_in_progress && hv_kexec_handler) 193 hv_kexec_handler(); 194 195 /* 196 * Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor 197 * corrupts the old VP Assist Pages and can crash the kexec kernel. 198 */ 199 if (kexec_in_progress && hyperv_init_cpuhp > 0) 200 cpuhp_remove_state(hyperv_init_cpuhp); 201 202 /* The function calls stop_other_cpus(). */ 203 native_machine_shutdown(); 204 205 /* Disable the hypercall page when there is only 1 active CPU. */ 206 if (kexec_in_progress) 207 hyperv_cleanup(); 208 } 209 210 static void hv_machine_crash_shutdown(struct pt_regs *regs) 211 { 212 if (hv_crash_handler) 213 hv_crash_handler(regs); 214 215 /* The function calls crash_smp_send_stop(). */ 216 native_machine_crash_shutdown(regs); 217 218 /* Disable the hypercall page when there is only 1 active CPU. */ 219 hyperv_cleanup(); 220 } 221 #endif /* CONFIG_KEXEC_CORE */ 222 #endif /* CONFIG_HYPERV */ 223 224 static uint32_t __init ms_hyperv_platform(void) 225 { 226 u32 eax; 227 u32 hyp_signature[3]; 228 229 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 230 return 0; 231 232 cpuid(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS, 233 &eax, &hyp_signature[0], &hyp_signature[1], &hyp_signature[2]); 234 235 if (eax < HYPERV_CPUID_MIN || eax > HYPERV_CPUID_MAX || 236 memcmp("Microsoft Hv", hyp_signature, 12)) 237 return 0; 238 239 /* HYPERCALL and VP_INDEX MSRs are mandatory for all features. */ 240 eax = cpuid_eax(HYPERV_CPUID_FEATURES); 241 if (!(eax & HV_MSR_HYPERCALL_AVAILABLE)) { 242 pr_warn("x86/hyperv: HYPERCALL MSR not available.\n"); 243 return 0; 244 } 245 if (!(eax & HV_MSR_VP_INDEX_AVAILABLE)) { 246 pr_warn("x86/hyperv: VP_INDEX MSR not available.\n"); 247 return 0; 248 } 249 250 return HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS; 251 } 252 253 static unsigned char hv_get_nmi_reason(void) 254 { 255 return 0; 256 } 257 258 #ifdef CONFIG_X86_LOCAL_APIC 259 /* 260 * Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes 261 * it difficult to process CHANNELMSG_UNLOAD in case of crash. Handle 262 * unknown NMI on the first CPU which gets it. 263 */ 264 static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs) 265 { 266 static atomic_t nmi_cpu = ATOMIC_INIT(-1); 267 268 if (!unknown_nmi_panic) 269 return NMI_DONE; 270 271 if (atomic_cmpxchg(&nmi_cpu, -1, raw_smp_processor_id()) != -1) 272 return NMI_HANDLED; 273 274 return NMI_DONE; 275 } 276 #endif 277 278 static unsigned long hv_get_tsc_khz(void) 279 { 280 unsigned long freq; 281 282 rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq); 283 284 return freq / 1000; 285 } 286 287 #if defined(CONFIG_SMP) && IS_ENABLED(CONFIG_HYPERV) 288 static void __init hv_smp_prepare_boot_cpu(void) 289 { 290 native_smp_prepare_boot_cpu(); 291 #if defined(CONFIG_X86_64) && defined(CONFIG_PARAVIRT_SPINLOCKS) 292 hv_init_spinlocks(); 293 #endif 294 } 295 296 static void __init hv_smp_prepare_cpus(unsigned int max_cpus) 297 { 298 #ifdef CONFIG_X86_64 299 int i; 300 int ret; 301 #endif 302 303 native_smp_prepare_cpus(max_cpus); 304 305 #ifdef CONFIG_X86_64 306 for_each_present_cpu(i) { 307 if (i == 0) 308 continue; 309 ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i)); 310 BUG_ON(ret); 311 } 312 313 for_each_present_cpu(i) { 314 if (i == 0) 315 continue; 316 ret = hv_call_create_vp(numa_cpu_node(i), hv_current_partition_id, i, i); 317 BUG_ON(ret); 318 } 319 #endif 320 } 321 #endif 322 323 static void __init ms_hyperv_init_platform(void) 324 { 325 int hv_max_functions_eax; 326 int hv_host_info_eax; 327 int hv_host_info_ebx; 328 int hv_host_info_ecx; 329 int hv_host_info_edx; 330 331 #ifdef CONFIG_PARAVIRT 332 pv_info.name = "Hyper-V"; 333 #endif 334 335 /* 336 * Extract the features and hints 337 */ 338 ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES); 339 ms_hyperv.priv_high = cpuid_ebx(HYPERV_CPUID_FEATURES); 340 ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES); 341 ms_hyperv.hints = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO); 342 343 hv_max_functions_eax = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS); 344 345 pr_info("Hyper-V: privilege flags low 0x%x, high 0x%x, hints 0x%x, misc 0x%x\n", 346 ms_hyperv.features, ms_hyperv.priv_high, ms_hyperv.hints, 347 ms_hyperv.misc_features); 348 349 ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS); 350 ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS); 351 352 pr_debug("Hyper-V: max %u virtual processors, %u logical processors\n", 353 ms_hyperv.max_vp_index, ms_hyperv.max_lp_index); 354 355 /* 356 * Check CPU management privilege. 357 * 358 * To mirror what Windows does we should extract CPU management 359 * features and use the ReservedIdentityBit to detect if Linux is the 360 * root partition. But that requires negotiating CPU management 361 * interface (a process to be finalized). For now, use the privilege 362 * flag as the indicator for running as root. 363 * 364 * Hyper-V should never specify running as root and as a Confidential 365 * VM. But to protect against a compromised/malicious Hyper-V trying 366 * to exploit root behavior to expose Confidential VM memory, ignore 367 * the root partition setting if also a Confidential VM. 368 */ 369 if ((ms_hyperv.priv_high & HV_CPU_MANAGEMENT) && 370 !(ms_hyperv.priv_high & HV_ISOLATION)) { 371 hv_root_partition = true; 372 pr_info("Hyper-V: running as root partition\n"); 373 } 374 375 if (ms_hyperv.hints & HV_X64_HYPERV_NESTED) { 376 hv_nested = true; 377 pr_info("Hyper-V: running on a nested hypervisor\n"); 378 } 379 380 /* 381 * Extract host information. 382 */ 383 if (hv_max_functions_eax >= HYPERV_CPUID_VERSION) { 384 hv_host_info_eax = cpuid_eax(HYPERV_CPUID_VERSION); 385 hv_host_info_ebx = cpuid_ebx(HYPERV_CPUID_VERSION); 386 hv_host_info_ecx = cpuid_ecx(HYPERV_CPUID_VERSION); 387 hv_host_info_edx = cpuid_edx(HYPERV_CPUID_VERSION); 388 389 pr_info("Hyper-V: Host Build %d.%d.%d.%d-%d-%d\n", 390 hv_host_info_ebx >> 16, hv_host_info_ebx & 0xFFFF, 391 hv_host_info_eax, hv_host_info_edx & 0xFFFFFF, 392 hv_host_info_ecx, hv_host_info_edx >> 24); 393 } 394 395 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 396 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 397 x86_platform.calibrate_tsc = hv_get_tsc_khz; 398 x86_platform.calibrate_cpu = hv_get_tsc_khz; 399 } 400 401 if (ms_hyperv.priv_high & HV_ISOLATION) { 402 ms_hyperv.isolation_config_a = cpuid_eax(HYPERV_CPUID_ISOLATION_CONFIG); 403 ms_hyperv.isolation_config_b = cpuid_ebx(HYPERV_CPUID_ISOLATION_CONFIG); 404 ms_hyperv.shared_gpa_boundary = 405 BIT_ULL(ms_hyperv.shared_gpa_boundary_bits); 406 407 pr_info("Hyper-V: Isolation Config: Group A 0x%x, Group B 0x%x\n", 408 ms_hyperv.isolation_config_a, ms_hyperv.isolation_config_b); 409 410 if (hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP) { 411 static_branch_enable(&isolation_type_snp); 412 #ifdef CONFIG_SWIOTLB 413 swiotlb_unencrypted_base = ms_hyperv.shared_gpa_boundary; 414 #endif 415 } 416 /* Isolation VMs are unenlightened SEV-based VMs, thus this check: */ 417 if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) { 418 if (hv_get_isolation_type() != HV_ISOLATION_TYPE_NONE) 419 cc_set_vendor(CC_VENDOR_HYPERV); 420 } 421 } 422 423 if (hv_max_functions_eax >= HYPERV_CPUID_NESTED_FEATURES) { 424 ms_hyperv.nested_features = 425 cpuid_eax(HYPERV_CPUID_NESTED_FEATURES); 426 pr_info("Hyper-V: Nested features: 0x%x\n", 427 ms_hyperv.nested_features); 428 } 429 430 #ifdef CONFIG_X86_LOCAL_APIC 431 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 432 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 433 /* 434 * Get the APIC frequency. 435 */ 436 u64 hv_lapic_frequency; 437 438 rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency); 439 hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ); 440 lapic_timer_period = hv_lapic_frequency; 441 pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n", 442 lapic_timer_period); 443 } 444 445 register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST, 446 "hv_nmi_unknown"); 447 #endif 448 449 #ifdef CONFIG_X86_IO_APIC 450 no_timer_check = 1; 451 #endif 452 453 #if IS_ENABLED(CONFIG_HYPERV) && defined(CONFIG_KEXEC_CORE) 454 machine_ops.shutdown = hv_machine_shutdown; 455 machine_ops.crash_shutdown = hv_machine_crash_shutdown; 456 #endif 457 if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) { 458 /* 459 * Writing to synthetic MSR 0x40000118 updates/changes the 460 * guest visible CPUIDs. Setting bit 0 of this MSR enables 461 * guests to report invariant TSC feature through CPUID 462 * instruction, CPUID 0x800000007/EDX, bit 8. See code in 463 * early_init_intel() where this bit is examined. The 464 * setting of this MSR bit should happen before init_intel() 465 * is called. 466 */ 467 wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC); 468 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); 469 } 470 471 /* 472 * Generation 2 instances don't support reading the NMI status from 473 * 0x61 port. 474 */ 475 if (efi_enabled(EFI_BOOT)) 476 x86_platform.get_nmi_reason = hv_get_nmi_reason; 477 478 /* 479 * Hyper-V VMs have a PIT emulation quirk such that zeroing the 480 * counter register during PIT shutdown restarts the PIT. So it 481 * continues to interrupt @18.2 HZ. Setting i8253_clear_counter 482 * to false tells pit_shutdown() not to zero the counter so that 483 * the PIT really is shutdown. Generation 2 VMs don't have a PIT, 484 * and setting this value has no effect. 485 */ 486 i8253_clear_counter_on_shutdown = false; 487 488 #if IS_ENABLED(CONFIG_HYPERV) 489 /* 490 * Setup the hook to get control post apic initialization. 491 */ 492 x86_platform.apic_post_init = hyperv_init; 493 hyperv_setup_mmu_ops(); 494 /* Setup the IDT for hypervisor callback */ 495 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_hyperv_callback); 496 497 /* Setup the IDT for reenlightenment notifications */ 498 if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) { 499 alloc_intr_gate(HYPERV_REENLIGHTENMENT_VECTOR, 500 asm_sysvec_hyperv_reenlightenment); 501 } 502 503 /* Setup the IDT for stimer0 */ 504 if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) { 505 alloc_intr_gate(HYPERV_STIMER0_VECTOR, 506 asm_sysvec_hyperv_stimer0); 507 } 508 509 # ifdef CONFIG_SMP 510 smp_ops.smp_prepare_boot_cpu = hv_smp_prepare_boot_cpu; 511 if (hv_root_partition) 512 smp_ops.smp_prepare_cpus = hv_smp_prepare_cpus; 513 # endif 514 515 /* 516 * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic, 517 * set x2apic destination mode to physical mode when x2apic is available 518 * and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs 519 * have 8-bit APIC id. 520 */ 521 # ifdef CONFIG_X86_X2APIC 522 if (x2apic_supported()) 523 x2apic_phys = 1; 524 # endif 525 526 /* Register Hyper-V specific clocksource */ 527 hv_init_clocksource(); 528 #endif 529 /* 530 * TSC should be marked as unstable only after Hyper-V 531 * clocksource has been initialized. This ensures that the 532 * stability of the sched_clock is not altered. 533 */ 534 if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT)) 535 mark_tsc_unstable("running on Hyper-V"); 536 537 hardlockup_detector_disable(); 538 } 539 540 static bool __init ms_hyperv_x2apic_available(void) 541 { 542 return x2apic_supported(); 543 } 544 545 /* 546 * If ms_hyperv_msi_ext_dest_id() returns true, hyperv_prepare_irq_remapping() 547 * returns -ENODEV and the Hyper-V IOMMU driver is not used; instead, the 548 * generic support of the 15-bit APIC ID is used: see __irq_msi_compose_msg(). 549 * 550 * Note: for a VM on Hyper-V, the I/O-APIC is the only device which 551 * (logically) generates MSIs directly to the system APIC irq domain. 552 * There is no HPET, and PCI MSI/MSI-X interrupts are remapped by the 553 * pci-hyperv host bridge. 554 * 555 * Note: for a Hyper-V root partition, this will always return false. 556 * The hypervisor doesn't expose these HYPERV_CPUID_VIRT_STACK_* cpuids by 557 * default, they are implemented as intercepts by the Windows Hyper-V stack. 558 * Even a nested root partition (L2 root) will not get them because the 559 * nested (L1) hypervisor filters them out. 560 */ 561 static bool __init ms_hyperv_msi_ext_dest_id(void) 562 { 563 u32 eax; 564 565 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_INTERFACE); 566 if (eax != HYPERV_VS_INTERFACE_EAX_SIGNATURE) 567 return false; 568 569 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_PROPERTIES); 570 return eax & HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE; 571 } 572 573 const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = { 574 .name = "Microsoft Hyper-V", 575 .detect = ms_hyperv_platform, 576 .type = X86_HYPER_MS_HYPERV, 577 .init.x2apic_available = ms_hyperv_x2apic_available, 578 .init.msi_ext_dest_id = ms_hyperv_msi_ext_dest_id, 579 .init.init_platform = ms_hyperv_init_platform, 580 }; 581