1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HyperV Detection code. 4 * 5 * Copyright (C) 2010, Novell, Inc. 6 * Author : K. Y. Srinivasan <ksrinivasan@novell.com> 7 */ 8 9 #include <linux/types.h> 10 #include <linux/time.h> 11 #include <linux/clocksource.h> 12 #include <linux/init.h> 13 #include <linux/export.h> 14 #include <linux/hardirq.h> 15 #include <linux/efi.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/kexec.h> 19 #include <linux/i8253.h> 20 #include <linux/random.h> 21 #include <asm/processor.h> 22 #include <asm/hypervisor.h> 23 #include <asm/hyperv-tlfs.h> 24 #include <asm/mshyperv.h> 25 #include <asm/desc.h> 26 #include <asm/idtentry.h> 27 #include <asm/irq_regs.h> 28 #include <asm/i8259.h> 29 #include <asm/apic.h> 30 #include <asm/timer.h> 31 #include <asm/reboot.h> 32 #include <asm/nmi.h> 33 #include <clocksource/hyperv_timer.h> 34 #include <asm/numa.h> 35 36 /* Is Linux running as the root partition? */ 37 bool hv_root_partition; 38 struct ms_hyperv_info ms_hyperv; 39 40 #if IS_ENABLED(CONFIG_HYPERV) 41 static void (*vmbus_handler)(void); 42 static void (*hv_stimer0_handler)(void); 43 static void (*hv_kexec_handler)(void); 44 static void (*hv_crash_handler)(struct pt_regs *regs); 45 46 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback) 47 { 48 struct pt_regs *old_regs = set_irq_regs(regs); 49 50 inc_irq_stat(irq_hv_callback_count); 51 if (vmbus_handler) 52 vmbus_handler(); 53 54 if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED) 55 ack_APIC_irq(); 56 57 set_irq_regs(old_regs); 58 } 59 60 void hv_setup_vmbus_handler(void (*handler)(void)) 61 { 62 vmbus_handler = handler; 63 } 64 65 void hv_remove_vmbus_handler(void) 66 { 67 /* We have no way to deallocate the interrupt gate */ 68 vmbus_handler = NULL; 69 } 70 71 /* 72 * Routines to do per-architecture handling of stimer0 73 * interrupts when in Direct Mode 74 */ 75 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0) 76 { 77 struct pt_regs *old_regs = set_irq_regs(regs); 78 79 inc_irq_stat(hyperv_stimer0_count); 80 if (hv_stimer0_handler) 81 hv_stimer0_handler(); 82 add_interrupt_randomness(HYPERV_STIMER0_VECTOR, 0); 83 ack_APIC_irq(); 84 85 set_irq_regs(old_regs); 86 } 87 88 /* For x86/x64, override weak placeholders in hyperv_timer.c */ 89 void hv_setup_stimer0_handler(void (*handler)(void)) 90 { 91 hv_stimer0_handler = handler; 92 } 93 94 void hv_remove_stimer0_handler(void) 95 { 96 /* We have no way to deallocate the interrupt gate */ 97 hv_stimer0_handler = NULL; 98 } 99 100 void hv_setup_kexec_handler(void (*handler)(void)) 101 { 102 hv_kexec_handler = handler; 103 } 104 105 void hv_remove_kexec_handler(void) 106 { 107 hv_kexec_handler = NULL; 108 } 109 110 void hv_setup_crash_handler(void (*handler)(struct pt_regs *regs)) 111 { 112 hv_crash_handler = handler; 113 } 114 115 void hv_remove_crash_handler(void) 116 { 117 hv_crash_handler = NULL; 118 } 119 120 #ifdef CONFIG_KEXEC_CORE 121 static void hv_machine_shutdown(void) 122 { 123 if (kexec_in_progress && hv_kexec_handler) 124 hv_kexec_handler(); 125 126 /* 127 * Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor 128 * corrupts the old VP Assist Pages and can crash the kexec kernel. 129 */ 130 if (kexec_in_progress && hyperv_init_cpuhp > 0) 131 cpuhp_remove_state(hyperv_init_cpuhp); 132 133 /* The function calls stop_other_cpus(). */ 134 native_machine_shutdown(); 135 136 /* Disable the hypercall page when there is only 1 active CPU. */ 137 if (kexec_in_progress) 138 hyperv_cleanup(); 139 } 140 141 static void hv_machine_crash_shutdown(struct pt_regs *regs) 142 { 143 if (hv_crash_handler) 144 hv_crash_handler(regs); 145 146 /* The function calls crash_smp_send_stop(). */ 147 native_machine_crash_shutdown(regs); 148 149 /* Disable the hypercall page when there is only 1 active CPU. */ 150 hyperv_cleanup(); 151 } 152 #endif /* CONFIG_KEXEC_CORE */ 153 #endif /* CONFIG_HYPERV */ 154 155 static uint32_t __init ms_hyperv_platform(void) 156 { 157 u32 eax; 158 u32 hyp_signature[3]; 159 160 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 161 return 0; 162 163 cpuid(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS, 164 &eax, &hyp_signature[0], &hyp_signature[1], &hyp_signature[2]); 165 166 if (eax >= HYPERV_CPUID_MIN && 167 eax <= HYPERV_CPUID_MAX && 168 !memcmp("Microsoft Hv", hyp_signature, 12)) 169 return HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS; 170 171 return 0; 172 } 173 174 static unsigned char hv_get_nmi_reason(void) 175 { 176 return 0; 177 } 178 179 #ifdef CONFIG_X86_LOCAL_APIC 180 /* 181 * Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes 182 * it difficult to process CHANNELMSG_UNLOAD in case of crash. Handle 183 * unknown NMI on the first CPU which gets it. 184 */ 185 static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs) 186 { 187 static atomic_t nmi_cpu = ATOMIC_INIT(-1); 188 189 if (!unknown_nmi_panic) 190 return NMI_DONE; 191 192 if (atomic_cmpxchg(&nmi_cpu, -1, raw_smp_processor_id()) != -1) 193 return NMI_HANDLED; 194 195 return NMI_DONE; 196 } 197 #endif 198 199 static unsigned long hv_get_tsc_khz(void) 200 { 201 unsigned long freq; 202 203 rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq); 204 205 return freq / 1000; 206 } 207 208 #if defined(CONFIG_SMP) && IS_ENABLED(CONFIG_HYPERV) 209 static void __init hv_smp_prepare_boot_cpu(void) 210 { 211 native_smp_prepare_boot_cpu(); 212 #if defined(CONFIG_X86_64) && defined(CONFIG_PARAVIRT_SPINLOCKS) 213 hv_init_spinlocks(); 214 #endif 215 } 216 217 static void __init hv_smp_prepare_cpus(unsigned int max_cpus) 218 { 219 #ifdef CONFIG_X86_64 220 int i; 221 int ret; 222 #endif 223 224 native_smp_prepare_cpus(max_cpus); 225 226 #ifdef CONFIG_X86_64 227 for_each_present_cpu(i) { 228 if (i == 0) 229 continue; 230 ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i)); 231 BUG_ON(ret); 232 } 233 234 for_each_present_cpu(i) { 235 if (i == 0) 236 continue; 237 ret = hv_call_create_vp(numa_cpu_node(i), hv_current_partition_id, i, i); 238 BUG_ON(ret); 239 } 240 #endif 241 } 242 #endif 243 244 static void __init ms_hyperv_init_platform(void) 245 { 246 int hv_max_functions_eax; 247 int hv_host_info_eax; 248 int hv_host_info_ebx; 249 int hv_host_info_ecx; 250 int hv_host_info_edx; 251 252 #ifdef CONFIG_PARAVIRT 253 pv_info.name = "Hyper-V"; 254 #endif 255 256 /* 257 * Extract the features and hints 258 */ 259 ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES); 260 ms_hyperv.priv_high = cpuid_ebx(HYPERV_CPUID_FEATURES); 261 ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES); 262 ms_hyperv.hints = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO); 263 264 hv_max_functions_eax = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS); 265 266 pr_info("Hyper-V: privilege flags low 0x%x, high 0x%x, hints 0x%x, misc 0x%x\n", 267 ms_hyperv.features, ms_hyperv.priv_high, ms_hyperv.hints, 268 ms_hyperv.misc_features); 269 270 ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS); 271 ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS); 272 273 pr_debug("Hyper-V: max %u virtual processors, %u logical processors\n", 274 ms_hyperv.max_vp_index, ms_hyperv.max_lp_index); 275 276 /* 277 * Check CPU management privilege. 278 * 279 * To mirror what Windows does we should extract CPU management 280 * features and use the ReservedIdentityBit to detect if Linux is the 281 * root partition. But that requires negotiating CPU management 282 * interface (a process to be finalized). 283 * 284 * For now, use the privilege flag as the indicator for running as 285 * root. 286 */ 287 if (cpuid_ebx(HYPERV_CPUID_FEATURES) & HV_CPU_MANAGEMENT) { 288 hv_root_partition = true; 289 pr_info("Hyper-V: running as root partition\n"); 290 } 291 292 /* 293 * Extract host information. 294 */ 295 if (hv_max_functions_eax >= HYPERV_CPUID_VERSION) { 296 hv_host_info_eax = cpuid_eax(HYPERV_CPUID_VERSION); 297 hv_host_info_ebx = cpuid_ebx(HYPERV_CPUID_VERSION); 298 hv_host_info_ecx = cpuid_ecx(HYPERV_CPUID_VERSION); 299 hv_host_info_edx = cpuid_edx(HYPERV_CPUID_VERSION); 300 301 pr_info("Hyper-V Host Build:%d-%d.%d-%d-%d.%d\n", 302 hv_host_info_eax, hv_host_info_ebx >> 16, 303 hv_host_info_ebx & 0xFFFF, hv_host_info_ecx, 304 hv_host_info_edx >> 24, hv_host_info_edx & 0xFFFFFF); 305 } 306 307 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 308 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 309 x86_platform.calibrate_tsc = hv_get_tsc_khz; 310 x86_platform.calibrate_cpu = hv_get_tsc_khz; 311 } 312 313 if (ms_hyperv.priv_high & HV_ISOLATION) { 314 ms_hyperv.isolation_config_a = cpuid_eax(HYPERV_CPUID_ISOLATION_CONFIG); 315 ms_hyperv.isolation_config_b = cpuid_ebx(HYPERV_CPUID_ISOLATION_CONFIG); 316 ms_hyperv.shared_gpa_boundary = 317 BIT_ULL(ms_hyperv.shared_gpa_boundary_bits); 318 319 pr_info("Hyper-V: Isolation Config: Group A 0x%x, Group B 0x%x\n", 320 ms_hyperv.isolation_config_a, ms_hyperv.isolation_config_b); 321 322 if (hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP) 323 static_branch_enable(&isolation_type_snp); 324 } 325 326 if (hv_max_functions_eax >= HYPERV_CPUID_NESTED_FEATURES) { 327 ms_hyperv.nested_features = 328 cpuid_eax(HYPERV_CPUID_NESTED_FEATURES); 329 pr_info("Hyper-V: Nested features: 0x%x\n", 330 ms_hyperv.nested_features); 331 } 332 333 #ifdef CONFIG_X86_LOCAL_APIC 334 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 335 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 336 /* 337 * Get the APIC frequency. 338 */ 339 u64 hv_lapic_frequency; 340 341 rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency); 342 hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ); 343 lapic_timer_period = hv_lapic_frequency; 344 pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n", 345 lapic_timer_period); 346 } 347 348 register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST, 349 "hv_nmi_unknown"); 350 #endif 351 352 #ifdef CONFIG_X86_IO_APIC 353 no_timer_check = 1; 354 #endif 355 356 #if IS_ENABLED(CONFIG_HYPERV) && defined(CONFIG_KEXEC_CORE) 357 machine_ops.shutdown = hv_machine_shutdown; 358 machine_ops.crash_shutdown = hv_machine_crash_shutdown; 359 #endif 360 if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) { 361 /* 362 * Writing to synthetic MSR 0x40000118 updates/changes the 363 * guest visible CPUIDs. Setting bit 0 of this MSR enables 364 * guests to report invariant TSC feature through CPUID 365 * instruction, CPUID 0x800000007/EDX, bit 8. See code in 366 * early_init_intel() where this bit is examined. The 367 * setting of this MSR bit should happen before init_intel() 368 * is called. 369 */ 370 wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1); 371 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); 372 } 373 374 /* 375 * Generation 2 instances don't support reading the NMI status from 376 * 0x61 port. 377 */ 378 if (efi_enabled(EFI_BOOT)) 379 x86_platform.get_nmi_reason = hv_get_nmi_reason; 380 381 /* 382 * Hyper-V VMs have a PIT emulation quirk such that zeroing the 383 * counter register during PIT shutdown restarts the PIT. So it 384 * continues to interrupt @18.2 HZ. Setting i8253_clear_counter 385 * to false tells pit_shutdown() not to zero the counter so that 386 * the PIT really is shutdown. Generation 2 VMs don't have a PIT, 387 * and setting this value has no effect. 388 */ 389 i8253_clear_counter_on_shutdown = false; 390 391 #if IS_ENABLED(CONFIG_HYPERV) 392 /* 393 * Setup the hook to get control post apic initialization. 394 */ 395 x86_platform.apic_post_init = hyperv_init; 396 hyperv_setup_mmu_ops(); 397 /* Setup the IDT for hypervisor callback */ 398 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_hyperv_callback); 399 400 /* Setup the IDT for reenlightenment notifications */ 401 if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) { 402 alloc_intr_gate(HYPERV_REENLIGHTENMENT_VECTOR, 403 asm_sysvec_hyperv_reenlightenment); 404 } 405 406 /* Setup the IDT for stimer0 */ 407 if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) { 408 alloc_intr_gate(HYPERV_STIMER0_VECTOR, 409 asm_sysvec_hyperv_stimer0); 410 } 411 412 # ifdef CONFIG_SMP 413 smp_ops.smp_prepare_boot_cpu = hv_smp_prepare_boot_cpu; 414 if (hv_root_partition) 415 smp_ops.smp_prepare_cpus = hv_smp_prepare_cpus; 416 # endif 417 418 /* 419 * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic, 420 * set x2apic destination mode to physical mode when x2apic is available 421 * and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs 422 * have 8-bit APIC id. 423 */ 424 # ifdef CONFIG_X86_X2APIC 425 if (x2apic_supported()) 426 x2apic_phys = 1; 427 # endif 428 429 /* Register Hyper-V specific clocksource */ 430 hv_init_clocksource(); 431 #endif 432 /* 433 * TSC should be marked as unstable only after Hyper-V 434 * clocksource has been initialized. This ensures that the 435 * stability of the sched_clock is not altered. 436 */ 437 if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT)) 438 mark_tsc_unstable("running on Hyper-V"); 439 } 440 441 static bool __init ms_hyperv_x2apic_available(void) 442 { 443 return x2apic_supported(); 444 } 445 446 /* 447 * If ms_hyperv_msi_ext_dest_id() returns true, hyperv_prepare_irq_remapping() 448 * returns -ENODEV and the Hyper-V IOMMU driver is not used; instead, the 449 * generic support of the 15-bit APIC ID is used: see __irq_msi_compose_msg(). 450 * 451 * Note: for a VM on Hyper-V, the I/O-APIC is the only device which 452 * (logically) generates MSIs directly to the system APIC irq domain. 453 * There is no HPET, and PCI MSI/MSI-X interrupts are remapped by the 454 * pci-hyperv host bridge. 455 */ 456 static bool __init ms_hyperv_msi_ext_dest_id(void) 457 { 458 u32 eax; 459 460 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_INTERFACE); 461 if (eax != HYPERV_VS_INTERFACE_EAX_SIGNATURE) 462 return false; 463 464 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_PROPERTIES); 465 return eax & HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE; 466 } 467 468 const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = { 469 .name = "Microsoft Hyper-V", 470 .detect = ms_hyperv_platform, 471 .type = X86_HYPER_MS_HYPERV, 472 .init.x2apic_available = ms_hyperv_x2apic_available, 473 .init.msi_ext_dest_id = ms_hyperv_msi_ext_dest_id, 474 .init.init_platform = ms_hyperv_init_platform, 475 }; 476