1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HyperV Detection code. 4 * 5 * Copyright (C) 2010, Novell, Inc. 6 * Author : K. Y. Srinivasan <ksrinivasan@novell.com> 7 */ 8 9 #include <linux/types.h> 10 #include <linux/time.h> 11 #include <linux/clocksource.h> 12 #include <linux/init.h> 13 #include <linux/export.h> 14 #include <linux/hardirq.h> 15 #include <linux/efi.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/kexec.h> 19 #include <linux/i8253.h> 20 #include <linux/random.h> 21 #include <asm/processor.h> 22 #include <asm/hypervisor.h> 23 #include <asm/hyperv-tlfs.h> 24 #include <asm/mshyperv.h> 25 #include <asm/desc.h> 26 #include <asm/idtentry.h> 27 #include <asm/irq_regs.h> 28 #include <asm/i8259.h> 29 #include <asm/apic.h> 30 #include <asm/timer.h> 31 #include <asm/reboot.h> 32 #include <asm/nmi.h> 33 #include <clocksource/hyperv_timer.h> 34 #include <asm/numa.h> 35 36 /* Is Linux running as the root partition? */ 37 bool hv_root_partition; 38 /* Is Linux running on nested Microsoft Hypervisor */ 39 bool hv_nested; 40 struct ms_hyperv_info ms_hyperv; 41 42 #if IS_ENABLED(CONFIG_HYPERV) 43 static inline unsigned int hv_get_nested_reg(unsigned int reg) 44 { 45 if (hv_is_sint_reg(reg)) 46 return reg - HV_REGISTER_SINT0 + HV_REGISTER_NESTED_SINT0; 47 48 switch (reg) { 49 case HV_REGISTER_SIMP: 50 return HV_REGISTER_NESTED_SIMP; 51 case HV_REGISTER_SIEFP: 52 return HV_REGISTER_NESTED_SIEFP; 53 case HV_REGISTER_SVERSION: 54 return HV_REGISTER_NESTED_SVERSION; 55 case HV_REGISTER_SCONTROL: 56 return HV_REGISTER_NESTED_SCONTROL; 57 case HV_REGISTER_EOM: 58 return HV_REGISTER_NESTED_EOM; 59 default: 60 return reg; 61 } 62 } 63 64 u64 hv_get_non_nested_register(unsigned int reg) 65 { 66 u64 value; 67 68 if (hv_is_synic_reg(reg) && hv_isolation_type_snp()) 69 hv_ghcb_msr_read(reg, &value); 70 else 71 rdmsrl(reg, value); 72 return value; 73 } 74 EXPORT_SYMBOL_GPL(hv_get_non_nested_register); 75 76 void hv_set_non_nested_register(unsigned int reg, u64 value) 77 { 78 if (hv_is_synic_reg(reg) && hv_isolation_type_snp()) { 79 hv_ghcb_msr_write(reg, value); 80 81 /* Write proxy bit via wrmsl instruction */ 82 if (hv_is_sint_reg(reg)) 83 wrmsrl(reg, value | 1 << 20); 84 } else { 85 wrmsrl(reg, value); 86 } 87 } 88 EXPORT_SYMBOL_GPL(hv_set_non_nested_register); 89 90 u64 hv_get_register(unsigned int reg) 91 { 92 if (hv_nested) 93 reg = hv_get_nested_reg(reg); 94 95 return hv_get_non_nested_register(reg); 96 } 97 EXPORT_SYMBOL_GPL(hv_get_register); 98 99 void hv_set_register(unsigned int reg, u64 value) 100 { 101 if (hv_nested) 102 reg = hv_get_nested_reg(reg); 103 104 hv_set_non_nested_register(reg, value); 105 } 106 EXPORT_SYMBOL_GPL(hv_set_register); 107 108 static void (*vmbus_handler)(void); 109 static void (*hv_stimer0_handler)(void); 110 static void (*hv_kexec_handler)(void); 111 static void (*hv_crash_handler)(struct pt_regs *regs); 112 113 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback) 114 { 115 struct pt_regs *old_regs = set_irq_regs(regs); 116 117 inc_irq_stat(irq_hv_callback_count); 118 if (vmbus_handler) 119 vmbus_handler(); 120 121 if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED) 122 apic_eoi(); 123 124 set_irq_regs(old_regs); 125 } 126 127 void hv_setup_vmbus_handler(void (*handler)(void)) 128 { 129 vmbus_handler = handler; 130 } 131 132 void hv_remove_vmbus_handler(void) 133 { 134 /* We have no way to deallocate the interrupt gate */ 135 vmbus_handler = NULL; 136 } 137 138 /* 139 * Routines to do per-architecture handling of stimer0 140 * interrupts when in Direct Mode 141 */ 142 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0) 143 { 144 struct pt_regs *old_regs = set_irq_regs(regs); 145 146 inc_irq_stat(hyperv_stimer0_count); 147 if (hv_stimer0_handler) 148 hv_stimer0_handler(); 149 add_interrupt_randomness(HYPERV_STIMER0_VECTOR); 150 apic_eoi(); 151 152 set_irq_regs(old_regs); 153 } 154 155 /* For x86/x64, override weak placeholders in hyperv_timer.c */ 156 void hv_setup_stimer0_handler(void (*handler)(void)) 157 { 158 hv_stimer0_handler = handler; 159 } 160 161 void hv_remove_stimer0_handler(void) 162 { 163 /* We have no way to deallocate the interrupt gate */ 164 hv_stimer0_handler = NULL; 165 } 166 167 void hv_setup_kexec_handler(void (*handler)(void)) 168 { 169 hv_kexec_handler = handler; 170 } 171 172 void hv_remove_kexec_handler(void) 173 { 174 hv_kexec_handler = NULL; 175 } 176 177 void hv_setup_crash_handler(void (*handler)(struct pt_regs *regs)) 178 { 179 hv_crash_handler = handler; 180 } 181 182 void hv_remove_crash_handler(void) 183 { 184 hv_crash_handler = NULL; 185 } 186 187 #ifdef CONFIG_KEXEC_CORE 188 static void hv_machine_shutdown(void) 189 { 190 if (kexec_in_progress && hv_kexec_handler) 191 hv_kexec_handler(); 192 193 /* 194 * Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor 195 * corrupts the old VP Assist Pages and can crash the kexec kernel. 196 */ 197 if (kexec_in_progress && hyperv_init_cpuhp > 0) 198 cpuhp_remove_state(hyperv_init_cpuhp); 199 200 /* The function calls stop_other_cpus(). */ 201 native_machine_shutdown(); 202 203 /* Disable the hypercall page when there is only 1 active CPU. */ 204 if (kexec_in_progress) 205 hyperv_cleanup(); 206 } 207 208 static void hv_machine_crash_shutdown(struct pt_regs *regs) 209 { 210 if (hv_crash_handler) 211 hv_crash_handler(regs); 212 213 /* The function calls crash_smp_send_stop(). */ 214 native_machine_crash_shutdown(regs); 215 216 /* Disable the hypercall page when there is only 1 active CPU. */ 217 hyperv_cleanup(); 218 } 219 #endif /* CONFIG_KEXEC_CORE */ 220 #endif /* CONFIG_HYPERV */ 221 222 static uint32_t __init ms_hyperv_platform(void) 223 { 224 u32 eax; 225 u32 hyp_signature[3]; 226 227 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 228 return 0; 229 230 cpuid(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS, 231 &eax, &hyp_signature[0], &hyp_signature[1], &hyp_signature[2]); 232 233 if (eax < HYPERV_CPUID_MIN || eax > HYPERV_CPUID_MAX || 234 memcmp("Microsoft Hv", hyp_signature, 12)) 235 return 0; 236 237 /* HYPERCALL and VP_INDEX MSRs are mandatory for all features. */ 238 eax = cpuid_eax(HYPERV_CPUID_FEATURES); 239 if (!(eax & HV_MSR_HYPERCALL_AVAILABLE)) { 240 pr_warn("x86/hyperv: HYPERCALL MSR not available.\n"); 241 return 0; 242 } 243 if (!(eax & HV_MSR_VP_INDEX_AVAILABLE)) { 244 pr_warn("x86/hyperv: VP_INDEX MSR not available.\n"); 245 return 0; 246 } 247 248 return HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS; 249 } 250 251 #ifdef CONFIG_X86_LOCAL_APIC 252 /* 253 * Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes 254 * it difficult to process CHANNELMSG_UNLOAD in case of crash. Handle 255 * unknown NMI on the first CPU which gets it. 256 */ 257 static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs) 258 { 259 static atomic_t nmi_cpu = ATOMIC_INIT(-1); 260 261 if (!unknown_nmi_panic) 262 return NMI_DONE; 263 264 if (atomic_cmpxchg(&nmi_cpu, -1, raw_smp_processor_id()) != -1) 265 return NMI_HANDLED; 266 267 return NMI_DONE; 268 } 269 #endif 270 271 static unsigned long hv_get_tsc_khz(void) 272 { 273 unsigned long freq; 274 275 rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq); 276 277 return freq / 1000; 278 } 279 280 #if defined(CONFIG_SMP) && IS_ENABLED(CONFIG_HYPERV) 281 static void __init hv_smp_prepare_boot_cpu(void) 282 { 283 native_smp_prepare_boot_cpu(); 284 #if defined(CONFIG_X86_64) && defined(CONFIG_PARAVIRT_SPINLOCKS) 285 hv_init_spinlocks(); 286 #endif 287 } 288 289 static void __init hv_smp_prepare_cpus(unsigned int max_cpus) 290 { 291 #ifdef CONFIG_X86_64 292 int i; 293 int ret; 294 #endif 295 296 native_smp_prepare_cpus(max_cpus); 297 298 #ifdef CONFIG_X86_64 299 for_each_present_cpu(i) { 300 if (i == 0) 301 continue; 302 ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i)); 303 BUG_ON(ret); 304 } 305 306 for_each_present_cpu(i) { 307 if (i == 0) 308 continue; 309 ret = hv_call_create_vp(numa_cpu_node(i), hv_current_partition_id, i, i); 310 BUG_ON(ret); 311 } 312 #endif 313 } 314 #endif 315 316 static void __init ms_hyperv_init_platform(void) 317 { 318 int hv_max_functions_eax; 319 int hv_host_info_eax; 320 int hv_host_info_ebx; 321 int hv_host_info_ecx; 322 int hv_host_info_edx; 323 324 #ifdef CONFIG_PARAVIRT 325 pv_info.name = "Hyper-V"; 326 #endif 327 328 /* 329 * Extract the features and hints 330 */ 331 ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES); 332 ms_hyperv.priv_high = cpuid_ebx(HYPERV_CPUID_FEATURES); 333 ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES); 334 ms_hyperv.hints = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO); 335 336 hv_max_functions_eax = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS); 337 338 pr_info("Hyper-V: privilege flags low 0x%x, high 0x%x, hints 0x%x, misc 0x%x\n", 339 ms_hyperv.features, ms_hyperv.priv_high, ms_hyperv.hints, 340 ms_hyperv.misc_features); 341 342 ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS); 343 ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS); 344 345 pr_debug("Hyper-V: max %u virtual processors, %u logical processors\n", 346 ms_hyperv.max_vp_index, ms_hyperv.max_lp_index); 347 348 /* 349 * Check CPU management privilege. 350 * 351 * To mirror what Windows does we should extract CPU management 352 * features and use the ReservedIdentityBit to detect if Linux is the 353 * root partition. But that requires negotiating CPU management 354 * interface (a process to be finalized). For now, use the privilege 355 * flag as the indicator for running as root. 356 * 357 * Hyper-V should never specify running as root and as a Confidential 358 * VM. But to protect against a compromised/malicious Hyper-V trying 359 * to exploit root behavior to expose Confidential VM memory, ignore 360 * the root partition setting if also a Confidential VM. 361 */ 362 if ((ms_hyperv.priv_high & HV_CPU_MANAGEMENT) && 363 !(ms_hyperv.priv_high & HV_ISOLATION)) { 364 hv_root_partition = true; 365 pr_info("Hyper-V: running as root partition\n"); 366 } 367 368 if (ms_hyperv.hints & HV_X64_HYPERV_NESTED) { 369 hv_nested = true; 370 pr_info("Hyper-V: running on a nested hypervisor\n"); 371 } 372 373 /* 374 * Extract host information. 375 */ 376 if (hv_max_functions_eax >= HYPERV_CPUID_VERSION) { 377 hv_host_info_eax = cpuid_eax(HYPERV_CPUID_VERSION); 378 hv_host_info_ebx = cpuid_ebx(HYPERV_CPUID_VERSION); 379 hv_host_info_ecx = cpuid_ecx(HYPERV_CPUID_VERSION); 380 hv_host_info_edx = cpuid_edx(HYPERV_CPUID_VERSION); 381 382 pr_info("Hyper-V: Host Build %d.%d.%d.%d-%d-%d\n", 383 hv_host_info_ebx >> 16, hv_host_info_ebx & 0xFFFF, 384 hv_host_info_eax, hv_host_info_edx & 0xFFFFFF, 385 hv_host_info_ecx, hv_host_info_edx >> 24); 386 } 387 388 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 389 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 390 x86_platform.calibrate_tsc = hv_get_tsc_khz; 391 x86_platform.calibrate_cpu = hv_get_tsc_khz; 392 } 393 394 if (ms_hyperv.priv_high & HV_ISOLATION) { 395 ms_hyperv.isolation_config_a = cpuid_eax(HYPERV_CPUID_ISOLATION_CONFIG); 396 ms_hyperv.isolation_config_b = cpuid_ebx(HYPERV_CPUID_ISOLATION_CONFIG); 397 398 if (ms_hyperv.shared_gpa_boundary_active) 399 ms_hyperv.shared_gpa_boundary = 400 BIT_ULL(ms_hyperv.shared_gpa_boundary_bits); 401 402 pr_info("Hyper-V: Isolation Config: Group A 0x%x, Group B 0x%x\n", 403 ms_hyperv.isolation_config_a, ms_hyperv.isolation_config_b); 404 405 if (hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP) 406 static_branch_enable(&isolation_type_snp); 407 } 408 409 if (hv_max_functions_eax >= HYPERV_CPUID_NESTED_FEATURES) { 410 ms_hyperv.nested_features = 411 cpuid_eax(HYPERV_CPUID_NESTED_FEATURES); 412 pr_info("Hyper-V: Nested features: 0x%x\n", 413 ms_hyperv.nested_features); 414 } 415 416 #ifdef CONFIG_X86_LOCAL_APIC 417 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 418 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 419 /* 420 * Get the APIC frequency. 421 */ 422 u64 hv_lapic_frequency; 423 424 rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency); 425 hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ); 426 lapic_timer_period = hv_lapic_frequency; 427 pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n", 428 lapic_timer_period); 429 } 430 431 register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST, 432 "hv_nmi_unknown"); 433 #endif 434 435 #ifdef CONFIG_X86_IO_APIC 436 no_timer_check = 1; 437 #endif 438 439 #if IS_ENABLED(CONFIG_HYPERV) && defined(CONFIG_KEXEC_CORE) 440 machine_ops.shutdown = hv_machine_shutdown; 441 machine_ops.crash_shutdown = hv_machine_crash_shutdown; 442 #endif 443 if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) { 444 /* 445 * Writing to synthetic MSR 0x40000118 updates/changes the 446 * guest visible CPUIDs. Setting bit 0 of this MSR enables 447 * guests to report invariant TSC feature through CPUID 448 * instruction, CPUID 0x800000007/EDX, bit 8. See code in 449 * early_init_intel() where this bit is examined. The 450 * setting of this MSR bit should happen before init_intel() 451 * is called. 452 */ 453 wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC); 454 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); 455 } 456 457 /* 458 * Generation 2 instances don't support reading the NMI status from 459 * 0x61 port. 460 */ 461 if (efi_enabled(EFI_BOOT)) 462 x86_platform.get_nmi_reason = hv_get_nmi_reason; 463 464 /* 465 * Hyper-V VMs have a PIT emulation quirk such that zeroing the 466 * counter register during PIT shutdown restarts the PIT. So it 467 * continues to interrupt @18.2 HZ. Setting i8253_clear_counter 468 * to false tells pit_shutdown() not to zero the counter so that 469 * the PIT really is shutdown. Generation 2 VMs don't have a PIT, 470 * and setting this value has no effect. 471 */ 472 i8253_clear_counter_on_shutdown = false; 473 474 #if IS_ENABLED(CONFIG_HYPERV) 475 if ((hv_get_isolation_type() == HV_ISOLATION_TYPE_VBS) || 476 (hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP)) 477 hv_vtom_init(); 478 /* 479 * Setup the hook to get control post apic initialization. 480 */ 481 x86_platform.apic_post_init = hyperv_init; 482 hyperv_setup_mmu_ops(); 483 /* Setup the IDT for hypervisor callback */ 484 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_hyperv_callback); 485 486 /* Setup the IDT for reenlightenment notifications */ 487 if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) { 488 alloc_intr_gate(HYPERV_REENLIGHTENMENT_VECTOR, 489 asm_sysvec_hyperv_reenlightenment); 490 } 491 492 /* Setup the IDT for stimer0 */ 493 if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) { 494 alloc_intr_gate(HYPERV_STIMER0_VECTOR, 495 asm_sysvec_hyperv_stimer0); 496 } 497 498 # ifdef CONFIG_SMP 499 smp_ops.smp_prepare_boot_cpu = hv_smp_prepare_boot_cpu; 500 if (hv_root_partition) 501 smp_ops.smp_prepare_cpus = hv_smp_prepare_cpus; 502 # endif 503 504 /* 505 * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic, 506 * set x2apic destination mode to physical mode when x2apic is available 507 * and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs 508 * have 8-bit APIC id. 509 */ 510 # ifdef CONFIG_X86_X2APIC 511 if (x2apic_supported()) 512 x2apic_phys = 1; 513 # endif 514 515 /* Register Hyper-V specific clocksource */ 516 hv_init_clocksource(); 517 hv_vtl_init_platform(); 518 #endif 519 /* 520 * TSC should be marked as unstable only after Hyper-V 521 * clocksource has been initialized. This ensures that the 522 * stability of the sched_clock is not altered. 523 */ 524 if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT)) 525 mark_tsc_unstable("running on Hyper-V"); 526 527 hardlockup_detector_disable(); 528 } 529 530 static bool __init ms_hyperv_x2apic_available(void) 531 { 532 return x2apic_supported(); 533 } 534 535 /* 536 * If ms_hyperv_msi_ext_dest_id() returns true, hyperv_prepare_irq_remapping() 537 * returns -ENODEV and the Hyper-V IOMMU driver is not used; instead, the 538 * generic support of the 15-bit APIC ID is used: see __irq_msi_compose_msg(). 539 * 540 * Note: for a VM on Hyper-V, the I/O-APIC is the only device which 541 * (logically) generates MSIs directly to the system APIC irq domain. 542 * There is no HPET, and PCI MSI/MSI-X interrupts are remapped by the 543 * pci-hyperv host bridge. 544 * 545 * Note: for a Hyper-V root partition, this will always return false. 546 * The hypervisor doesn't expose these HYPERV_CPUID_VIRT_STACK_* cpuids by 547 * default, they are implemented as intercepts by the Windows Hyper-V stack. 548 * Even a nested root partition (L2 root) will not get them because the 549 * nested (L1) hypervisor filters them out. 550 */ 551 static bool __init ms_hyperv_msi_ext_dest_id(void) 552 { 553 u32 eax; 554 555 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_INTERFACE); 556 if (eax != HYPERV_VS_INTERFACE_EAX_SIGNATURE) 557 return false; 558 559 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_PROPERTIES); 560 return eax & HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE; 561 } 562 563 const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = { 564 .name = "Microsoft Hyper-V", 565 .detect = ms_hyperv_platform, 566 .type = X86_HYPER_MS_HYPERV, 567 .init.x2apic_available = ms_hyperv_x2apic_available, 568 .init.msi_ext_dest_id = ms_hyperv_msi_ext_dest_id, 569 .init.init_platform = ms_hyperv_init_platform, 570 }; 571