xref: /openbmc/linux/arch/x86/kernel/cpu/mshyperv.c (revision 10756dc5)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * HyperV  Detection code.
4  *
5  * Copyright (C) 2010, Novell, Inc.
6  * Author : K. Y. Srinivasan <ksrinivasan@novell.com>
7  */
8 
9 #include <linux/types.h>
10 #include <linux/time.h>
11 #include <linux/clocksource.h>
12 #include <linux/init.h>
13 #include <linux/export.h>
14 #include <linux/hardirq.h>
15 #include <linux/efi.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/kexec.h>
19 #include <linux/i8253.h>
20 #include <linux/random.h>
21 #include <linux/swiotlb.h>
22 #include <asm/processor.h>
23 #include <asm/hypervisor.h>
24 #include <asm/hyperv-tlfs.h>
25 #include <asm/mshyperv.h>
26 #include <asm/desc.h>
27 #include <asm/idtentry.h>
28 #include <asm/irq_regs.h>
29 #include <asm/i8259.h>
30 #include <asm/apic.h>
31 #include <asm/timer.h>
32 #include <asm/reboot.h>
33 #include <asm/nmi.h>
34 #include <clocksource/hyperv_timer.h>
35 #include <asm/numa.h>
36 
37 /* Is Linux running as the root partition? */
38 bool hv_root_partition;
39 struct ms_hyperv_info ms_hyperv;
40 
41 #if IS_ENABLED(CONFIG_HYPERV)
42 static void (*vmbus_handler)(void);
43 static void (*hv_stimer0_handler)(void);
44 static void (*hv_kexec_handler)(void);
45 static void (*hv_crash_handler)(struct pt_regs *regs);
46 
47 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback)
48 {
49 	struct pt_regs *old_regs = set_irq_regs(regs);
50 
51 	inc_irq_stat(irq_hv_callback_count);
52 	if (vmbus_handler)
53 		vmbus_handler();
54 
55 	if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED)
56 		ack_APIC_irq();
57 
58 	set_irq_regs(old_regs);
59 }
60 
61 void hv_setup_vmbus_handler(void (*handler)(void))
62 {
63 	vmbus_handler = handler;
64 }
65 
66 void hv_remove_vmbus_handler(void)
67 {
68 	/* We have no way to deallocate the interrupt gate */
69 	vmbus_handler = NULL;
70 }
71 
72 /*
73  * Routines to do per-architecture handling of stimer0
74  * interrupts when in Direct Mode
75  */
76 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0)
77 {
78 	struct pt_regs *old_regs = set_irq_regs(regs);
79 
80 	inc_irq_stat(hyperv_stimer0_count);
81 	if (hv_stimer0_handler)
82 		hv_stimer0_handler();
83 	add_interrupt_randomness(HYPERV_STIMER0_VECTOR);
84 	ack_APIC_irq();
85 
86 	set_irq_regs(old_regs);
87 }
88 
89 /* For x86/x64, override weak placeholders in hyperv_timer.c */
90 void hv_setup_stimer0_handler(void (*handler)(void))
91 {
92 	hv_stimer0_handler = handler;
93 }
94 
95 void hv_remove_stimer0_handler(void)
96 {
97 	/* We have no way to deallocate the interrupt gate */
98 	hv_stimer0_handler = NULL;
99 }
100 
101 void hv_setup_kexec_handler(void (*handler)(void))
102 {
103 	hv_kexec_handler = handler;
104 }
105 
106 void hv_remove_kexec_handler(void)
107 {
108 	hv_kexec_handler = NULL;
109 }
110 
111 void hv_setup_crash_handler(void (*handler)(struct pt_regs *regs))
112 {
113 	hv_crash_handler = handler;
114 }
115 
116 void hv_remove_crash_handler(void)
117 {
118 	hv_crash_handler = NULL;
119 }
120 
121 #ifdef CONFIG_KEXEC_CORE
122 static void hv_machine_shutdown(void)
123 {
124 	if (kexec_in_progress && hv_kexec_handler)
125 		hv_kexec_handler();
126 
127 	/*
128 	 * Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor
129 	 * corrupts the old VP Assist Pages and can crash the kexec kernel.
130 	 */
131 	if (kexec_in_progress && hyperv_init_cpuhp > 0)
132 		cpuhp_remove_state(hyperv_init_cpuhp);
133 
134 	/* The function calls stop_other_cpus(). */
135 	native_machine_shutdown();
136 
137 	/* Disable the hypercall page when there is only 1 active CPU. */
138 	if (kexec_in_progress)
139 		hyperv_cleanup();
140 }
141 
142 static void hv_machine_crash_shutdown(struct pt_regs *regs)
143 {
144 	if (hv_crash_handler)
145 		hv_crash_handler(regs);
146 
147 	/* The function calls crash_smp_send_stop(). */
148 	native_machine_crash_shutdown(regs);
149 
150 	/* Disable the hypercall page when there is only 1 active CPU. */
151 	hyperv_cleanup();
152 }
153 #endif /* CONFIG_KEXEC_CORE */
154 #endif /* CONFIG_HYPERV */
155 
156 static uint32_t  __init ms_hyperv_platform(void)
157 {
158 	u32 eax;
159 	u32 hyp_signature[3];
160 
161 	if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
162 		return 0;
163 
164 	cpuid(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS,
165 	      &eax, &hyp_signature[0], &hyp_signature[1], &hyp_signature[2]);
166 
167 	if (eax < HYPERV_CPUID_MIN || eax > HYPERV_CPUID_MAX ||
168 	    memcmp("Microsoft Hv", hyp_signature, 12))
169 		return 0;
170 
171 	/* HYPERCALL and VP_INDEX MSRs are mandatory for all features. */
172 	eax = cpuid_eax(HYPERV_CPUID_FEATURES);
173 	if (!(eax & HV_MSR_HYPERCALL_AVAILABLE)) {
174 		pr_warn("x86/hyperv: HYPERCALL MSR not available.\n");
175 		return 0;
176 	}
177 	if (!(eax & HV_MSR_VP_INDEX_AVAILABLE)) {
178 		pr_warn("x86/hyperv: VP_INDEX MSR not available.\n");
179 		return 0;
180 	}
181 
182 	return HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
183 }
184 
185 static unsigned char hv_get_nmi_reason(void)
186 {
187 	return 0;
188 }
189 
190 #ifdef CONFIG_X86_LOCAL_APIC
191 /*
192  * Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes
193  * it difficult to process CHANNELMSG_UNLOAD in case of crash. Handle
194  * unknown NMI on the first CPU which gets it.
195  */
196 static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs)
197 {
198 	static atomic_t nmi_cpu = ATOMIC_INIT(-1);
199 
200 	if (!unknown_nmi_panic)
201 		return NMI_DONE;
202 
203 	if (atomic_cmpxchg(&nmi_cpu, -1, raw_smp_processor_id()) != -1)
204 		return NMI_HANDLED;
205 
206 	return NMI_DONE;
207 }
208 #endif
209 
210 static unsigned long hv_get_tsc_khz(void)
211 {
212 	unsigned long freq;
213 
214 	rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq);
215 
216 	return freq / 1000;
217 }
218 
219 #if defined(CONFIG_SMP) && IS_ENABLED(CONFIG_HYPERV)
220 static void __init hv_smp_prepare_boot_cpu(void)
221 {
222 	native_smp_prepare_boot_cpu();
223 #if defined(CONFIG_X86_64) && defined(CONFIG_PARAVIRT_SPINLOCKS)
224 	hv_init_spinlocks();
225 #endif
226 }
227 
228 static void __init hv_smp_prepare_cpus(unsigned int max_cpus)
229 {
230 #ifdef CONFIG_X86_64
231 	int i;
232 	int ret;
233 #endif
234 
235 	native_smp_prepare_cpus(max_cpus);
236 
237 #ifdef CONFIG_X86_64
238 	for_each_present_cpu(i) {
239 		if (i == 0)
240 			continue;
241 		ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i));
242 		BUG_ON(ret);
243 	}
244 
245 	for_each_present_cpu(i) {
246 		if (i == 0)
247 			continue;
248 		ret = hv_call_create_vp(numa_cpu_node(i), hv_current_partition_id, i, i);
249 		BUG_ON(ret);
250 	}
251 #endif
252 }
253 #endif
254 
255 static void __init ms_hyperv_init_platform(void)
256 {
257 	int hv_max_functions_eax;
258 	int hv_host_info_eax;
259 	int hv_host_info_ebx;
260 	int hv_host_info_ecx;
261 	int hv_host_info_edx;
262 
263 #ifdef CONFIG_PARAVIRT
264 	pv_info.name = "Hyper-V";
265 #endif
266 
267 	/*
268 	 * Extract the features and hints
269 	 */
270 	ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES);
271 	ms_hyperv.priv_high = cpuid_ebx(HYPERV_CPUID_FEATURES);
272 	ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES);
273 	ms_hyperv.hints    = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO);
274 
275 	hv_max_functions_eax = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS);
276 
277 	pr_info("Hyper-V: privilege flags low 0x%x, high 0x%x, hints 0x%x, misc 0x%x\n",
278 		ms_hyperv.features, ms_hyperv.priv_high, ms_hyperv.hints,
279 		ms_hyperv.misc_features);
280 
281 	ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS);
282 	ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS);
283 
284 	pr_debug("Hyper-V: max %u virtual processors, %u logical processors\n",
285 		 ms_hyperv.max_vp_index, ms_hyperv.max_lp_index);
286 
287 	/*
288 	 * Check CPU management privilege.
289 	 *
290 	 * To mirror what Windows does we should extract CPU management
291 	 * features and use the ReservedIdentityBit to detect if Linux is the
292 	 * root partition. But that requires negotiating CPU management
293 	 * interface (a process to be finalized).
294 	 *
295 	 * For now, use the privilege flag as the indicator for running as
296 	 * root.
297 	 */
298 	if (cpuid_ebx(HYPERV_CPUID_FEATURES) & HV_CPU_MANAGEMENT) {
299 		hv_root_partition = true;
300 		pr_info("Hyper-V: running as root partition\n");
301 	}
302 
303 	/*
304 	 * Extract host information.
305 	 */
306 	if (hv_max_functions_eax >= HYPERV_CPUID_VERSION) {
307 		hv_host_info_eax = cpuid_eax(HYPERV_CPUID_VERSION);
308 		hv_host_info_ebx = cpuid_ebx(HYPERV_CPUID_VERSION);
309 		hv_host_info_ecx = cpuid_ecx(HYPERV_CPUID_VERSION);
310 		hv_host_info_edx = cpuid_edx(HYPERV_CPUID_VERSION);
311 
312 		pr_info("Hyper-V Host Build:%d-%d.%d-%d-%d.%d\n",
313 			hv_host_info_eax, hv_host_info_ebx >> 16,
314 			hv_host_info_ebx & 0xFFFF, hv_host_info_ecx,
315 			hv_host_info_edx >> 24, hv_host_info_edx & 0xFFFFFF);
316 	}
317 
318 	if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS &&
319 	    ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
320 		x86_platform.calibrate_tsc = hv_get_tsc_khz;
321 		x86_platform.calibrate_cpu = hv_get_tsc_khz;
322 	}
323 
324 	if (ms_hyperv.priv_high & HV_ISOLATION) {
325 		ms_hyperv.isolation_config_a = cpuid_eax(HYPERV_CPUID_ISOLATION_CONFIG);
326 		ms_hyperv.isolation_config_b = cpuid_ebx(HYPERV_CPUID_ISOLATION_CONFIG);
327 		ms_hyperv.shared_gpa_boundary =
328 			BIT_ULL(ms_hyperv.shared_gpa_boundary_bits);
329 
330 		pr_info("Hyper-V: Isolation Config: Group A 0x%x, Group B 0x%x\n",
331 			ms_hyperv.isolation_config_a, ms_hyperv.isolation_config_b);
332 
333 		if (hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP) {
334 			static_branch_enable(&isolation_type_snp);
335 #ifdef CONFIG_SWIOTLB
336 			swiotlb_unencrypted_base = ms_hyperv.shared_gpa_boundary;
337 #endif
338 		}
339 
340 #ifdef CONFIG_SWIOTLB
341 		/*
342 		 * Enable swiotlb force mode in Isolation VM to
343 		 * use swiotlb bounce buffer for dma transaction.
344 		 */
345 		swiotlb_force = SWIOTLB_FORCE;
346 #endif
347 	}
348 
349 	if (hv_max_functions_eax >= HYPERV_CPUID_NESTED_FEATURES) {
350 		ms_hyperv.nested_features =
351 			cpuid_eax(HYPERV_CPUID_NESTED_FEATURES);
352 		pr_info("Hyper-V: Nested features: 0x%x\n",
353 			ms_hyperv.nested_features);
354 	}
355 
356 #ifdef CONFIG_X86_LOCAL_APIC
357 	if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS &&
358 	    ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
359 		/*
360 		 * Get the APIC frequency.
361 		 */
362 		u64	hv_lapic_frequency;
363 
364 		rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency);
365 		hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ);
366 		lapic_timer_period = hv_lapic_frequency;
367 		pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n",
368 			lapic_timer_period);
369 	}
370 
371 	register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST,
372 			     "hv_nmi_unknown");
373 #endif
374 
375 #ifdef CONFIG_X86_IO_APIC
376 	no_timer_check = 1;
377 #endif
378 
379 #if IS_ENABLED(CONFIG_HYPERV) && defined(CONFIG_KEXEC_CORE)
380 	machine_ops.shutdown = hv_machine_shutdown;
381 	machine_ops.crash_shutdown = hv_machine_crash_shutdown;
382 #endif
383 	if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
384 		/*
385 		 * Writing to synthetic MSR 0x40000118 updates/changes the
386 		 * guest visible CPUIDs. Setting bit 0 of this MSR  enables
387 		 * guests to report invariant TSC feature through CPUID
388 		 * instruction, CPUID 0x800000007/EDX, bit 8. See code in
389 		 * early_init_intel() where this bit is examined. The
390 		 * setting of this MSR bit should happen before init_intel()
391 		 * is called.
392 		 */
393 		wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1);
394 		setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
395 	}
396 
397 	/*
398 	 * Generation 2 instances don't support reading the NMI status from
399 	 * 0x61 port.
400 	 */
401 	if (efi_enabled(EFI_BOOT))
402 		x86_platform.get_nmi_reason = hv_get_nmi_reason;
403 
404 	/*
405 	 * Hyper-V VMs have a PIT emulation quirk such that zeroing the
406 	 * counter register during PIT shutdown restarts the PIT. So it
407 	 * continues to interrupt @18.2 HZ. Setting i8253_clear_counter
408 	 * to false tells pit_shutdown() not to zero the counter so that
409 	 * the PIT really is shutdown. Generation 2 VMs don't have a PIT,
410 	 * and setting this value has no effect.
411 	 */
412 	i8253_clear_counter_on_shutdown = false;
413 
414 #if IS_ENABLED(CONFIG_HYPERV)
415 	/*
416 	 * Setup the hook to get control post apic initialization.
417 	 */
418 	x86_platform.apic_post_init = hyperv_init;
419 	hyperv_setup_mmu_ops();
420 	/* Setup the IDT for hypervisor callback */
421 	alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_hyperv_callback);
422 
423 	/* Setup the IDT for reenlightenment notifications */
424 	if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) {
425 		alloc_intr_gate(HYPERV_REENLIGHTENMENT_VECTOR,
426 				asm_sysvec_hyperv_reenlightenment);
427 	}
428 
429 	/* Setup the IDT for stimer0 */
430 	if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) {
431 		alloc_intr_gate(HYPERV_STIMER0_VECTOR,
432 				asm_sysvec_hyperv_stimer0);
433 	}
434 
435 # ifdef CONFIG_SMP
436 	smp_ops.smp_prepare_boot_cpu = hv_smp_prepare_boot_cpu;
437 	if (hv_root_partition)
438 		smp_ops.smp_prepare_cpus = hv_smp_prepare_cpus;
439 # endif
440 
441 	/*
442 	 * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic,
443 	 * set x2apic destination mode to physical mode when x2apic is available
444 	 * and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs
445 	 * have 8-bit APIC id.
446 	 */
447 # ifdef CONFIG_X86_X2APIC
448 	if (x2apic_supported())
449 		x2apic_phys = 1;
450 # endif
451 
452 	/* Register Hyper-V specific clocksource */
453 	hv_init_clocksource();
454 #endif
455 	/*
456 	 * TSC should be marked as unstable only after Hyper-V
457 	 * clocksource has been initialized. This ensures that the
458 	 * stability of the sched_clock is not altered.
459 	 */
460 	if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT))
461 		mark_tsc_unstable("running on Hyper-V");
462 }
463 
464 static bool __init ms_hyperv_x2apic_available(void)
465 {
466 	return x2apic_supported();
467 }
468 
469 /*
470  * If ms_hyperv_msi_ext_dest_id() returns true, hyperv_prepare_irq_remapping()
471  * returns -ENODEV and the Hyper-V IOMMU driver is not used; instead, the
472  * generic support of the 15-bit APIC ID is used: see __irq_msi_compose_msg().
473  *
474  * Note: for a VM on Hyper-V, the I/O-APIC is the only device which
475  * (logically) generates MSIs directly to the system APIC irq domain.
476  * There is no HPET, and PCI MSI/MSI-X interrupts are remapped by the
477  * pci-hyperv host bridge.
478  */
479 static bool __init ms_hyperv_msi_ext_dest_id(void)
480 {
481 	u32 eax;
482 
483 	eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_INTERFACE);
484 	if (eax != HYPERV_VS_INTERFACE_EAX_SIGNATURE)
485 		return false;
486 
487 	eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_PROPERTIES);
488 	return eax & HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE;
489 }
490 
491 const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = {
492 	.name			= "Microsoft Hyper-V",
493 	.detect			= ms_hyperv_platform,
494 	.type			= X86_HYPER_MS_HYPERV,
495 	.init.x2apic_available	= ms_hyperv_x2apic_available,
496 	.init.msi_ext_dest_id	= ms_hyperv_msi_ext_dest_id,
497 	.init.init_platform	= ms_hyperv_init_platform,
498 };
499