1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HyperV Detection code. 4 * 5 * Copyright (C) 2010, Novell, Inc. 6 * Author : K. Y. Srinivasan <ksrinivasan@novell.com> 7 */ 8 9 #include <linux/types.h> 10 #include <linux/time.h> 11 #include <linux/clocksource.h> 12 #include <linux/init.h> 13 #include <linux/export.h> 14 #include <linux/hardirq.h> 15 #include <linux/efi.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/kexec.h> 19 #include <linux/i8253.h> 20 #include <linux/random.h> 21 #include <asm/processor.h> 22 #include <asm/hypervisor.h> 23 #include <asm/hyperv-tlfs.h> 24 #include <asm/mshyperv.h> 25 #include <asm/desc.h> 26 #include <asm/idtentry.h> 27 #include <asm/irq_regs.h> 28 #include <asm/i8259.h> 29 #include <asm/apic.h> 30 #include <asm/timer.h> 31 #include <asm/reboot.h> 32 #include <asm/nmi.h> 33 #include <clocksource/hyperv_timer.h> 34 #include <asm/numa.h> 35 #include <asm/svm.h> 36 37 /* Is Linux running as the root partition? */ 38 bool hv_root_partition; 39 /* Is Linux running on nested Microsoft Hypervisor */ 40 bool hv_nested; 41 struct ms_hyperv_info ms_hyperv; 42 43 #if IS_ENABLED(CONFIG_HYPERV) 44 static inline unsigned int hv_get_nested_reg(unsigned int reg) 45 { 46 if (hv_is_sint_reg(reg)) 47 return reg - HV_REGISTER_SINT0 + HV_REGISTER_NESTED_SINT0; 48 49 switch (reg) { 50 case HV_REGISTER_SIMP: 51 return HV_REGISTER_NESTED_SIMP; 52 case HV_REGISTER_SIEFP: 53 return HV_REGISTER_NESTED_SIEFP; 54 case HV_REGISTER_SVERSION: 55 return HV_REGISTER_NESTED_SVERSION; 56 case HV_REGISTER_SCONTROL: 57 return HV_REGISTER_NESTED_SCONTROL; 58 case HV_REGISTER_EOM: 59 return HV_REGISTER_NESTED_EOM; 60 default: 61 return reg; 62 } 63 } 64 65 u64 hv_get_non_nested_register(unsigned int reg) 66 { 67 u64 value; 68 69 if (hv_is_synic_reg(reg) && hv_isolation_type_snp()) 70 hv_ghcb_msr_read(reg, &value); 71 else 72 rdmsrl(reg, value); 73 return value; 74 } 75 EXPORT_SYMBOL_GPL(hv_get_non_nested_register); 76 77 void hv_set_non_nested_register(unsigned int reg, u64 value) 78 { 79 if (hv_is_synic_reg(reg) && hv_isolation_type_snp()) { 80 hv_ghcb_msr_write(reg, value); 81 82 /* Write proxy bit via wrmsl instruction */ 83 if (hv_is_sint_reg(reg)) 84 wrmsrl(reg, value | 1 << 20); 85 } else { 86 wrmsrl(reg, value); 87 } 88 } 89 EXPORT_SYMBOL_GPL(hv_set_non_nested_register); 90 91 u64 hv_get_register(unsigned int reg) 92 { 93 if (hv_nested) 94 reg = hv_get_nested_reg(reg); 95 96 return hv_get_non_nested_register(reg); 97 } 98 EXPORT_SYMBOL_GPL(hv_get_register); 99 100 void hv_set_register(unsigned int reg, u64 value) 101 { 102 if (hv_nested) 103 reg = hv_get_nested_reg(reg); 104 105 hv_set_non_nested_register(reg, value); 106 } 107 EXPORT_SYMBOL_GPL(hv_set_register); 108 109 static void (*vmbus_handler)(void); 110 static void (*hv_stimer0_handler)(void); 111 static void (*hv_kexec_handler)(void); 112 static void (*hv_crash_handler)(struct pt_regs *regs); 113 114 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback) 115 { 116 struct pt_regs *old_regs = set_irq_regs(regs); 117 118 inc_irq_stat(irq_hv_callback_count); 119 if (vmbus_handler) 120 vmbus_handler(); 121 122 if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED) 123 ack_APIC_irq(); 124 125 set_irq_regs(old_regs); 126 } 127 128 void hv_setup_vmbus_handler(void (*handler)(void)) 129 { 130 vmbus_handler = handler; 131 } 132 133 void hv_remove_vmbus_handler(void) 134 { 135 /* We have no way to deallocate the interrupt gate */ 136 vmbus_handler = NULL; 137 } 138 139 /* 140 * Routines to do per-architecture handling of stimer0 141 * interrupts when in Direct Mode 142 */ 143 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0) 144 { 145 struct pt_regs *old_regs = set_irq_regs(regs); 146 147 inc_irq_stat(hyperv_stimer0_count); 148 if (hv_stimer0_handler) 149 hv_stimer0_handler(); 150 add_interrupt_randomness(HYPERV_STIMER0_VECTOR); 151 ack_APIC_irq(); 152 153 set_irq_regs(old_regs); 154 } 155 156 /* For x86/x64, override weak placeholders in hyperv_timer.c */ 157 void hv_setup_stimer0_handler(void (*handler)(void)) 158 { 159 hv_stimer0_handler = handler; 160 } 161 162 void hv_remove_stimer0_handler(void) 163 { 164 /* We have no way to deallocate the interrupt gate */ 165 hv_stimer0_handler = NULL; 166 } 167 168 void hv_setup_kexec_handler(void (*handler)(void)) 169 { 170 hv_kexec_handler = handler; 171 } 172 173 void hv_remove_kexec_handler(void) 174 { 175 hv_kexec_handler = NULL; 176 } 177 178 void hv_setup_crash_handler(void (*handler)(struct pt_regs *regs)) 179 { 180 hv_crash_handler = handler; 181 } 182 183 void hv_remove_crash_handler(void) 184 { 185 hv_crash_handler = NULL; 186 } 187 188 #ifdef CONFIG_KEXEC_CORE 189 static void hv_machine_shutdown(void) 190 { 191 if (kexec_in_progress && hv_kexec_handler) 192 hv_kexec_handler(); 193 194 /* 195 * Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor 196 * corrupts the old VP Assist Pages and can crash the kexec kernel. 197 */ 198 if (kexec_in_progress && hyperv_init_cpuhp > 0) 199 cpuhp_remove_state(hyperv_init_cpuhp); 200 201 /* The function calls stop_other_cpus(). */ 202 native_machine_shutdown(); 203 204 /* Disable the hypercall page when there is only 1 active CPU. */ 205 if (kexec_in_progress) 206 hyperv_cleanup(); 207 } 208 209 static void hv_machine_crash_shutdown(struct pt_regs *regs) 210 { 211 if (hv_crash_handler) 212 hv_crash_handler(regs); 213 214 /* The function calls crash_smp_send_stop(). */ 215 native_machine_crash_shutdown(regs); 216 217 /* Disable the hypercall page when there is only 1 active CPU. */ 218 hyperv_cleanup(); 219 } 220 #endif /* CONFIG_KEXEC_CORE */ 221 #endif /* CONFIG_HYPERV */ 222 223 static uint32_t __init ms_hyperv_platform(void) 224 { 225 u32 eax; 226 u32 hyp_signature[3]; 227 228 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 229 return 0; 230 231 cpuid(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS, 232 &eax, &hyp_signature[0], &hyp_signature[1], &hyp_signature[2]); 233 234 if (eax < HYPERV_CPUID_MIN || eax > HYPERV_CPUID_MAX || 235 memcmp("Microsoft Hv", hyp_signature, 12)) 236 return 0; 237 238 /* HYPERCALL and VP_INDEX MSRs are mandatory for all features. */ 239 eax = cpuid_eax(HYPERV_CPUID_FEATURES); 240 if (!(eax & HV_MSR_HYPERCALL_AVAILABLE)) { 241 pr_warn("x86/hyperv: HYPERCALL MSR not available.\n"); 242 return 0; 243 } 244 if (!(eax & HV_MSR_VP_INDEX_AVAILABLE)) { 245 pr_warn("x86/hyperv: VP_INDEX MSR not available.\n"); 246 return 0; 247 } 248 249 return HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS; 250 } 251 252 #ifdef CONFIG_X86_LOCAL_APIC 253 /* 254 * Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes 255 * it difficult to process CHANNELMSG_UNLOAD in case of crash. Handle 256 * unknown NMI on the first CPU which gets it. 257 */ 258 static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs) 259 { 260 static atomic_t nmi_cpu = ATOMIC_INIT(-1); 261 262 if (!unknown_nmi_panic) 263 return NMI_DONE; 264 265 if (atomic_cmpxchg(&nmi_cpu, -1, raw_smp_processor_id()) != -1) 266 return NMI_HANDLED; 267 268 return NMI_DONE; 269 } 270 #endif 271 272 static unsigned long hv_get_tsc_khz(void) 273 { 274 unsigned long freq; 275 276 rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq); 277 278 return freq / 1000; 279 } 280 281 #if defined(CONFIG_SMP) && IS_ENABLED(CONFIG_HYPERV) 282 static void __init hv_smp_prepare_boot_cpu(void) 283 { 284 native_smp_prepare_boot_cpu(); 285 #if defined(CONFIG_X86_64) && defined(CONFIG_PARAVIRT_SPINLOCKS) 286 hv_init_spinlocks(); 287 #endif 288 } 289 290 static void __init hv_smp_prepare_cpus(unsigned int max_cpus) 291 { 292 #ifdef CONFIG_X86_64 293 int i; 294 int ret; 295 #endif 296 297 native_smp_prepare_cpus(max_cpus); 298 299 /* 300 * Override wakeup_secondary_cpu_64 callback for SEV-SNP 301 * enlightened guest. 302 */ 303 if (hv_isolation_type_en_snp()) { 304 apic->wakeup_secondary_cpu_64 = hv_snp_boot_ap; 305 return; 306 } 307 308 #ifdef CONFIG_X86_64 309 for_each_present_cpu(i) { 310 if (i == 0) 311 continue; 312 ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i)); 313 BUG_ON(ret); 314 } 315 316 for_each_present_cpu(i) { 317 if (i == 0) 318 continue; 319 ret = hv_call_create_vp(numa_cpu_node(i), hv_current_partition_id, i, i); 320 BUG_ON(ret); 321 } 322 #endif 323 } 324 #endif 325 326 static void __init ms_hyperv_init_platform(void) 327 { 328 int hv_max_functions_eax; 329 int hv_host_info_eax; 330 int hv_host_info_ebx; 331 int hv_host_info_ecx; 332 int hv_host_info_edx; 333 334 #ifdef CONFIG_PARAVIRT 335 pv_info.name = "Hyper-V"; 336 #endif 337 338 /* 339 * Extract the features and hints 340 */ 341 ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES); 342 ms_hyperv.priv_high = cpuid_ebx(HYPERV_CPUID_FEATURES); 343 ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES); 344 ms_hyperv.hints = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO); 345 346 hv_max_functions_eax = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS); 347 348 pr_info("Hyper-V: privilege flags low 0x%x, high 0x%x, hints 0x%x, misc 0x%x\n", 349 ms_hyperv.features, ms_hyperv.priv_high, ms_hyperv.hints, 350 ms_hyperv.misc_features); 351 352 ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS); 353 ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS); 354 355 pr_debug("Hyper-V: max %u virtual processors, %u logical processors\n", 356 ms_hyperv.max_vp_index, ms_hyperv.max_lp_index); 357 358 /* 359 * Check CPU management privilege. 360 * 361 * To mirror what Windows does we should extract CPU management 362 * features and use the ReservedIdentityBit to detect if Linux is the 363 * root partition. But that requires negotiating CPU management 364 * interface (a process to be finalized). For now, use the privilege 365 * flag as the indicator for running as root. 366 * 367 * Hyper-V should never specify running as root and as a Confidential 368 * VM. But to protect against a compromised/malicious Hyper-V trying 369 * to exploit root behavior to expose Confidential VM memory, ignore 370 * the root partition setting if also a Confidential VM. 371 */ 372 if ((ms_hyperv.priv_high & HV_CPU_MANAGEMENT) && 373 !(ms_hyperv.priv_high & HV_ISOLATION)) { 374 hv_root_partition = true; 375 pr_info("Hyper-V: running as root partition\n"); 376 } 377 378 if (ms_hyperv.hints & HV_X64_HYPERV_NESTED) { 379 hv_nested = true; 380 pr_info("Hyper-V: running on a nested hypervisor\n"); 381 } 382 383 /* 384 * Extract host information. 385 */ 386 if (hv_max_functions_eax >= HYPERV_CPUID_VERSION) { 387 hv_host_info_eax = cpuid_eax(HYPERV_CPUID_VERSION); 388 hv_host_info_ebx = cpuid_ebx(HYPERV_CPUID_VERSION); 389 hv_host_info_ecx = cpuid_ecx(HYPERV_CPUID_VERSION); 390 hv_host_info_edx = cpuid_edx(HYPERV_CPUID_VERSION); 391 392 pr_info("Hyper-V: Host Build %d.%d.%d.%d-%d-%d\n", 393 hv_host_info_ebx >> 16, hv_host_info_ebx & 0xFFFF, 394 hv_host_info_eax, hv_host_info_edx & 0xFFFFFF, 395 hv_host_info_ecx, hv_host_info_edx >> 24); 396 } 397 398 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 399 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 400 x86_platform.calibrate_tsc = hv_get_tsc_khz; 401 x86_platform.calibrate_cpu = hv_get_tsc_khz; 402 } 403 404 if (ms_hyperv.priv_high & HV_ISOLATION) { 405 ms_hyperv.isolation_config_a = cpuid_eax(HYPERV_CPUID_ISOLATION_CONFIG); 406 ms_hyperv.isolation_config_b = cpuid_ebx(HYPERV_CPUID_ISOLATION_CONFIG); 407 408 if (ms_hyperv.shared_gpa_boundary_active) 409 ms_hyperv.shared_gpa_boundary = 410 BIT_ULL(ms_hyperv.shared_gpa_boundary_bits); 411 412 pr_info("Hyper-V: Isolation Config: Group A 0x%x, Group B 0x%x\n", 413 ms_hyperv.isolation_config_a, ms_hyperv.isolation_config_b); 414 415 416 if (hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP) { 417 if (ms_hyperv.paravisor_present) 418 static_branch_enable(&isolation_type_snp); 419 else 420 static_branch_enable(&isolation_type_en_snp); 421 } else if (hv_get_isolation_type() == HV_ISOLATION_TYPE_TDX) { 422 static_branch_enable(&isolation_type_tdx); 423 } 424 } 425 426 if (hv_max_functions_eax >= HYPERV_CPUID_NESTED_FEATURES) { 427 ms_hyperv.nested_features = 428 cpuid_eax(HYPERV_CPUID_NESTED_FEATURES); 429 pr_info("Hyper-V: Nested features: 0x%x\n", 430 ms_hyperv.nested_features); 431 } 432 433 #ifdef CONFIG_X86_LOCAL_APIC 434 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 435 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 436 /* 437 * Get the APIC frequency. 438 */ 439 u64 hv_lapic_frequency; 440 441 rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency); 442 hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ); 443 lapic_timer_period = hv_lapic_frequency; 444 pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n", 445 lapic_timer_period); 446 } 447 448 register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST, 449 "hv_nmi_unknown"); 450 #endif 451 452 #ifdef CONFIG_X86_IO_APIC 453 no_timer_check = 1; 454 #endif 455 456 #if IS_ENABLED(CONFIG_HYPERV) && defined(CONFIG_KEXEC_CORE) 457 machine_ops.shutdown = hv_machine_shutdown; 458 machine_ops.crash_shutdown = hv_machine_crash_shutdown; 459 #endif 460 if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) { 461 /* 462 * Writing to synthetic MSR 0x40000118 updates/changes the 463 * guest visible CPUIDs. Setting bit 0 of this MSR enables 464 * guests to report invariant TSC feature through CPUID 465 * instruction, CPUID 0x800000007/EDX, bit 8. See code in 466 * early_init_intel() where this bit is examined. The 467 * setting of this MSR bit should happen before init_intel() 468 * is called. 469 */ 470 wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC); 471 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); 472 } 473 474 /* 475 * Generation 2 instances don't support reading the NMI status from 476 * 0x61 port. 477 */ 478 if (efi_enabled(EFI_BOOT)) 479 x86_platform.get_nmi_reason = hv_get_nmi_reason; 480 481 /* 482 * Hyper-V VMs have a PIT emulation quirk such that zeroing the 483 * counter register during PIT shutdown restarts the PIT. So it 484 * continues to interrupt @18.2 HZ. Setting i8253_clear_counter 485 * to false tells pit_shutdown() not to zero the counter so that 486 * the PIT really is shutdown. Generation 2 VMs don't have a PIT, 487 * and setting this value has no effect. 488 */ 489 i8253_clear_counter_on_shutdown = false; 490 491 #if IS_ENABLED(CONFIG_HYPERV) 492 if ((hv_get_isolation_type() == HV_ISOLATION_TYPE_VBS) || 493 ((hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP) && 494 ms_hyperv.paravisor_present)) 495 hv_vtom_init(); 496 /* 497 * Setup the hook to get control post apic initialization. 498 */ 499 x86_platform.apic_post_init = hyperv_init; 500 hyperv_setup_mmu_ops(); 501 /* Setup the IDT for hypervisor callback */ 502 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_hyperv_callback); 503 504 /* Setup the IDT for reenlightenment notifications */ 505 if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) { 506 alloc_intr_gate(HYPERV_REENLIGHTENMENT_VECTOR, 507 asm_sysvec_hyperv_reenlightenment); 508 } 509 510 /* Setup the IDT for stimer0 */ 511 if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) { 512 alloc_intr_gate(HYPERV_STIMER0_VECTOR, 513 asm_sysvec_hyperv_stimer0); 514 } 515 516 # ifdef CONFIG_SMP 517 smp_ops.smp_prepare_boot_cpu = hv_smp_prepare_boot_cpu; 518 if (hv_root_partition || hv_isolation_type_en_snp()) 519 smp_ops.smp_prepare_cpus = hv_smp_prepare_cpus; 520 # endif 521 522 /* 523 * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic, 524 * set x2apic destination mode to physical mode when x2apic is available 525 * and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs 526 * have 8-bit APIC id. 527 */ 528 # ifdef CONFIG_X86_X2APIC 529 if (x2apic_supported()) 530 x2apic_phys = 1; 531 # endif 532 533 /* Register Hyper-V specific clocksource */ 534 hv_init_clocksource(); 535 hv_vtl_init_platform(); 536 #endif 537 /* 538 * TSC should be marked as unstable only after Hyper-V 539 * clocksource has been initialized. This ensures that the 540 * stability of the sched_clock is not altered. 541 */ 542 if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT)) 543 mark_tsc_unstable("running on Hyper-V"); 544 545 hardlockup_detector_disable(); 546 } 547 548 static bool __init ms_hyperv_x2apic_available(void) 549 { 550 return x2apic_supported(); 551 } 552 553 /* 554 * If ms_hyperv_msi_ext_dest_id() returns true, hyperv_prepare_irq_remapping() 555 * returns -ENODEV and the Hyper-V IOMMU driver is not used; instead, the 556 * generic support of the 15-bit APIC ID is used: see __irq_msi_compose_msg(). 557 * 558 * Note: for a VM on Hyper-V, the I/O-APIC is the only device which 559 * (logically) generates MSIs directly to the system APIC irq domain. 560 * There is no HPET, and PCI MSI/MSI-X interrupts are remapped by the 561 * pci-hyperv host bridge. 562 * 563 * Note: for a Hyper-V root partition, this will always return false. 564 * The hypervisor doesn't expose these HYPERV_CPUID_VIRT_STACK_* cpuids by 565 * default, they are implemented as intercepts by the Windows Hyper-V stack. 566 * Even a nested root partition (L2 root) will not get them because the 567 * nested (L1) hypervisor filters them out. 568 */ 569 static bool __init ms_hyperv_msi_ext_dest_id(void) 570 { 571 u32 eax; 572 573 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_INTERFACE); 574 if (eax != HYPERV_VS_INTERFACE_EAX_SIGNATURE) 575 return false; 576 577 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_PROPERTIES); 578 return eax & HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE; 579 } 580 581 #ifdef CONFIG_AMD_MEM_ENCRYPT 582 static void hv_sev_es_hcall_prepare(struct ghcb *ghcb, struct pt_regs *regs) 583 { 584 /* RAX and CPL are already in the GHCB */ 585 ghcb_set_rcx(ghcb, regs->cx); 586 ghcb_set_rdx(ghcb, regs->dx); 587 ghcb_set_r8(ghcb, regs->r8); 588 } 589 590 static bool hv_sev_es_hcall_finish(struct ghcb *ghcb, struct pt_regs *regs) 591 { 592 /* No checking of the return state needed */ 593 return true; 594 } 595 #endif 596 597 const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = { 598 .name = "Microsoft Hyper-V", 599 .detect = ms_hyperv_platform, 600 .type = X86_HYPER_MS_HYPERV, 601 .init.x2apic_available = ms_hyperv_x2apic_available, 602 .init.msi_ext_dest_id = ms_hyperv_msi_ext_dest_id, 603 .init.init_platform = ms_hyperv_init_platform, 604 #ifdef CONFIG_AMD_MEM_ENCRYPT 605 .runtime.sev_es_hcall_prepare = hv_sev_es_hcall_prepare, 606 .runtime.sev_es_hcall_finish = hv_sev_es_hcall_finish, 607 #endif 608 }; 609