1 /* 2 * Intel CPU Microcode Update Driver for Linux 3 * 4 * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk> 5 * 2006 Shaohua Li <shaohua.li@intel.com> 6 * 7 * Intel CPU microcode early update for Linux 8 * 9 * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com> 10 * H Peter Anvin" <hpa@zytor.com> 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * as published by the Free Software Foundation; either version 15 * 2 of the License, or (at your option) any later version. 16 */ 17 18 /* 19 * This needs to be before all headers so that pr_debug in printk.h doesn't turn 20 * printk calls into no_printk(). 21 * 22 *#define DEBUG 23 */ 24 #define pr_fmt(fmt) "microcode: " fmt 25 26 #include <linux/earlycpio.h> 27 #include <linux/firmware.h> 28 #include <linux/uaccess.h> 29 #include <linux/vmalloc.h> 30 #include <linux/initrd.h> 31 #include <linux/kernel.h> 32 #include <linux/slab.h> 33 #include <linux/cpu.h> 34 #include <linux/mm.h> 35 36 #include <asm/microcode_intel.h> 37 #include <asm/processor.h> 38 #include <asm/tlbflush.h> 39 #include <asm/setup.h> 40 #include <asm/msr.h> 41 42 static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; 43 44 /* Current microcode patch used in early patching */ 45 struct microcode_intel *intel_ucode_patch; 46 47 static inline bool cpu_signatures_match(unsigned int s1, unsigned int p1, 48 unsigned int s2, unsigned int p2) 49 { 50 if (s1 != s2) 51 return false; 52 53 /* Processor flags are either both 0 ... */ 54 if (!p1 && !p2) 55 return true; 56 57 /* ... or they intersect. */ 58 return p1 & p2; 59 } 60 61 /* 62 * Returns 1 if update has been found, 0 otherwise. 63 */ 64 static int find_matching_signature(void *mc, unsigned int csig, int cpf) 65 { 66 struct microcode_header_intel *mc_hdr = mc; 67 struct extended_sigtable *ext_hdr; 68 struct extended_signature *ext_sig; 69 int i; 70 71 if (cpu_signatures_match(csig, cpf, mc_hdr->sig, mc_hdr->pf)) 72 return 1; 73 74 /* Look for ext. headers: */ 75 if (get_totalsize(mc_hdr) <= get_datasize(mc_hdr) + MC_HEADER_SIZE) 76 return 0; 77 78 ext_hdr = mc + get_datasize(mc_hdr) + MC_HEADER_SIZE; 79 ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE; 80 81 for (i = 0; i < ext_hdr->count; i++) { 82 if (cpu_signatures_match(csig, cpf, ext_sig->sig, ext_sig->pf)) 83 return 1; 84 ext_sig++; 85 } 86 return 0; 87 } 88 89 /* 90 * Returns 1 if update has been found, 0 otherwise. 91 */ 92 static int has_newer_microcode(void *mc, unsigned int csig, int cpf, int new_rev) 93 { 94 struct microcode_header_intel *mc_hdr = mc; 95 96 if (mc_hdr->rev <= new_rev) 97 return 0; 98 99 return find_matching_signature(mc, csig, cpf); 100 } 101 102 /* 103 * Given CPU signature and a microcode patch, this function finds if the 104 * microcode patch has matching family and model with the CPU. 105 * 106 * %true - if there's a match 107 * %false - otherwise 108 */ 109 static bool microcode_matches(struct microcode_header_intel *mc_header, 110 unsigned long sig) 111 { 112 unsigned long total_size = get_totalsize(mc_header); 113 unsigned long data_size = get_datasize(mc_header); 114 struct extended_sigtable *ext_header; 115 unsigned int fam_ucode, model_ucode; 116 struct extended_signature *ext_sig; 117 unsigned int fam, model; 118 int ext_sigcount, i; 119 120 fam = x86_family(sig); 121 model = x86_model(sig); 122 123 fam_ucode = x86_family(mc_header->sig); 124 model_ucode = x86_model(mc_header->sig); 125 126 if (fam == fam_ucode && model == model_ucode) 127 return true; 128 129 /* Look for ext. headers: */ 130 if (total_size <= data_size + MC_HEADER_SIZE) 131 return false; 132 133 ext_header = (void *) mc_header + data_size + MC_HEADER_SIZE; 134 ext_sig = (void *)ext_header + EXT_HEADER_SIZE; 135 ext_sigcount = ext_header->count; 136 137 for (i = 0; i < ext_sigcount; i++) { 138 fam_ucode = x86_family(ext_sig->sig); 139 model_ucode = x86_model(ext_sig->sig); 140 141 if (fam == fam_ucode && model == model_ucode) 142 return true; 143 144 ext_sig++; 145 } 146 return false; 147 } 148 149 static struct ucode_patch *__alloc_microcode_buf(void *data, unsigned int size) 150 { 151 struct ucode_patch *p; 152 153 p = kzalloc(size, GFP_KERNEL); 154 if (!p) 155 return ERR_PTR(-ENOMEM); 156 157 p->data = kmemdup(data, size, GFP_KERNEL); 158 if (!p->data) { 159 kfree(p); 160 return ERR_PTR(-ENOMEM); 161 } 162 163 return p; 164 } 165 166 static void save_microcode_patch(void *data, unsigned int size) 167 { 168 struct microcode_header_intel *mc_hdr, *mc_saved_hdr; 169 struct ucode_patch *iter, *tmp, *p; 170 bool prev_found = false; 171 unsigned int sig, pf; 172 173 mc_hdr = (struct microcode_header_intel *)data; 174 175 list_for_each_entry_safe(iter, tmp, µcode_cache, plist) { 176 mc_saved_hdr = (struct microcode_header_intel *)iter->data; 177 sig = mc_saved_hdr->sig; 178 pf = mc_saved_hdr->pf; 179 180 if (find_matching_signature(data, sig, pf)) { 181 prev_found = true; 182 183 if (mc_hdr->rev <= mc_saved_hdr->rev) 184 continue; 185 186 p = __alloc_microcode_buf(data, size); 187 if (IS_ERR(p)) 188 pr_err("Error allocating buffer %p\n", data); 189 else 190 list_replace(&iter->plist, &p->plist); 191 } 192 } 193 194 /* 195 * There weren't any previous patches found in the list cache; save the 196 * newly found. 197 */ 198 if (!prev_found) { 199 p = __alloc_microcode_buf(data, size); 200 if (IS_ERR(p)) 201 pr_err("Error allocating buffer for %p\n", data); 202 else 203 list_add_tail(&p->plist, µcode_cache); 204 } 205 } 206 207 static int microcode_sanity_check(void *mc, int print_err) 208 { 209 unsigned long total_size, data_size, ext_table_size; 210 struct microcode_header_intel *mc_header = mc; 211 struct extended_sigtable *ext_header = NULL; 212 u32 sum, orig_sum, ext_sigcount = 0, i; 213 struct extended_signature *ext_sig; 214 215 total_size = get_totalsize(mc_header); 216 data_size = get_datasize(mc_header); 217 218 if (data_size + MC_HEADER_SIZE > total_size) { 219 if (print_err) 220 pr_err("Error: bad microcode data file size.\n"); 221 return -EINVAL; 222 } 223 224 if (mc_header->ldrver != 1 || mc_header->hdrver != 1) { 225 if (print_err) 226 pr_err("Error: invalid/unknown microcode update format.\n"); 227 return -EINVAL; 228 } 229 230 ext_table_size = total_size - (MC_HEADER_SIZE + data_size); 231 if (ext_table_size) { 232 u32 ext_table_sum = 0; 233 u32 *ext_tablep; 234 235 if ((ext_table_size < EXT_HEADER_SIZE) 236 || ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) { 237 if (print_err) 238 pr_err("Error: truncated extended signature table.\n"); 239 return -EINVAL; 240 } 241 242 ext_header = mc + MC_HEADER_SIZE + data_size; 243 if (ext_table_size != exttable_size(ext_header)) { 244 if (print_err) 245 pr_err("Error: extended signature table size mismatch.\n"); 246 return -EFAULT; 247 } 248 249 ext_sigcount = ext_header->count; 250 251 /* 252 * Check extended table checksum: the sum of all dwords that 253 * comprise a valid table must be 0. 254 */ 255 ext_tablep = (u32 *)ext_header; 256 257 i = ext_table_size / sizeof(u32); 258 while (i--) 259 ext_table_sum += ext_tablep[i]; 260 261 if (ext_table_sum) { 262 if (print_err) 263 pr_warn("Bad extended signature table checksum, aborting.\n"); 264 return -EINVAL; 265 } 266 } 267 268 /* 269 * Calculate the checksum of update data and header. The checksum of 270 * valid update data and header including the extended signature table 271 * must be 0. 272 */ 273 orig_sum = 0; 274 i = (MC_HEADER_SIZE + data_size) / sizeof(u32); 275 while (i--) 276 orig_sum += ((u32 *)mc)[i]; 277 278 if (orig_sum) { 279 if (print_err) 280 pr_err("Bad microcode data checksum, aborting.\n"); 281 return -EINVAL; 282 } 283 284 if (!ext_table_size) 285 return 0; 286 287 /* 288 * Check extended signature checksum: 0 => valid. 289 */ 290 for (i = 0; i < ext_sigcount; i++) { 291 ext_sig = (void *)ext_header + EXT_HEADER_SIZE + 292 EXT_SIGNATURE_SIZE * i; 293 294 sum = (mc_header->sig + mc_header->pf + mc_header->cksum) - 295 (ext_sig->sig + ext_sig->pf + ext_sig->cksum); 296 if (sum) { 297 if (print_err) 298 pr_err("Bad extended signature checksum, aborting.\n"); 299 return -EINVAL; 300 } 301 } 302 return 0; 303 } 304 305 /* 306 * Get microcode matching with BSP's model. Only CPUs with the same model as 307 * BSP can stay in the platform. 308 */ 309 static struct microcode_intel * 310 scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save) 311 { 312 struct microcode_header_intel *mc_header; 313 struct microcode_intel *patch = NULL; 314 unsigned int mc_size; 315 316 while (size) { 317 if (size < sizeof(struct microcode_header_intel)) 318 break; 319 320 mc_header = (struct microcode_header_intel *)data; 321 322 mc_size = get_totalsize(mc_header); 323 if (!mc_size || 324 mc_size > size || 325 microcode_sanity_check(data, 0) < 0) 326 break; 327 328 size -= mc_size; 329 330 if (!microcode_matches(mc_header, uci->cpu_sig.sig)) { 331 data += mc_size; 332 continue; 333 } 334 335 if (save) { 336 save_microcode_patch(data, mc_size); 337 goto next; 338 } 339 340 341 if (!patch) { 342 if (!has_newer_microcode(data, 343 uci->cpu_sig.sig, 344 uci->cpu_sig.pf, 345 uci->cpu_sig.rev)) 346 goto next; 347 348 } else { 349 struct microcode_header_intel *phdr = &patch->hdr; 350 351 if (!has_newer_microcode(data, 352 phdr->sig, 353 phdr->pf, 354 phdr->rev)) 355 goto next; 356 } 357 358 /* We have a newer patch, save it. */ 359 patch = data; 360 361 next: 362 data += mc_size; 363 } 364 365 if (size) 366 return NULL; 367 368 return patch; 369 } 370 371 static void cpuid_1(void) 372 { 373 /* 374 * According to the Intel SDM, Volume 3, 9.11.7: 375 * 376 * CPUID returns a value in a model specific register in 377 * addition to its usual register return values. The 378 * semantics of CPUID cause it to deposit an update ID value 379 * in the 64-bit model-specific register at address 08BH 380 * (IA32_BIOS_SIGN_ID). If no update is present in the 381 * processor, the value in the MSR remains unmodified. 382 * 383 * Use native_cpuid -- this code runs very early and we don't 384 * want to mess with paravirt. 385 */ 386 unsigned int eax = 1, ebx, ecx = 0, edx; 387 388 native_cpuid(&eax, &ebx, &ecx, &edx); 389 } 390 391 static int collect_cpu_info_early(struct ucode_cpu_info *uci) 392 { 393 unsigned int val[2]; 394 unsigned int family, model; 395 struct cpu_signature csig = { 0 }; 396 unsigned int eax, ebx, ecx, edx; 397 398 memset(uci, 0, sizeof(*uci)); 399 400 eax = 0x00000001; 401 ecx = 0; 402 native_cpuid(&eax, &ebx, &ecx, &edx); 403 csig.sig = eax; 404 405 family = x86_family(eax); 406 model = x86_model(eax); 407 408 if ((model >= 5) || (family > 6)) { 409 /* get processor flags from MSR 0x17 */ 410 native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); 411 csig.pf = 1 << ((val[1] >> 18) & 7); 412 } 413 native_wrmsrl(MSR_IA32_UCODE_REV, 0); 414 415 /* As documented in the SDM: Do a CPUID 1 here */ 416 cpuid_1(); 417 418 /* get the current revision from MSR 0x8B */ 419 native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); 420 421 csig.rev = val[1]; 422 423 uci->cpu_sig = csig; 424 uci->valid = 1; 425 426 return 0; 427 } 428 429 static void show_saved_mc(void) 430 { 431 #ifdef DEBUG 432 int i = 0, j; 433 unsigned int sig, pf, rev, total_size, data_size, date; 434 struct ucode_cpu_info uci; 435 struct ucode_patch *p; 436 437 if (list_empty(µcode_cache)) { 438 pr_debug("no microcode data saved.\n"); 439 return; 440 } 441 442 collect_cpu_info_early(&uci); 443 444 sig = uci.cpu_sig.sig; 445 pf = uci.cpu_sig.pf; 446 rev = uci.cpu_sig.rev; 447 pr_debug("CPU: sig=0x%x, pf=0x%x, rev=0x%x\n", sig, pf, rev); 448 449 list_for_each_entry(p, µcode_cache, plist) { 450 struct microcode_header_intel *mc_saved_header; 451 struct extended_sigtable *ext_header; 452 struct extended_signature *ext_sig; 453 int ext_sigcount; 454 455 mc_saved_header = (struct microcode_header_intel *)p->data; 456 457 sig = mc_saved_header->sig; 458 pf = mc_saved_header->pf; 459 rev = mc_saved_header->rev; 460 date = mc_saved_header->date; 461 462 total_size = get_totalsize(mc_saved_header); 463 data_size = get_datasize(mc_saved_header); 464 465 pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, total size=0x%x, date = %04x-%02x-%02x\n", 466 i++, sig, pf, rev, total_size, 467 date & 0xffff, 468 date >> 24, 469 (date >> 16) & 0xff); 470 471 /* Look for ext. headers: */ 472 if (total_size <= data_size + MC_HEADER_SIZE) 473 continue; 474 475 ext_header = (void *)mc_saved_header + data_size + MC_HEADER_SIZE; 476 ext_sigcount = ext_header->count; 477 ext_sig = (void *)ext_header + EXT_HEADER_SIZE; 478 479 for (j = 0; j < ext_sigcount; j++) { 480 sig = ext_sig->sig; 481 pf = ext_sig->pf; 482 483 pr_debug("\tExtended[%d]: sig=0x%x, pf=0x%x\n", 484 j, sig, pf); 485 486 ext_sig++; 487 } 488 } 489 #endif 490 } 491 492 /* 493 * Save this microcode patch. It will be loaded early when a CPU is 494 * hot-added or resumes. 495 */ 496 static void save_mc_for_early(u8 *mc, unsigned int size) 497 { 498 #ifdef CONFIG_HOTPLUG_CPU 499 /* Synchronization during CPU hotplug. */ 500 static DEFINE_MUTEX(x86_cpu_microcode_mutex); 501 502 mutex_lock(&x86_cpu_microcode_mutex); 503 504 save_microcode_patch(mc, size); 505 show_saved_mc(); 506 507 mutex_unlock(&x86_cpu_microcode_mutex); 508 #endif 509 } 510 511 static bool load_builtin_intel_microcode(struct cpio_data *cp) 512 { 513 unsigned int eax = 1, ebx, ecx = 0, edx; 514 char name[30]; 515 516 if (IS_ENABLED(CONFIG_X86_32)) 517 return false; 518 519 native_cpuid(&eax, &ebx, &ecx, &edx); 520 521 sprintf(name, "intel-ucode/%02x-%02x-%02x", 522 x86_family(eax), x86_model(eax), x86_stepping(eax)); 523 524 return get_builtin_firmware(cp, name); 525 } 526 527 /* 528 * Print ucode update info. 529 */ 530 static void 531 print_ucode_info(struct ucode_cpu_info *uci, unsigned int date) 532 { 533 pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n", 534 uci->cpu_sig.rev, 535 date & 0xffff, 536 date >> 24, 537 (date >> 16) & 0xff); 538 } 539 540 #ifdef CONFIG_X86_32 541 542 static int delay_ucode_info; 543 static int current_mc_date; 544 545 /* 546 * Print early updated ucode info after printk works. This is delayed info dump. 547 */ 548 void show_ucode_info_early(void) 549 { 550 struct ucode_cpu_info uci; 551 552 if (delay_ucode_info) { 553 collect_cpu_info_early(&uci); 554 print_ucode_info(&uci, current_mc_date); 555 delay_ucode_info = 0; 556 } 557 } 558 559 /* 560 * At this point, we can not call printk() yet. Delay printing microcode info in 561 * show_ucode_info_early() until printk() works. 562 */ 563 static void print_ucode(struct ucode_cpu_info *uci) 564 { 565 struct microcode_intel *mc; 566 int *delay_ucode_info_p; 567 int *current_mc_date_p; 568 569 mc = uci->mc; 570 if (!mc) 571 return; 572 573 delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); 574 current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); 575 576 *delay_ucode_info_p = 1; 577 *current_mc_date_p = mc->hdr.date; 578 } 579 #else 580 581 /* 582 * Flush global tlb. We only do this in x86_64 where paging has been enabled 583 * already and PGE should be enabled as well. 584 */ 585 static inline void flush_tlb_early(void) 586 { 587 __native_flush_tlb_global_irq_disabled(); 588 } 589 590 static inline void print_ucode(struct ucode_cpu_info *uci) 591 { 592 struct microcode_intel *mc; 593 594 mc = uci->mc; 595 if (!mc) 596 return; 597 598 print_ucode_info(uci, mc->hdr.date); 599 } 600 #endif 601 602 static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) 603 { 604 struct microcode_intel *mc; 605 unsigned int val[2]; 606 607 mc = uci->mc; 608 if (!mc) 609 return 0; 610 611 /* write microcode via MSR 0x79 */ 612 native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); 613 native_wrmsrl(MSR_IA32_UCODE_REV, 0); 614 615 /* As documented in the SDM: Do a CPUID 1 here */ 616 cpuid_1(); 617 618 /* get the current revision from MSR 0x8B */ 619 native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); 620 if (val[1] != mc->hdr.rev) 621 return -1; 622 623 #ifdef CONFIG_X86_64 624 /* Flush global tlb. This is precaution. */ 625 flush_tlb_early(); 626 #endif 627 uci->cpu_sig.rev = val[1]; 628 629 if (early) 630 print_ucode(uci); 631 else 632 print_ucode_info(uci, mc->hdr.date); 633 634 return 0; 635 } 636 637 int __init save_microcode_in_initrd_intel(void) 638 { 639 struct ucode_cpu_info uci; 640 struct cpio_data cp; 641 642 /* 643 * AP loading didn't find any microcode patch, no need to save anything. 644 */ 645 if (!intel_ucode_patch || IS_ERR(intel_ucode_patch)) 646 return 0; 647 648 if (!load_builtin_intel_microcode(&cp)) 649 cp = find_microcode_in_initrd(ucode_path, false); 650 651 if (!(cp.data && cp.size)) 652 return 0; 653 654 collect_cpu_info_early(&uci); 655 656 scan_microcode(cp.data, cp.size, &uci, true); 657 658 show_saved_mc(); 659 660 return 0; 661 } 662 663 664 /* 665 * @res_patch, output: a pointer to the patch we found. 666 */ 667 static struct microcode_intel *__load_ucode_intel(struct ucode_cpu_info *uci) 668 { 669 static const char *path; 670 struct cpio_data cp; 671 bool use_pa; 672 673 if (IS_ENABLED(CONFIG_X86_32)) { 674 path = (const char *)__pa_nodebug(ucode_path); 675 use_pa = true; 676 } else { 677 path = ucode_path; 678 use_pa = false; 679 } 680 681 /* try built-in microcode first */ 682 if (!load_builtin_intel_microcode(&cp)) 683 cp = find_microcode_in_initrd(path, use_pa); 684 685 if (!(cp.data && cp.size)) 686 return NULL; 687 688 collect_cpu_info_early(uci); 689 690 return scan_microcode(cp.data, cp.size, uci, false); 691 } 692 693 void __init load_ucode_intel_bsp(void) 694 { 695 struct microcode_intel *patch; 696 struct ucode_cpu_info uci; 697 698 patch = __load_ucode_intel(&uci); 699 if (!patch) 700 return; 701 702 uci.mc = patch; 703 704 apply_microcode_early(&uci, true); 705 } 706 707 void load_ucode_intel_ap(void) 708 { 709 struct microcode_intel *patch, **iup; 710 struct ucode_cpu_info uci; 711 712 if (IS_ENABLED(CONFIG_X86_32)) 713 iup = (struct microcode_intel **) __pa_nodebug(&intel_ucode_patch); 714 else 715 iup = &intel_ucode_patch; 716 717 reget: 718 if (!*iup) { 719 patch = __load_ucode_intel(&uci); 720 if (!patch) 721 return; 722 723 *iup = patch; 724 } 725 726 uci.mc = *iup; 727 728 if (apply_microcode_early(&uci, true)) { 729 /* Mixed-silicon system? Try to refetch the proper patch: */ 730 *iup = NULL; 731 732 goto reget; 733 } 734 } 735 736 static struct microcode_intel *find_patch(struct ucode_cpu_info *uci) 737 { 738 struct microcode_header_intel *phdr; 739 struct ucode_patch *iter, *tmp; 740 741 list_for_each_entry_safe(iter, tmp, µcode_cache, plist) { 742 743 phdr = (struct microcode_header_intel *)iter->data; 744 745 if (phdr->rev <= uci->cpu_sig.rev) 746 continue; 747 748 if (!find_matching_signature(phdr, 749 uci->cpu_sig.sig, 750 uci->cpu_sig.pf)) 751 continue; 752 753 return iter->data; 754 } 755 return NULL; 756 } 757 758 void reload_ucode_intel(void) 759 { 760 struct microcode_intel *p; 761 struct ucode_cpu_info uci; 762 763 collect_cpu_info_early(&uci); 764 765 p = find_patch(&uci); 766 if (!p) 767 return; 768 769 uci.mc = p; 770 771 apply_microcode_early(&uci, false); 772 } 773 774 static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) 775 { 776 static struct cpu_signature prev; 777 struct cpuinfo_x86 *c = &cpu_data(cpu_num); 778 unsigned int val[2]; 779 780 memset(csig, 0, sizeof(*csig)); 781 782 csig->sig = cpuid_eax(0x00000001); 783 784 if ((c->x86_model >= 5) || (c->x86 > 6)) { 785 /* get processor flags from MSR 0x17 */ 786 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); 787 csig->pf = 1 << ((val[1] >> 18) & 7); 788 } 789 790 csig->rev = c->microcode; 791 792 /* No extra locking on prev, races are harmless. */ 793 if (csig->sig != prev.sig || csig->pf != prev.pf || csig->rev != prev.rev) { 794 pr_info("sig=0x%x, pf=0x%x, revision=0x%x\n", 795 csig->sig, csig->pf, csig->rev); 796 prev = *csig; 797 } 798 799 return 0; 800 } 801 802 static int apply_microcode_intel(int cpu) 803 { 804 struct microcode_intel *mc; 805 struct ucode_cpu_info *uci; 806 struct cpuinfo_x86 *c; 807 unsigned int val[2]; 808 static int prev_rev; 809 810 /* We should bind the task to the CPU */ 811 if (WARN_ON(raw_smp_processor_id() != cpu)) 812 return -1; 813 814 uci = ucode_cpu_info + cpu; 815 mc = uci->mc; 816 if (!mc) { 817 /* Look for a newer patch in our cache: */ 818 mc = find_patch(uci); 819 if (!mc) 820 return 0; 821 } 822 823 /* write microcode via MSR 0x79 */ 824 wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); 825 wrmsrl(MSR_IA32_UCODE_REV, 0); 826 827 /* As documented in the SDM: Do a CPUID 1 here */ 828 cpuid_1(); 829 830 /* get the current revision from MSR 0x8B */ 831 rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); 832 833 if (val[1] != mc->hdr.rev) { 834 pr_err("CPU%d update to revision 0x%x failed\n", 835 cpu, mc->hdr.rev); 836 return -1; 837 } 838 839 if (val[1] != prev_rev) { 840 pr_info("updated to revision 0x%x, date = %04x-%02x-%02x\n", 841 val[1], 842 mc->hdr.date & 0xffff, 843 mc->hdr.date >> 24, 844 (mc->hdr.date >> 16) & 0xff); 845 prev_rev = val[1]; 846 } 847 848 c = &cpu_data(cpu); 849 850 uci->cpu_sig.rev = val[1]; 851 c->microcode = val[1]; 852 853 return 0; 854 } 855 856 static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size, 857 int (*get_ucode_data)(void *, const void *, size_t)) 858 { 859 struct ucode_cpu_info *uci = ucode_cpu_info + cpu; 860 u8 *ucode_ptr = data, *new_mc = NULL, *mc = NULL; 861 int new_rev = uci->cpu_sig.rev; 862 unsigned int leftover = size; 863 unsigned int curr_mc_size = 0; 864 unsigned int csig, cpf; 865 866 while (leftover) { 867 struct microcode_header_intel mc_header; 868 unsigned int mc_size; 869 870 if (leftover < sizeof(mc_header)) { 871 pr_err("error! Truncated header in microcode data file\n"); 872 break; 873 } 874 875 if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header))) 876 break; 877 878 mc_size = get_totalsize(&mc_header); 879 if (!mc_size || mc_size > leftover) { 880 pr_err("error! Bad data in microcode data file\n"); 881 break; 882 } 883 884 /* For performance reasons, reuse mc area when possible */ 885 if (!mc || mc_size > curr_mc_size) { 886 vfree(mc); 887 mc = vmalloc(mc_size); 888 if (!mc) 889 break; 890 curr_mc_size = mc_size; 891 } 892 893 if (get_ucode_data(mc, ucode_ptr, mc_size) || 894 microcode_sanity_check(mc, 1) < 0) { 895 break; 896 } 897 898 csig = uci->cpu_sig.sig; 899 cpf = uci->cpu_sig.pf; 900 if (has_newer_microcode(mc, csig, cpf, new_rev)) { 901 vfree(new_mc); 902 new_rev = mc_header.rev; 903 new_mc = mc; 904 mc = NULL; /* trigger new vmalloc */ 905 } 906 907 ucode_ptr += mc_size; 908 leftover -= mc_size; 909 } 910 911 vfree(mc); 912 913 if (leftover) { 914 vfree(new_mc); 915 return UCODE_ERROR; 916 } 917 918 if (!new_mc) 919 return UCODE_NFOUND; 920 921 vfree(uci->mc); 922 uci->mc = (struct microcode_intel *)new_mc; 923 924 /* 925 * If early loading microcode is supported, save this mc into 926 * permanent memory. So it will be loaded early when a CPU is hot added 927 * or resumes. 928 */ 929 save_mc_for_early(new_mc, curr_mc_size); 930 931 pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", 932 cpu, new_rev, uci->cpu_sig.rev); 933 934 return UCODE_OK; 935 } 936 937 static int get_ucode_fw(void *to, const void *from, size_t n) 938 { 939 memcpy(to, from, n); 940 return 0; 941 } 942 943 static enum ucode_state request_microcode_fw(int cpu, struct device *device, 944 bool refresh_fw) 945 { 946 char name[30]; 947 struct cpuinfo_x86 *c = &cpu_data(cpu); 948 const struct firmware *firmware; 949 enum ucode_state ret; 950 951 sprintf(name, "intel-ucode/%02x-%02x-%02x", 952 c->x86, c->x86_model, c->x86_mask); 953 954 if (request_firmware_direct(&firmware, name, device)) { 955 pr_debug("data file %s load failed\n", name); 956 return UCODE_NFOUND; 957 } 958 959 ret = generic_load_microcode(cpu, (void *)firmware->data, 960 firmware->size, &get_ucode_fw); 961 962 release_firmware(firmware); 963 964 return ret; 965 } 966 967 static int get_ucode_user(void *to, const void *from, size_t n) 968 { 969 return copy_from_user(to, from, n); 970 } 971 972 static enum ucode_state 973 request_microcode_user(int cpu, const void __user *buf, size_t size) 974 { 975 return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user); 976 } 977 978 static struct microcode_ops microcode_intel_ops = { 979 .request_microcode_user = request_microcode_user, 980 .request_microcode_fw = request_microcode_fw, 981 .collect_cpu_info = collect_cpu_info, 982 .apply_microcode = apply_microcode_intel, 983 }; 984 985 struct microcode_ops * __init init_intel_microcode(void) 986 { 987 struct cpuinfo_x86 *c = &boot_cpu_data; 988 989 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 || 990 cpu_has(c, X86_FEATURE_IA64)) { 991 pr_err("Intel CPU family 0x%x not supported\n", c->x86); 992 return NULL; 993 } 994 995 return µcode_intel_ops; 996 } 997