1 /* 2 * AMD CPU Microcode Update Driver for Linux 3 * 4 * This driver allows to upgrade microcode on F10h AMD 5 * CPUs and later. 6 * 7 * Copyright (C) 2008-2011 Advanced Micro Devices Inc. 8 * 2013-2016 Borislav Petkov <bp@alien8.de> 9 * 10 * Author: Peter Oruba <peter.oruba@amd.com> 11 * 12 * Based on work by: 13 * Tigran Aivazian <aivazian.tigran@gmail.com> 14 * 15 * early loader: 16 * Copyright (C) 2013 Advanced Micro Devices, Inc. 17 * 18 * Author: Jacob Shin <jacob.shin@amd.com> 19 * Fixes: Borislav Petkov <bp@suse.de> 20 * 21 * Licensed under the terms of the GNU General Public 22 * License version 2. See file COPYING for details. 23 */ 24 #define pr_fmt(fmt) "microcode: " fmt 25 26 #include <linux/earlycpio.h> 27 #include <linux/firmware.h> 28 #include <linux/uaccess.h> 29 #include <linux/vmalloc.h> 30 #include <linux/initrd.h> 31 #include <linux/kernel.h> 32 #include <linux/pci.h> 33 34 #include <asm/microcode_amd.h> 35 #include <asm/microcode.h> 36 #include <asm/processor.h> 37 #include <asm/setup.h> 38 #include <asm/cpu.h> 39 #include <asm/msr.h> 40 41 static struct equiv_cpu_entry *equiv_cpu_table; 42 43 /* 44 * This points to the current valid container of microcode patches which we will 45 * save from the initrd/builtin before jettisoning its contents. @mc is the 46 * microcode patch we found to match. 47 */ 48 struct cont_desc { 49 struct microcode_amd *mc; 50 u32 cpuid_1_eax; 51 u32 psize; 52 u8 *data; 53 size_t size; 54 }; 55 56 static u32 ucode_new_rev; 57 static u8 amd_ucode_patch[PATCH_MAX_SIZE]; 58 59 /* 60 * Microcode patch container file is prepended to the initrd in cpio 61 * format. See Documentation/x86/early-microcode.txt 62 */ 63 static const char 64 ucode_path[] __maybe_unused = "kernel/x86/microcode/AuthenticAMD.bin"; 65 66 static u16 find_equiv_id(struct equiv_cpu_entry *equiv_table, u32 sig) 67 { 68 for (; equiv_table && equiv_table->installed_cpu; equiv_table++) { 69 if (sig == equiv_table->installed_cpu) 70 return equiv_table->equiv_cpu; 71 } 72 73 return 0; 74 } 75 76 /* 77 * This scans the ucode blob for the proper container as we can have multiple 78 * containers glued together. Returns the equivalence ID from the equivalence 79 * table or 0 if none found. 80 * Returns the amount of bytes consumed while scanning. @desc contains all the 81 * data we're going to use in later stages of the application. 82 */ 83 static ssize_t parse_container(u8 *ucode, ssize_t size, struct cont_desc *desc) 84 { 85 struct equiv_cpu_entry *eq; 86 ssize_t orig_size = size; 87 u32 *hdr = (u32 *)ucode; 88 u16 eq_id; 89 u8 *buf; 90 91 /* Am I looking at an equivalence table header? */ 92 if (hdr[0] != UCODE_MAGIC || 93 hdr[1] != UCODE_EQUIV_CPU_TABLE_TYPE || 94 hdr[2] == 0) 95 return CONTAINER_HDR_SZ; 96 97 buf = ucode; 98 99 eq = (struct equiv_cpu_entry *)(buf + CONTAINER_HDR_SZ); 100 101 /* Find the equivalence ID of our CPU in this table: */ 102 eq_id = find_equiv_id(eq, desc->cpuid_1_eax); 103 104 buf += hdr[2] + CONTAINER_HDR_SZ; 105 size -= hdr[2] + CONTAINER_HDR_SZ; 106 107 /* 108 * Scan through the rest of the container to find where it ends. We do 109 * some basic sanity-checking too. 110 */ 111 while (size > 0) { 112 struct microcode_amd *mc; 113 u32 patch_size; 114 115 hdr = (u32 *)buf; 116 117 if (hdr[0] != UCODE_UCODE_TYPE) 118 break; 119 120 /* Sanity-check patch size. */ 121 patch_size = hdr[1]; 122 if (patch_size > PATCH_MAX_SIZE) 123 break; 124 125 /* Skip patch section header: */ 126 buf += SECTION_HDR_SIZE; 127 size -= SECTION_HDR_SIZE; 128 129 mc = (struct microcode_amd *)buf; 130 if (eq_id == mc->hdr.processor_rev_id) { 131 desc->psize = patch_size; 132 desc->mc = mc; 133 } 134 135 buf += patch_size; 136 size -= patch_size; 137 } 138 139 /* 140 * If we have found a patch (desc->mc), it means we're looking at the 141 * container which has a patch for this CPU so return 0 to mean, @ucode 142 * already points to the proper container. Otherwise, we return the size 143 * we scanned so that we can advance to the next container in the 144 * buffer. 145 */ 146 if (desc->mc) { 147 desc->data = ucode; 148 desc->size = orig_size - size; 149 150 return 0; 151 } 152 153 return orig_size - size; 154 } 155 156 /* 157 * Scan the ucode blob for the proper container as we can have multiple 158 * containers glued together. 159 */ 160 static void scan_containers(u8 *ucode, size_t size, struct cont_desc *desc) 161 { 162 ssize_t rem = size; 163 164 while (rem >= 0) { 165 ssize_t s = parse_container(ucode, rem, desc); 166 if (!s) 167 return; 168 169 ucode += s; 170 rem -= s; 171 } 172 } 173 174 static int __apply_microcode_amd(struct microcode_amd *mc) 175 { 176 u32 rev, dummy; 177 178 native_wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc->hdr.data_code); 179 180 /* verify patch application was successful */ 181 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); 182 if (rev != mc->hdr.patch_id) 183 return -1; 184 185 return 0; 186 } 187 188 /* 189 * Early load occurs before we can vmalloc(). So we look for the microcode 190 * patch container file in initrd, traverse equivalent cpu table, look for a 191 * matching microcode patch, and update, all in initrd memory in place. 192 * When vmalloc() is available for use later -- on 64-bit during first AP load, 193 * and on 32-bit during save_microcode_in_initrd_amd() -- we can call 194 * load_microcode_amd() to save equivalent cpu table and microcode patches in 195 * kernel heap memory. 196 * 197 * Returns true if container found (sets @desc), false otherwise. 198 */ 199 static bool 200 apply_microcode_early_amd(u32 cpuid_1_eax, void *ucode, size_t size, bool save_patch) 201 { 202 struct cont_desc desc = { 0 }; 203 u8 (*patch)[PATCH_MAX_SIZE]; 204 struct microcode_amd *mc; 205 u32 rev, dummy, *new_rev; 206 bool ret = false; 207 208 #ifdef CONFIG_X86_32 209 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev); 210 patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch); 211 #else 212 new_rev = &ucode_new_rev; 213 patch = &amd_ucode_patch; 214 #endif 215 216 desc.cpuid_1_eax = cpuid_1_eax; 217 218 scan_containers(ucode, size, &desc); 219 220 mc = desc.mc; 221 if (!mc) 222 return ret; 223 224 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); 225 if (rev >= mc->hdr.patch_id) 226 return ret; 227 228 if (!__apply_microcode_amd(mc)) { 229 *new_rev = mc->hdr.patch_id; 230 ret = true; 231 232 if (save_patch) 233 memcpy(patch, mc, min_t(u32, desc.psize, PATCH_MAX_SIZE)); 234 } 235 236 return ret; 237 } 238 239 static bool get_builtin_microcode(struct cpio_data *cp, unsigned int family) 240 { 241 #ifdef CONFIG_X86_64 242 char fw_name[36] = "amd-ucode/microcode_amd.bin"; 243 244 if (family >= 0x15) 245 snprintf(fw_name, sizeof(fw_name), 246 "amd-ucode/microcode_amd_fam%.2xh.bin", family); 247 248 return get_builtin_firmware(cp, fw_name); 249 #else 250 return false; 251 #endif 252 } 253 254 static void __load_ucode_amd(unsigned int cpuid_1_eax, struct cpio_data *ret) 255 { 256 struct ucode_cpu_info *uci; 257 struct cpio_data cp; 258 const char *path; 259 bool use_pa; 260 261 if (IS_ENABLED(CONFIG_X86_32)) { 262 uci = (struct ucode_cpu_info *)__pa_nodebug(ucode_cpu_info); 263 path = (const char *)__pa_nodebug(ucode_path); 264 use_pa = true; 265 } else { 266 uci = ucode_cpu_info; 267 path = ucode_path; 268 use_pa = false; 269 } 270 271 if (!get_builtin_microcode(&cp, x86_family(cpuid_1_eax))) 272 cp = find_microcode_in_initrd(path, use_pa); 273 274 /* Needed in load_microcode_amd() */ 275 uci->cpu_sig.sig = cpuid_1_eax; 276 277 *ret = cp; 278 } 279 280 void __init load_ucode_amd_bsp(unsigned int cpuid_1_eax) 281 { 282 struct cpio_data cp = { }; 283 284 __load_ucode_amd(cpuid_1_eax, &cp); 285 if (!(cp.data && cp.size)) 286 return; 287 288 apply_microcode_early_amd(cpuid_1_eax, cp.data, cp.size, true); 289 } 290 291 void load_ucode_amd_ap(unsigned int cpuid_1_eax) 292 { 293 struct microcode_amd *mc; 294 struct cpio_data cp; 295 u32 *new_rev, rev, dummy; 296 297 if (IS_ENABLED(CONFIG_X86_32)) { 298 mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch); 299 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev); 300 } else { 301 mc = (struct microcode_amd *)amd_ucode_patch; 302 new_rev = &ucode_new_rev; 303 } 304 305 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); 306 307 /* Check whether we have saved a new patch already: */ 308 if (*new_rev && rev < mc->hdr.patch_id) { 309 if (!__apply_microcode_amd(mc)) { 310 *new_rev = mc->hdr.patch_id; 311 return; 312 } 313 } 314 315 __load_ucode_amd(cpuid_1_eax, &cp); 316 if (!(cp.data && cp.size)) 317 return; 318 319 apply_microcode_early_amd(cpuid_1_eax, cp.data, cp.size, false); 320 } 321 322 static enum ucode_state 323 load_microcode_amd(bool save, u8 family, const u8 *data, size_t size); 324 325 int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax) 326 { 327 struct cont_desc desc = { 0 }; 328 enum ucode_state ret; 329 struct cpio_data cp; 330 331 cp = find_microcode_in_initrd(ucode_path, false); 332 if (!(cp.data && cp.size)) 333 return -EINVAL; 334 335 desc.cpuid_1_eax = cpuid_1_eax; 336 337 scan_containers(cp.data, cp.size, &desc); 338 if (!desc.mc) 339 return -EINVAL; 340 341 ret = load_microcode_amd(true, x86_family(cpuid_1_eax), desc.data, desc.size); 342 if (ret != UCODE_OK) 343 return -EINVAL; 344 345 return 0; 346 } 347 348 void reload_ucode_amd(void) 349 { 350 struct microcode_amd *mc; 351 u32 rev, dummy; 352 353 mc = (struct microcode_amd *)amd_ucode_patch; 354 355 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); 356 357 if (rev < mc->hdr.patch_id) { 358 if (!__apply_microcode_amd(mc)) { 359 ucode_new_rev = mc->hdr.patch_id; 360 pr_info("reload patch_level=0x%08x\n", ucode_new_rev); 361 } 362 } 363 } 364 static u16 __find_equiv_id(unsigned int cpu) 365 { 366 struct ucode_cpu_info *uci = ucode_cpu_info + cpu; 367 return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig); 368 } 369 370 static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu) 371 { 372 int i = 0; 373 374 BUG_ON(!equiv_cpu_table); 375 376 while (equiv_cpu_table[i].equiv_cpu != 0) { 377 if (equiv_cpu == equiv_cpu_table[i].equiv_cpu) 378 return equiv_cpu_table[i].installed_cpu; 379 i++; 380 } 381 return 0; 382 } 383 384 /* 385 * a small, trivial cache of per-family ucode patches 386 */ 387 static struct ucode_patch *cache_find_patch(u16 equiv_cpu) 388 { 389 struct ucode_patch *p; 390 391 list_for_each_entry(p, µcode_cache, plist) 392 if (p->equiv_cpu == equiv_cpu) 393 return p; 394 return NULL; 395 } 396 397 static void update_cache(struct ucode_patch *new_patch) 398 { 399 struct ucode_patch *p; 400 401 list_for_each_entry(p, µcode_cache, plist) { 402 if (p->equiv_cpu == new_patch->equiv_cpu) { 403 if (p->patch_id >= new_patch->patch_id) { 404 /* we already have the latest patch */ 405 kfree(new_patch->data); 406 kfree(new_patch); 407 return; 408 } 409 410 list_replace(&p->plist, &new_patch->plist); 411 kfree(p->data); 412 kfree(p); 413 return; 414 } 415 } 416 /* no patch found, add it */ 417 list_add_tail(&new_patch->plist, µcode_cache); 418 } 419 420 static void free_cache(void) 421 { 422 struct ucode_patch *p, *tmp; 423 424 list_for_each_entry_safe(p, tmp, µcode_cache, plist) { 425 __list_del(p->plist.prev, p->plist.next); 426 kfree(p->data); 427 kfree(p); 428 } 429 } 430 431 static struct ucode_patch *find_patch(unsigned int cpu) 432 { 433 u16 equiv_id; 434 435 equiv_id = __find_equiv_id(cpu); 436 if (!equiv_id) 437 return NULL; 438 439 return cache_find_patch(equiv_id); 440 } 441 442 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) 443 { 444 struct cpuinfo_x86 *c = &cpu_data(cpu); 445 struct ucode_cpu_info *uci = ucode_cpu_info + cpu; 446 struct ucode_patch *p; 447 448 csig->sig = cpuid_eax(0x00000001); 449 csig->rev = c->microcode; 450 451 /* 452 * a patch could have been loaded early, set uci->mc so that 453 * mc_bp_resume() can call apply_microcode() 454 */ 455 p = find_patch(cpu); 456 if (p && (p->patch_id == csig->rev)) 457 uci->mc = p->data; 458 459 pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev); 460 461 return 0; 462 } 463 464 static unsigned int verify_patch_size(u8 family, u32 patch_size, 465 unsigned int size) 466 { 467 u32 max_size; 468 469 #define F1XH_MPB_MAX_SIZE 2048 470 #define F14H_MPB_MAX_SIZE 1824 471 #define F15H_MPB_MAX_SIZE 4096 472 #define F16H_MPB_MAX_SIZE 3458 473 #define F17H_MPB_MAX_SIZE 3200 474 475 switch (family) { 476 case 0x14: 477 max_size = F14H_MPB_MAX_SIZE; 478 break; 479 case 0x15: 480 max_size = F15H_MPB_MAX_SIZE; 481 break; 482 case 0x16: 483 max_size = F16H_MPB_MAX_SIZE; 484 break; 485 case 0x17: 486 max_size = F17H_MPB_MAX_SIZE; 487 break; 488 default: 489 max_size = F1XH_MPB_MAX_SIZE; 490 break; 491 } 492 493 if (patch_size > min_t(u32, size, max_size)) { 494 pr_err("patch size mismatch\n"); 495 return 0; 496 } 497 498 return patch_size; 499 } 500 501 static int apply_microcode_amd(int cpu) 502 { 503 struct cpuinfo_x86 *c = &cpu_data(cpu); 504 struct microcode_amd *mc_amd; 505 struct ucode_cpu_info *uci; 506 struct ucode_patch *p; 507 u32 rev, dummy; 508 509 BUG_ON(raw_smp_processor_id() != cpu); 510 511 uci = ucode_cpu_info + cpu; 512 513 p = find_patch(cpu); 514 if (!p) 515 return 0; 516 517 mc_amd = p->data; 518 uci->mc = p->data; 519 520 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); 521 522 /* need to apply patch? */ 523 if (rev >= mc_amd->hdr.patch_id) { 524 c->microcode = rev; 525 uci->cpu_sig.rev = rev; 526 return 0; 527 } 528 529 if (__apply_microcode_amd(mc_amd)) { 530 pr_err("CPU%d: update failed for patch_level=0x%08x\n", 531 cpu, mc_amd->hdr.patch_id); 532 return -1; 533 } 534 pr_info("CPU%d: new patch_level=0x%08x\n", cpu, 535 mc_amd->hdr.patch_id); 536 537 uci->cpu_sig.rev = mc_amd->hdr.patch_id; 538 c->microcode = mc_amd->hdr.patch_id; 539 540 return 0; 541 } 542 543 static int install_equiv_cpu_table(const u8 *buf) 544 { 545 unsigned int *ibuf = (unsigned int *)buf; 546 unsigned int type = ibuf[1]; 547 unsigned int size = ibuf[2]; 548 549 if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) { 550 pr_err("empty section/" 551 "invalid type field in container file section header\n"); 552 return -EINVAL; 553 } 554 555 equiv_cpu_table = vmalloc(size); 556 if (!equiv_cpu_table) { 557 pr_err("failed to allocate equivalent CPU table\n"); 558 return -ENOMEM; 559 } 560 561 memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size); 562 563 /* add header length */ 564 return size + CONTAINER_HDR_SZ; 565 } 566 567 static void free_equiv_cpu_table(void) 568 { 569 vfree(equiv_cpu_table); 570 equiv_cpu_table = NULL; 571 } 572 573 static void cleanup(void) 574 { 575 free_equiv_cpu_table(); 576 free_cache(); 577 } 578 579 /* 580 * We return the current size even if some of the checks failed so that 581 * we can skip over the next patch. If we return a negative value, we 582 * signal a grave error like a memory allocation has failed and the 583 * driver cannot continue functioning normally. In such cases, we tear 584 * down everything we've used up so far and exit. 585 */ 586 static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover) 587 { 588 struct microcode_header_amd *mc_hdr; 589 struct ucode_patch *patch; 590 unsigned int patch_size, crnt_size, ret; 591 u32 proc_fam; 592 u16 proc_id; 593 594 patch_size = *(u32 *)(fw + 4); 595 crnt_size = patch_size + SECTION_HDR_SIZE; 596 mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE); 597 proc_id = mc_hdr->processor_rev_id; 598 599 proc_fam = find_cpu_family_by_equiv_cpu(proc_id); 600 if (!proc_fam) { 601 pr_err("No patch family for equiv ID: 0x%04x\n", proc_id); 602 return crnt_size; 603 } 604 605 /* check if patch is for the current family */ 606 proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff); 607 if (proc_fam != family) 608 return crnt_size; 609 610 if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) { 611 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n", 612 mc_hdr->patch_id); 613 return crnt_size; 614 } 615 616 ret = verify_patch_size(family, patch_size, leftover); 617 if (!ret) { 618 pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id); 619 return crnt_size; 620 } 621 622 patch = kzalloc(sizeof(*patch), GFP_KERNEL); 623 if (!patch) { 624 pr_err("Patch allocation failure.\n"); 625 return -EINVAL; 626 } 627 628 patch->data = kmemdup(fw + SECTION_HDR_SIZE, patch_size, GFP_KERNEL); 629 if (!patch->data) { 630 pr_err("Patch data allocation failure.\n"); 631 kfree(patch); 632 return -EINVAL; 633 } 634 635 INIT_LIST_HEAD(&patch->plist); 636 patch->patch_id = mc_hdr->patch_id; 637 patch->equiv_cpu = proc_id; 638 639 pr_debug("%s: Added patch_id: 0x%08x, proc_id: 0x%04x\n", 640 __func__, patch->patch_id, proc_id); 641 642 /* ... and add to cache. */ 643 update_cache(patch); 644 645 return crnt_size; 646 } 647 648 static enum ucode_state __load_microcode_amd(u8 family, const u8 *data, 649 size_t size) 650 { 651 enum ucode_state ret = UCODE_ERROR; 652 unsigned int leftover; 653 u8 *fw = (u8 *)data; 654 int crnt_size = 0; 655 int offset; 656 657 offset = install_equiv_cpu_table(data); 658 if (offset < 0) { 659 pr_err("failed to create equivalent cpu table\n"); 660 return ret; 661 } 662 fw += offset; 663 leftover = size - offset; 664 665 if (*(u32 *)fw != UCODE_UCODE_TYPE) { 666 pr_err("invalid type field in container file section header\n"); 667 free_equiv_cpu_table(); 668 return ret; 669 } 670 671 while (leftover) { 672 crnt_size = verify_and_add_patch(family, fw, leftover); 673 if (crnt_size < 0) 674 return ret; 675 676 fw += crnt_size; 677 leftover -= crnt_size; 678 } 679 680 return UCODE_OK; 681 } 682 683 static enum ucode_state 684 load_microcode_amd(bool save, u8 family, const u8 *data, size_t size) 685 { 686 enum ucode_state ret; 687 688 /* free old equiv table */ 689 free_equiv_cpu_table(); 690 691 ret = __load_microcode_amd(family, data, size); 692 693 if (ret != UCODE_OK) 694 cleanup(); 695 696 #ifdef CONFIG_X86_32 697 /* save BSP's matching patch for early load */ 698 if (save) { 699 struct ucode_patch *p = find_patch(0); 700 if (p) { 701 memset(amd_ucode_patch, 0, PATCH_MAX_SIZE); 702 memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data), 703 PATCH_MAX_SIZE)); 704 } 705 } 706 #endif 707 return ret; 708 } 709 710 /* 711 * AMD microcode firmware naming convention, up to family 15h they are in 712 * the legacy file: 713 * 714 * amd-ucode/microcode_amd.bin 715 * 716 * This legacy file is always smaller than 2K in size. 717 * 718 * Beginning with family 15h, they are in family-specific firmware files: 719 * 720 * amd-ucode/microcode_amd_fam15h.bin 721 * amd-ucode/microcode_amd_fam16h.bin 722 * ... 723 * 724 * These might be larger than 2K. 725 */ 726 static enum ucode_state request_microcode_amd(int cpu, struct device *device, 727 bool refresh_fw) 728 { 729 char fw_name[36] = "amd-ucode/microcode_amd.bin"; 730 struct cpuinfo_x86 *c = &cpu_data(cpu); 731 bool bsp = c->cpu_index == boot_cpu_data.cpu_index; 732 enum ucode_state ret = UCODE_NFOUND; 733 const struct firmware *fw; 734 735 /* reload ucode container only on the boot cpu */ 736 if (!refresh_fw || !bsp) 737 return UCODE_OK; 738 739 if (c->x86 >= 0x15) 740 snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86); 741 742 if (request_firmware_direct(&fw, (const char *)fw_name, device)) { 743 pr_debug("failed to load file %s\n", fw_name); 744 goto out; 745 } 746 747 ret = UCODE_ERROR; 748 if (*(u32 *)fw->data != UCODE_MAGIC) { 749 pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data); 750 goto fw_release; 751 } 752 753 ret = load_microcode_amd(bsp, c->x86, fw->data, fw->size); 754 755 fw_release: 756 release_firmware(fw); 757 758 out: 759 return ret; 760 } 761 762 static enum ucode_state 763 request_microcode_user(int cpu, const void __user *buf, size_t size) 764 { 765 return UCODE_ERROR; 766 } 767 768 static void microcode_fini_cpu_amd(int cpu) 769 { 770 struct ucode_cpu_info *uci = ucode_cpu_info + cpu; 771 772 uci->mc = NULL; 773 } 774 775 static struct microcode_ops microcode_amd_ops = { 776 .request_microcode_user = request_microcode_user, 777 .request_microcode_fw = request_microcode_amd, 778 .collect_cpu_info = collect_cpu_info_amd, 779 .apply_microcode = apply_microcode_amd, 780 .microcode_fini_cpu = microcode_fini_cpu_amd, 781 }; 782 783 struct microcode_ops * __init init_amd_microcode(void) 784 { 785 struct cpuinfo_x86 *c = &boot_cpu_data; 786 787 if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { 788 pr_warn("AMD CPU family 0x%x not supported\n", c->x86); 789 return NULL; 790 } 791 792 if (ucode_new_rev) 793 pr_info_once("microcode updated early to new patch_level=0x%08x\n", 794 ucode_new_rev); 795 796 return µcode_amd_ops; 797 } 798 799 void __exit exit_amd_microcode(void) 800 { 801 cleanup(); 802 } 803