1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MCE grading rules. 4 * Copyright 2008, 2009 Intel Corporation. 5 * 6 * Author: Andi Kleen 7 */ 8 #include <linux/kernel.h> 9 #include <linux/seq_file.h> 10 #include <linux/init.h> 11 #include <linux/debugfs.h> 12 #include <linux/uaccess.h> 13 14 #include <asm/mce.h> 15 #include <asm/intel-family.h> 16 #include <asm/traps.h> 17 #include <asm/insn.h> 18 #include <asm/insn-eval.h> 19 20 #include "internal.h" 21 22 /* 23 * Grade an mce by severity. In general the most severe ones are processed 24 * first. Since there are quite a lot of combinations test the bits in a 25 * table-driven way. The rules are simply processed in order, first 26 * match wins. 27 * 28 * Note this is only used for machine check exceptions, the corrected 29 * errors use much simpler rules. The exceptions still check for the corrected 30 * errors, but only to leave them alone for the CMCI handler (except for 31 * panic situations) 32 */ 33 34 enum context { IN_KERNEL = 1, IN_USER = 2, IN_KERNEL_RECOV = 3 }; 35 enum ser { SER_REQUIRED = 1, NO_SER = 2 }; 36 enum exception { EXCP_CONTEXT = 1, NO_EXCP = 2 }; 37 38 static struct severity { 39 u64 mask; 40 u64 result; 41 unsigned char sev; 42 unsigned char mcgmask; 43 unsigned char mcgres; 44 unsigned char ser; 45 unsigned char context; 46 unsigned char excp; 47 unsigned char covered; 48 unsigned char cpu_model; 49 unsigned char cpu_minstepping; 50 unsigned char bank_lo, bank_hi; 51 char *msg; 52 } severities[] = { 53 #define MCESEV(s, m, c...) { .sev = MCE_ ## s ## _SEVERITY, .msg = m, ## c } 54 #define BANK_RANGE(l, h) .bank_lo = l, .bank_hi = h 55 #define MODEL_STEPPING(m, s) .cpu_model = m, .cpu_minstepping = s 56 #define KERNEL .context = IN_KERNEL 57 #define USER .context = IN_USER 58 #define KERNEL_RECOV .context = IN_KERNEL_RECOV 59 #define SER .ser = SER_REQUIRED 60 #define NOSER .ser = NO_SER 61 #define EXCP .excp = EXCP_CONTEXT 62 #define NOEXCP .excp = NO_EXCP 63 #define BITCLR(x) .mask = x, .result = 0 64 #define BITSET(x) .mask = x, .result = x 65 #define MCGMASK(x, y) .mcgmask = x, .mcgres = y 66 #define MASK(x, y) .mask = x, .result = y 67 #define MCI_UC_S (MCI_STATUS_UC|MCI_STATUS_S) 68 #define MCI_UC_AR (MCI_STATUS_UC|MCI_STATUS_AR) 69 #define MCI_UC_SAR (MCI_STATUS_UC|MCI_STATUS_S|MCI_STATUS_AR) 70 #define MCI_ADDR (MCI_STATUS_ADDRV|MCI_STATUS_MISCV) 71 72 MCESEV( 73 NO, "Invalid", 74 BITCLR(MCI_STATUS_VAL) 75 ), 76 MCESEV( 77 NO, "Not enabled", 78 EXCP, BITCLR(MCI_STATUS_EN) 79 ), 80 MCESEV( 81 PANIC, "Processor context corrupt", 82 BITSET(MCI_STATUS_PCC) 83 ), 84 /* When MCIP is not set something is very confused */ 85 MCESEV( 86 PANIC, "MCIP not set in MCA handler", 87 EXCP, MCGMASK(MCG_STATUS_MCIP, 0) 88 ), 89 /* Neither return not error IP -- no chance to recover -> PANIC */ 90 MCESEV( 91 PANIC, "Neither restart nor error IP", 92 EXCP, MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0) 93 ), 94 MCESEV( 95 PANIC, "In kernel and no restart IP", 96 EXCP, KERNEL, MCGMASK(MCG_STATUS_RIPV, 0) 97 ), 98 MCESEV( 99 PANIC, "In kernel and no restart IP", 100 EXCP, KERNEL_RECOV, MCGMASK(MCG_STATUS_RIPV, 0) 101 ), 102 MCESEV( 103 KEEP, "Corrected error", 104 NOSER, BITCLR(MCI_STATUS_UC) 105 ), 106 /* 107 * known AO MCACODs reported via MCE or CMC: 108 * 109 * SRAO could be signaled either via a machine check exception or 110 * CMCI with the corresponding bit S 1 or 0. So we don't need to 111 * check bit S for SRAO. 112 */ 113 MCESEV( 114 AO, "Action optional: memory scrubbing error", 115 SER, MASK(MCI_UC_AR|MCACOD_SCRUBMSK, MCI_STATUS_UC|MCACOD_SCRUB) 116 ), 117 MCESEV( 118 AO, "Action optional: last level cache writeback error", 119 SER, MASK(MCI_UC_AR|MCACOD, MCI_STATUS_UC|MCACOD_L3WB) 120 ), 121 /* 122 * Quirk for Skylake/Cascade Lake. Patrol scrubber may be configured 123 * to report uncorrected errors using CMCI with a special signature. 124 * UC=0, MSCOD=0x0010, MCACOD=binary(000X 0000 1100 XXXX) reported 125 * in one of the memory controller banks. 126 * Set severity to "AO" for same action as normal patrol scrub error. 127 */ 128 MCESEV( 129 AO, "Uncorrected Patrol Scrub Error", 130 SER, MASK(MCI_STATUS_UC|MCI_ADDR|0xffffeff0, MCI_ADDR|0x001000c0), 131 MODEL_STEPPING(INTEL_FAM6_SKYLAKE_X, 4), BANK_RANGE(13, 18) 132 ), 133 134 /* ignore OVER for UCNA */ 135 MCESEV( 136 UCNA, "Uncorrected no action required", 137 SER, MASK(MCI_UC_SAR, MCI_STATUS_UC) 138 ), 139 MCESEV( 140 PANIC, "Illegal combination (UCNA with AR=1)", 141 SER, 142 MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR) 143 ), 144 MCESEV( 145 KEEP, "Non signaled machine check", 146 SER, BITCLR(MCI_STATUS_S) 147 ), 148 149 MCESEV( 150 PANIC, "Action required with lost events", 151 SER, BITSET(MCI_STATUS_OVER|MCI_UC_SAR) 152 ), 153 154 /* known AR MCACODs: */ 155 #ifdef CONFIG_MEMORY_FAILURE 156 MCESEV( 157 KEEP, "Action required but unaffected thread is continuable", 158 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR, MCI_UC_SAR|MCI_ADDR), 159 MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, MCG_STATUS_RIPV) 160 ), 161 MCESEV( 162 AR, "Action required: data load in error recoverable area of kernel", 163 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA), 164 KERNEL_RECOV 165 ), 166 MCESEV( 167 AR, "Action required: data load error in a user process", 168 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA), 169 USER 170 ), 171 MCESEV( 172 AR, "Action required: instruction fetch error in a user process", 173 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR), 174 USER 175 ), 176 MCESEV( 177 PANIC, "Data load in unrecoverable area of kernel", 178 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA), 179 KERNEL 180 ), 181 MCESEV( 182 PANIC, "Instruction fetch error in kernel", 183 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR), 184 KERNEL 185 ), 186 #endif 187 MCESEV( 188 PANIC, "Action required: unknown MCACOD", 189 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_SAR) 190 ), 191 192 MCESEV( 193 SOME, "Action optional: unknown MCACOD", 194 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_S) 195 ), 196 MCESEV( 197 SOME, "Action optional with lost events", 198 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_OVER|MCI_UC_S) 199 ), 200 201 MCESEV( 202 PANIC, "Overflowed uncorrected", 203 BITSET(MCI_STATUS_OVER|MCI_STATUS_UC) 204 ), 205 MCESEV( 206 UC, "Uncorrected", 207 BITSET(MCI_STATUS_UC) 208 ), 209 MCESEV( 210 SOME, "No match", 211 BITSET(0) 212 ) /* always matches. keep at end */ 213 }; 214 215 #define mc_recoverable(mcg) (((mcg) & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) == \ 216 (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) 217 218 static bool is_copy_from_user(struct pt_regs *regs) 219 { 220 u8 insn_buf[MAX_INSN_SIZE]; 221 unsigned long addr; 222 struct insn insn; 223 int ret; 224 225 if (!regs) 226 return false; 227 228 if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip, MAX_INSN_SIZE)) 229 return false; 230 231 ret = insn_decode_kernel(&insn, insn_buf); 232 if (ret < 0) 233 return false; 234 235 switch (insn.opcode.value) { 236 /* MOV mem,reg */ 237 case 0x8A: case 0x8B: 238 /* MOVZ mem,reg */ 239 case 0xB60F: case 0xB70F: 240 addr = (unsigned long)insn_get_addr_ref(&insn, regs); 241 break; 242 /* REP MOVS */ 243 case 0xA4: case 0xA5: 244 addr = regs->si; 245 break; 246 default: 247 return false; 248 } 249 250 if (fault_in_kernel_space(addr)) 251 return false; 252 253 current->mce_vaddr = (void __user *)addr; 254 255 return true; 256 } 257 258 /* 259 * If mcgstatus indicated that ip/cs on the stack were 260 * no good, then "m->cs" will be zero and we will have 261 * to assume the worst case (IN_KERNEL) as we actually 262 * have no idea what we were executing when the machine 263 * check hit. 264 * If we do have a good "m->cs" (or a faked one in the 265 * case we were executing in VM86 mode) we can use it to 266 * distinguish an exception taken in user from from one 267 * taken in the kernel. 268 */ 269 static noinstr int error_context(struct mce *m, struct pt_regs *regs) 270 { 271 int fixup_type; 272 bool copy_user; 273 274 if ((m->cs & 3) == 3) 275 return IN_USER; 276 277 if (!mc_recoverable(m->mcgstatus)) 278 return IN_KERNEL; 279 280 /* Allow instrumentation around external facilities usage. */ 281 instrumentation_begin(); 282 fixup_type = ex_get_fixup_type(m->ip); 283 copy_user = is_copy_from_user(regs); 284 instrumentation_end(); 285 286 switch (fixup_type) { 287 case EX_TYPE_UACCESS: 288 case EX_TYPE_COPY: 289 if (!copy_user) 290 return IN_KERNEL; 291 m->kflags |= MCE_IN_KERNEL_COPYIN; 292 fallthrough; 293 294 case EX_TYPE_FAULT_MCE_SAFE: 295 case EX_TYPE_DEFAULT_MCE_SAFE: 296 m->kflags |= MCE_IN_KERNEL_RECOV; 297 return IN_KERNEL_RECOV; 298 299 default: 300 return IN_KERNEL; 301 } 302 } 303 304 /* See AMD PPR(s) section Machine Check Error Handling. */ 305 static noinstr int mce_severity_amd(struct mce *m, struct pt_regs *regs, char **msg, bool is_excp) 306 { 307 int ret; 308 309 /* 310 * Default return value: Action required, the error must be handled 311 * immediately. 312 */ 313 ret = MCE_AR_SEVERITY; 314 315 /* Processor Context Corrupt, no need to fumble too much, die! */ 316 if (m->status & MCI_STATUS_PCC) { 317 ret = MCE_PANIC_SEVERITY; 318 goto out; 319 } 320 321 if (m->status & MCI_STATUS_DEFERRED) { 322 ret = MCE_DEFERRED_SEVERITY; 323 goto out; 324 } 325 326 /* 327 * If the UC bit is not set, the system either corrected or deferred 328 * the error. No action will be required after logging the error. 329 */ 330 if (!(m->status & MCI_STATUS_UC)) { 331 ret = MCE_KEEP_SEVERITY; 332 goto out; 333 } 334 335 /* 336 * On MCA overflow, without the MCA overflow recovery feature the 337 * system will not be able to recover, panic. 338 */ 339 if ((m->status & MCI_STATUS_OVER) && !mce_flags.overflow_recov) { 340 ret = MCE_PANIC_SEVERITY; 341 goto out; 342 } 343 344 if (!mce_flags.succor) { 345 ret = MCE_PANIC_SEVERITY; 346 goto out; 347 } 348 349 if (error_context(m, regs) == IN_KERNEL) 350 ret = MCE_PANIC_SEVERITY; 351 352 out: 353 return ret; 354 } 355 356 static noinstr int mce_severity_intel(struct mce *m, struct pt_regs *regs, char **msg, bool is_excp) 357 { 358 enum exception excp = (is_excp ? EXCP_CONTEXT : NO_EXCP); 359 enum context ctx = error_context(m, regs); 360 struct severity *s; 361 362 for (s = severities;; s++) { 363 if ((m->status & s->mask) != s->result) 364 continue; 365 if ((m->mcgstatus & s->mcgmask) != s->mcgres) 366 continue; 367 if (s->ser == SER_REQUIRED && !mca_cfg.ser) 368 continue; 369 if (s->ser == NO_SER && mca_cfg.ser) 370 continue; 371 if (s->context && ctx != s->context) 372 continue; 373 if (s->excp && excp != s->excp) 374 continue; 375 if (s->cpu_model && boot_cpu_data.x86_model != s->cpu_model) 376 continue; 377 if (s->cpu_minstepping && boot_cpu_data.x86_stepping < s->cpu_minstepping) 378 continue; 379 if (s->bank_lo && (m->bank < s->bank_lo || m->bank > s->bank_hi)) 380 continue; 381 if (msg) 382 *msg = s->msg; 383 s->covered = 1; 384 385 if (s->sev >= MCE_UC_SEVERITY && ctx == IN_KERNEL) 386 return MCE_PANIC_SEVERITY; 387 388 return s->sev; 389 } 390 } 391 392 int noinstr mce_severity(struct mce *m, struct pt_regs *regs, char **msg, bool is_excp) 393 { 394 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 395 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 396 return mce_severity_amd(m, regs, msg, is_excp); 397 else 398 return mce_severity_intel(m, regs, msg, is_excp); 399 } 400 401 #ifdef CONFIG_DEBUG_FS 402 static void *s_start(struct seq_file *f, loff_t *pos) 403 { 404 if (*pos >= ARRAY_SIZE(severities)) 405 return NULL; 406 return &severities[*pos]; 407 } 408 409 static void *s_next(struct seq_file *f, void *data, loff_t *pos) 410 { 411 if (++(*pos) >= ARRAY_SIZE(severities)) 412 return NULL; 413 return &severities[*pos]; 414 } 415 416 static void s_stop(struct seq_file *f, void *data) 417 { 418 } 419 420 static int s_show(struct seq_file *f, void *data) 421 { 422 struct severity *ser = data; 423 seq_printf(f, "%d\t%s\n", ser->covered, ser->msg); 424 return 0; 425 } 426 427 static const struct seq_operations severities_seq_ops = { 428 .start = s_start, 429 .next = s_next, 430 .stop = s_stop, 431 .show = s_show, 432 }; 433 434 static int severities_coverage_open(struct inode *inode, struct file *file) 435 { 436 return seq_open(file, &severities_seq_ops); 437 } 438 439 static ssize_t severities_coverage_write(struct file *file, 440 const char __user *ubuf, 441 size_t count, loff_t *ppos) 442 { 443 int i; 444 for (i = 0; i < ARRAY_SIZE(severities); i++) 445 severities[i].covered = 0; 446 return count; 447 } 448 449 static const struct file_operations severities_coverage_fops = { 450 .open = severities_coverage_open, 451 .release = seq_release, 452 .read = seq_read, 453 .write = severities_coverage_write, 454 .llseek = seq_lseek, 455 }; 456 457 static int __init severities_debugfs_init(void) 458 { 459 struct dentry *dmce; 460 461 dmce = mce_get_debugfs_dir(); 462 463 debugfs_create_file("severities-coverage", 0444, dmce, NULL, 464 &severities_coverage_fops); 465 return 0; 466 } 467 late_initcall(severities_debugfs_init); 468 #endif /* CONFIG_DEBUG_FS */ 469