1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * P5 specific Machine Check Exception Reporting 4 * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk> 5 */ 6 #include <linux/interrupt.h> 7 #include <linux/kernel.h> 8 #include <linux/types.h> 9 #include <linux/smp.h> 10 #include <linux/hardirq.h> 11 12 #include <asm/processor.h> 13 #include <asm/traps.h> 14 #include <asm/tlbflush.h> 15 #include <asm/mce.h> 16 #include <asm/msr.h> 17 18 #include "internal.h" 19 20 /* By default disabled */ 21 int mce_p5_enabled __read_mostly; 22 23 /* Machine check handler for Pentium class Intel CPUs: */ 24 static void pentium_machine_check(struct pt_regs *regs, long error_code) 25 { 26 u32 loaddr, hi, lotype; 27 28 nmi_enter(); 29 30 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); 31 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); 32 33 pr_emerg("CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", 34 smp_processor_id(), loaddr, lotype); 35 36 if (lotype & (1<<5)) { 37 pr_emerg("CPU#%d: Possible thermal failure (CPU on fire ?).\n", 38 smp_processor_id()); 39 } 40 41 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 42 43 nmi_exit(); 44 } 45 46 /* Set up machine check reporting for processors with Intel style MCE: */ 47 void intel_p5_mcheck_init(struct cpuinfo_x86 *c) 48 { 49 u32 l, h; 50 51 /* Default P5 to off as its often misconnected: */ 52 if (!mce_p5_enabled) 53 return; 54 55 /* Check for MCE support: */ 56 if (!cpu_has(c, X86_FEATURE_MCE)) 57 return; 58 59 machine_check_vector = pentium_machine_check; 60 /* Make sure the vector pointer is visible before we enable MCEs: */ 61 wmb(); 62 63 /* Read registers before enabling: */ 64 rdmsr(MSR_IA32_P5_MC_ADDR, l, h); 65 rdmsr(MSR_IA32_P5_MC_TYPE, l, h); 66 pr_info("Intel old style machine check architecture supported.\n"); 67 68 /* Enable MCE: */ 69 cr4_set_bits(X86_CR4_MCE); 70 pr_info("Intel old style machine check reporting enabled on CPU#%d.\n", 71 smp_processor_id()); 72 } 73