1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __X86_MCE_INTERNAL_H__ 3 #define __X86_MCE_INTERNAL_H__ 4 5 #undef pr_fmt 6 #define pr_fmt(fmt) "mce: " fmt 7 8 #include <linux/device.h> 9 #include <asm/mce.h> 10 11 /* Pointer to the installed machine check handler for this CPU setup. */ 12 extern void (*machine_check_vector)(struct pt_regs *, long error_code); 13 14 enum severity_level { 15 MCE_NO_SEVERITY, 16 MCE_DEFERRED_SEVERITY, 17 MCE_UCNA_SEVERITY = MCE_DEFERRED_SEVERITY, 18 MCE_KEEP_SEVERITY, 19 MCE_SOME_SEVERITY, 20 MCE_AO_SEVERITY, 21 MCE_UC_SEVERITY, 22 MCE_AR_SEVERITY, 23 MCE_PANIC_SEVERITY, 24 }; 25 26 extern struct blocking_notifier_head x86_mce_decoder_chain; 27 28 #define INITIAL_CHECK_INTERVAL 5 * 60 /* 5 minutes */ 29 30 struct mce_evt_llist { 31 struct llist_node llnode; 32 struct mce mce; 33 }; 34 35 void mce_gen_pool_process(struct work_struct *__unused); 36 bool mce_gen_pool_empty(void); 37 int mce_gen_pool_add(struct mce *mce); 38 int mce_gen_pool_init(void); 39 struct llist_node *mce_gen_pool_prepare_records(void); 40 41 extern int (*mce_severity)(struct mce *a, int tolerant, char **msg, bool is_excp); 42 struct dentry *mce_get_debugfs_dir(void); 43 44 extern mce_banks_t mce_banks_ce_disabled; 45 46 #ifdef CONFIG_X86_MCE_INTEL 47 unsigned long cmci_intel_adjust_timer(unsigned long interval); 48 bool mce_intel_cmci_poll(void); 49 void mce_intel_hcpu_update(unsigned long cpu); 50 void cmci_disable_bank(int bank); 51 void intel_init_cmci(void); 52 void intel_init_lmce(void); 53 void intel_clear_lmce(void); 54 bool intel_filter_mce(struct mce *m); 55 #else 56 # define cmci_intel_adjust_timer mce_adjust_timer_default 57 static inline bool mce_intel_cmci_poll(void) { return false; } 58 static inline void mce_intel_hcpu_update(unsigned long cpu) { } 59 static inline void cmci_disable_bank(int bank) { } 60 static inline void intel_init_cmci(void) { } 61 static inline void intel_init_lmce(void) { } 62 static inline void intel_clear_lmce(void) { } 63 static inline bool intel_filter_mce(struct mce *m) { return false; }; 64 #endif 65 66 void mce_timer_kick(unsigned long interval); 67 68 #ifdef CONFIG_ACPI_APEI 69 int apei_write_mce(struct mce *m); 70 ssize_t apei_read_mce(struct mce *m, u64 *record_id); 71 int apei_check_mce(void); 72 int apei_clear_mce(u64 record_id); 73 #else 74 static inline int apei_write_mce(struct mce *m) 75 { 76 return -EINVAL; 77 } 78 static inline ssize_t apei_read_mce(struct mce *m, u64 *record_id) 79 { 80 return 0; 81 } 82 static inline int apei_check_mce(void) 83 { 84 return 0; 85 } 86 static inline int apei_clear_mce(u64 record_id) 87 { 88 return -EINVAL; 89 } 90 #endif 91 92 /* 93 * We consider records to be equivalent if bank+status+addr+misc all match. 94 * This is only used when the system is going down because of a fatal error 95 * to avoid cluttering the console log with essentially repeated information. 96 * In normal processing all errors seen are logged. 97 */ 98 static inline bool mce_cmp(struct mce *m1, struct mce *m2) 99 { 100 return m1->bank != m2->bank || 101 m1->status != m2->status || 102 m1->addr != m2->addr || 103 m1->misc != m2->misc; 104 } 105 106 extern struct device_attribute dev_attr_trigger; 107 108 #ifdef CONFIG_X86_MCELOG_LEGACY 109 void mce_work_trigger(void); 110 void mce_register_injector_chain(struct notifier_block *nb); 111 void mce_unregister_injector_chain(struct notifier_block *nb); 112 #else 113 static inline void mce_work_trigger(void) { } 114 static inline void mce_register_injector_chain(struct notifier_block *nb) { } 115 static inline void mce_unregister_injector_chain(struct notifier_block *nb) { } 116 #endif 117 118 struct mca_config { 119 bool dont_log_ce; 120 bool cmci_disabled; 121 bool ignore_ce; 122 123 __u64 lmce_disabled : 1, 124 disabled : 1, 125 ser : 1, 126 recovery : 1, 127 bios_cmci_threshold : 1, 128 __reserved : 59; 129 130 s8 bootlog; 131 int tolerant; 132 int monarch_timeout; 133 int panic_timeout; 134 u32 rip_msr; 135 }; 136 137 extern struct mca_config mca_cfg; 138 DECLARE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks); 139 140 struct mce_vendor_flags { 141 /* 142 * Indicates that overflow conditions are not fatal, when set. 143 */ 144 __u64 overflow_recov : 1, 145 146 /* 147 * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and 148 * Recovery. It indicates support for data poisoning in HW and deferred 149 * error interrupts. 150 */ 151 succor : 1, 152 153 /* 154 * (AMD) SMCA: This bit indicates support for Scalable MCA which expands 155 * the register space for each MCA bank and also increases number of 156 * banks. Also, to accommodate the new banks and registers, the MCA 157 * register space is moved to a new MSR range. 158 */ 159 smca : 1, 160 161 __reserved_0 : 61; 162 }; 163 164 extern struct mce_vendor_flags mce_flags; 165 166 struct mca_msr_regs { 167 u32 (*ctl) (int bank); 168 u32 (*status) (int bank); 169 u32 (*addr) (int bank); 170 u32 (*misc) (int bank); 171 }; 172 173 extern struct mca_msr_regs msr_ops; 174 175 /* Decide whether to add MCE record to MCE event pool or filter it out. */ 176 extern bool filter_mce(struct mce *m); 177 178 #ifdef CONFIG_X86_MCE_AMD 179 extern bool amd_filter_mce(struct mce *m); 180 #else 181 static inline bool amd_filter_mce(struct mce *m) { return false; }; 182 #endif 183 184 #endif /* __X86_MCE_INTERNAL_H__ */ 185