1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Machine check handler. 4 * 5 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. 6 * Rest from unknown author(s). 7 * 2004 Andi Kleen. Rewrote most of it. 8 * Copyright 2008 Intel Corporation 9 * Author: Andi Kleen 10 */ 11 12 #include <linux/thread_info.h> 13 #include <linux/capability.h> 14 #include <linux/miscdevice.h> 15 #include <linux/ratelimit.h> 16 #include <linux/rcupdate.h> 17 #include <linux/kobject.h> 18 #include <linux/uaccess.h> 19 #include <linux/kdebug.h> 20 #include <linux/kernel.h> 21 #include <linux/percpu.h> 22 #include <linux/string.h> 23 #include <linux/device.h> 24 #include <linux/syscore_ops.h> 25 #include <linux/delay.h> 26 #include <linux/ctype.h> 27 #include <linux/sched.h> 28 #include <linux/sysfs.h> 29 #include <linux/types.h> 30 #include <linux/slab.h> 31 #include <linux/init.h> 32 #include <linux/kmod.h> 33 #include <linux/poll.h> 34 #include <linux/nmi.h> 35 #include <linux/cpu.h> 36 #include <linux/ras.h> 37 #include <linux/smp.h> 38 #include <linux/fs.h> 39 #include <linux/mm.h> 40 #include <linux/debugfs.h> 41 #include <linux/irq_work.h> 42 #include <linux/export.h> 43 #include <linux/set_memory.h> 44 #include <linux/sync_core.h> 45 #include <linux/task_work.h> 46 #include <linux/hardirq.h> 47 48 #include <asm/intel-family.h> 49 #include <asm/processor.h> 50 #include <asm/traps.h> 51 #include <asm/tlbflush.h> 52 #include <asm/mce.h> 53 #include <asm/msr.h> 54 #include <asm/reboot.h> 55 56 #include "internal.h" 57 58 /* sysfs synchronization */ 59 static DEFINE_MUTEX(mce_sysfs_mutex); 60 61 #define CREATE_TRACE_POINTS 62 #include <trace/events/mce.h> 63 64 #define SPINUNIT 100 /* 100ns */ 65 66 DEFINE_PER_CPU(unsigned, mce_exception_count); 67 68 DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks); 69 70 struct mce_bank { 71 u64 ctl; /* subevents to enable */ 72 bool init; /* initialise bank? */ 73 }; 74 static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); 75 76 #define ATTR_LEN 16 77 /* One object for each MCE bank, shared by all CPUs */ 78 struct mce_bank_dev { 79 struct device_attribute attr; /* device attribute */ 80 char attrname[ATTR_LEN]; /* attribute name */ 81 u8 bank; /* bank number */ 82 }; 83 static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS]; 84 85 struct mce_vendor_flags mce_flags __read_mostly; 86 87 struct mca_config mca_cfg __read_mostly = { 88 .bootlog = -1, 89 /* 90 * Tolerant levels: 91 * 0: always panic on uncorrected errors, log corrected errors 92 * 1: panic or SIGBUS on uncorrected errors, log corrected errors 93 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors 94 * 3: never panic or SIGBUS, log all errors (for testing only) 95 */ 96 .tolerant = 1, 97 .monarch_timeout = -1 98 }; 99 100 static DEFINE_PER_CPU(struct mce, mces_seen); 101 static unsigned long mce_need_notify; 102 static int cpu_missing; 103 104 /* 105 * MCA banks polled by the period polling timer for corrected events. 106 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). 107 */ 108 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { 109 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL 110 }; 111 112 /* 113 * MCA banks controlled through firmware first for corrected errors. 114 * This is a global list of banks for which we won't enable CMCI and we 115 * won't poll. Firmware controls these banks and is responsible for 116 * reporting corrected errors through GHES. Uncorrected/recoverable 117 * errors are still notified through a machine check. 118 */ 119 mce_banks_t mce_banks_ce_disabled; 120 121 static struct work_struct mce_work; 122 static struct irq_work mce_irq_work; 123 124 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); 125 126 /* 127 * CPU/chipset specific EDAC code can register a notifier call here to print 128 * MCE errors in a human-readable form. 129 */ 130 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); 131 132 /* Do initial initialization of a struct mce */ 133 noinstr void mce_setup(struct mce *m) 134 { 135 memset(m, 0, sizeof(struct mce)); 136 m->cpu = m->extcpu = smp_processor_id(); 137 /* need the internal __ version to avoid deadlocks */ 138 m->time = __ktime_get_real_seconds(); 139 m->cpuvendor = boot_cpu_data.x86_vendor; 140 m->cpuid = cpuid_eax(1); 141 m->socketid = cpu_data(m->extcpu).phys_proc_id; 142 m->apicid = cpu_data(m->extcpu).initial_apicid; 143 m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); 144 145 if (this_cpu_has(X86_FEATURE_INTEL_PPIN)) 146 m->ppin = __rdmsr(MSR_PPIN); 147 else if (this_cpu_has(X86_FEATURE_AMD_PPIN)) 148 m->ppin = __rdmsr(MSR_AMD_PPIN); 149 150 m->microcode = boot_cpu_data.microcode; 151 } 152 153 DEFINE_PER_CPU(struct mce, injectm); 154 EXPORT_PER_CPU_SYMBOL_GPL(injectm); 155 156 void mce_log(struct mce *m) 157 { 158 if (!mce_gen_pool_add(m)) 159 irq_work_queue(&mce_irq_work); 160 } 161 EXPORT_SYMBOL_GPL(mce_log); 162 163 void mce_register_decode_chain(struct notifier_block *nb) 164 { 165 if (WARN_ON(nb->priority < MCE_PRIO_LOWEST || 166 nb->priority > MCE_PRIO_HIGHEST)) 167 return; 168 169 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb); 170 } 171 EXPORT_SYMBOL_GPL(mce_register_decode_chain); 172 173 void mce_unregister_decode_chain(struct notifier_block *nb) 174 { 175 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb); 176 } 177 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); 178 179 static inline u32 ctl_reg(int bank) 180 { 181 return MSR_IA32_MCx_CTL(bank); 182 } 183 184 static inline u32 status_reg(int bank) 185 { 186 return MSR_IA32_MCx_STATUS(bank); 187 } 188 189 static inline u32 addr_reg(int bank) 190 { 191 return MSR_IA32_MCx_ADDR(bank); 192 } 193 194 static inline u32 misc_reg(int bank) 195 { 196 return MSR_IA32_MCx_MISC(bank); 197 } 198 199 static inline u32 smca_ctl_reg(int bank) 200 { 201 return MSR_AMD64_SMCA_MCx_CTL(bank); 202 } 203 204 static inline u32 smca_status_reg(int bank) 205 { 206 return MSR_AMD64_SMCA_MCx_STATUS(bank); 207 } 208 209 static inline u32 smca_addr_reg(int bank) 210 { 211 return MSR_AMD64_SMCA_MCx_ADDR(bank); 212 } 213 214 static inline u32 smca_misc_reg(int bank) 215 { 216 return MSR_AMD64_SMCA_MCx_MISC(bank); 217 } 218 219 struct mca_msr_regs msr_ops = { 220 .ctl = ctl_reg, 221 .status = status_reg, 222 .addr = addr_reg, 223 .misc = misc_reg 224 }; 225 226 static void __print_mce(struct mce *m) 227 { 228 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", 229 m->extcpu, 230 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""), 231 m->mcgstatus, m->bank, m->status); 232 233 if (m->ip) { 234 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", 235 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", 236 m->cs, m->ip); 237 238 if (m->cs == __KERNEL_CS) 239 pr_cont("{%pS}", (void *)(unsigned long)m->ip); 240 pr_cont("\n"); 241 } 242 243 pr_emerg(HW_ERR "TSC %llx ", m->tsc); 244 if (m->addr) 245 pr_cont("ADDR %llx ", m->addr); 246 if (m->misc) 247 pr_cont("MISC %llx ", m->misc); 248 if (m->ppin) 249 pr_cont("PPIN %llx ", m->ppin); 250 251 if (mce_flags.smca) { 252 if (m->synd) 253 pr_cont("SYND %llx ", m->synd); 254 if (m->ipid) 255 pr_cont("IPID %llx ", m->ipid); 256 } 257 258 pr_cont("\n"); 259 260 /* 261 * Note this output is parsed by external tools and old fields 262 * should not be changed. 263 */ 264 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", 265 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, 266 m->microcode); 267 } 268 269 static void print_mce(struct mce *m) 270 { 271 __print_mce(m); 272 273 if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON) 274 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); 275 } 276 277 #define PANIC_TIMEOUT 5 /* 5 seconds */ 278 279 static atomic_t mce_panicked; 280 281 static int fake_panic; 282 static atomic_t mce_fake_panicked; 283 284 /* Panic in progress. Enable interrupts and wait for final IPI */ 285 static void wait_for_panic(void) 286 { 287 long timeout = PANIC_TIMEOUT*USEC_PER_SEC; 288 289 preempt_disable(); 290 local_irq_enable(); 291 while (timeout-- > 0) 292 udelay(1); 293 if (panic_timeout == 0) 294 panic_timeout = mca_cfg.panic_timeout; 295 panic("Panicing machine check CPU died"); 296 } 297 298 static void mce_panic(const char *msg, struct mce *final, char *exp) 299 { 300 int apei_err = 0; 301 struct llist_node *pending; 302 struct mce_evt_llist *l; 303 304 if (!fake_panic) { 305 /* 306 * Make sure only one CPU runs in machine check panic 307 */ 308 if (atomic_inc_return(&mce_panicked) > 1) 309 wait_for_panic(); 310 barrier(); 311 312 bust_spinlocks(1); 313 console_verbose(); 314 } else { 315 /* Don't log too much for fake panic */ 316 if (atomic_inc_return(&mce_fake_panicked) > 1) 317 return; 318 } 319 pending = mce_gen_pool_prepare_records(); 320 /* First print corrected ones that are still unlogged */ 321 llist_for_each_entry(l, pending, llnode) { 322 struct mce *m = &l->mce; 323 if (!(m->status & MCI_STATUS_UC)) { 324 print_mce(m); 325 if (!apei_err) 326 apei_err = apei_write_mce(m); 327 } 328 } 329 /* Now print uncorrected but with the final one last */ 330 llist_for_each_entry(l, pending, llnode) { 331 struct mce *m = &l->mce; 332 if (!(m->status & MCI_STATUS_UC)) 333 continue; 334 if (!final || mce_cmp(m, final)) { 335 print_mce(m); 336 if (!apei_err) 337 apei_err = apei_write_mce(m); 338 } 339 } 340 if (final) { 341 print_mce(final); 342 if (!apei_err) 343 apei_err = apei_write_mce(final); 344 } 345 if (cpu_missing) 346 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); 347 if (exp) 348 pr_emerg(HW_ERR "Machine check: %s\n", exp); 349 if (!fake_panic) { 350 if (panic_timeout == 0) 351 panic_timeout = mca_cfg.panic_timeout; 352 panic(msg); 353 } else 354 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); 355 } 356 357 /* Support code for software error injection */ 358 359 static int msr_to_offset(u32 msr) 360 { 361 unsigned bank = __this_cpu_read(injectm.bank); 362 363 if (msr == mca_cfg.rip_msr) 364 return offsetof(struct mce, ip); 365 if (msr == msr_ops.status(bank)) 366 return offsetof(struct mce, status); 367 if (msr == msr_ops.addr(bank)) 368 return offsetof(struct mce, addr); 369 if (msr == msr_ops.misc(bank)) 370 return offsetof(struct mce, misc); 371 if (msr == MSR_IA32_MCG_STATUS) 372 return offsetof(struct mce, mcgstatus); 373 return -1; 374 } 375 376 __visible bool ex_handler_rdmsr_fault(const struct exception_table_entry *fixup, 377 struct pt_regs *regs, int trapnr, 378 unsigned long error_code, 379 unsigned long fault_addr) 380 { 381 pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n", 382 (unsigned int)regs->cx, regs->ip, (void *)regs->ip); 383 384 show_stack_regs(regs); 385 386 panic("MCA architectural violation!\n"); 387 388 while (true) 389 cpu_relax(); 390 391 return true; 392 } 393 394 /* MSR access wrappers used for error injection */ 395 static noinstr u64 mce_rdmsrl(u32 msr) 396 { 397 DECLARE_ARGS(val, low, high); 398 399 if (__this_cpu_read(injectm.finished)) { 400 int offset; 401 u64 ret; 402 403 instrumentation_begin(); 404 405 offset = msr_to_offset(msr); 406 if (offset < 0) 407 ret = 0; 408 else 409 ret = *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); 410 411 instrumentation_end(); 412 413 return ret; 414 } 415 416 /* 417 * RDMSR on MCA MSRs should not fault. If they do, this is very much an 418 * architectural violation and needs to be reported to hw vendor. Panic 419 * the box to not allow any further progress. 420 */ 421 asm volatile("1: rdmsr\n" 422 "2:\n" 423 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_rdmsr_fault) 424 : EAX_EDX_RET(val, low, high) : "c" (msr)); 425 426 427 return EAX_EDX_VAL(val, low, high); 428 } 429 430 __visible bool ex_handler_wrmsr_fault(const struct exception_table_entry *fixup, 431 struct pt_regs *regs, int trapnr, 432 unsigned long error_code, 433 unsigned long fault_addr) 434 { 435 pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n", 436 (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax, 437 regs->ip, (void *)regs->ip); 438 439 show_stack_regs(regs); 440 441 panic("MCA architectural violation!\n"); 442 443 while (true) 444 cpu_relax(); 445 446 return true; 447 } 448 449 static noinstr void mce_wrmsrl(u32 msr, u64 v) 450 { 451 u32 low, high; 452 453 if (__this_cpu_read(injectm.finished)) { 454 int offset; 455 456 instrumentation_begin(); 457 458 offset = msr_to_offset(msr); 459 if (offset >= 0) 460 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; 461 462 instrumentation_end(); 463 464 return; 465 } 466 467 low = (u32)v; 468 high = (u32)(v >> 32); 469 470 /* See comment in mce_rdmsrl() */ 471 asm volatile("1: wrmsr\n" 472 "2:\n" 473 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wrmsr_fault) 474 : : "c" (msr), "a"(low), "d" (high) : "memory"); 475 } 476 477 /* 478 * Collect all global (w.r.t. this processor) status about this machine 479 * check into our "mce" struct so that we can use it later to assess 480 * the severity of the problem as we read per-bank specific details. 481 */ 482 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) 483 { 484 mce_setup(m); 485 486 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 487 if (regs) { 488 /* 489 * Get the address of the instruction at the time of 490 * the machine check error. 491 */ 492 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { 493 m->ip = regs->ip; 494 m->cs = regs->cs; 495 496 /* 497 * When in VM86 mode make the cs look like ring 3 498 * always. This is a lie, but it's better than passing 499 * the additional vm86 bit around everywhere. 500 */ 501 if (v8086_mode(regs)) 502 m->cs |= 3; 503 } 504 /* Use accurate RIP reporting if available. */ 505 if (mca_cfg.rip_msr) 506 m->ip = mce_rdmsrl(mca_cfg.rip_msr); 507 } 508 } 509 510 int mce_available(struct cpuinfo_x86 *c) 511 { 512 if (mca_cfg.disabled) 513 return 0; 514 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); 515 } 516 517 static void mce_schedule_work(void) 518 { 519 if (!mce_gen_pool_empty()) 520 schedule_work(&mce_work); 521 } 522 523 static void mce_irq_work_cb(struct irq_work *entry) 524 { 525 mce_schedule_work(); 526 } 527 528 /* 529 * Check if the address reported by the CPU is in a format we can parse. 530 * It would be possible to add code for most other cases, but all would 531 * be somewhat complicated (e.g. segment offset would require an instruction 532 * parser). So only support physical addresses up to page granuality for now. 533 */ 534 int mce_usable_address(struct mce *m) 535 { 536 if (!(m->status & MCI_STATUS_ADDRV)) 537 return 0; 538 539 /* Checks after this one are Intel/Zhaoxin-specific: */ 540 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && 541 boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) 542 return 1; 543 544 if (!(m->status & MCI_STATUS_MISCV)) 545 return 0; 546 547 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) 548 return 0; 549 550 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) 551 return 0; 552 553 return 1; 554 } 555 EXPORT_SYMBOL_GPL(mce_usable_address); 556 557 bool mce_is_memory_error(struct mce *m) 558 { 559 switch (m->cpuvendor) { 560 case X86_VENDOR_AMD: 561 case X86_VENDOR_HYGON: 562 return amd_mce_is_memory_error(m); 563 564 case X86_VENDOR_INTEL: 565 case X86_VENDOR_ZHAOXIN: 566 /* 567 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes 568 * 569 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for 570 * indicating a memory error. Bit 8 is used for indicating a 571 * cache hierarchy error. The combination of bit 2 and bit 3 572 * is used for indicating a `generic' cache hierarchy error 573 * But we can't just blindly check the above bits, because if 574 * bit 11 is set, then it is a bus/interconnect error - and 575 * either way the above bits just gives more detail on what 576 * bus/interconnect error happened. Note that bit 12 can be 577 * ignored, as it's the "filter" bit. 578 */ 579 return (m->status & 0xef80) == BIT(7) || 580 (m->status & 0xef00) == BIT(8) || 581 (m->status & 0xeffc) == 0xc; 582 583 default: 584 return false; 585 } 586 } 587 EXPORT_SYMBOL_GPL(mce_is_memory_error); 588 589 static bool whole_page(struct mce *m) 590 { 591 if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV)) 592 return true; 593 594 return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT; 595 } 596 597 bool mce_is_correctable(struct mce *m) 598 { 599 if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED) 600 return false; 601 602 if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED) 603 return false; 604 605 if (m->status & MCI_STATUS_UC) 606 return false; 607 608 return true; 609 } 610 EXPORT_SYMBOL_GPL(mce_is_correctable); 611 612 static int mce_early_notifier(struct notifier_block *nb, unsigned long val, 613 void *data) 614 { 615 struct mce *m = (struct mce *)data; 616 617 if (!m) 618 return NOTIFY_DONE; 619 620 /* Emit the trace record: */ 621 trace_mce_record(m); 622 623 set_bit(0, &mce_need_notify); 624 625 mce_notify_irq(); 626 627 return NOTIFY_DONE; 628 } 629 630 static struct notifier_block early_nb = { 631 .notifier_call = mce_early_notifier, 632 .priority = MCE_PRIO_EARLY, 633 }; 634 635 static int uc_decode_notifier(struct notifier_block *nb, unsigned long val, 636 void *data) 637 { 638 struct mce *mce = (struct mce *)data; 639 unsigned long pfn; 640 641 if (!mce || !mce_usable_address(mce)) 642 return NOTIFY_DONE; 643 644 if (mce->severity != MCE_AO_SEVERITY && 645 mce->severity != MCE_DEFERRED_SEVERITY) 646 return NOTIFY_DONE; 647 648 pfn = mce->addr >> PAGE_SHIFT; 649 if (!memory_failure(pfn, 0)) { 650 set_mce_nospec(pfn, whole_page(mce)); 651 mce->kflags |= MCE_HANDLED_UC; 652 } 653 654 return NOTIFY_OK; 655 } 656 657 static struct notifier_block mce_uc_nb = { 658 .notifier_call = uc_decode_notifier, 659 .priority = MCE_PRIO_UC, 660 }; 661 662 static int mce_default_notifier(struct notifier_block *nb, unsigned long val, 663 void *data) 664 { 665 struct mce *m = (struct mce *)data; 666 667 if (!m) 668 return NOTIFY_DONE; 669 670 if (mca_cfg.print_all || !m->kflags) 671 __print_mce(m); 672 673 return NOTIFY_DONE; 674 } 675 676 static struct notifier_block mce_default_nb = { 677 .notifier_call = mce_default_notifier, 678 /* lowest prio, we want it to run last. */ 679 .priority = MCE_PRIO_LOWEST, 680 }; 681 682 /* 683 * Read ADDR and MISC registers. 684 */ 685 static void mce_read_aux(struct mce *m, int i) 686 { 687 if (m->status & MCI_STATUS_MISCV) 688 m->misc = mce_rdmsrl(msr_ops.misc(i)); 689 690 if (m->status & MCI_STATUS_ADDRV) { 691 m->addr = mce_rdmsrl(msr_ops.addr(i)); 692 693 /* 694 * Mask the reported address by the reported granularity. 695 */ 696 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { 697 u8 shift = MCI_MISC_ADDR_LSB(m->misc); 698 m->addr >>= shift; 699 m->addr <<= shift; 700 } 701 702 /* 703 * Extract [55:<lsb>] where lsb is the least significant 704 * *valid* bit of the address bits. 705 */ 706 if (mce_flags.smca) { 707 u8 lsb = (m->addr >> 56) & 0x3f; 708 709 m->addr &= GENMASK_ULL(55, lsb); 710 } 711 } 712 713 if (mce_flags.smca) { 714 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); 715 716 if (m->status & MCI_STATUS_SYNDV) 717 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); 718 } 719 } 720 721 DEFINE_PER_CPU(unsigned, mce_poll_count); 722 723 /* 724 * Poll for corrected events or events that happened before reset. 725 * Those are just logged through /dev/mcelog. 726 * 727 * This is executed in standard interrupt context. 728 * 729 * Note: spec recommends to panic for fatal unsignalled 730 * errors here. However this would be quite problematic -- 731 * we would need to reimplement the Monarch handling and 732 * it would mess up the exclusion between exception handler 733 * and poll handler -- * so we skip this for now. 734 * These cases should not happen anyways, or only when the CPU 735 * is already totally * confused. In this case it's likely it will 736 * not fully execute the machine check handler either. 737 */ 738 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) 739 { 740 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 741 bool error_seen = false; 742 struct mce m; 743 int i; 744 745 this_cpu_inc(mce_poll_count); 746 747 mce_gather_info(&m, NULL); 748 749 if (flags & MCP_TIMESTAMP) 750 m.tsc = rdtsc(); 751 752 for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 753 if (!mce_banks[i].ctl || !test_bit(i, *b)) 754 continue; 755 756 m.misc = 0; 757 m.addr = 0; 758 m.bank = i; 759 760 barrier(); 761 m.status = mce_rdmsrl(msr_ops.status(i)); 762 763 /* If this entry is not valid, ignore it */ 764 if (!(m.status & MCI_STATUS_VAL)) 765 continue; 766 767 /* 768 * If we are logging everything (at CPU online) or this 769 * is a corrected error, then we must log it. 770 */ 771 if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC)) 772 goto log_it; 773 774 /* 775 * Newer Intel systems that support software error 776 * recovery need to make additional checks. Other 777 * CPUs should skip over uncorrected errors, but log 778 * everything else. 779 */ 780 if (!mca_cfg.ser) { 781 if (m.status & MCI_STATUS_UC) 782 continue; 783 goto log_it; 784 } 785 786 /* Log "not enabled" (speculative) errors */ 787 if (!(m.status & MCI_STATUS_EN)) 788 goto log_it; 789 790 /* 791 * Log UCNA (SDM: 15.6.3 "UCR Error Classification") 792 * UC == 1 && PCC == 0 && S == 0 793 */ 794 if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S)) 795 goto log_it; 796 797 /* 798 * Skip anything else. Presumption is that our read of this 799 * bank is racing with a machine check. Leave the log alone 800 * for do_machine_check() to deal with it. 801 */ 802 continue; 803 804 log_it: 805 error_seen = true; 806 807 if (flags & MCP_DONTLOG) 808 goto clear_it; 809 810 mce_read_aux(&m, i); 811 m.severity = mce_severity(&m, NULL, mca_cfg.tolerant, NULL, false); 812 /* 813 * Don't get the IP here because it's unlikely to 814 * have anything to do with the actual error location. 815 */ 816 817 if (mca_cfg.dont_log_ce && !mce_usable_address(&m)) 818 goto clear_it; 819 820 mce_log(&m); 821 822 clear_it: 823 /* 824 * Clear state for this bank. 825 */ 826 mce_wrmsrl(msr_ops.status(i), 0); 827 } 828 829 /* 830 * Don't clear MCG_STATUS here because it's only defined for 831 * exceptions. 832 */ 833 834 sync_core(); 835 836 return error_seen; 837 } 838 EXPORT_SYMBOL_GPL(machine_check_poll); 839 840 /* 841 * Do a quick check if any of the events requires a panic. 842 * This decides if we keep the events around or clear them. 843 */ 844 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, 845 struct pt_regs *regs) 846 { 847 char *tmp = *msg; 848 int i; 849 850 for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 851 m->status = mce_rdmsrl(msr_ops.status(i)); 852 if (!(m->status & MCI_STATUS_VAL)) 853 continue; 854 855 __set_bit(i, validp); 856 if (quirk_no_way_out) 857 quirk_no_way_out(i, m, regs); 858 859 m->bank = i; 860 if (mce_severity(m, regs, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) { 861 mce_read_aux(m, i); 862 *msg = tmp; 863 return 1; 864 } 865 } 866 return 0; 867 } 868 869 /* 870 * Variable to establish order between CPUs while scanning. 871 * Each CPU spins initially until executing is equal its number. 872 */ 873 static atomic_t mce_executing; 874 875 /* 876 * Defines order of CPUs on entry. First CPU becomes Monarch. 877 */ 878 static atomic_t mce_callin; 879 880 /* 881 * Check if a timeout waiting for other CPUs happened. 882 */ 883 static int mce_timed_out(u64 *t, const char *msg) 884 { 885 /* 886 * The others already did panic for some reason. 887 * Bail out like in a timeout. 888 * rmb() to tell the compiler that system_state 889 * might have been modified by someone else. 890 */ 891 rmb(); 892 if (atomic_read(&mce_panicked)) 893 wait_for_panic(); 894 if (!mca_cfg.monarch_timeout) 895 goto out; 896 if ((s64)*t < SPINUNIT) { 897 if (mca_cfg.tolerant <= 1) 898 mce_panic(msg, NULL, NULL); 899 cpu_missing = 1; 900 return 1; 901 } 902 *t -= SPINUNIT; 903 out: 904 touch_nmi_watchdog(); 905 return 0; 906 } 907 908 /* 909 * The Monarch's reign. The Monarch is the CPU who entered 910 * the machine check handler first. It waits for the others to 911 * raise the exception too and then grades them. When any 912 * error is fatal panic. Only then let the others continue. 913 * 914 * The other CPUs entering the MCE handler will be controlled by the 915 * Monarch. They are called Subjects. 916 * 917 * This way we prevent any potential data corruption in a unrecoverable case 918 * and also makes sure always all CPU's errors are examined. 919 * 920 * Also this detects the case of a machine check event coming from outer 921 * space (not detected by any CPUs) In this case some external agent wants 922 * us to shut down, so panic too. 923 * 924 * The other CPUs might still decide to panic if the handler happens 925 * in a unrecoverable place, but in this case the system is in a semi-stable 926 * state and won't corrupt anything by itself. It's ok to let the others 927 * continue for a bit first. 928 * 929 * All the spin loops have timeouts; when a timeout happens a CPU 930 * typically elects itself to be Monarch. 931 */ 932 static void mce_reign(void) 933 { 934 int cpu; 935 struct mce *m = NULL; 936 int global_worst = 0; 937 char *msg = NULL; 938 939 /* 940 * This CPU is the Monarch and the other CPUs have run 941 * through their handlers. 942 * Grade the severity of the errors of all the CPUs. 943 */ 944 for_each_possible_cpu(cpu) { 945 struct mce *mtmp = &per_cpu(mces_seen, cpu); 946 947 if (mtmp->severity > global_worst) { 948 global_worst = mtmp->severity; 949 m = &per_cpu(mces_seen, cpu); 950 } 951 } 952 953 /* 954 * Cannot recover? Panic here then. 955 * This dumps all the mces in the log buffer and stops the 956 * other CPUs. 957 */ 958 if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) { 959 /* call mce_severity() to get "msg" for panic */ 960 mce_severity(m, NULL, mca_cfg.tolerant, &msg, true); 961 mce_panic("Fatal machine check", m, msg); 962 } 963 964 /* 965 * For UC somewhere we let the CPU who detects it handle it. 966 * Also must let continue the others, otherwise the handling 967 * CPU could deadlock on a lock. 968 */ 969 970 /* 971 * No machine check event found. Must be some external 972 * source or one CPU is hung. Panic. 973 */ 974 if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) 975 mce_panic("Fatal machine check from unknown source", NULL, NULL); 976 977 /* 978 * Now clear all the mces_seen so that they don't reappear on 979 * the next mce. 980 */ 981 for_each_possible_cpu(cpu) 982 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); 983 } 984 985 static atomic_t global_nwo; 986 987 /* 988 * Start of Monarch synchronization. This waits until all CPUs have 989 * entered the exception handler and then determines if any of them 990 * saw a fatal event that requires panic. Then it executes them 991 * in the entry order. 992 * TBD double check parallel CPU hotunplug 993 */ 994 static int mce_start(int *no_way_out) 995 { 996 int order; 997 int cpus = num_online_cpus(); 998 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 999 1000 if (!timeout) 1001 return -1; 1002 1003 atomic_add(*no_way_out, &global_nwo); 1004 /* 1005 * Rely on the implied barrier below, such that global_nwo 1006 * is updated before mce_callin. 1007 */ 1008 order = atomic_inc_return(&mce_callin); 1009 1010 /* 1011 * Wait for everyone. 1012 */ 1013 while (atomic_read(&mce_callin) != cpus) { 1014 if (mce_timed_out(&timeout, 1015 "Timeout: Not all CPUs entered broadcast exception handler")) { 1016 atomic_set(&global_nwo, 0); 1017 return -1; 1018 } 1019 ndelay(SPINUNIT); 1020 } 1021 1022 /* 1023 * mce_callin should be read before global_nwo 1024 */ 1025 smp_rmb(); 1026 1027 if (order == 1) { 1028 /* 1029 * Monarch: Starts executing now, the others wait. 1030 */ 1031 atomic_set(&mce_executing, 1); 1032 } else { 1033 /* 1034 * Subject: Now start the scanning loop one by one in 1035 * the original callin order. 1036 * This way when there are any shared banks it will be 1037 * only seen by one CPU before cleared, avoiding duplicates. 1038 */ 1039 while (atomic_read(&mce_executing) < order) { 1040 if (mce_timed_out(&timeout, 1041 "Timeout: Subject CPUs unable to finish machine check processing")) { 1042 atomic_set(&global_nwo, 0); 1043 return -1; 1044 } 1045 ndelay(SPINUNIT); 1046 } 1047 } 1048 1049 /* 1050 * Cache the global no_way_out state. 1051 */ 1052 *no_way_out = atomic_read(&global_nwo); 1053 1054 return order; 1055 } 1056 1057 /* 1058 * Synchronize between CPUs after main scanning loop. 1059 * This invokes the bulk of the Monarch processing. 1060 */ 1061 static int mce_end(int order) 1062 { 1063 int ret = -1; 1064 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 1065 1066 if (!timeout) 1067 goto reset; 1068 if (order < 0) 1069 goto reset; 1070 1071 /* 1072 * Allow others to run. 1073 */ 1074 atomic_inc(&mce_executing); 1075 1076 if (order == 1) { 1077 /* CHECKME: Can this race with a parallel hotplug? */ 1078 int cpus = num_online_cpus(); 1079 1080 /* 1081 * Monarch: Wait for everyone to go through their scanning 1082 * loops. 1083 */ 1084 while (atomic_read(&mce_executing) <= cpus) { 1085 if (mce_timed_out(&timeout, 1086 "Timeout: Monarch CPU unable to finish machine check processing")) 1087 goto reset; 1088 ndelay(SPINUNIT); 1089 } 1090 1091 mce_reign(); 1092 barrier(); 1093 ret = 0; 1094 } else { 1095 /* 1096 * Subject: Wait for Monarch to finish. 1097 */ 1098 while (atomic_read(&mce_executing) != 0) { 1099 if (mce_timed_out(&timeout, 1100 "Timeout: Monarch CPU did not finish machine check processing")) 1101 goto reset; 1102 ndelay(SPINUNIT); 1103 } 1104 1105 /* 1106 * Don't reset anything. That's done by the Monarch. 1107 */ 1108 return 0; 1109 } 1110 1111 /* 1112 * Reset all global state. 1113 */ 1114 reset: 1115 atomic_set(&global_nwo, 0); 1116 atomic_set(&mce_callin, 0); 1117 barrier(); 1118 1119 /* 1120 * Let others run again. 1121 */ 1122 atomic_set(&mce_executing, 0); 1123 return ret; 1124 } 1125 1126 static void mce_clear_state(unsigned long *toclear) 1127 { 1128 int i; 1129 1130 for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1131 if (test_bit(i, toclear)) 1132 mce_wrmsrl(msr_ops.status(i), 0); 1133 } 1134 } 1135 1136 /* 1137 * Cases where we avoid rendezvous handler timeout: 1138 * 1) If this CPU is offline. 1139 * 1140 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to 1141 * skip those CPUs which remain looping in the 1st kernel - see 1142 * crash_nmi_callback(). 1143 * 1144 * Note: there still is a small window between kexec-ing and the new, 1145 * kdump kernel establishing a new #MC handler where a broadcasted MCE 1146 * might not get handled properly. 1147 */ 1148 static noinstr bool mce_check_crashing_cpu(void) 1149 { 1150 unsigned int cpu = smp_processor_id(); 1151 1152 if (arch_cpu_is_offline(cpu) || 1153 (crashing_cpu != -1 && crashing_cpu != cpu)) { 1154 u64 mcgstatus; 1155 1156 mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS); 1157 1158 if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { 1159 if (mcgstatus & MCG_STATUS_LMCES) 1160 return false; 1161 } 1162 1163 if (mcgstatus & MCG_STATUS_RIPV) { 1164 __wrmsr(MSR_IA32_MCG_STATUS, 0, 0); 1165 return true; 1166 } 1167 } 1168 return false; 1169 } 1170 1171 static void __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final, 1172 unsigned long *toclear, unsigned long *valid_banks, 1173 int no_way_out, int *worst) 1174 { 1175 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1176 struct mca_config *cfg = &mca_cfg; 1177 int severity, i; 1178 1179 for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1180 __clear_bit(i, toclear); 1181 if (!test_bit(i, valid_banks)) 1182 continue; 1183 1184 if (!mce_banks[i].ctl) 1185 continue; 1186 1187 m->misc = 0; 1188 m->addr = 0; 1189 m->bank = i; 1190 1191 m->status = mce_rdmsrl(msr_ops.status(i)); 1192 if (!(m->status & MCI_STATUS_VAL)) 1193 continue; 1194 1195 /* 1196 * Corrected or non-signaled errors are handled by 1197 * machine_check_poll(). Leave them alone, unless this panics. 1198 */ 1199 if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && 1200 !no_way_out) 1201 continue; 1202 1203 /* Set taint even when machine check was not enabled. */ 1204 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 1205 1206 severity = mce_severity(m, regs, cfg->tolerant, NULL, true); 1207 1208 /* 1209 * When machine check was for corrected/deferred handler don't 1210 * touch, unless we're panicking. 1211 */ 1212 if ((severity == MCE_KEEP_SEVERITY || 1213 severity == MCE_UCNA_SEVERITY) && !no_way_out) 1214 continue; 1215 1216 __set_bit(i, toclear); 1217 1218 /* Machine check event was not enabled. Clear, but ignore. */ 1219 if (severity == MCE_NO_SEVERITY) 1220 continue; 1221 1222 mce_read_aux(m, i); 1223 1224 /* assuming valid severity level != 0 */ 1225 m->severity = severity; 1226 1227 mce_log(m); 1228 1229 if (severity > *worst) { 1230 *final = *m; 1231 *worst = severity; 1232 } 1233 } 1234 1235 /* mce_clear_state will clear *final, save locally for use later */ 1236 *m = *final; 1237 } 1238 1239 static void kill_me_now(struct callback_head *ch) 1240 { 1241 force_sig(SIGBUS); 1242 } 1243 1244 static void kill_me_maybe(struct callback_head *cb) 1245 { 1246 struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me); 1247 int flags = MF_ACTION_REQUIRED; 1248 1249 pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr); 1250 1251 if (!p->mce_ripv) 1252 flags |= MF_MUST_KILL; 1253 1254 if (!memory_failure(p->mce_addr >> PAGE_SHIFT, flags) && 1255 !(p->mce_kflags & MCE_IN_KERNEL_COPYIN)) { 1256 set_mce_nospec(p->mce_addr >> PAGE_SHIFT, p->mce_whole_page); 1257 sync_core(); 1258 return; 1259 } 1260 1261 if (p->mce_vaddr != (void __user *)-1l) { 1262 force_sig_mceerr(BUS_MCEERR_AR, p->mce_vaddr, PAGE_SHIFT); 1263 } else { 1264 pr_err("Memory error not recovered"); 1265 kill_me_now(cb); 1266 } 1267 } 1268 1269 static void queue_task_work(struct mce *m, int kill_current_task) 1270 { 1271 current->mce_addr = m->addr; 1272 current->mce_kflags = m->kflags; 1273 current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV); 1274 current->mce_whole_page = whole_page(m); 1275 1276 if (kill_current_task) 1277 current->mce_kill_me.func = kill_me_now; 1278 else 1279 current->mce_kill_me.func = kill_me_maybe; 1280 1281 task_work_add(current, ¤t->mce_kill_me, TWA_RESUME); 1282 } 1283 1284 /* 1285 * The actual machine check handler. This only handles real 1286 * exceptions when something got corrupted coming in through int 18. 1287 * 1288 * This is executed in NMI context not subject to normal locking rules. This 1289 * implies that most kernel services cannot be safely used. Don't even 1290 * think about putting a printk in there! 1291 * 1292 * On Intel systems this is entered on all CPUs in parallel through 1293 * MCE broadcast. However some CPUs might be broken beyond repair, 1294 * so be always careful when synchronizing with others. 1295 * 1296 * Tracing and kprobes are disabled: if we interrupted a kernel context 1297 * with IF=1, we need to minimize stack usage. There are also recursion 1298 * issues: if the machine check was due to a failure of the memory 1299 * backing the user stack, tracing that reads the user stack will cause 1300 * potentially infinite recursion. 1301 */ 1302 noinstr void do_machine_check(struct pt_regs *regs) 1303 { 1304 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); 1305 DECLARE_BITMAP(toclear, MAX_NR_BANKS); 1306 struct mca_config *cfg = &mca_cfg; 1307 struct mce m, *final; 1308 char *msg = NULL; 1309 int worst = 0; 1310 1311 /* 1312 * Establish sequential order between the CPUs entering the machine 1313 * check handler. 1314 */ 1315 int order = -1; 1316 1317 /* 1318 * If no_way_out gets set, there is no safe way to recover from this 1319 * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. 1320 */ 1321 int no_way_out = 0; 1322 1323 /* 1324 * If kill_current_task is not set, there might be a way to recover from this 1325 * error. 1326 */ 1327 int kill_current_task = 0; 1328 1329 /* 1330 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES 1331 * on Intel. 1332 */ 1333 int lmce = 1; 1334 1335 this_cpu_inc(mce_exception_count); 1336 1337 mce_gather_info(&m, regs); 1338 m.tsc = rdtsc(); 1339 1340 final = this_cpu_ptr(&mces_seen); 1341 *final = m; 1342 1343 memset(valid_banks, 0, sizeof(valid_banks)); 1344 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); 1345 1346 barrier(); 1347 1348 /* 1349 * When no restart IP might need to kill or panic. 1350 * Assume the worst for now, but if we find the 1351 * severity is MCE_AR_SEVERITY we have other options. 1352 */ 1353 if (!(m.mcgstatus & MCG_STATUS_RIPV)) 1354 kill_current_task = (cfg->tolerant == 3) ? 0 : 1; 1355 /* 1356 * Check if this MCE is signaled to only this logical processor, 1357 * on Intel, Zhaoxin only. 1358 */ 1359 if (m.cpuvendor == X86_VENDOR_INTEL || 1360 m.cpuvendor == X86_VENDOR_ZHAOXIN) 1361 lmce = m.mcgstatus & MCG_STATUS_LMCES; 1362 1363 /* 1364 * Local machine check may already know that we have to panic. 1365 * Broadcast machine check begins rendezvous in mce_start() 1366 * Go through all banks in exclusion of the other CPUs. This way we 1367 * don't report duplicated events on shared banks because the first one 1368 * to see it will clear it. 1369 */ 1370 if (lmce) { 1371 if (no_way_out && cfg->tolerant < 3) 1372 mce_panic("Fatal local machine check", &m, msg); 1373 } else { 1374 order = mce_start(&no_way_out); 1375 } 1376 1377 __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst); 1378 1379 if (!no_way_out) 1380 mce_clear_state(toclear); 1381 1382 /* 1383 * Do most of the synchronization with other CPUs. 1384 * When there's any problem use only local no_way_out state. 1385 */ 1386 if (!lmce) { 1387 if (mce_end(order) < 0) { 1388 if (!no_way_out) 1389 no_way_out = worst >= MCE_PANIC_SEVERITY; 1390 1391 if (no_way_out && cfg->tolerant < 3) 1392 mce_panic("Fatal machine check on current CPU", &m, msg); 1393 } 1394 } else { 1395 /* 1396 * If there was a fatal machine check we should have 1397 * already called mce_panic earlier in this function. 1398 * Since we re-read the banks, we might have found 1399 * something new. Check again to see if we found a 1400 * fatal error. We call "mce_severity()" again to 1401 * make sure we have the right "msg". 1402 */ 1403 if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) { 1404 mce_severity(&m, regs, cfg->tolerant, &msg, true); 1405 mce_panic("Local fatal machine check!", &m, msg); 1406 } 1407 } 1408 1409 if (worst != MCE_AR_SEVERITY && !kill_current_task) 1410 goto out; 1411 1412 /* Fault was in user mode and we need to take some action */ 1413 if ((m.cs & 3) == 3) { 1414 /* If this triggers there is no way to recover. Die hard. */ 1415 BUG_ON(!on_thread_stack() || !user_mode(regs)); 1416 1417 queue_task_work(&m, kill_current_task); 1418 1419 } else { 1420 /* 1421 * Handle an MCE which has happened in kernel space but from 1422 * which the kernel can recover: ex_has_fault_handler() has 1423 * already verified that the rIP at which the error happened is 1424 * a rIP from which the kernel can recover (by jumping to 1425 * recovery code specified in _ASM_EXTABLE_FAULT()) and the 1426 * corresponding exception handler which would do that is the 1427 * proper one. 1428 */ 1429 if (m.kflags & MCE_IN_KERNEL_RECOV) { 1430 if (!fixup_exception(regs, X86_TRAP_MC, 0, 0)) 1431 mce_panic("Failed kernel mode recovery", &m, msg); 1432 } 1433 1434 if (m.kflags & MCE_IN_KERNEL_COPYIN) 1435 queue_task_work(&m, kill_current_task); 1436 } 1437 out: 1438 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); 1439 } 1440 EXPORT_SYMBOL_GPL(do_machine_check); 1441 1442 #ifndef CONFIG_MEMORY_FAILURE 1443 int memory_failure(unsigned long pfn, int flags) 1444 { 1445 /* mce_severity() should not hand us an ACTION_REQUIRED error */ 1446 BUG_ON(flags & MF_ACTION_REQUIRED); 1447 pr_err("Uncorrected memory error in page 0x%lx ignored\n" 1448 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", 1449 pfn); 1450 1451 return 0; 1452 } 1453 #endif 1454 1455 /* 1456 * Periodic polling timer for "silent" machine check errors. If the 1457 * poller finds an MCE, poll 2x faster. When the poller finds no more 1458 * errors, poll 2x slower (up to check_interval seconds). 1459 */ 1460 static unsigned long check_interval = INITIAL_CHECK_INTERVAL; 1461 1462 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ 1463 static DEFINE_PER_CPU(struct timer_list, mce_timer); 1464 1465 static unsigned long mce_adjust_timer_default(unsigned long interval) 1466 { 1467 return interval; 1468 } 1469 1470 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; 1471 1472 static void __start_timer(struct timer_list *t, unsigned long interval) 1473 { 1474 unsigned long when = jiffies + interval; 1475 unsigned long flags; 1476 1477 local_irq_save(flags); 1478 1479 if (!timer_pending(t) || time_before(when, t->expires)) 1480 mod_timer(t, round_jiffies(when)); 1481 1482 local_irq_restore(flags); 1483 } 1484 1485 static void mce_timer_fn(struct timer_list *t) 1486 { 1487 struct timer_list *cpu_t = this_cpu_ptr(&mce_timer); 1488 unsigned long iv; 1489 1490 WARN_ON(cpu_t != t); 1491 1492 iv = __this_cpu_read(mce_next_interval); 1493 1494 if (mce_available(this_cpu_ptr(&cpu_info))) { 1495 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks)); 1496 1497 if (mce_intel_cmci_poll()) { 1498 iv = mce_adjust_timer(iv); 1499 goto done; 1500 } 1501 } 1502 1503 /* 1504 * Alert userspace if needed. If we logged an MCE, reduce the polling 1505 * interval, otherwise increase the polling interval. 1506 */ 1507 if (mce_notify_irq()) 1508 iv = max(iv / 2, (unsigned long) HZ/100); 1509 else 1510 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); 1511 1512 done: 1513 __this_cpu_write(mce_next_interval, iv); 1514 __start_timer(t, iv); 1515 } 1516 1517 /* 1518 * Ensure that the timer is firing in @interval from now. 1519 */ 1520 void mce_timer_kick(unsigned long interval) 1521 { 1522 struct timer_list *t = this_cpu_ptr(&mce_timer); 1523 unsigned long iv = __this_cpu_read(mce_next_interval); 1524 1525 __start_timer(t, interval); 1526 1527 if (interval < iv) 1528 __this_cpu_write(mce_next_interval, interval); 1529 } 1530 1531 /* Must not be called in IRQ context where del_timer_sync() can deadlock */ 1532 static void mce_timer_delete_all(void) 1533 { 1534 int cpu; 1535 1536 for_each_online_cpu(cpu) 1537 del_timer_sync(&per_cpu(mce_timer, cpu)); 1538 } 1539 1540 /* 1541 * Notify the user(s) about new machine check events. 1542 * Can be called from interrupt context, but not from machine check/NMI 1543 * context. 1544 */ 1545 int mce_notify_irq(void) 1546 { 1547 /* Not more than two messages every minute */ 1548 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); 1549 1550 if (test_and_clear_bit(0, &mce_need_notify)) { 1551 mce_work_trigger(); 1552 1553 if (__ratelimit(&ratelimit)) 1554 pr_info(HW_ERR "Machine check events logged\n"); 1555 1556 return 1; 1557 } 1558 return 0; 1559 } 1560 EXPORT_SYMBOL_GPL(mce_notify_irq); 1561 1562 static void __mcheck_cpu_mce_banks_init(void) 1563 { 1564 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1565 u8 n_banks = this_cpu_read(mce_num_banks); 1566 int i; 1567 1568 for (i = 0; i < n_banks; i++) { 1569 struct mce_bank *b = &mce_banks[i]; 1570 1571 /* 1572 * Init them all, __mcheck_cpu_apply_quirks() is going to apply 1573 * the required vendor quirks before 1574 * __mcheck_cpu_init_clear_banks() does the final bank setup. 1575 */ 1576 b->ctl = -1ULL; 1577 b->init = true; 1578 } 1579 } 1580 1581 /* 1582 * Initialize Machine Checks for a CPU. 1583 */ 1584 static void __mcheck_cpu_cap_init(void) 1585 { 1586 u64 cap; 1587 u8 b; 1588 1589 rdmsrl(MSR_IA32_MCG_CAP, cap); 1590 1591 b = cap & MCG_BANKCNT_MASK; 1592 1593 if (b > MAX_NR_BANKS) { 1594 pr_warn("CPU%d: Using only %u machine check banks out of %u\n", 1595 smp_processor_id(), MAX_NR_BANKS, b); 1596 b = MAX_NR_BANKS; 1597 } 1598 1599 this_cpu_write(mce_num_banks, b); 1600 1601 __mcheck_cpu_mce_banks_init(); 1602 1603 /* Use accurate RIP reporting if available. */ 1604 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) 1605 mca_cfg.rip_msr = MSR_IA32_MCG_EIP; 1606 1607 if (cap & MCG_SER_P) 1608 mca_cfg.ser = 1; 1609 } 1610 1611 static void __mcheck_cpu_init_generic(void) 1612 { 1613 enum mcp_flags m_fl = 0; 1614 mce_banks_t all_banks; 1615 u64 cap; 1616 1617 if (!mca_cfg.bootlog) 1618 m_fl = MCP_DONTLOG; 1619 1620 /* 1621 * Log the machine checks left over from the previous reset. 1622 */ 1623 bitmap_fill(all_banks, MAX_NR_BANKS); 1624 machine_check_poll(MCP_UC | m_fl, &all_banks); 1625 1626 cr4_set_bits(X86_CR4_MCE); 1627 1628 rdmsrl(MSR_IA32_MCG_CAP, cap); 1629 if (cap & MCG_CTL_P) 1630 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); 1631 } 1632 1633 static void __mcheck_cpu_init_clear_banks(void) 1634 { 1635 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1636 int i; 1637 1638 for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1639 struct mce_bank *b = &mce_banks[i]; 1640 1641 if (!b->init) 1642 continue; 1643 wrmsrl(msr_ops.ctl(i), b->ctl); 1644 wrmsrl(msr_ops.status(i), 0); 1645 } 1646 } 1647 1648 /* 1649 * Do a final check to see if there are any unused/RAZ banks. 1650 * 1651 * This must be done after the banks have been initialized and any quirks have 1652 * been applied. 1653 * 1654 * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs. 1655 * Otherwise, a user who disables a bank will not be able to re-enable it 1656 * without a system reboot. 1657 */ 1658 static void __mcheck_cpu_check_banks(void) 1659 { 1660 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1661 u64 msrval; 1662 int i; 1663 1664 for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1665 struct mce_bank *b = &mce_banks[i]; 1666 1667 if (!b->init) 1668 continue; 1669 1670 rdmsrl(msr_ops.ctl(i), msrval); 1671 b->init = !!msrval; 1672 } 1673 } 1674 1675 /* 1676 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and 1677 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM 1678 * Vol 3B Table 15-20). But this confuses both the code that determines 1679 * whether the machine check occurred in kernel or user mode, and also 1680 * the severity assessment code. Pretend that EIPV was set, and take the 1681 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. 1682 */ 1683 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) 1684 { 1685 if (bank != 0) 1686 return; 1687 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) 1688 return; 1689 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| 1690 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| 1691 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| 1692 MCACOD)) != 1693 (MCI_STATUS_UC|MCI_STATUS_EN| 1694 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| 1695 MCI_STATUS_AR|MCACOD_INSTR)) 1696 return; 1697 1698 m->mcgstatus |= MCG_STATUS_EIPV; 1699 m->ip = regs->ip; 1700 m->cs = regs->cs; 1701 } 1702 1703 /* Add per CPU specific workarounds here */ 1704 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) 1705 { 1706 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1707 struct mca_config *cfg = &mca_cfg; 1708 1709 if (c->x86_vendor == X86_VENDOR_UNKNOWN) { 1710 pr_info("unknown CPU type - not enabling MCE support\n"); 1711 return -EOPNOTSUPP; 1712 } 1713 1714 /* This should be disabled by the BIOS, but isn't always */ 1715 if (c->x86_vendor == X86_VENDOR_AMD) { 1716 if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { 1717 /* 1718 * disable GART TBL walk error reporting, which 1719 * trips off incorrectly with the IOMMU & 3ware 1720 * & Cerberus: 1721 */ 1722 clear_bit(10, (unsigned long *)&mce_banks[4].ctl); 1723 } 1724 if (c->x86 < 0x11 && cfg->bootlog < 0) { 1725 /* 1726 * Lots of broken BIOS around that don't clear them 1727 * by default and leave crap in there. Don't log: 1728 */ 1729 cfg->bootlog = 0; 1730 } 1731 /* 1732 * Various K7s with broken bank 0 around. Always disable 1733 * by default. 1734 */ 1735 if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0) 1736 mce_banks[0].ctl = 0; 1737 1738 /* 1739 * overflow_recov is supported for F15h Models 00h-0fh 1740 * even though we don't have a CPUID bit for it. 1741 */ 1742 if (c->x86 == 0x15 && c->x86_model <= 0xf) 1743 mce_flags.overflow_recov = 1; 1744 1745 } 1746 1747 if (c->x86_vendor == X86_VENDOR_INTEL) { 1748 /* 1749 * SDM documents that on family 6 bank 0 should not be written 1750 * because it aliases to another special BIOS controlled 1751 * register. 1752 * But it's not aliased anymore on model 0x1a+ 1753 * Don't ignore bank 0 completely because there could be a 1754 * valid event later, merely don't write CTL0. 1755 */ 1756 1757 if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) 1758 mce_banks[0].init = false; 1759 1760 /* 1761 * All newer Intel systems support MCE broadcasting. Enable 1762 * synchronization with a one second timeout. 1763 */ 1764 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && 1765 cfg->monarch_timeout < 0) 1766 cfg->monarch_timeout = USEC_PER_SEC; 1767 1768 /* 1769 * There are also broken BIOSes on some Pentium M and 1770 * earlier systems: 1771 */ 1772 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) 1773 cfg->bootlog = 0; 1774 1775 if (c->x86 == 6 && c->x86_model == 45) 1776 quirk_no_way_out = quirk_sandybridge_ifu; 1777 } 1778 1779 if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { 1780 /* 1781 * All newer Zhaoxin CPUs support MCE broadcasting. Enable 1782 * synchronization with a one second timeout. 1783 */ 1784 if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 1785 if (cfg->monarch_timeout < 0) 1786 cfg->monarch_timeout = USEC_PER_SEC; 1787 } 1788 } 1789 1790 if (cfg->monarch_timeout < 0) 1791 cfg->monarch_timeout = 0; 1792 if (cfg->bootlog != 0) 1793 cfg->panic_timeout = 30; 1794 1795 return 0; 1796 } 1797 1798 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) 1799 { 1800 if (c->x86 != 5) 1801 return 0; 1802 1803 switch (c->x86_vendor) { 1804 case X86_VENDOR_INTEL: 1805 intel_p5_mcheck_init(c); 1806 return 1; 1807 case X86_VENDOR_CENTAUR: 1808 winchip_mcheck_init(c); 1809 return 1; 1810 default: 1811 return 0; 1812 } 1813 1814 return 0; 1815 } 1816 1817 /* 1818 * Init basic CPU features needed for early decoding of MCEs. 1819 */ 1820 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) 1821 { 1822 if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) { 1823 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); 1824 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); 1825 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); 1826 mce_flags.amd_threshold = 1; 1827 1828 if (mce_flags.smca) { 1829 msr_ops.ctl = smca_ctl_reg; 1830 msr_ops.status = smca_status_reg; 1831 msr_ops.addr = smca_addr_reg; 1832 msr_ops.misc = smca_misc_reg; 1833 } 1834 } 1835 } 1836 1837 static void mce_centaur_feature_init(struct cpuinfo_x86 *c) 1838 { 1839 struct mca_config *cfg = &mca_cfg; 1840 1841 /* 1842 * All newer Centaur CPUs support MCE broadcasting. Enable 1843 * synchronization with a one second timeout. 1844 */ 1845 if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) || 1846 c->x86 > 6) { 1847 if (cfg->monarch_timeout < 0) 1848 cfg->monarch_timeout = USEC_PER_SEC; 1849 } 1850 } 1851 1852 static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) 1853 { 1854 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1855 1856 /* 1857 * These CPUs have MCA bank 8 which reports only one error type called 1858 * SVAD (System View Address Decoder). The reporting of that error is 1859 * controlled by IA32_MC8.CTL.0. 1860 * 1861 * If enabled, prefetching on these CPUs will cause SVAD MCE when 1862 * virtual machines start and result in a system panic. Always disable 1863 * bank 8 SVAD error by default. 1864 */ 1865 if ((c->x86 == 7 && c->x86_model == 0x1b) || 1866 (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 1867 if (this_cpu_read(mce_num_banks) > 8) 1868 mce_banks[8].ctl = 0; 1869 } 1870 1871 intel_init_cmci(); 1872 intel_init_lmce(); 1873 mce_adjust_timer = cmci_intel_adjust_timer; 1874 } 1875 1876 static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) 1877 { 1878 intel_clear_lmce(); 1879 } 1880 1881 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) 1882 { 1883 switch (c->x86_vendor) { 1884 case X86_VENDOR_INTEL: 1885 mce_intel_feature_init(c); 1886 mce_adjust_timer = cmci_intel_adjust_timer; 1887 break; 1888 1889 case X86_VENDOR_AMD: { 1890 mce_amd_feature_init(c); 1891 break; 1892 } 1893 1894 case X86_VENDOR_HYGON: 1895 mce_hygon_feature_init(c); 1896 break; 1897 1898 case X86_VENDOR_CENTAUR: 1899 mce_centaur_feature_init(c); 1900 break; 1901 1902 case X86_VENDOR_ZHAOXIN: 1903 mce_zhaoxin_feature_init(c); 1904 break; 1905 1906 default: 1907 break; 1908 } 1909 } 1910 1911 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) 1912 { 1913 switch (c->x86_vendor) { 1914 case X86_VENDOR_INTEL: 1915 mce_intel_feature_clear(c); 1916 break; 1917 1918 case X86_VENDOR_ZHAOXIN: 1919 mce_zhaoxin_feature_clear(c); 1920 break; 1921 1922 default: 1923 break; 1924 } 1925 } 1926 1927 static void mce_start_timer(struct timer_list *t) 1928 { 1929 unsigned long iv = check_interval * HZ; 1930 1931 if (mca_cfg.ignore_ce || !iv) 1932 return; 1933 1934 this_cpu_write(mce_next_interval, iv); 1935 __start_timer(t, iv); 1936 } 1937 1938 static void __mcheck_cpu_setup_timer(void) 1939 { 1940 struct timer_list *t = this_cpu_ptr(&mce_timer); 1941 1942 timer_setup(t, mce_timer_fn, TIMER_PINNED); 1943 } 1944 1945 static void __mcheck_cpu_init_timer(void) 1946 { 1947 struct timer_list *t = this_cpu_ptr(&mce_timer); 1948 1949 timer_setup(t, mce_timer_fn, TIMER_PINNED); 1950 mce_start_timer(t); 1951 } 1952 1953 bool filter_mce(struct mce *m) 1954 { 1955 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1956 return amd_filter_mce(m); 1957 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 1958 return intel_filter_mce(m); 1959 1960 return false; 1961 } 1962 1963 /* Handle unconfigured int18 (should never happen) */ 1964 static noinstr void unexpected_machine_check(struct pt_regs *regs) 1965 { 1966 instrumentation_begin(); 1967 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", 1968 smp_processor_id()); 1969 instrumentation_end(); 1970 } 1971 1972 /* Call the installed machine check handler for this CPU setup. */ 1973 void (*machine_check_vector)(struct pt_regs *) = unexpected_machine_check; 1974 1975 static __always_inline void exc_machine_check_kernel(struct pt_regs *regs) 1976 { 1977 irqentry_state_t irq_state; 1978 1979 WARN_ON_ONCE(user_mode(regs)); 1980 1981 /* 1982 * Only required when from kernel mode. See 1983 * mce_check_crashing_cpu() for details. 1984 */ 1985 if (machine_check_vector == do_machine_check && 1986 mce_check_crashing_cpu()) 1987 return; 1988 1989 irq_state = irqentry_nmi_enter(regs); 1990 /* 1991 * The call targets are marked noinstr, but objtool can't figure 1992 * that out because it's an indirect call. Annotate it. 1993 */ 1994 instrumentation_begin(); 1995 trace_hardirqs_off_finish(); 1996 machine_check_vector(regs); 1997 if (regs->flags & X86_EFLAGS_IF) 1998 trace_hardirqs_on_prepare(); 1999 instrumentation_end(); 2000 irqentry_nmi_exit(regs, irq_state); 2001 } 2002 2003 static __always_inline void exc_machine_check_user(struct pt_regs *regs) 2004 { 2005 irqentry_enter_from_user_mode(regs); 2006 instrumentation_begin(); 2007 machine_check_vector(regs); 2008 instrumentation_end(); 2009 irqentry_exit_to_user_mode(regs); 2010 } 2011 2012 #ifdef CONFIG_X86_64 2013 /* MCE hit kernel mode */ 2014 DEFINE_IDTENTRY_MCE(exc_machine_check) 2015 { 2016 unsigned long dr7; 2017 2018 dr7 = local_db_save(); 2019 exc_machine_check_kernel(regs); 2020 local_db_restore(dr7); 2021 } 2022 2023 /* The user mode variant. */ 2024 DEFINE_IDTENTRY_MCE_USER(exc_machine_check) 2025 { 2026 unsigned long dr7; 2027 2028 dr7 = local_db_save(); 2029 exc_machine_check_user(regs); 2030 local_db_restore(dr7); 2031 } 2032 #else 2033 /* 32bit unified entry point */ 2034 DEFINE_IDTENTRY_RAW(exc_machine_check) 2035 { 2036 unsigned long dr7; 2037 2038 dr7 = local_db_save(); 2039 if (user_mode(regs)) 2040 exc_machine_check_user(regs); 2041 else 2042 exc_machine_check_kernel(regs); 2043 local_db_restore(dr7); 2044 } 2045 #endif 2046 2047 /* 2048 * Called for each booted CPU to set up machine checks. 2049 * Must be called with preempt off: 2050 */ 2051 void mcheck_cpu_init(struct cpuinfo_x86 *c) 2052 { 2053 if (mca_cfg.disabled) 2054 return; 2055 2056 if (__mcheck_cpu_ancient_init(c)) 2057 return; 2058 2059 if (!mce_available(c)) 2060 return; 2061 2062 __mcheck_cpu_cap_init(); 2063 2064 if (__mcheck_cpu_apply_quirks(c) < 0) { 2065 mca_cfg.disabled = 1; 2066 return; 2067 } 2068 2069 if (mce_gen_pool_init()) { 2070 mca_cfg.disabled = 1; 2071 pr_emerg("Couldn't allocate MCE records pool!\n"); 2072 return; 2073 } 2074 2075 machine_check_vector = do_machine_check; 2076 2077 __mcheck_cpu_init_early(c); 2078 __mcheck_cpu_init_generic(); 2079 __mcheck_cpu_init_vendor(c); 2080 __mcheck_cpu_init_clear_banks(); 2081 __mcheck_cpu_check_banks(); 2082 __mcheck_cpu_setup_timer(); 2083 } 2084 2085 /* 2086 * Called for each booted CPU to clear some machine checks opt-ins 2087 */ 2088 void mcheck_cpu_clear(struct cpuinfo_x86 *c) 2089 { 2090 if (mca_cfg.disabled) 2091 return; 2092 2093 if (!mce_available(c)) 2094 return; 2095 2096 /* 2097 * Possibly to clear general settings generic to x86 2098 * __mcheck_cpu_clear_generic(c); 2099 */ 2100 __mcheck_cpu_clear_vendor(c); 2101 2102 } 2103 2104 static void __mce_disable_bank(void *arg) 2105 { 2106 int bank = *((int *)arg); 2107 __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); 2108 cmci_disable_bank(bank); 2109 } 2110 2111 void mce_disable_bank(int bank) 2112 { 2113 if (bank >= this_cpu_read(mce_num_banks)) { 2114 pr_warn(FW_BUG 2115 "Ignoring request to disable invalid MCA bank %d.\n", 2116 bank); 2117 return; 2118 } 2119 set_bit(bank, mce_banks_ce_disabled); 2120 on_each_cpu(__mce_disable_bank, &bank, 1); 2121 } 2122 2123 /* 2124 * mce=off Disables machine check 2125 * mce=no_cmci Disables CMCI 2126 * mce=no_lmce Disables LMCE 2127 * mce=dont_log_ce Clears corrected events silently, no log created for CEs. 2128 * mce=print_all Print all machine check logs to console 2129 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. 2130 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) 2131 * monarchtimeout is how long to wait for other CPUs on machine 2132 * check, or 0 to not wait 2133 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h 2134 and older. 2135 * mce=nobootlog Don't log MCEs from before booting. 2136 * mce=bios_cmci_threshold Don't program the CMCI threshold 2137 * mce=recovery force enable copy_mc_fragile() 2138 */ 2139 static int __init mcheck_enable(char *str) 2140 { 2141 struct mca_config *cfg = &mca_cfg; 2142 2143 if (*str == 0) { 2144 enable_p5_mce(); 2145 return 1; 2146 } 2147 if (*str == '=') 2148 str++; 2149 if (!strcmp(str, "off")) 2150 cfg->disabled = 1; 2151 else if (!strcmp(str, "no_cmci")) 2152 cfg->cmci_disabled = true; 2153 else if (!strcmp(str, "no_lmce")) 2154 cfg->lmce_disabled = 1; 2155 else if (!strcmp(str, "dont_log_ce")) 2156 cfg->dont_log_ce = true; 2157 else if (!strcmp(str, "print_all")) 2158 cfg->print_all = true; 2159 else if (!strcmp(str, "ignore_ce")) 2160 cfg->ignore_ce = true; 2161 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) 2162 cfg->bootlog = (str[0] == 'b'); 2163 else if (!strcmp(str, "bios_cmci_threshold")) 2164 cfg->bios_cmci_threshold = 1; 2165 else if (!strcmp(str, "recovery")) 2166 cfg->recovery = 1; 2167 else if (isdigit(str[0])) { 2168 if (get_option(&str, &cfg->tolerant) == 2) 2169 get_option(&str, &(cfg->monarch_timeout)); 2170 } else { 2171 pr_info("mce argument %s ignored. Please use /sys\n", str); 2172 return 0; 2173 } 2174 return 1; 2175 } 2176 __setup("mce", mcheck_enable); 2177 2178 int __init mcheck_init(void) 2179 { 2180 mcheck_intel_therm_init(); 2181 mce_register_decode_chain(&early_nb); 2182 mce_register_decode_chain(&mce_uc_nb); 2183 mce_register_decode_chain(&mce_default_nb); 2184 mcheck_vendor_init_severity(); 2185 2186 INIT_WORK(&mce_work, mce_gen_pool_process); 2187 init_irq_work(&mce_irq_work, mce_irq_work_cb); 2188 2189 return 0; 2190 } 2191 2192 /* 2193 * mce_syscore: PM support 2194 */ 2195 2196 /* 2197 * Disable machine checks on suspend and shutdown. We can't really handle 2198 * them later. 2199 */ 2200 static void mce_disable_error_reporting(void) 2201 { 2202 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 2203 int i; 2204 2205 for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 2206 struct mce_bank *b = &mce_banks[i]; 2207 2208 if (b->init) 2209 wrmsrl(msr_ops.ctl(i), 0); 2210 } 2211 return; 2212 } 2213 2214 static void vendor_disable_error_reporting(void) 2215 { 2216 /* 2217 * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these 2218 * MSRs are socket-wide. Disabling them for just a single offlined CPU 2219 * is bad, since it will inhibit reporting for all shared resources on 2220 * the socket like the last level cache (LLC), the integrated memory 2221 * controller (iMC), etc. 2222 */ 2223 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || 2224 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || 2225 boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 2226 boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) 2227 return; 2228 2229 mce_disable_error_reporting(); 2230 } 2231 2232 static int mce_syscore_suspend(void) 2233 { 2234 vendor_disable_error_reporting(); 2235 return 0; 2236 } 2237 2238 static void mce_syscore_shutdown(void) 2239 { 2240 vendor_disable_error_reporting(); 2241 } 2242 2243 /* 2244 * On resume clear all MCE state. Don't want to see leftovers from the BIOS. 2245 * Only one CPU is active at this time, the others get re-added later using 2246 * CPU hotplug: 2247 */ 2248 static void mce_syscore_resume(void) 2249 { 2250 __mcheck_cpu_init_generic(); 2251 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); 2252 __mcheck_cpu_init_clear_banks(); 2253 } 2254 2255 static struct syscore_ops mce_syscore_ops = { 2256 .suspend = mce_syscore_suspend, 2257 .shutdown = mce_syscore_shutdown, 2258 .resume = mce_syscore_resume, 2259 }; 2260 2261 /* 2262 * mce_device: Sysfs support 2263 */ 2264 2265 static void mce_cpu_restart(void *data) 2266 { 2267 if (!mce_available(raw_cpu_ptr(&cpu_info))) 2268 return; 2269 __mcheck_cpu_init_generic(); 2270 __mcheck_cpu_init_clear_banks(); 2271 __mcheck_cpu_init_timer(); 2272 } 2273 2274 /* Reinit MCEs after user configuration changes */ 2275 static void mce_restart(void) 2276 { 2277 mce_timer_delete_all(); 2278 on_each_cpu(mce_cpu_restart, NULL, 1); 2279 } 2280 2281 /* Toggle features for corrected errors */ 2282 static void mce_disable_cmci(void *data) 2283 { 2284 if (!mce_available(raw_cpu_ptr(&cpu_info))) 2285 return; 2286 cmci_clear(); 2287 } 2288 2289 static void mce_enable_ce(void *all) 2290 { 2291 if (!mce_available(raw_cpu_ptr(&cpu_info))) 2292 return; 2293 cmci_reenable(); 2294 cmci_recheck(); 2295 if (all) 2296 __mcheck_cpu_init_timer(); 2297 } 2298 2299 static struct bus_type mce_subsys = { 2300 .name = "machinecheck", 2301 .dev_name = "machinecheck", 2302 }; 2303 2304 DEFINE_PER_CPU(struct device *, mce_device); 2305 2306 static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr) 2307 { 2308 return container_of(attr, struct mce_bank_dev, attr); 2309 } 2310 2311 static ssize_t show_bank(struct device *s, struct device_attribute *attr, 2312 char *buf) 2313 { 2314 u8 bank = attr_to_bank(attr)->bank; 2315 struct mce_bank *b; 2316 2317 if (bank >= per_cpu(mce_num_banks, s->id)) 2318 return -EINVAL; 2319 2320 b = &per_cpu(mce_banks_array, s->id)[bank]; 2321 2322 if (!b->init) 2323 return -ENODEV; 2324 2325 return sprintf(buf, "%llx\n", b->ctl); 2326 } 2327 2328 static ssize_t set_bank(struct device *s, struct device_attribute *attr, 2329 const char *buf, size_t size) 2330 { 2331 u8 bank = attr_to_bank(attr)->bank; 2332 struct mce_bank *b; 2333 u64 new; 2334 2335 if (kstrtou64(buf, 0, &new) < 0) 2336 return -EINVAL; 2337 2338 if (bank >= per_cpu(mce_num_banks, s->id)) 2339 return -EINVAL; 2340 2341 b = &per_cpu(mce_banks_array, s->id)[bank]; 2342 2343 if (!b->init) 2344 return -ENODEV; 2345 2346 b->ctl = new; 2347 mce_restart(); 2348 2349 return size; 2350 } 2351 2352 static ssize_t set_ignore_ce(struct device *s, 2353 struct device_attribute *attr, 2354 const char *buf, size_t size) 2355 { 2356 u64 new; 2357 2358 if (kstrtou64(buf, 0, &new) < 0) 2359 return -EINVAL; 2360 2361 mutex_lock(&mce_sysfs_mutex); 2362 if (mca_cfg.ignore_ce ^ !!new) { 2363 if (new) { 2364 /* disable ce features */ 2365 mce_timer_delete_all(); 2366 on_each_cpu(mce_disable_cmci, NULL, 1); 2367 mca_cfg.ignore_ce = true; 2368 } else { 2369 /* enable ce features */ 2370 mca_cfg.ignore_ce = false; 2371 on_each_cpu(mce_enable_ce, (void *)1, 1); 2372 } 2373 } 2374 mutex_unlock(&mce_sysfs_mutex); 2375 2376 return size; 2377 } 2378 2379 static ssize_t set_cmci_disabled(struct device *s, 2380 struct device_attribute *attr, 2381 const char *buf, size_t size) 2382 { 2383 u64 new; 2384 2385 if (kstrtou64(buf, 0, &new) < 0) 2386 return -EINVAL; 2387 2388 mutex_lock(&mce_sysfs_mutex); 2389 if (mca_cfg.cmci_disabled ^ !!new) { 2390 if (new) { 2391 /* disable cmci */ 2392 on_each_cpu(mce_disable_cmci, NULL, 1); 2393 mca_cfg.cmci_disabled = true; 2394 } else { 2395 /* enable cmci */ 2396 mca_cfg.cmci_disabled = false; 2397 on_each_cpu(mce_enable_ce, NULL, 1); 2398 } 2399 } 2400 mutex_unlock(&mce_sysfs_mutex); 2401 2402 return size; 2403 } 2404 2405 static ssize_t store_int_with_restart(struct device *s, 2406 struct device_attribute *attr, 2407 const char *buf, size_t size) 2408 { 2409 unsigned long old_check_interval = check_interval; 2410 ssize_t ret = device_store_ulong(s, attr, buf, size); 2411 2412 if (check_interval == old_check_interval) 2413 return ret; 2414 2415 mutex_lock(&mce_sysfs_mutex); 2416 mce_restart(); 2417 mutex_unlock(&mce_sysfs_mutex); 2418 2419 return ret; 2420 } 2421 2422 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); 2423 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); 2424 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); 2425 static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all); 2426 2427 static struct dev_ext_attribute dev_attr_check_interval = { 2428 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), 2429 &check_interval 2430 }; 2431 2432 static struct dev_ext_attribute dev_attr_ignore_ce = { 2433 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), 2434 &mca_cfg.ignore_ce 2435 }; 2436 2437 static struct dev_ext_attribute dev_attr_cmci_disabled = { 2438 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), 2439 &mca_cfg.cmci_disabled 2440 }; 2441 2442 static struct device_attribute *mce_device_attrs[] = { 2443 &dev_attr_tolerant.attr, 2444 &dev_attr_check_interval.attr, 2445 #ifdef CONFIG_X86_MCELOG_LEGACY 2446 &dev_attr_trigger, 2447 #endif 2448 &dev_attr_monarch_timeout.attr, 2449 &dev_attr_dont_log_ce.attr, 2450 &dev_attr_print_all.attr, 2451 &dev_attr_ignore_ce.attr, 2452 &dev_attr_cmci_disabled.attr, 2453 NULL 2454 }; 2455 2456 static cpumask_var_t mce_device_initialized; 2457 2458 static void mce_device_release(struct device *dev) 2459 { 2460 kfree(dev); 2461 } 2462 2463 /* Per CPU device init. All of the CPUs still share the same bank device: */ 2464 static int mce_device_create(unsigned int cpu) 2465 { 2466 struct device *dev; 2467 int err; 2468 int i, j; 2469 2470 if (!mce_available(&boot_cpu_data)) 2471 return -EIO; 2472 2473 dev = per_cpu(mce_device, cpu); 2474 if (dev) 2475 return 0; 2476 2477 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 2478 if (!dev) 2479 return -ENOMEM; 2480 dev->id = cpu; 2481 dev->bus = &mce_subsys; 2482 dev->release = &mce_device_release; 2483 2484 err = device_register(dev); 2485 if (err) { 2486 put_device(dev); 2487 return err; 2488 } 2489 2490 for (i = 0; mce_device_attrs[i]; i++) { 2491 err = device_create_file(dev, mce_device_attrs[i]); 2492 if (err) 2493 goto error; 2494 } 2495 for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) { 2496 err = device_create_file(dev, &mce_bank_devs[j].attr); 2497 if (err) 2498 goto error2; 2499 } 2500 cpumask_set_cpu(cpu, mce_device_initialized); 2501 per_cpu(mce_device, cpu) = dev; 2502 2503 return 0; 2504 error2: 2505 while (--j >= 0) 2506 device_remove_file(dev, &mce_bank_devs[j].attr); 2507 error: 2508 while (--i >= 0) 2509 device_remove_file(dev, mce_device_attrs[i]); 2510 2511 device_unregister(dev); 2512 2513 return err; 2514 } 2515 2516 static void mce_device_remove(unsigned int cpu) 2517 { 2518 struct device *dev = per_cpu(mce_device, cpu); 2519 int i; 2520 2521 if (!cpumask_test_cpu(cpu, mce_device_initialized)) 2522 return; 2523 2524 for (i = 0; mce_device_attrs[i]; i++) 2525 device_remove_file(dev, mce_device_attrs[i]); 2526 2527 for (i = 0; i < per_cpu(mce_num_banks, cpu); i++) 2528 device_remove_file(dev, &mce_bank_devs[i].attr); 2529 2530 device_unregister(dev); 2531 cpumask_clear_cpu(cpu, mce_device_initialized); 2532 per_cpu(mce_device, cpu) = NULL; 2533 } 2534 2535 /* Make sure there are no machine checks on offlined CPUs. */ 2536 static void mce_disable_cpu(void) 2537 { 2538 if (!mce_available(raw_cpu_ptr(&cpu_info))) 2539 return; 2540 2541 if (!cpuhp_tasks_frozen) 2542 cmci_clear(); 2543 2544 vendor_disable_error_reporting(); 2545 } 2546 2547 static void mce_reenable_cpu(void) 2548 { 2549 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 2550 int i; 2551 2552 if (!mce_available(raw_cpu_ptr(&cpu_info))) 2553 return; 2554 2555 if (!cpuhp_tasks_frozen) 2556 cmci_reenable(); 2557 for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 2558 struct mce_bank *b = &mce_banks[i]; 2559 2560 if (b->init) 2561 wrmsrl(msr_ops.ctl(i), b->ctl); 2562 } 2563 } 2564 2565 static int mce_cpu_dead(unsigned int cpu) 2566 { 2567 mce_intel_hcpu_update(cpu); 2568 2569 /* intentionally ignoring frozen here */ 2570 if (!cpuhp_tasks_frozen) 2571 cmci_rediscover(); 2572 return 0; 2573 } 2574 2575 static int mce_cpu_online(unsigned int cpu) 2576 { 2577 struct timer_list *t = this_cpu_ptr(&mce_timer); 2578 int ret; 2579 2580 mce_device_create(cpu); 2581 2582 ret = mce_threshold_create_device(cpu); 2583 if (ret) { 2584 mce_device_remove(cpu); 2585 return ret; 2586 } 2587 mce_reenable_cpu(); 2588 mce_start_timer(t); 2589 return 0; 2590 } 2591 2592 static int mce_cpu_pre_down(unsigned int cpu) 2593 { 2594 struct timer_list *t = this_cpu_ptr(&mce_timer); 2595 2596 mce_disable_cpu(); 2597 del_timer_sync(t); 2598 mce_threshold_remove_device(cpu); 2599 mce_device_remove(cpu); 2600 return 0; 2601 } 2602 2603 static __init void mce_init_banks(void) 2604 { 2605 int i; 2606 2607 for (i = 0; i < MAX_NR_BANKS; i++) { 2608 struct mce_bank_dev *b = &mce_bank_devs[i]; 2609 struct device_attribute *a = &b->attr; 2610 2611 b->bank = i; 2612 2613 sysfs_attr_init(&a->attr); 2614 a->attr.name = b->attrname; 2615 snprintf(b->attrname, ATTR_LEN, "bank%d", i); 2616 2617 a->attr.mode = 0644; 2618 a->show = show_bank; 2619 a->store = set_bank; 2620 } 2621 } 2622 2623 /* 2624 * When running on XEN, this initcall is ordered against the XEN mcelog 2625 * initcall: 2626 * 2627 * device_initcall(xen_late_init_mcelog); 2628 * device_initcall_sync(mcheck_init_device); 2629 */ 2630 static __init int mcheck_init_device(void) 2631 { 2632 int err; 2633 2634 /* 2635 * Check if we have a spare virtual bit. This will only become 2636 * a problem if/when we move beyond 5-level page tables. 2637 */ 2638 MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63); 2639 2640 if (!mce_available(&boot_cpu_data)) { 2641 err = -EIO; 2642 goto err_out; 2643 } 2644 2645 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { 2646 err = -ENOMEM; 2647 goto err_out; 2648 } 2649 2650 mce_init_banks(); 2651 2652 err = subsys_system_register(&mce_subsys, NULL); 2653 if (err) 2654 goto err_out_mem; 2655 2656 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL, 2657 mce_cpu_dead); 2658 if (err) 2659 goto err_out_mem; 2660 2661 /* 2662 * Invokes mce_cpu_online() on all CPUs which are online when 2663 * the state is installed. 2664 */ 2665 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online", 2666 mce_cpu_online, mce_cpu_pre_down); 2667 if (err < 0) 2668 goto err_out_online; 2669 2670 register_syscore_ops(&mce_syscore_ops); 2671 2672 return 0; 2673 2674 err_out_online: 2675 cpuhp_remove_state(CPUHP_X86_MCE_DEAD); 2676 2677 err_out_mem: 2678 free_cpumask_var(mce_device_initialized); 2679 2680 err_out: 2681 pr_err("Unable to init MCE device (rc: %d)\n", err); 2682 2683 return err; 2684 } 2685 device_initcall_sync(mcheck_init_device); 2686 2687 /* 2688 * Old style boot options parsing. Only for compatibility. 2689 */ 2690 static int __init mcheck_disable(char *str) 2691 { 2692 mca_cfg.disabled = 1; 2693 return 1; 2694 } 2695 __setup("nomce", mcheck_disable); 2696 2697 #ifdef CONFIG_DEBUG_FS 2698 struct dentry *mce_get_debugfs_dir(void) 2699 { 2700 static struct dentry *dmce; 2701 2702 if (!dmce) 2703 dmce = debugfs_create_dir("mce", NULL); 2704 2705 return dmce; 2706 } 2707 2708 static void mce_reset(void) 2709 { 2710 cpu_missing = 0; 2711 atomic_set(&mce_fake_panicked, 0); 2712 atomic_set(&mce_executing, 0); 2713 atomic_set(&mce_callin, 0); 2714 atomic_set(&global_nwo, 0); 2715 } 2716 2717 static int fake_panic_get(void *data, u64 *val) 2718 { 2719 *val = fake_panic; 2720 return 0; 2721 } 2722 2723 static int fake_panic_set(void *data, u64 val) 2724 { 2725 mce_reset(); 2726 fake_panic = val; 2727 return 0; 2728 } 2729 2730 DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set, 2731 "%llu\n"); 2732 2733 static void __init mcheck_debugfs_init(void) 2734 { 2735 struct dentry *dmce; 2736 2737 dmce = mce_get_debugfs_dir(); 2738 debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL, 2739 &fake_panic_fops); 2740 } 2741 #else 2742 static void __init mcheck_debugfs_init(void) { } 2743 #endif 2744 2745 static int __init mcheck_late_init(void) 2746 { 2747 if (mca_cfg.recovery) 2748 enable_copy_mc_fragile(); 2749 2750 mcheck_debugfs_init(); 2751 2752 /* 2753 * Flush out everything that has been logged during early boot, now that 2754 * everything has been initialized (workqueues, decoders, ...). 2755 */ 2756 mce_schedule_work(); 2757 2758 return 0; 2759 } 2760 late_initcall(mcheck_late_init); 2761