xref: /openbmc/linux/arch/x86/kernel/cpu/mce/core.c (revision 61bf3293)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Machine check handler.
4  *
5  * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
6  * Rest from unknown author(s).
7  * 2004 Andi Kleen. Rewrote most of it.
8  * Copyright 2008 Intel Corporation
9  * Author: Andi Kleen
10  */
11 
12 #include <linux/thread_info.h>
13 #include <linux/capability.h>
14 #include <linux/miscdevice.h>
15 #include <linux/ratelimit.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/device.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/delay.h>
26 #include <linux/ctype.h>
27 #include <linux/sched.h>
28 #include <linux/sysfs.h>
29 #include <linux/types.h>
30 #include <linux/slab.h>
31 #include <linux/init.h>
32 #include <linux/kmod.h>
33 #include <linux/poll.h>
34 #include <linux/nmi.h>
35 #include <linux/cpu.h>
36 #include <linux/ras.h>
37 #include <linux/smp.h>
38 #include <linux/fs.h>
39 #include <linux/mm.h>
40 #include <linux/debugfs.h>
41 #include <linux/irq_work.h>
42 #include <linux/export.h>
43 #include <linux/jump_label.h>
44 #include <linux/set_memory.h>
45 #include <linux/task_work.h>
46 #include <linux/hardirq.h>
47 
48 #include <asm/intel-family.h>
49 #include <asm/processor.h>
50 #include <asm/traps.h>
51 #include <asm/tlbflush.h>
52 #include <asm/mce.h>
53 #include <asm/msr.h>
54 #include <asm/reboot.h>
55 
56 #include "internal.h"
57 
58 /* sysfs synchronization */
59 static DEFINE_MUTEX(mce_sysfs_mutex);
60 
61 #define CREATE_TRACE_POINTS
62 #include <trace/events/mce.h>
63 
64 #define SPINUNIT		100	/* 100ns */
65 
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
67 
68 DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks);
69 
70 struct mce_bank {
71 	u64			ctl;			/* subevents to enable */
72 	bool			init;			/* initialise bank? */
73 };
74 static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);
75 
76 #define ATTR_LEN               16
77 /* One object for each MCE bank, shared by all CPUs */
78 struct mce_bank_dev {
79 	struct device_attribute	attr;			/* device attribute */
80 	char			attrname[ATTR_LEN];	/* attribute name */
81 	u8			bank;			/* bank number */
82 };
83 static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS];
84 
85 struct mce_vendor_flags mce_flags __read_mostly;
86 
87 struct mca_config mca_cfg __read_mostly = {
88 	.bootlog  = -1,
89 	/*
90 	 * Tolerant levels:
91 	 * 0: always panic on uncorrected errors, log corrected errors
92 	 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
93 	 * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors
94 	 * 3: never panic or SIGBUS, log all errors (for testing only)
95 	 */
96 	.tolerant = 1,
97 	.monarch_timeout = -1
98 };
99 
100 static DEFINE_PER_CPU(struct mce, mces_seen);
101 static unsigned long mce_need_notify;
102 static int cpu_missing;
103 
104 /*
105  * MCA banks polled by the period polling timer for corrected events.
106  * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
107  */
108 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
109 	[0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
110 };
111 
112 /*
113  * MCA banks controlled through firmware first for corrected errors.
114  * This is a global list of banks for which we won't enable CMCI and we
115  * won't poll. Firmware controls these banks and is responsible for
116  * reporting corrected errors through GHES. Uncorrected/recoverable
117  * errors are still notified through a machine check.
118  */
119 mce_banks_t mce_banks_ce_disabled;
120 
121 static struct work_struct mce_work;
122 static struct irq_work mce_irq_work;
123 
124 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
125 
126 /*
127  * CPU/chipset specific EDAC code can register a notifier call here to print
128  * MCE errors in a human-readable form.
129  */
130 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
131 
132 /* Do initial initialization of a struct mce */
133 noinstr void mce_setup(struct mce *m)
134 {
135 	memset(m, 0, sizeof(struct mce));
136 	m->cpu = m->extcpu = smp_processor_id();
137 	/* need the internal __ version to avoid deadlocks */
138 	m->time = __ktime_get_real_seconds();
139 	m->cpuvendor = boot_cpu_data.x86_vendor;
140 	m->cpuid = cpuid_eax(1);
141 	m->socketid = cpu_data(m->extcpu).phys_proc_id;
142 	m->apicid = cpu_data(m->extcpu).initial_apicid;
143 	m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP);
144 
145 	if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
146 		m->ppin = __rdmsr(MSR_PPIN);
147 	else if (this_cpu_has(X86_FEATURE_AMD_PPIN))
148 		m->ppin = __rdmsr(MSR_AMD_PPIN);
149 
150 	m->microcode = boot_cpu_data.microcode;
151 }
152 
153 DEFINE_PER_CPU(struct mce, injectm);
154 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
155 
156 void mce_log(struct mce *m)
157 {
158 	if (!mce_gen_pool_add(m))
159 		irq_work_queue(&mce_irq_work);
160 }
161 EXPORT_SYMBOL_GPL(mce_log);
162 
163 void mce_register_decode_chain(struct notifier_block *nb)
164 {
165 	if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC))
166 		return;
167 
168 	blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
169 }
170 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
171 
172 void mce_unregister_decode_chain(struct notifier_block *nb)
173 {
174 	blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
175 }
176 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
177 
178 static inline u32 ctl_reg(int bank)
179 {
180 	return MSR_IA32_MCx_CTL(bank);
181 }
182 
183 static inline u32 status_reg(int bank)
184 {
185 	return MSR_IA32_MCx_STATUS(bank);
186 }
187 
188 static inline u32 addr_reg(int bank)
189 {
190 	return MSR_IA32_MCx_ADDR(bank);
191 }
192 
193 static inline u32 misc_reg(int bank)
194 {
195 	return MSR_IA32_MCx_MISC(bank);
196 }
197 
198 static inline u32 smca_ctl_reg(int bank)
199 {
200 	return MSR_AMD64_SMCA_MCx_CTL(bank);
201 }
202 
203 static inline u32 smca_status_reg(int bank)
204 {
205 	return MSR_AMD64_SMCA_MCx_STATUS(bank);
206 }
207 
208 static inline u32 smca_addr_reg(int bank)
209 {
210 	return MSR_AMD64_SMCA_MCx_ADDR(bank);
211 }
212 
213 static inline u32 smca_misc_reg(int bank)
214 {
215 	return MSR_AMD64_SMCA_MCx_MISC(bank);
216 }
217 
218 struct mca_msr_regs msr_ops = {
219 	.ctl	= ctl_reg,
220 	.status	= status_reg,
221 	.addr	= addr_reg,
222 	.misc	= misc_reg
223 };
224 
225 static void __print_mce(struct mce *m)
226 {
227 	pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
228 		 m->extcpu,
229 		 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
230 		 m->mcgstatus, m->bank, m->status);
231 
232 	if (m->ip) {
233 		pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
234 			!(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
235 			m->cs, m->ip);
236 
237 		if (m->cs == __KERNEL_CS)
238 			pr_cont("{%pS}", (void *)(unsigned long)m->ip);
239 		pr_cont("\n");
240 	}
241 
242 	pr_emerg(HW_ERR "TSC %llx ", m->tsc);
243 	if (m->addr)
244 		pr_cont("ADDR %llx ", m->addr);
245 	if (m->misc)
246 		pr_cont("MISC %llx ", m->misc);
247 
248 	if (mce_flags.smca) {
249 		if (m->synd)
250 			pr_cont("SYND %llx ", m->synd);
251 		if (m->ipid)
252 			pr_cont("IPID %llx ", m->ipid);
253 	}
254 
255 	pr_cont("\n");
256 
257 	/*
258 	 * Note this output is parsed by external tools and old fields
259 	 * should not be changed.
260 	 */
261 	pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
262 		m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
263 		m->microcode);
264 }
265 
266 static void print_mce(struct mce *m)
267 {
268 	__print_mce(m);
269 
270 	if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON)
271 		pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
272 }
273 
274 #define PANIC_TIMEOUT 5 /* 5 seconds */
275 
276 static atomic_t mce_panicked;
277 
278 static int fake_panic;
279 static atomic_t mce_fake_panicked;
280 
281 /* Panic in progress. Enable interrupts and wait for final IPI */
282 static void wait_for_panic(void)
283 {
284 	long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
285 
286 	preempt_disable();
287 	local_irq_enable();
288 	while (timeout-- > 0)
289 		udelay(1);
290 	if (panic_timeout == 0)
291 		panic_timeout = mca_cfg.panic_timeout;
292 	panic("Panicing machine check CPU died");
293 }
294 
295 static void mce_panic(const char *msg, struct mce *final, char *exp)
296 {
297 	int apei_err = 0;
298 	struct llist_node *pending;
299 	struct mce_evt_llist *l;
300 
301 	if (!fake_panic) {
302 		/*
303 		 * Make sure only one CPU runs in machine check panic
304 		 */
305 		if (atomic_inc_return(&mce_panicked) > 1)
306 			wait_for_panic();
307 		barrier();
308 
309 		bust_spinlocks(1);
310 		console_verbose();
311 	} else {
312 		/* Don't log too much for fake panic */
313 		if (atomic_inc_return(&mce_fake_panicked) > 1)
314 			return;
315 	}
316 	pending = mce_gen_pool_prepare_records();
317 	/* First print corrected ones that are still unlogged */
318 	llist_for_each_entry(l, pending, llnode) {
319 		struct mce *m = &l->mce;
320 		if (!(m->status & MCI_STATUS_UC)) {
321 			print_mce(m);
322 			if (!apei_err)
323 				apei_err = apei_write_mce(m);
324 		}
325 	}
326 	/* Now print uncorrected but with the final one last */
327 	llist_for_each_entry(l, pending, llnode) {
328 		struct mce *m = &l->mce;
329 		if (!(m->status & MCI_STATUS_UC))
330 			continue;
331 		if (!final || mce_cmp(m, final)) {
332 			print_mce(m);
333 			if (!apei_err)
334 				apei_err = apei_write_mce(m);
335 		}
336 	}
337 	if (final) {
338 		print_mce(final);
339 		if (!apei_err)
340 			apei_err = apei_write_mce(final);
341 	}
342 	if (cpu_missing)
343 		pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
344 	if (exp)
345 		pr_emerg(HW_ERR "Machine check: %s\n", exp);
346 	if (!fake_panic) {
347 		if (panic_timeout == 0)
348 			panic_timeout = mca_cfg.panic_timeout;
349 		panic(msg);
350 	} else
351 		pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
352 }
353 
354 /* Support code for software error injection */
355 
356 static int msr_to_offset(u32 msr)
357 {
358 	unsigned bank = __this_cpu_read(injectm.bank);
359 
360 	if (msr == mca_cfg.rip_msr)
361 		return offsetof(struct mce, ip);
362 	if (msr == msr_ops.status(bank))
363 		return offsetof(struct mce, status);
364 	if (msr == msr_ops.addr(bank))
365 		return offsetof(struct mce, addr);
366 	if (msr == msr_ops.misc(bank))
367 		return offsetof(struct mce, misc);
368 	if (msr == MSR_IA32_MCG_STATUS)
369 		return offsetof(struct mce, mcgstatus);
370 	return -1;
371 }
372 
373 /* MSR access wrappers used for error injection */
374 static u64 mce_rdmsrl(u32 msr)
375 {
376 	u64 v;
377 
378 	if (__this_cpu_read(injectm.finished)) {
379 		int offset = msr_to_offset(msr);
380 
381 		if (offset < 0)
382 			return 0;
383 		return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
384 	}
385 
386 	if (rdmsrl_safe(msr, &v)) {
387 		WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr);
388 		/*
389 		 * Return zero in case the access faulted. This should
390 		 * not happen normally but can happen if the CPU does
391 		 * something weird, or if the code is buggy.
392 		 */
393 		v = 0;
394 	}
395 
396 	return v;
397 }
398 
399 static void mce_wrmsrl(u32 msr, u64 v)
400 {
401 	if (__this_cpu_read(injectm.finished)) {
402 		int offset = msr_to_offset(msr);
403 
404 		if (offset >= 0)
405 			*(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
406 		return;
407 	}
408 	wrmsrl(msr, v);
409 }
410 
411 /*
412  * Collect all global (w.r.t. this processor) status about this machine
413  * check into our "mce" struct so that we can use it later to assess
414  * the severity of the problem as we read per-bank specific details.
415  */
416 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
417 {
418 	mce_setup(m);
419 
420 	m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
421 	if (regs) {
422 		/*
423 		 * Get the address of the instruction at the time of
424 		 * the machine check error.
425 		 */
426 		if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
427 			m->ip = regs->ip;
428 			m->cs = regs->cs;
429 
430 			/*
431 			 * When in VM86 mode make the cs look like ring 3
432 			 * always. This is a lie, but it's better than passing
433 			 * the additional vm86 bit around everywhere.
434 			 */
435 			if (v8086_mode(regs))
436 				m->cs |= 3;
437 		}
438 		/* Use accurate RIP reporting if available. */
439 		if (mca_cfg.rip_msr)
440 			m->ip = mce_rdmsrl(mca_cfg.rip_msr);
441 	}
442 }
443 
444 int mce_available(struct cpuinfo_x86 *c)
445 {
446 	if (mca_cfg.disabled)
447 		return 0;
448 	return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
449 }
450 
451 static void mce_schedule_work(void)
452 {
453 	if (!mce_gen_pool_empty())
454 		schedule_work(&mce_work);
455 }
456 
457 static void mce_irq_work_cb(struct irq_work *entry)
458 {
459 	mce_schedule_work();
460 }
461 
462 /*
463  * Check if the address reported by the CPU is in a format we can parse.
464  * It would be possible to add code for most other cases, but all would
465  * be somewhat complicated (e.g. segment offset would require an instruction
466  * parser). So only support physical addresses up to page granuality for now.
467  */
468 int mce_usable_address(struct mce *m)
469 {
470 	if (!(m->status & MCI_STATUS_ADDRV))
471 		return 0;
472 
473 	/* Checks after this one are Intel/Zhaoxin-specific: */
474 	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
475 	    boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
476 		return 1;
477 
478 	if (!(m->status & MCI_STATUS_MISCV))
479 		return 0;
480 
481 	if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
482 		return 0;
483 
484 	if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
485 		return 0;
486 
487 	return 1;
488 }
489 EXPORT_SYMBOL_GPL(mce_usable_address);
490 
491 bool mce_is_memory_error(struct mce *m)
492 {
493 	switch (m->cpuvendor) {
494 	case X86_VENDOR_AMD:
495 	case X86_VENDOR_HYGON:
496 		return amd_mce_is_memory_error(m);
497 
498 	case X86_VENDOR_INTEL:
499 	case X86_VENDOR_ZHAOXIN:
500 		/*
501 		 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
502 		 *
503 		 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
504 		 * indicating a memory error. Bit 8 is used for indicating a
505 		 * cache hierarchy error. The combination of bit 2 and bit 3
506 		 * is used for indicating a `generic' cache hierarchy error
507 		 * But we can't just blindly check the above bits, because if
508 		 * bit 11 is set, then it is a bus/interconnect error - and
509 		 * either way the above bits just gives more detail on what
510 		 * bus/interconnect error happened. Note that bit 12 can be
511 		 * ignored, as it's the "filter" bit.
512 		 */
513 		return (m->status & 0xef80) == BIT(7) ||
514 		       (m->status & 0xef00) == BIT(8) ||
515 		       (m->status & 0xeffc) == 0xc;
516 
517 	default:
518 		return false;
519 	}
520 }
521 EXPORT_SYMBOL_GPL(mce_is_memory_error);
522 
523 static bool whole_page(struct mce *m)
524 {
525 	if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV))
526 		return true;
527 
528 	return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT;
529 }
530 
531 bool mce_is_correctable(struct mce *m)
532 {
533 	if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
534 		return false;
535 
536 	if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED)
537 		return false;
538 
539 	if (m->status & MCI_STATUS_UC)
540 		return false;
541 
542 	return true;
543 }
544 EXPORT_SYMBOL_GPL(mce_is_correctable);
545 
546 static int mce_early_notifier(struct notifier_block *nb, unsigned long val,
547 			      void *data)
548 {
549 	struct mce *m = (struct mce *)data;
550 
551 	if (!m)
552 		return NOTIFY_DONE;
553 
554 	/* Emit the trace record: */
555 	trace_mce_record(m);
556 
557 	set_bit(0, &mce_need_notify);
558 
559 	mce_notify_irq();
560 
561 	return NOTIFY_DONE;
562 }
563 
564 static struct notifier_block early_nb = {
565 	.notifier_call	= mce_early_notifier,
566 	.priority	= MCE_PRIO_EARLY,
567 };
568 
569 static int uc_decode_notifier(struct notifier_block *nb, unsigned long val,
570 			      void *data)
571 {
572 	struct mce *mce = (struct mce *)data;
573 	unsigned long pfn;
574 
575 	if (!mce || !mce_usable_address(mce))
576 		return NOTIFY_DONE;
577 
578 	if (mce->severity != MCE_AO_SEVERITY &&
579 	    mce->severity != MCE_DEFERRED_SEVERITY)
580 		return NOTIFY_DONE;
581 
582 	pfn = mce->addr >> PAGE_SHIFT;
583 	if (!memory_failure(pfn, 0)) {
584 		set_mce_nospec(pfn, whole_page(mce));
585 		mce->kflags |= MCE_HANDLED_UC;
586 	}
587 
588 	return NOTIFY_OK;
589 }
590 
591 static struct notifier_block mce_uc_nb = {
592 	.notifier_call	= uc_decode_notifier,
593 	.priority	= MCE_PRIO_UC,
594 };
595 
596 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
597 				void *data)
598 {
599 	struct mce *m = (struct mce *)data;
600 
601 	if (!m)
602 		return NOTIFY_DONE;
603 
604 	if (mca_cfg.print_all || !m->kflags)
605 		__print_mce(m);
606 
607 	return NOTIFY_DONE;
608 }
609 
610 static struct notifier_block mce_default_nb = {
611 	.notifier_call	= mce_default_notifier,
612 	/* lowest prio, we want it to run last. */
613 	.priority	= MCE_PRIO_LOWEST,
614 };
615 
616 /*
617  * Read ADDR and MISC registers.
618  */
619 static void mce_read_aux(struct mce *m, int i)
620 {
621 	if (m->status & MCI_STATUS_MISCV)
622 		m->misc = mce_rdmsrl(msr_ops.misc(i));
623 
624 	if (m->status & MCI_STATUS_ADDRV) {
625 		m->addr = mce_rdmsrl(msr_ops.addr(i));
626 
627 		/*
628 		 * Mask the reported address by the reported granularity.
629 		 */
630 		if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
631 			u8 shift = MCI_MISC_ADDR_LSB(m->misc);
632 			m->addr >>= shift;
633 			m->addr <<= shift;
634 		}
635 
636 		/*
637 		 * Extract [55:<lsb>] where lsb is the least significant
638 		 * *valid* bit of the address bits.
639 		 */
640 		if (mce_flags.smca) {
641 			u8 lsb = (m->addr >> 56) & 0x3f;
642 
643 			m->addr &= GENMASK_ULL(55, lsb);
644 		}
645 	}
646 
647 	if (mce_flags.smca) {
648 		m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
649 
650 		if (m->status & MCI_STATUS_SYNDV)
651 			m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
652 	}
653 }
654 
655 DEFINE_PER_CPU(unsigned, mce_poll_count);
656 
657 /*
658  * Poll for corrected events or events that happened before reset.
659  * Those are just logged through /dev/mcelog.
660  *
661  * This is executed in standard interrupt context.
662  *
663  * Note: spec recommends to panic for fatal unsignalled
664  * errors here. However this would be quite problematic --
665  * we would need to reimplement the Monarch handling and
666  * it would mess up the exclusion between exception handler
667  * and poll handler -- * so we skip this for now.
668  * These cases should not happen anyways, or only when the CPU
669  * is already totally * confused. In this case it's likely it will
670  * not fully execute the machine check handler either.
671  */
672 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
673 {
674 	struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
675 	bool error_seen = false;
676 	struct mce m;
677 	int i;
678 
679 	this_cpu_inc(mce_poll_count);
680 
681 	mce_gather_info(&m, NULL);
682 
683 	if (flags & MCP_TIMESTAMP)
684 		m.tsc = rdtsc();
685 
686 	for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
687 		if (!mce_banks[i].ctl || !test_bit(i, *b))
688 			continue;
689 
690 		m.misc = 0;
691 		m.addr = 0;
692 		m.bank = i;
693 
694 		barrier();
695 		m.status = mce_rdmsrl(msr_ops.status(i));
696 
697 		/* If this entry is not valid, ignore it */
698 		if (!(m.status & MCI_STATUS_VAL))
699 			continue;
700 
701 		/*
702 		 * If we are logging everything (at CPU online) or this
703 		 * is a corrected error, then we must log it.
704 		 */
705 		if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
706 			goto log_it;
707 
708 		/*
709 		 * Newer Intel systems that support software error
710 		 * recovery need to make additional checks. Other
711 		 * CPUs should skip over uncorrected errors, but log
712 		 * everything else.
713 		 */
714 		if (!mca_cfg.ser) {
715 			if (m.status & MCI_STATUS_UC)
716 				continue;
717 			goto log_it;
718 		}
719 
720 		/* Log "not enabled" (speculative) errors */
721 		if (!(m.status & MCI_STATUS_EN))
722 			goto log_it;
723 
724 		/*
725 		 * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
726 		 * UC == 1 && PCC == 0 && S == 0
727 		 */
728 		if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
729 			goto log_it;
730 
731 		/*
732 		 * Skip anything else. Presumption is that our read of this
733 		 * bank is racing with a machine check. Leave the log alone
734 		 * for do_machine_check() to deal with it.
735 		 */
736 		continue;
737 
738 log_it:
739 		error_seen = true;
740 
741 		if (flags & MCP_DONTLOG)
742 			goto clear_it;
743 
744 		mce_read_aux(&m, i);
745 		m.severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
746 		/*
747 		 * Don't get the IP here because it's unlikely to
748 		 * have anything to do with the actual error location.
749 		 */
750 
751 		if (mca_cfg.dont_log_ce && !mce_usable_address(&m))
752 			goto clear_it;
753 
754 		mce_log(&m);
755 
756 clear_it:
757 		/*
758 		 * Clear state for this bank.
759 		 */
760 		mce_wrmsrl(msr_ops.status(i), 0);
761 	}
762 
763 	/*
764 	 * Don't clear MCG_STATUS here because it's only defined for
765 	 * exceptions.
766 	 */
767 
768 	sync_core();
769 
770 	return error_seen;
771 }
772 EXPORT_SYMBOL_GPL(machine_check_poll);
773 
774 /*
775  * Do a quick check if any of the events requires a panic.
776  * This decides if we keep the events around or clear them.
777  */
778 static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
779 			  struct pt_regs *regs)
780 {
781 	char *tmp = *msg;
782 	int i;
783 
784 	for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
785 		m->status = mce_rdmsrl(msr_ops.status(i));
786 		if (!(m->status & MCI_STATUS_VAL))
787 			continue;
788 
789 		__set_bit(i, validp);
790 		if (quirk_no_way_out)
791 			quirk_no_way_out(i, m, regs);
792 
793 		m->bank = i;
794 		if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
795 			mce_read_aux(m, i);
796 			*msg = tmp;
797 			return 1;
798 		}
799 	}
800 	return 0;
801 }
802 
803 /*
804  * Variable to establish order between CPUs while scanning.
805  * Each CPU spins initially until executing is equal its number.
806  */
807 static atomic_t mce_executing;
808 
809 /*
810  * Defines order of CPUs on entry. First CPU becomes Monarch.
811  */
812 static atomic_t mce_callin;
813 
814 /*
815  * Check if a timeout waiting for other CPUs happened.
816  */
817 static int mce_timed_out(u64 *t, const char *msg)
818 {
819 	/*
820 	 * The others already did panic for some reason.
821 	 * Bail out like in a timeout.
822 	 * rmb() to tell the compiler that system_state
823 	 * might have been modified by someone else.
824 	 */
825 	rmb();
826 	if (atomic_read(&mce_panicked))
827 		wait_for_panic();
828 	if (!mca_cfg.monarch_timeout)
829 		goto out;
830 	if ((s64)*t < SPINUNIT) {
831 		if (mca_cfg.tolerant <= 1)
832 			mce_panic(msg, NULL, NULL);
833 		cpu_missing = 1;
834 		return 1;
835 	}
836 	*t -= SPINUNIT;
837 out:
838 	touch_nmi_watchdog();
839 	return 0;
840 }
841 
842 /*
843  * The Monarch's reign.  The Monarch is the CPU who entered
844  * the machine check handler first. It waits for the others to
845  * raise the exception too and then grades them. When any
846  * error is fatal panic. Only then let the others continue.
847  *
848  * The other CPUs entering the MCE handler will be controlled by the
849  * Monarch. They are called Subjects.
850  *
851  * This way we prevent any potential data corruption in a unrecoverable case
852  * and also makes sure always all CPU's errors are examined.
853  *
854  * Also this detects the case of a machine check event coming from outer
855  * space (not detected by any CPUs) In this case some external agent wants
856  * us to shut down, so panic too.
857  *
858  * The other CPUs might still decide to panic if the handler happens
859  * in a unrecoverable place, but in this case the system is in a semi-stable
860  * state and won't corrupt anything by itself. It's ok to let the others
861  * continue for a bit first.
862  *
863  * All the spin loops have timeouts; when a timeout happens a CPU
864  * typically elects itself to be Monarch.
865  */
866 static void mce_reign(void)
867 {
868 	int cpu;
869 	struct mce *m = NULL;
870 	int global_worst = 0;
871 	char *msg = NULL;
872 	char *nmsg = NULL;
873 
874 	/*
875 	 * This CPU is the Monarch and the other CPUs have run
876 	 * through their handlers.
877 	 * Grade the severity of the errors of all the CPUs.
878 	 */
879 	for_each_possible_cpu(cpu) {
880 		int severity = mce_severity(&per_cpu(mces_seen, cpu),
881 					    mca_cfg.tolerant,
882 					    &nmsg, true);
883 		if (severity > global_worst) {
884 			msg = nmsg;
885 			global_worst = severity;
886 			m = &per_cpu(mces_seen, cpu);
887 		}
888 	}
889 
890 	/*
891 	 * Cannot recover? Panic here then.
892 	 * This dumps all the mces in the log buffer and stops the
893 	 * other CPUs.
894 	 */
895 	if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3)
896 		mce_panic("Fatal machine check", m, msg);
897 
898 	/*
899 	 * For UC somewhere we let the CPU who detects it handle it.
900 	 * Also must let continue the others, otherwise the handling
901 	 * CPU could deadlock on a lock.
902 	 */
903 
904 	/*
905 	 * No machine check event found. Must be some external
906 	 * source or one CPU is hung. Panic.
907 	 */
908 	if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3)
909 		mce_panic("Fatal machine check from unknown source", NULL, NULL);
910 
911 	/*
912 	 * Now clear all the mces_seen so that they don't reappear on
913 	 * the next mce.
914 	 */
915 	for_each_possible_cpu(cpu)
916 		memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
917 }
918 
919 static atomic_t global_nwo;
920 
921 /*
922  * Start of Monarch synchronization. This waits until all CPUs have
923  * entered the exception handler and then determines if any of them
924  * saw a fatal event that requires panic. Then it executes them
925  * in the entry order.
926  * TBD double check parallel CPU hotunplug
927  */
928 static int mce_start(int *no_way_out)
929 {
930 	int order;
931 	int cpus = num_online_cpus();
932 	u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
933 
934 	if (!timeout)
935 		return -1;
936 
937 	atomic_add(*no_way_out, &global_nwo);
938 	/*
939 	 * Rely on the implied barrier below, such that global_nwo
940 	 * is updated before mce_callin.
941 	 */
942 	order = atomic_inc_return(&mce_callin);
943 
944 	/*
945 	 * Wait for everyone.
946 	 */
947 	while (atomic_read(&mce_callin) != cpus) {
948 		if (mce_timed_out(&timeout,
949 				  "Timeout: Not all CPUs entered broadcast exception handler")) {
950 			atomic_set(&global_nwo, 0);
951 			return -1;
952 		}
953 		ndelay(SPINUNIT);
954 	}
955 
956 	/*
957 	 * mce_callin should be read before global_nwo
958 	 */
959 	smp_rmb();
960 
961 	if (order == 1) {
962 		/*
963 		 * Monarch: Starts executing now, the others wait.
964 		 */
965 		atomic_set(&mce_executing, 1);
966 	} else {
967 		/*
968 		 * Subject: Now start the scanning loop one by one in
969 		 * the original callin order.
970 		 * This way when there are any shared banks it will be
971 		 * only seen by one CPU before cleared, avoiding duplicates.
972 		 */
973 		while (atomic_read(&mce_executing) < order) {
974 			if (mce_timed_out(&timeout,
975 					  "Timeout: Subject CPUs unable to finish machine check processing")) {
976 				atomic_set(&global_nwo, 0);
977 				return -1;
978 			}
979 			ndelay(SPINUNIT);
980 		}
981 	}
982 
983 	/*
984 	 * Cache the global no_way_out state.
985 	 */
986 	*no_way_out = atomic_read(&global_nwo);
987 
988 	return order;
989 }
990 
991 /*
992  * Synchronize between CPUs after main scanning loop.
993  * This invokes the bulk of the Monarch processing.
994  */
995 static int mce_end(int order)
996 {
997 	int ret = -1;
998 	u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
999 
1000 	if (!timeout)
1001 		goto reset;
1002 	if (order < 0)
1003 		goto reset;
1004 
1005 	/*
1006 	 * Allow others to run.
1007 	 */
1008 	atomic_inc(&mce_executing);
1009 
1010 	if (order == 1) {
1011 		/* CHECKME: Can this race with a parallel hotplug? */
1012 		int cpus = num_online_cpus();
1013 
1014 		/*
1015 		 * Monarch: Wait for everyone to go through their scanning
1016 		 * loops.
1017 		 */
1018 		while (atomic_read(&mce_executing) <= cpus) {
1019 			if (mce_timed_out(&timeout,
1020 					  "Timeout: Monarch CPU unable to finish machine check processing"))
1021 				goto reset;
1022 			ndelay(SPINUNIT);
1023 		}
1024 
1025 		mce_reign();
1026 		barrier();
1027 		ret = 0;
1028 	} else {
1029 		/*
1030 		 * Subject: Wait for Monarch to finish.
1031 		 */
1032 		while (atomic_read(&mce_executing) != 0) {
1033 			if (mce_timed_out(&timeout,
1034 					  "Timeout: Monarch CPU did not finish machine check processing"))
1035 				goto reset;
1036 			ndelay(SPINUNIT);
1037 		}
1038 
1039 		/*
1040 		 * Don't reset anything. That's done by the Monarch.
1041 		 */
1042 		return 0;
1043 	}
1044 
1045 	/*
1046 	 * Reset all global state.
1047 	 */
1048 reset:
1049 	atomic_set(&global_nwo, 0);
1050 	atomic_set(&mce_callin, 0);
1051 	barrier();
1052 
1053 	/*
1054 	 * Let others run again.
1055 	 */
1056 	atomic_set(&mce_executing, 0);
1057 	return ret;
1058 }
1059 
1060 static void mce_clear_state(unsigned long *toclear)
1061 {
1062 	int i;
1063 
1064 	for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1065 		if (test_bit(i, toclear))
1066 			mce_wrmsrl(msr_ops.status(i), 0);
1067 	}
1068 }
1069 
1070 /*
1071  * Cases where we avoid rendezvous handler timeout:
1072  * 1) If this CPU is offline.
1073  *
1074  * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1075  *  skip those CPUs which remain looping in the 1st kernel - see
1076  *  crash_nmi_callback().
1077  *
1078  * Note: there still is a small window between kexec-ing and the new,
1079  * kdump kernel establishing a new #MC handler where a broadcasted MCE
1080  * might not get handled properly.
1081  */
1082 static noinstr bool mce_check_crashing_cpu(void)
1083 {
1084 	unsigned int cpu = smp_processor_id();
1085 
1086 	if (cpu_is_offline(cpu) ||
1087 	    (crashing_cpu != -1 && crashing_cpu != cpu)) {
1088 		u64 mcgstatus;
1089 
1090 		mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS);
1091 
1092 		if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
1093 			if (mcgstatus & MCG_STATUS_LMCES)
1094 				return false;
1095 		}
1096 
1097 		if (mcgstatus & MCG_STATUS_RIPV) {
1098 			__wrmsr(MSR_IA32_MCG_STATUS, 0, 0);
1099 			return true;
1100 		}
1101 	}
1102 	return false;
1103 }
1104 
1105 static void __mc_scan_banks(struct mce *m, struct mce *final,
1106 			    unsigned long *toclear, unsigned long *valid_banks,
1107 			    int no_way_out, int *worst)
1108 {
1109 	struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1110 	struct mca_config *cfg = &mca_cfg;
1111 	int severity, i;
1112 
1113 	for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1114 		__clear_bit(i, toclear);
1115 		if (!test_bit(i, valid_banks))
1116 			continue;
1117 
1118 		if (!mce_banks[i].ctl)
1119 			continue;
1120 
1121 		m->misc = 0;
1122 		m->addr = 0;
1123 		m->bank = i;
1124 
1125 		m->status = mce_rdmsrl(msr_ops.status(i));
1126 		if (!(m->status & MCI_STATUS_VAL))
1127 			continue;
1128 
1129 		/*
1130 		 * Corrected or non-signaled errors are handled by
1131 		 * machine_check_poll(). Leave them alone, unless this panics.
1132 		 */
1133 		if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1134 			!no_way_out)
1135 			continue;
1136 
1137 		/* Set taint even when machine check was not enabled. */
1138 		add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1139 
1140 		severity = mce_severity(m, cfg->tolerant, NULL, true);
1141 
1142 		/*
1143 		 * When machine check was for corrected/deferred handler don't
1144 		 * touch, unless we're panicking.
1145 		 */
1146 		if ((severity == MCE_KEEP_SEVERITY ||
1147 		     severity == MCE_UCNA_SEVERITY) && !no_way_out)
1148 			continue;
1149 
1150 		__set_bit(i, toclear);
1151 
1152 		/* Machine check event was not enabled. Clear, but ignore. */
1153 		if (severity == MCE_NO_SEVERITY)
1154 			continue;
1155 
1156 		mce_read_aux(m, i);
1157 
1158 		/* assuming valid severity level != 0 */
1159 		m->severity = severity;
1160 
1161 		mce_log(m);
1162 
1163 		if (severity > *worst) {
1164 			*final = *m;
1165 			*worst = severity;
1166 		}
1167 	}
1168 
1169 	/* mce_clear_state will clear *final, save locally for use later */
1170 	*m = *final;
1171 }
1172 
1173 static void kill_me_now(struct callback_head *ch)
1174 {
1175 	force_sig(SIGBUS);
1176 }
1177 
1178 static void kill_me_maybe(struct callback_head *cb)
1179 {
1180 	struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me);
1181 	int flags = MF_ACTION_REQUIRED;
1182 
1183 	pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr);
1184 
1185 	if (!p->mce_ripv)
1186 		flags |= MF_MUST_KILL;
1187 
1188 	if (!memory_failure(p->mce_addr >> PAGE_SHIFT, flags)) {
1189 		set_mce_nospec(p->mce_addr >> PAGE_SHIFT, p->mce_whole_page);
1190 		return;
1191 	}
1192 
1193 	pr_err("Memory error not recovered");
1194 	kill_me_now(cb);
1195 }
1196 
1197 /*
1198  * The actual machine check handler. This only handles real
1199  * exceptions when something got corrupted coming in through int 18.
1200  *
1201  * This is executed in NMI context not subject to normal locking rules. This
1202  * implies that most kernel services cannot be safely used. Don't even
1203  * think about putting a printk in there!
1204  *
1205  * On Intel systems this is entered on all CPUs in parallel through
1206  * MCE broadcast. However some CPUs might be broken beyond repair,
1207  * so be always careful when synchronizing with others.
1208  *
1209  * Tracing and kprobes are disabled: if we interrupted a kernel context
1210  * with IF=1, we need to minimize stack usage.  There are also recursion
1211  * issues: if the machine check was due to a failure of the memory
1212  * backing the user stack, tracing that reads the user stack will cause
1213  * potentially infinite recursion.
1214  */
1215 void noinstr do_machine_check(struct pt_regs *regs)
1216 {
1217 	DECLARE_BITMAP(valid_banks, MAX_NR_BANKS);
1218 	DECLARE_BITMAP(toclear, MAX_NR_BANKS);
1219 	struct mca_config *cfg = &mca_cfg;
1220 	struct mce m, *final;
1221 	char *msg = NULL;
1222 	int worst = 0;
1223 
1224 	/*
1225 	 * Establish sequential order between the CPUs entering the machine
1226 	 * check handler.
1227 	 */
1228 	int order = -1;
1229 
1230 	/*
1231 	 * If no_way_out gets set, there is no safe way to recover from this
1232 	 * MCE.  If mca_cfg.tolerant is cranked up, we'll try anyway.
1233 	 */
1234 	int no_way_out = 0;
1235 
1236 	/*
1237 	 * If kill_it gets set, there might be a way to recover from this
1238 	 * error.
1239 	 */
1240 	int kill_it = 0;
1241 
1242 	/*
1243 	 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1244 	 * on Intel.
1245 	 */
1246 	int lmce = 1;
1247 
1248 	this_cpu_inc(mce_exception_count);
1249 
1250 	mce_gather_info(&m, regs);
1251 	m.tsc = rdtsc();
1252 
1253 	final = this_cpu_ptr(&mces_seen);
1254 	*final = m;
1255 
1256 	memset(valid_banks, 0, sizeof(valid_banks));
1257 	no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1258 
1259 	barrier();
1260 
1261 	/*
1262 	 * When no restart IP might need to kill or panic.
1263 	 * Assume the worst for now, but if we find the
1264 	 * severity is MCE_AR_SEVERITY we have other options.
1265 	 */
1266 	if (!(m.mcgstatus & MCG_STATUS_RIPV))
1267 		kill_it = 1;
1268 
1269 	/*
1270 	 * Check if this MCE is signaled to only this logical processor,
1271 	 * on Intel, Zhaoxin only.
1272 	 */
1273 	if (m.cpuvendor == X86_VENDOR_INTEL ||
1274 	    m.cpuvendor == X86_VENDOR_ZHAOXIN)
1275 		lmce = m.mcgstatus & MCG_STATUS_LMCES;
1276 
1277 	/*
1278 	 * Local machine check may already know that we have to panic.
1279 	 * Broadcast machine check begins rendezvous in mce_start()
1280 	 * Go through all banks in exclusion of the other CPUs. This way we
1281 	 * don't report duplicated events on shared banks because the first one
1282 	 * to see it will clear it.
1283 	 */
1284 	if (lmce) {
1285 		if (no_way_out)
1286 			mce_panic("Fatal local machine check", &m, msg);
1287 	} else {
1288 		order = mce_start(&no_way_out);
1289 	}
1290 
1291 	__mc_scan_banks(&m, final, toclear, valid_banks, no_way_out, &worst);
1292 
1293 	if (!no_way_out)
1294 		mce_clear_state(toclear);
1295 
1296 	/*
1297 	 * Do most of the synchronization with other CPUs.
1298 	 * When there's any problem use only local no_way_out state.
1299 	 */
1300 	if (!lmce) {
1301 		if (mce_end(order) < 0)
1302 			no_way_out = worst >= MCE_PANIC_SEVERITY;
1303 	} else {
1304 		/*
1305 		 * If there was a fatal machine check we should have
1306 		 * already called mce_panic earlier in this function.
1307 		 * Since we re-read the banks, we might have found
1308 		 * something new. Check again to see if we found a
1309 		 * fatal error. We call "mce_severity()" again to
1310 		 * make sure we have the right "msg".
1311 		 */
1312 		if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) {
1313 			mce_severity(&m, cfg->tolerant, &msg, true);
1314 			mce_panic("Local fatal machine check!", &m, msg);
1315 		}
1316 	}
1317 
1318 	/*
1319 	 * If tolerant is at an insane level we drop requests to kill
1320 	 * processes and continue even when there is no way out.
1321 	 */
1322 	if (cfg->tolerant == 3)
1323 		kill_it = 0;
1324 	else if (no_way_out)
1325 		mce_panic("Fatal machine check on current CPU", &m, msg);
1326 
1327 	if (worst > 0)
1328 		irq_work_queue(&mce_irq_work);
1329 
1330 	mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1331 
1332 	sync_core();
1333 
1334 	if (worst != MCE_AR_SEVERITY && !kill_it)
1335 		return;
1336 
1337 	/* Fault was in user mode and we need to take some action */
1338 	if ((m.cs & 3) == 3) {
1339 		/* If this triggers there is no way to recover. Die hard. */
1340 		BUG_ON(!on_thread_stack() || !user_mode(regs));
1341 
1342 		current->mce_addr = m.addr;
1343 		current->mce_ripv = !!(m.mcgstatus & MCG_STATUS_RIPV);
1344 		current->mce_whole_page = whole_page(&m);
1345 		current->mce_kill_me.func = kill_me_maybe;
1346 		if (kill_it)
1347 			current->mce_kill_me.func = kill_me_now;
1348 		task_work_add(current, &current->mce_kill_me, true);
1349 	} else {
1350 		/*
1351 		 * Handle an MCE which has happened in kernel space but from
1352 		 * which the kernel can recover: ex_has_fault_handler() has
1353 		 * already verified that the rIP at which the error happened is
1354 		 * a rIP from which the kernel can recover (by jumping to
1355 		 * recovery code specified in _ASM_EXTABLE_FAULT()) and the
1356 		 * corresponding exception handler which would do that is the
1357 		 * proper one.
1358 		 */
1359 		if (m.kflags & MCE_IN_KERNEL_RECOV) {
1360 			if (!fixup_exception(regs, X86_TRAP_MC, 0, 0))
1361 				mce_panic("Failed kernel mode recovery", &m, msg);
1362 		}
1363 	}
1364 }
1365 EXPORT_SYMBOL_GPL(do_machine_check);
1366 
1367 #ifndef CONFIG_MEMORY_FAILURE
1368 int memory_failure(unsigned long pfn, int flags)
1369 {
1370 	/* mce_severity() should not hand us an ACTION_REQUIRED error */
1371 	BUG_ON(flags & MF_ACTION_REQUIRED);
1372 	pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1373 	       "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1374 	       pfn);
1375 
1376 	return 0;
1377 }
1378 #endif
1379 
1380 /*
1381  * Periodic polling timer for "silent" machine check errors.  If the
1382  * poller finds an MCE, poll 2x faster.  When the poller finds no more
1383  * errors, poll 2x slower (up to check_interval seconds).
1384  */
1385 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1386 
1387 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1388 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1389 
1390 static unsigned long mce_adjust_timer_default(unsigned long interval)
1391 {
1392 	return interval;
1393 }
1394 
1395 static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
1396 
1397 static void __start_timer(struct timer_list *t, unsigned long interval)
1398 {
1399 	unsigned long when = jiffies + interval;
1400 	unsigned long flags;
1401 
1402 	local_irq_save(flags);
1403 
1404 	if (!timer_pending(t) || time_before(when, t->expires))
1405 		mod_timer(t, round_jiffies(when));
1406 
1407 	local_irq_restore(flags);
1408 }
1409 
1410 static void mce_timer_fn(struct timer_list *t)
1411 {
1412 	struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
1413 	unsigned long iv;
1414 
1415 	WARN_ON(cpu_t != t);
1416 
1417 	iv = __this_cpu_read(mce_next_interval);
1418 
1419 	if (mce_available(this_cpu_ptr(&cpu_info))) {
1420 		machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1421 
1422 		if (mce_intel_cmci_poll()) {
1423 			iv = mce_adjust_timer(iv);
1424 			goto done;
1425 		}
1426 	}
1427 
1428 	/*
1429 	 * Alert userspace if needed. If we logged an MCE, reduce the polling
1430 	 * interval, otherwise increase the polling interval.
1431 	 */
1432 	if (mce_notify_irq())
1433 		iv = max(iv / 2, (unsigned long) HZ/100);
1434 	else
1435 		iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1436 
1437 done:
1438 	__this_cpu_write(mce_next_interval, iv);
1439 	__start_timer(t, iv);
1440 }
1441 
1442 /*
1443  * Ensure that the timer is firing in @interval from now.
1444  */
1445 void mce_timer_kick(unsigned long interval)
1446 {
1447 	struct timer_list *t = this_cpu_ptr(&mce_timer);
1448 	unsigned long iv = __this_cpu_read(mce_next_interval);
1449 
1450 	__start_timer(t, interval);
1451 
1452 	if (interval < iv)
1453 		__this_cpu_write(mce_next_interval, interval);
1454 }
1455 
1456 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1457 static void mce_timer_delete_all(void)
1458 {
1459 	int cpu;
1460 
1461 	for_each_online_cpu(cpu)
1462 		del_timer_sync(&per_cpu(mce_timer, cpu));
1463 }
1464 
1465 /*
1466  * Notify the user(s) about new machine check events.
1467  * Can be called from interrupt context, but not from machine check/NMI
1468  * context.
1469  */
1470 int mce_notify_irq(void)
1471 {
1472 	/* Not more than two messages every minute */
1473 	static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1474 
1475 	if (test_and_clear_bit(0, &mce_need_notify)) {
1476 		mce_work_trigger();
1477 
1478 		if (__ratelimit(&ratelimit))
1479 			pr_info(HW_ERR "Machine check events logged\n");
1480 
1481 		return 1;
1482 	}
1483 	return 0;
1484 }
1485 EXPORT_SYMBOL_GPL(mce_notify_irq);
1486 
1487 static void __mcheck_cpu_mce_banks_init(void)
1488 {
1489 	struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1490 	u8 n_banks = this_cpu_read(mce_num_banks);
1491 	int i;
1492 
1493 	for (i = 0; i < n_banks; i++) {
1494 		struct mce_bank *b = &mce_banks[i];
1495 
1496 		/*
1497 		 * Init them all, __mcheck_cpu_apply_quirks() is going to apply
1498 		 * the required vendor quirks before
1499 		 * __mcheck_cpu_init_clear_banks() does the final bank setup.
1500 		 */
1501 		b->ctl = -1ULL;
1502 		b->init = 1;
1503 	}
1504 }
1505 
1506 /*
1507  * Initialize Machine Checks for a CPU.
1508  */
1509 static void __mcheck_cpu_cap_init(void)
1510 {
1511 	u64 cap;
1512 	u8 b;
1513 
1514 	rdmsrl(MSR_IA32_MCG_CAP, cap);
1515 
1516 	b = cap & MCG_BANKCNT_MASK;
1517 
1518 	if (b > MAX_NR_BANKS) {
1519 		pr_warn("CPU%d: Using only %u machine check banks out of %u\n",
1520 			smp_processor_id(), MAX_NR_BANKS, b);
1521 		b = MAX_NR_BANKS;
1522 	}
1523 
1524 	this_cpu_write(mce_num_banks, b);
1525 
1526 	__mcheck_cpu_mce_banks_init();
1527 
1528 	/* Use accurate RIP reporting if available. */
1529 	if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1530 		mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1531 
1532 	if (cap & MCG_SER_P)
1533 		mca_cfg.ser = 1;
1534 }
1535 
1536 static void __mcheck_cpu_init_generic(void)
1537 {
1538 	enum mcp_flags m_fl = 0;
1539 	mce_banks_t all_banks;
1540 	u64 cap;
1541 
1542 	if (!mca_cfg.bootlog)
1543 		m_fl = MCP_DONTLOG;
1544 
1545 	/*
1546 	 * Log the machine checks left over from the previous reset.
1547 	 */
1548 	bitmap_fill(all_banks, MAX_NR_BANKS);
1549 	machine_check_poll(MCP_UC | m_fl, &all_banks);
1550 
1551 	cr4_set_bits(X86_CR4_MCE);
1552 
1553 	rdmsrl(MSR_IA32_MCG_CAP, cap);
1554 	if (cap & MCG_CTL_P)
1555 		wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1556 }
1557 
1558 static void __mcheck_cpu_init_clear_banks(void)
1559 {
1560 	struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1561 	int i;
1562 
1563 	for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1564 		struct mce_bank *b = &mce_banks[i];
1565 
1566 		if (!b->init)
1567 			continue;
1568 		wrmsrl(msr_ops.ctl(i), b->ctl);
1569 		wrmsrl(msr_ops.status(i), 0);
1570 	}
1571 }
1572 
1573 /*
1574  * Do a final check to see if there are any unused/RAZ banks.
1575  *
1576  * This must be done after the banks have been initialized and any quirks have
1577  * been applied.
1578  *
1579  * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs.
1580  * Otherwise, a user who disables a bank will not be able to re-enable it
1581  * without a system reboot.
1582  */
1583 static void __mcheck_cpu_check_banks(void)
1584 {
1585 	struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1586 	u64 msrval;
1587 	int i;
1588 
1589 	for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1590 		struct mce_bank *b = &mce_banks[i];
1591 
1592 		if (!b->init)
1593 			continue;
1594 
1595 		rdmsrl(msr_ops.ctl(i), msrval);
1596 		b->init = !!msrval;
1597 	}
1598 }
1599 
1600 /*
1601  * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
1602  * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
1603  * Vol 3B Table 15-20). But this confuses both the code that determines
1604  * whether the machine check occurred in kernel or user mode, and also
1605  * the severity assessment code. Pretend that EIPV was set, and take the
1606  * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
1607  */
1608 static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
1609 {
1610 	if (bank != 0)
1611 		return;
1612 	if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
1613 		return;
1614 	if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
1615 		          MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
1616 			  MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
1617 			  MCACOD)) !=
1618 			 (MCI_STATUS_UC|MCI_STATUS_EN|
1619 			  MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
1620 			  MCI_STATUS_AR|MCACOD_INSTR))
1621 		return;
1622 
1623 	m->mcgstatus |= MCG_STATUS_EIPV;
1624 	m->ip = regs->ip;
1625 	m->cs = regs->cs;
1626 }
1627 
1628 /* Add per CPU specific workarounds here */
1629 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1630 {
1631 	struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1632 	struct mca_config *cfg = &mca_cfg;
1633 
1634 	if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1635 		pr_info("unknown CPU type - not enabling MCE support\n");
1636 		return -EOPNOTSUPP;
1637 	}
1638 
1639 	/* This should be disabled by the BIOS, but isn't always */
1640 	if (c->x86_vendor == X86_VENDOR_AMD) {
1641 		if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
1642 			/*
1643 			 * disable GART TBL walk error reporting, which
1644 			 * trips off incorrectly with the IOMMU & 3ware
1645 			 * & Cerberus:
1646 			 */
1647 			clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1648 		}
1649 		if (c->x86 < 0x11 && cfg->bootlog < 0) {
1650 			/*
1651 			 * Lots of broken BIOS around that don't clear them
1652 			 * by default and leave crap in there. Don't log:
1653 			 */
1654 			cfg->bootlog = 0;
1655 		}
1656 		/*
1657 		 * Various K7s with broken bank 0 around. Always disable
1658 		 * by default.
1659 		 */
1660 		if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
1661 			mce_banks[0].ctl = 0;
1662 
1663 		/*
1664 		 * overflow_recov is supported for F15h Models 00h-0fh
1665 		 * even though we don't have a CPUID bit for it.
1666 		 */
1667 		if (c->x86 == 0x15 && c->x86_model <= 0xf)
1668 			mce_flags.overflow_recov = 1;
1669 
1670 	}
1671 
1672 	if (c->x86_vendor == X86_VENDOR_INTEL) {
1673 		/*
1674 		 * SDM documents that on family 6 bank 0 should not be written
1675 		 * because it aliases to another special BIOS controlled
1676 		 * register.
1677 		 * But it's not aliased anymore on model 0x1a+
1678 		 * Don't ignore bank 0 completely because there could be a
1679 		 * valid event later, merely don't write CTL0.
1680 		 */
1681 
1682 		if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
1683 			mce_banks[0].init = 0;
1684 
1685 		/*
1686 		 * All newer Intel systems support MCE broadcasting. Enable
1687 		 * synchronization with a one second timeout.
1688 		 */
1689 		if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1690 			cfg->monarch_timeout < 0)
1691 			cfg->monarch_timeout = USEC_PER_SEC;
1692 
1693 		/*
1694 		 * There are also broken BIOSes on some Pentium M and
1695 		 * earlier systems:
1696 		 */
1697 		if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1698 			cfg->bootlog = 0;
1699 
1700 		if (c->x86 == 6 && c->x86_model == 45)
1701 			quirk_no_way_out = quirk_sandybridge_ifu;
1702 	}
1703 
1704 	if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
1705 		/*
1706 		 * All newer Zhaoxin CPUs support MCE broadcasting. Enable
1707 		 * synchronization with a one second timeout.
1708 		 */
1709 		if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1710 			if (cfg->monarch_timeout < 0)
1711 				cfg->monarch_timeout = USEC_PER_SEC;
1712 		}
1713 	}
1714 
1715 	if (cfg->monarch_timeout < 0)
1716 		cfg->monarch_timeout = 0;
1717 	if (cfg->bootlog != 0)
1718 		cfg->panic_timeout = 30;
1719 
1720 	return 0;
1721 }
1722 
1723 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1724 {
1725 	if (c->x86 != 5)
1726 		return 0;
1727 
1728 	switch (c->x86_vendor) {
1729 	case X86_VENDOR_INTEL:
1730 		intel_p5_mcheck_init(c);
1731 		return 1;
1732 		break;
1733 	case X86_VENDOR_CENTAUR:
1734 		winchip_mcheck_init(c);
1735 		return 1;
1736 		break;
1737 	default:
1738 		return 0;
1739 	}
1740 
1741 	return 0;
1742 }
1743 
1744 /*
1745  * Init basic CPU features needed for early decoding of MCEs.
1746  */
1747 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1748 {
1749 	if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {
1750 		mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1751 		mce_flags.succor	 = !!cpu_has(c, X86_FEATURE_SUCCOR);
1752 		mce_flags.smca		 = !!cpu_has(c, X86_FEATURE_SMCA);
1753 		mce_flags.amd_threshold	 = 1;
1754 
1755 		if (mce_flags.smca) {
1756 			msr_ops.ctl	= smca_ctl_reg;
1757 			msr_ops.status	= smca_status_reg;
1758 			msr_ops.addr	= smca_addr_reg;
1759 			msr_ops.misc	= smca_misc_reg;
1760 		}
1761 	}
1762 }
1763 
1764 static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
1765 {
1766 	struct mca_config *cfg = &mca_cfg;
1767 
1768 	 /*
1769 	  * All newer Centaur CPUs support MCE broadcasting. Enable
1770 	  * synchronization with a one second timeout.
1771 	  */
1772 	if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
1773 	     c->x86 > 6) {
1774 		if (cfg->monarch_timeout < 0)
1775 			cfg->monarch_timeout = USEC_PER_SEC;
1776 	}
1777 }
1778 
1779 static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
1780 {
1781 	struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1782 
1783 	/*
1784 	 * These CPUs have MCA bank 8 which reports only one error type called
1785 	 * SVAD (System View Address Decoder). The reporting of that error is
1786 	 * controlled by IA32_MC8.CTL.0.
1787 	 *
1788 	 * If enabled, prefetching on these CPUs will cause SVAD MCE when
1789 	 * virtual machines start and result in a system  panic. Always disable
1790 	 * bank 8 SVAD error by default.
1791 	 */
1792 	if ((c->x86 == 7 && c->x86_model == 0x1b) ||
1793 	    (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1794 		if (this_cpu_read(mce_num_banks) > 8)
1795 			mce_banks[8].ctl = 0;
1796 	}
1797 
1798 	intel_init_cmci();
1799 	intel_init_lmce();
1800 	mce_adjust_timer = cmci_intel_adjust_timer;
1801 }
1802 
1803 static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
1804 {
1805 	intel_clear_lmce();
1806 }
1807 
1808 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1809 {
1810 	switch (c->x86_vendor) {
1811 	case X86_VENDOR_INTEL:
1812 		mce_intel_feature_init(c);
1813 		mce_adjust_timer = cmci_intel_adjust_timer;
1814 		break;
1815 
1816 	case X86_VENDOR_AMD: {
1817 		mce_amd_feature_init(c);
1818 		break;
1819 		}
1820 
1821 	case X86_VENDOR_HYGON:
1822 		mce_hygon_feature_init(c);
1823 		break;
1824 
1825 	case X86_VENDOR_CENTAUR:
1826 		mce_centaur_feature_init(c);
1827 		break;
1828 
1829 	case X86_VENDOR_ZHAOXIN:
1830 		mce_zhaoxin_feature_init(c);
1831 		break;
1832 
1833 	default:
1834 		break;
1835 	}
1836 }
1837 
1838 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
1839 {
1840 	switch (c->x86_vendor) {
1841 	case X86_VENDOR_INTEL:
1842 		mce_intel_feature_clear(c);
1843 		break;
1844 
1845 	case X86_VENDOR_ZHAOXIN:
1846 		mce_zhaoxin_feature_clear(c);
1847 		break;
1848 
1849 	default:
1850 		break;
1851 	}
1852 }
1853 
1854 static void mce_start_timer(struct timer_list *t)
1855 {
1856 	unsigned long iv = check_interval * HZ;
1857 
1858 	if (mca_cfg.ignore_ce || !iv)
1859 		return;
1860 
1861 	this_cpu_write(mce_next_interval, iv);
1862 	__start_timer(t, iv);
1863 }
1864 
1865 static void __mcheck_cpu_setup_timer(void)
1866 {
1867 	struct timer_list *t = this_cpu_ptr(&mce_timer);
1868 
1869 	timer_setup(t, mce_timer_fn, TIMER_PINNED);
1870 }
1871 
1872 static void __mcheck_cpu_init_timer(void)
1873 {
1874 	struct timer_list *t = this_cpu_ptr(&mce_timer);
1875 
1876 	timer_setup(t, mce_timer_fn, TIMER_PINNED);
1877 	mce_start_timer(t);
1878 }
1879 
1880 bool filter_mce(struct mce *m)
1881 {
1882 	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1883 		return amd_filter_mce(m);
1884 	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1885 		return intel_filter_mce(m);
1886 
1887 	return false;
1888 }
1889 
1890 /* Handle unconfigured int18 (should never happen) */
1891 static noinstr void unexpected_machine_check(struct pt_regs *regs)
1892 {
1893 	instrumentation_begin();
1894 	pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1895 	       smp_processor_id());
1896 	instrumentation_end();
1897 }
1898 
1899 /* Call the installed machine check handler for this CPU setup. */
1900 void (*machine_check_vector)(struct pt_regs *) = unexpected_machine_check;
1901 
1902 static __always_inline void exc_machine_check_kernel(struct pt_regs *regs)
1903 {
1904 	/*
1905 	 * Only required when from kernel mode. See
1906 	 * mce_check_crashing_cpu() for details.
1907 	 */
1908 	if (machine_check_vector == do_machine_check &&
1909 	    mce_check_crashing_cpu())
1910 		return;
1911 
1912 	nmi_enter();
1913 	/*
1914 	 * The call targets are marked noinstr, but objtool can't figure
1915 	 * that out because it's an indirect call. Annotate it.
1916 	 */
1917 	instrumentation_begin();
1918 	trace_hardirqs_off_finish();
1919 	machine_check_vector(regs);
1920 	if (regs->flags & X86_EFLAGS_IF)
1921 		trace_hardirqs_on_prepare();
1922 	instrumentation_end();
1923 	nmi_exit();
1924 }
1925 
1926 static __always_inline void exc_machine_check_user(struct pt_regs *regs)
1927 {
1928 	idtentry_enter_user(regs);
1929 	instrumentation_begin();
1930 	machine_check_vector(regs);
1931 	instrumentation_end();
1932 	idtentry_exit_user(regs);
1933 }
1934 
1935 #ifdef CONFIG_X86_64
1936 /* MCE hit kernel mode */
1937 DEFINE_IDTENTRY_MCE(exc_machine_check)
1938 {
1939 	unsigned long dr7;
1940 
1941 	dr7 = local_db_save();
1942 	exc_machine_check_kernel(regs);
1943 	local_db_restore(dr7);
1944 }
1945 
1946 /* The user mode variant. */
1947 DEFINE_IDTENTRY_MCE_USER(exc_machine_check)
1948 {
1949 	unsigned long dr7;
1950 
1951 	dr7 = local_db_save();
1952 	exc_machine_check_user(regs);
1953 	local_db_restore(dr7);
1954 }
1955 #else
1956 /* 32bit unified entry point */
1957 DEFINE_IDTENTRY_MCE(exc_machine_check)
1958 {
1959 	unsigned long dr7;
1960 
1961 	dr7 = local_db_save();
1962 	if (user_mode(regs))
1963 		exc_machine_check_user(regs);
1964 	else
1965 		exc_machine_check_kernel(regs);
1966 	local_db_restore(dr7);
1967 }
1968 #endif
1969 
1970 /*
1971  * Called for each booted CPU to set up machine checks.
1972  * Must be called with preempt off:
1973  */
1974 void mcheck_cpu_init(struct cpuinfo_x86 *c)
1975 {
1976 	if (mca_cfg.disabled)
1977 		return;
1978 
1979 	if (__mcheck_cpu_ancient_init(c))
1980 		return;
1981 
1982 	if (!mce_available(c))
1983 		return;
1984 
1985 	__mcheck_cpu_cap_init();
1986 
1987 	if (__mcheck_cpu_apply_quirks(c) < 0) {
1988 		mca_cfg.disabled = 1;
1989 		return;
1990 	}
1991 
1992 	if (mce_gen_pool_init()) {
1993 		mca_cfg.disabled = 1;
1994 		pr_emerg("Couldn't allocate MCE records pool!\n");
1995 		return;
1996 	}
1997 
1998 	machine_check_vector = do_machine_check;
1999 
2000 	__mcheck_cpu_init_early(c);
2001 	__mcheck_cpu_init_generic();
2002 	__mcheck_cpu_init_vendor(c);
2003 	__mcheck_cpu_init_clear_banks();
2004 	__mcheck_cpu_check_banks();
2005 	__mcheck_cpu_setup_timer();
2006 }
2007 
2008 /*
2009  * Called for each booted CPU to clear some machine checks opt-ins
2010  */
2011 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
2012 {
2013 	if (mca_cfg.disabled)
2014 		return;
2015 
2016 	if (!mce_available(c))
2017 		return;
2018 
2019 	/*
2020 	 * Possibly to clear general settings generic to x86
2021 	 * __mcheck_cpu_clear_generic(c);
2022 	 */
2023 	__mcheck_cpu_clear_vendor(c);
2024 
2025 }
2026 
2027 static void __mce_disable_bank(void *arg)
2028 {
2029 	int bank = *((int *)arg);
2030 	__clear_bit(bank, this_cpu_ptr(mce_poll_banks));
2031 	cmci_disable_bank(bank);
2032 }
2033 
2034 void mce_disable_bank(int bank)
2035 {
2036 	if (bank >= this_cpu_read(mce_num_banks)) {
2037 		pr_warn(FW_BUG
2038 			"Ignoring request to disable invalid MCA bank %d.\n",
2039 			bank);
2040 		return;
2041 	}
2042 	set_bit(bank, mce_banks_ce_disabled);
2043 	on_each_cpu(__mce_disable_bank, &bank, 1);
2044 }
2045 
2046 /*
2047  * mce=off Disables machine check
2048  * mce=no_cmci Disables CMCI
2049  * mce=no_lmce Disables LMCE
2050  * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
2051  * mce=print_all Print all machine check logs to console
2052  * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
2053  * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
2054  *	monarchtimeout is how long to wait for other CPUs on machine
2055  *	check, or 0 to not wait
2056  * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
2057 	and older.
2058  * mce=nobootlog Don't log MCEs from before booting.
2059  * mce=bios_cmci_threshold Don't program the CMCI threshold
2060  * mce=recovery force enable memcpy_mcsafe()
2061  */
2062 static int __init mcheck_enable(char *str)
2063 {
2064 	struct mca_config *cfg = &mca_cfg;
2065 
2066 	if (*str == 0) {
2067 		enable_p5_mce();
2068 		return 1;
2069 	}
2070 	if (*str == '=')
2071 		str++;
2072 	if (!strcmp(str, "off"))
2073 		cfg->disabled = 1;
2074 	else if (!strcmp(str, "no_cmci"))
2075 		cfg->cmci_disabled = true;
2076 	else if (!strcmp(str, "no_lmce"))
2077 		cfg->lmce_disabled = 1;
2078 	else if (!strcmp(str, "dont_log_ce"))
2079 		cfg->dont_log_ce = true;
2080 	else if (!strcmp(str, "print_all"))
2081 		cfg->print_all = true;
2082 	else if (!strcmp(str, "ignore_ce"))
2083 		cfg->ignore_ce = true;
2084 	else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
2085 		cfg->bootlog = (str[0] == 'b');
2086 	else if (!strcmp(str, "bios_cmci_threshold"))
2087 		cfg->bios_cmci_threshold = 1;
2088 	else if (!strcmp(str, "recovery"))
2089 		cfg->recovery = 1;
2090 	else if (isdigit(str[0])) {
2091 		if (get_option(&str, &cfg->tolerant) == 2)
2092 			get_option(&str, &(cfg->monarch_timeout));
2093 	} else {
2094 		pr_info("mce argument %s ignored. Please use /sys\n", str);
2095 		return 0;
2096 	}
2097 	return 1;
2098 }
2099 __setup("mce", mcheck_enable);
2100 
2101 int __init mcheck_init(void)
2102 {
2103 	mcheck_intel_therm_init();
2104 	mce_register_decode_chain(&early_nb);
2105 	mce_register_decode_chain(&mce_uc_nb);
2106 	mce_register_decode_chain(&mce_default_nb);
2107 	mcheck_vendor_init_severity();
2108 
2109 	INIT_WORK(&mce_work, mce_gen_pool_process);
2110 	init_irq_work(&mce_irq_work, mce_irq_work_cb);
2111 
2112 	return 0;
2113 }
2114 
2115 /*
2116  * mce_syscore: PM support
2117  */
2118 
2119 /*
2120  * Disable machine checks on suspend and shutdown. We can't really handle
2121  * them later.
2122  */
2123 static void mce_disable_error_reporting(void)
2124 {
2125 	struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2126 	int i;
2127 
2128 	for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2129 		struct mce_bank *b = &mce_banks[i];
2130 
2131 		if (b->init)
2132 			wrmsrl(msr_ops.ctl(i), 0);
2133 	}
2134 	return;
2135 }
2136 
2137 static void vendor_disable_error_reporting(void)
2138 {
2139 	/*
2140 	 * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
2141 	 * MSRs are socket-wide. Disabling them for just a single offlined CPU
2142 	 * is bad, since it will inhibit reporting for all shared resources on
2143 	 * the socket like the last level cache (LLC), the integrated memory
2144 	 * controller (iMC), etc.
2145 	 */
2146 	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
2147 	    boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
2148 	    boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
2149 	    boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
2150 		return;
2151 
2152 	mce_disable_error_reporting();
2153 }
2154 
2155 static int mce_syscore_suspend(void)
2156 {
2157 	vendor_disable_error_reporting();
2158 	return 0;
2159 }
2160 
2161 static void mce_syscore_shutdown(void)
2162 {
2163 	vendor_disable_error_reporting();
2164 }
2165 
2166 /*
2167  * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2168  * Only one CPU is active at this time, the others get re-added later using
2169  * CPU hotplug:
2170  */
2171 static void mce_syscore_resume(void)
2172 {
2173 	__mcheck_cpu_init_generic();
2174 	__mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2175 	__mcheck_cpu_init_clear_banks();
2176 }
2177 
2178 static struct syscore_ops mce_syscore_ops = {
2179 	.suspend	= mce_syscore_suspend,
2180 	.shutdown	= mce_syscore_shutdown,
2181 	.resume		= mce_syscore_resume,
2182 };
2183 
2184 /*
2185  * mce_device: Sysfs support
2186  */
2187 
2188 static void mce_cpu_restart(void *data)
2189 {
2190 	if (!mce_available(raw_cpu_ptr(&cpu_info)))
2191 		return;
2192 	__mcheck_cpu_init_generic();
2193 	__mcheck_cpu_init_clear_banks();
2194 	__mcheck_cpu_init_timer();
2195 }
2196 
2197 /* Reinit MCEs after user configuration changes */
2198 static void mce_restart(void)
2199 {
2200 	mce_timer_delete_all();
2201 	on_each_cpu(mce_cpu_restart, NULL, 1);
2202 }
2203 
2204 /* Toggle features for corrected errors */
2205 static void mce_disable_cmci(void *data)
2206 {
2207 	if (!mce_available(raw_cpu_ptr(&cpu_info)))
2208 		return;
2209 	cmci_clear();
2210 }
2211 
2212 static void mce_enable_ce(void *all)
2213 {
2214 	if (!mce_available(raw_cpu_ptr(&cpu_info)))
2215 		return;
2216 	cmci_reenable();
2217 	cmci_recheck();
2218 	if (all)
2219 		__mcheck_cpu_init_timer();
2220 }
2221 
2222 static struct bus_type mce_subsys = {
2223 	.name		= "machinecheck",
2224 	.dev_name	= "machinecheck",
2225 };
2226 
2227 DEFINE_PER_CPU(struct device *, mce_device);
2228 
2229 static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr)
2230 {
2231 	return container_of(attr, struct mce_bank_dev, attr);
2232 }
2233 
2234 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2235 			 char *buf)
2236 {
2237 	u8 bank = attr_to_bank(attr)->bank;
2238 	struct mce_bank *b;
2239 
2240 	if (bank >= per_cpu(mce_num_banks, s->id))
2241 		return -EINVAL;
2242 
2243 	b = &per_cpu(mce_banks_array, s->id)[bank];
2244 
2245 	if (!b->init)
2246 		return -ENODEV;
2247 
2248 	return sprintf(buf, "%llx\n", b->ctl);
2249 }
2250 
2251 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2252 			const char *buf, size_t size)
2253 {
2254 	u8 bank = attr_to_bank(attr)->bank;
2255 	struct mce_bank *b;
2256 	u64 new;
2257 
2258 	if (kstrtou64(buf, 0, &new) < 0)
2259 		return -EINVAL;
2260 
2261 	if (bank >= per_cpu(mce_num_banks, s->id))
2262 		return -EINVAL;
2263 
2264 	b = &per_cpu(mce_banks_array, s->id)[bank];
2265 
2266 	if (!b->init)
2267 		return -ENODEV;
2268 
2269 	b->ctl = new;
2270 	mce_restart();
2271 
2272 	return size;
2273 }
2274 
2275 static ssize_t set_ignore_ce(struct device *s,
2276 			     struct device_attribute *attr,
2277 			     const char *buf, size_t size)
2278 {
2279 	u64 new;
2280 
2281 	if (kstrtou64(buf, 0, &new) < 0)
2282 		return -EINVAL;
2283 
2284 	mutex_lock(&mce_sysfs_mutex);
2285 	if (mca_cfg.ignore_ce ^ !!new) {
2286 		if (new) {
2287 			/* disable ce features */
2288 			mce_timer_delete_all();
2289 			on_each_cpu(mce_disable_cmci, NULL, 1);
2290 			mca_cfg.ignore_ce = true;
2291 		} else {
2292 			/* enable ce features */
2293 			mca_cfg.ignore_ce = false;
2294 			on_each_cpu(mce_enable_ce, (void *)1, 1);
2295 		}
2296 	}
2297 	mutex_unlock(&mce_sysfs_mutex);
2298 
2299 	return size;
2300 }
2301 
2302 static ssize_t set_cmci_disabled(struct device *s,
2303 				 struct device_attribute *attr,
2304 				 const char *buf, size_t size)
2305 {
2306 	u64 new;
2307 
2308 	if (kstrtou64(buf, 0, &new) < 0)
2309 		return -EINVAL;
2310 
2311 	mutex_lock(&mce_sysfs_mutex);
2312 	if (mca_cfg.cmci_disabled ^ !!new) {
2313 		if (new) {
2314 			/* disable cmci */
2315 			on_each_cpu(mce_disable_cmci, NULL, 1);
2316 			mca_cfg.cmci_disabled = true;
2317 		} else {
2318 			/* enable cmci */
2319 			mca_cfg.cmci_disabled = false;
2320 			on_each_cpu(mce_enable_ce, NULL, 1);
2321 		}
2322 	}
2323 	mutex_unlock(&mce_sysfs_mutex);
2324 
2325 	return size;
2326 }
2327 
2328 static ssize_t store_int_with_restart(struct device *s,
2329 				      struct device_attribute *attr,
2330 				      const char *buf, size_t size)
2331 {
2332 	unsigned long old_check_interval = check_interval;
2333 	ssize_t ret = device_store_ulong(s, attr, buf, size);
2334 
2335 	if (check_interval == old_check_interval)
2336 		return ret;
2337 
2338 	mutex_lock(&mce_sysfs_mutex);
2339 	mce_restart();
2340 	mutex_unlock(&mce_sysfs_mutex);
2341 
2342 	return ret;
2343 }
2344 
2345 static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant);
2346 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2347 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2348 static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all);
2349 
2350 static struct dev_ext_attribute dev_attr_check_interval = {
2351 	__ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2352 	&check_interval
2353 };
2354 
2355 static struct dev_ext_attribute dev_attr_ignore_ce = {
2356 	__ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2357 	&mca_cfg.ignore_ce
2358 };
2359 
2360 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2361 	__ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2362 	&mca_cfg.cmci_disabled
2363 };
2364 
2365 static struct device_attribute *mce_device_attrs[] = {
2366 	&dev_attr_tolerant.attr,
2367 	&dev_attr_check_interval.attr,
2368 #ifdef CONFIG_X86_MCELOG_LEGACY
2369 	&dev_attr_trigger,
2370 #endif
2371 	&dev_attr_monarch_timeout.attr,
2372 	&dev_attr_dont_log_ce.attr,
2373 	&dev_attr_print_all.attr,
2374 	&dev_attr_ignore_ce.attr,
2375 	&dev_attr_cmci_disabled.attr,
2376 	NULL
2377 };
2378 
2379 static cpumask_var_t mce_device_initialized;
2380 
2381 static void mce_device_release(struct device *dev)
2382 {
2383 	kfree(dev);
2384 }
2385 
2386 /* Per CPU device init. All of the CPUs still share the same bank device: */
2387 static int mce_device_create(unsigned int cpu)
2388 {
2389 	struct device *dev;
2390 	int err;
2391 	int i, j;
2392 
2393 	if (!mce_available(&boot_cpu_data))
2394 		return -EIO;
2395 
2396 	dev = per_cpu(mce_device, cpu);
2397 	if (dev)
2398 		return 0;
2399 
2400 	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2401 	if (!dev)
2402 		return -ENOMEM;
2403 	dev->id  = cpu;
2404 	dev->bus = &mce_subsys;
2405 	dev->release = &mce_device_release;
2406 
2407 	err = device_register(dev);
2408 	if (err) {
2409 		put_device(dev);
2410 		return err;
2411 	}
2412 
2413 	for (i = 0; mce_device_attrs[i]; i++) {
2414 		err = device_create_file(dev, mce_device_attrs[i]);
2415 		if (err)
2416 			goto error;
2417 	}
2418 	for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) {
2419 		err = device_create_file(dev, &mce_bank_devs[j].attr);
2420 		if (err)
2421 			goto error2;
2422 	}
2423 	cpumask_set_cpu(cpu, mce_device_initialized);
2424 	per_cpu(mce_device, cpu) = dev;
2425 
2426 	return 0;
2427 error2:
2428 	while (--j >= 0)
2429 		device_remove_file(dev, &mce_bank_devs[j].attr);
2430 error:
2431 	while (--i >= 0)
2432 		device_remove_file(dev, mce_device_attrs[i]);
2433 
2434 	device_unregister(dev);
2435 
2436 	return err;
2437 }
2438 
2439 static void mce_device_remove(unsigned int cpu)
2440 {
2441 	struct device *dev = per_cpu(mce_device, cpu);
2442 	int i;
2443 
2444 	if (!cpumask_test_cpu(cpu, mce_device_initialized))
2445 		return;
2446 
2447 	for (i = 0; mce_device_attrs[i]; i++)
2448 		device_remove_file(dev, mce_device_attrs[i]);
2449 
2450 	for (i = 0; i < per_cpu(mce_num_banks, cpu); i++)
2451 		device_remove_file(dev, &mce_bank_devs[i].attr);
2452 
2453 	device_unregister(dev);
2454 	cpumask_clear_cpu(cpu, mce_device_initialized);
2455 	per_cpu(mce_device, cpu) = NULL;
2456 }
2457 
2458 /* Make sure there are no machine checks on offlined CPUs. */
2459 static void mce_disable_cpu(void)
2460 {
2461 	if (!mce_available(raw_cpu_ptr(&cpu_info)))
2462 		return;
2463 
2464 	if (!cpuhp_tasks_frozen)
2465 		cmci_clear();
2466 
2467 	vendor_disable_error_reporting();
2468 }
2469 
2470 static void mce_reenable_cpu(void)
2471 {
2472 	struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2473 	int i;
2474 
2475 	if (!mce_available(raw_cpu_ptr(&cpu_info)))
2476 		return;
2477 
2478 	if (!cpuhp_tasks_frozen)
2479 		cmci_reenable();
2480 	for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2481 		struct mce_bank *b = &mce_banks[i];
2482 
2483 		if (b->init)
2484 			wrmsrl(msr_ops.ctl(i), b->ctl);
2485 	}
2486 }
2487 
2488 static int mce_cpu_dead(unsigned int cpu)
2489 {
2490 	mce_intel_hcpu_update(cpu);
2491 
2492 	/* intentionally ignoring frozen here */
2493 	if (!cpuhp_tasks_frozen)
2494 		cmci_rediscover();
2495 	return 0;
2496 }
2497 
2498 static int mce_cpu_online(unsigned int cpu)
2499 {
2500 	struct timer_list *t = this_cpu_ptr(&mce_timer);
2501 	int ret;
2502 
2503 	mce_device_create(cpu);
2504 
2505 	ret = mce_threshold_create_device(cpu);
2506 	if (ret) {
2507 		mce_device_remove(cpu);
2508 		return ret;
2509 	}
2510 	mce_reenable_cpu();
2511 	mce_start_timer(t);
2512 	return 0;
2513 }
2514 
2515 static int mce_cpu_pre_down(unsigned int cpu)
2516 {
2517 	struct timer_list *t = this_cpu_ptr(&mce_timer);
2518 
2519 	mce_disable_cpu();
2520 	del_timer_sync(t);
2521 	mce_threshold_remove_device(cpu);
2522 	mce_device_remove(cpu);
2523 	return 0;
2524 }
2525 
2526 static __init void mce_init_banks(void)
2527 {
2528 	int i;
2529 
2530 	for (i = 0; i < MAX_NR_BANKS; i++) {
2531 		struct mce_bank_dev *b = &mce_bank_devs[i];
2532 		struct device_attribute *a = &b->attr;
2533 
2534 		b->bank = i;
2535 
2536 		sysfs_attr_init(&a->attr);
2537 		a->attr.name	= b->attrname;
2538 		snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2539 
2540 		a->attr.mode	= 0644;
2541 		a->show		= show_bank;
2542 		a->store	= set_bank;
2543 	}
2544 }
2545 
2546 /*
2547  * When running on XEN, this initcall is ordered against the XEN mcelog
2548  * initcall:
2549  *
2550  *   device_initcall(xen_late_init_mcelog);
2551  *   device_initcall_sync(mcheck_init_device);
2552  */
2553 static __init int mcheck_init_device(void)
2554 {
2555 	int err;
2556 
2557 	/*
2558 	 * Check if we have a spare virtual bit. This will only become
2559 	 * a problem if/when we move beyond 5-level page tables.
2560 	 */
2561 	MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
2562 
2563 	if (!mce_available(&boot_cpu_data)) {
2564 		err = -EIO;
2565 		goto err_out;
2566 	}
2567 
2568 	if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2569 		err = -ENOMEM;
2570 		goto err_out;
2571 	}
2572 
2573 	mce_init_banks();
2574 
2575 	err = subsys_system_register(&mce_subsys, NULL);
2576 	if (err)
2577 		goto err_out_mem;
2578 
2579 	err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2580 				mce_cpu_dead);
2581 	if (err)
2582 		goto err_out_mem;
2583 
2584 	/*
2585 	 * Invokes mce_cpu_online() on all CPUs which are online when
2586 	 * the state is installed.
2587 	 */
2588 	err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2589 				mce_cpu_online, mce_cpu_pre_down);
2590 	if (err < 0)
2591 		goto err_out_online;
2592 
2593 	register_syscore_ops(&mce_syscore_ops);
2594 
2595 	return 0;
2596 
2597 err_out_online:
2598 	cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2599 
2600 err_out_mem:
2601 	free_cpumask_var(mce_device_initialized);
2602 
2603 err_out:
2604 	pr_err("Unable to init MCE device (rc: %d)\n", err);
2605 
2606 	return err;
2607 }
2608 device_initcall_sync(mcheck_init_device);
2609 
2610 /*
2611  * Old style boot options parsing. Only for compatibility.
2612  */
2613 static int __init mcheck_disable(char *str)
2614 {
2615 	mca_cfg.disabled = 1;
2616 	return 1;
2617 }
2618 __setup("nomce", mcheck_disable);
2619 
2620 #ifdef CONFIG_DEBUG_FS
2621 struct dentry *mce_get_debugfs_dir(void)
2622 {
2623 	static struct dentry *dmce;
2624 
2625 	if (!dmce)
2626 		dmce = debugfs_create_dir("mce", NULL);
2627 
2628 	return dmce;
2629 }
2630 
2631 static void mce_reset(void)
2632 {
2633 	cpu_missing = 0;
2634 	atomic_set(&mce_fake_panicked, 0);
2635 	atomic_set(&mce_executing, 0);
2636 	atomic_set(&mce_callin, 0);
2637 	atomic_set(&global_nwo, 0);
2638 }
2639 
2640 static int fake_panic_get(void *data, u64 *val)
2641 {
2642 	*val = fake_panic;
2643 	return 0;
2644 }
2645 
2646 static int fake_panic_set(void *data, u64 val)
2647 {
2648 	mce_reset();
2649 	fake_panic = val;
2650 	return 0;
2651 }
2652 
2653 DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set,
2654 			 "%llu\n");
2655 
2656 static void __init mcheck_debugfs_init(void)
2657 {
2658 	struct dentry *dmce;
2659 
2660 	dmce = mce_get_debugfs_dir();
2661 	debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL,
2662 				   &fake_panic_fops);
2663 }
2664 #else
2665 static void __init mcheck_debugfs_init(void) { }
2666 #endif
2667 
2668 DEFINE_STATIC_KEY_FALSE(mcsafe_key);
2669 EXPORT_SYMBOL_GPL(mcsafe_key);
2670 
2671 static int __init mcheck_late_init(void)
2672 {
2673 	if (mca_cfg.recovery)
2674 		static_branch_inc(&mcsafe_key);
2675 
2676 	mcheck_debugfs_init();
2677 
2678 	/*
2679 	 * Flush out everything that has been logged during early boot, now that
2680 	 * everything has been initialized (workqueues, decoders, ...).
2681 	 */
2682 	mce_schedule_work();
2683 
2684 	return 0;
2685 }
2686 late_initcall(mcheck_late_init);
2687