1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 221afaf18SBorislav Petkov /* 321afaf18SBorislav Petkov * Machine check handler. 421afaf18SBorislav Petkov * 521afaf18SBorislav Petkov * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. 621afaf18SBorislav Petkov * Rest from unknown author(s). 721afaf18SBorislav Petkov * 2004 Andi Kleen. Rewrote most of it. 821afaf18SBorislav Petkov * Copyright 2008 Intel Corporation 921afaf18SBorislav Petkov * Author: Andi Kleen 1021afaf18SBorislav Petkov */ 1121afaf18SBorislav Petkov 1221afaf18SBorislav Petkov #include <linux/thread_info.h> 1321afaf18SBorislav Petkov #include <linux/capability.h> 1421afaf18SBorislav Petkov #include <linux/miscdevice.h> 1521afaf18SBorislav Petkov #include <linux/ratelimit.h> 1621afaf18SBorislav Petkov #include <linux/rcupdate.h> 1721afaf18SBorislav Petkov #include <linux/kobject.h> 1821afaf18SBorislav Petkov #include <linux/uaccess.h> 1921afaf18SBorislav Petkov #include <linux/kdebug.h> 2021afaf18SBorislav Petkov #include <linux/kernel.h> 2121afaf18SBorislav Petkov #include <linux/percpu.h> 2221afaf18SBorislav Petkov #include <linux/string.h> 2321afaf18SBorislav Petkov #include <linux/device.h> 2421afaf18SBorislav Petkov #include <linux/syscore_ops.h> 2521afaf18SBorislav Petkov #include <linux/delay.h> 2621afaf18SBorislav Petkov #include <linux/ctype.h> 2721afaf18SBorislav Petkov #include <linux/sched.h> 2821afaf18SBorislav Petkov #include <linux/sysfs.h> 2921afaf18SBorislav Petkov #include <linux/types.h> 3021afaf18SBorislav Petkov #include <linux/slab.h> 3121afaf18SBorislav Petkov #include <linux/init.h> 3221afaf18SBorislav Petkov #include <linux/kmod.h> 3321afaf18SBorislav Petkov #include <linux/poll.h> 3421afaf18SBorislav Petkov #include <linux/nmi.h> 3521afaf18SBorislav Petkov #include <linux/cpu.h> 3621afaf18SBorislav Petkov #include <linux/ras.h> 3721afaf18SBorislav Petkov #include <linux/smp.h> 3821afaf18SBorislav Petkov #include <linux/fs.h> 3921afaf18SBorislav Petkov #include <linux/mm.h> 4021afaf18SBorislav Petkov #include <linux/debugfs.h> 4121afaf18SBorislav Petkov #include <linux/irq_work.h> 4221afaf18SBorislav Petkov #include <linux/export.h> 4321afaf18SBorislav Petkov #include <linux/set_memory.h> 449998a983SRicardo Neri #include <linux/sync_core.h> 455567d11cSPeter Zijlstra #include <linux/task_work.h> 460d00449cSPeter Zijlstra #include <linux/hardirq.h> 4721afaf18SBorislav Petkov 4821afaf18SBorislav Petkov #include <asm/intel-family.h> 4921afaf18SBorislav Petkov #include <asm/processor.h> 5021afaf18SBorislav Petkov #include <asm/traps.h> 5121afaf18SBorislav Petkov #include <asm/tlbflush.h> 5221afaf18SBorislav Petkov #include <asm/mce.h> 5321afaf18SBorislav Petkov #include <asm/msr.h> 5421afaf18SBorislav Petkov #include <asm/reboot.h> 5521afaf18SBorislav Petkov 5621afaf18SBorislav Petkov #include "internal.h" 5721afaf18SBorislav Petkov 5821afaf18SBorislav Petkov /* sysfs synchronization */ 5921afaf18SBorislav Petkov static DEFINE_MUTEX(mce_sysfs_mutex); 6021afaf18SBorislav Petkov 6121afaf18SBorislav Petkov #define CREATE_TRACE_POINTS 6221afaf18SBorislav Petkov #include <trace/events/mce.h> 6321afaf18SBorislav Petkov 6421afaf18SBorislav Petkov #define SPINUNIT 100 /* 100ns */ 6521afaf18SBorislav Petkov 6621afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_exception_count); 6721afaf18SBorislav Petkov 68c7d314f3SYazen Ghannam DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks); 69c7d314f3SYazen Ghannam 7095fdce6bSYazen Ghannam struct mce_bank { 7195fdce6bSYazen Ghannam u64 ctl; /* subevents to enable */ 7295fdce6bSYazen Ghannam bool init; /* initialise bank? */ 73b4914508SYazen Ghannam }; 74b4914508SYazen Ghannam static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); 75b4914508SYazen Ghannam 76b4914508SYazen Ghannam #define ATTR_LEN 16 77b4914508SYazen Ghannam /* One object for each MCE bank, shared by all CPUs */ 78b4914508SYazen Ghannam struct mce_bank_dev { 7995fdce6bSYazen Ghannam struct device_attribute attr; /* device attribute */ 8095fdce6bSYazen Ghannam char attrname[ATTR_LEN]; /* attribute name */ 81b4914508SYazen Ghannam u8 bank; /* bank number */ 8295fdce6bSYazen Ghannam }; 83b4914508SYazen Ghannam static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS]; 8495fdce6bSYazen Ghannam 8521afaf18SBorislav Petkov struct mce_vendor_flags mce_flags __read_mostly; 8621afaf18SBorislav Petkov 8721afaf18SBorislav Petkov struct mca_config mca_cfg __read_mostly = { 8821afaf18SBorislav Petkov .bootlog = -1, 8921afaf18SBorislav Petkov /* 9021afaf18SBorislav Petkov * Tolerant levels: 9121afaf18SBorislav Petkov * 0: always panic on uncorrected errors, log corrected errors 9221afaf18SBorislav Petkov * 1: panic or SIGBUS on uncorrected errors, log corrected errors 9321afaf18SBorislav Petkov * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors 9421afaf18SBorislav Petkov * 3: never panic or SIGBUS, log all errors (for testing only) 9521afaf18SBorislav Petkov */ 9621afaf18SBorislav Petkov .tolerant = 1, 9721afaf18SBorislav Petkov .monarch_timeout = -1 9821afaf18SBorislav Petkov }; 9921afaf18SBorislav Petkov 10021afaf18SBorislav Petkov static DEFINE_PER_CPU(struct mce, mces_seen); 10121afaf18SBorislav Petkov static unsigned long mce_need_notify; 10221afaf18SBorislav Petkov 10321afaf18SBorislav Petkov /* 10421afaf18SBorislav Petkov * MCA banks polled by the period polling timer for corrected events. 10521afaf18SBorislav Petkov * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). 10621afaf18SBorislav Petkov */ 10721afaf18SBorislav Petkov DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { 10821afaf18SBorislav Petkov [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL 10921afaf18SBorislav Petkov }; 11021afaf18SBorislav Petkov 11121afaf18SBorislav Petkov /* 11221afaf18SBorislav Petkov * MCA banks controlled through firmware first for corrected errors. 11321afaf18SBorislav Petkov * This is a global list of banks for which we won't enable CMCI and we 11421afaf18SBorislav Petkov * won't poll. Firmware controls these banks and is responsible for 11521afaf18SBorislav Petkov * reporting corrected errors through GHES. Uncorrected/recoverable 11621afaf18SBorislav Petkov * errors are still notified through a machine check. 11721afaf18SBorislav Petkov */ 11821afaf18SBorislav Petkov mce_banks_t mce_banks_ce_disabled; 11921afaf18SBorislav Petkov 12021afaf18SBorislav Petkov static struct work_struct mce_work; 12121afaf18SBorislav Petkov static struct irq_work mce_irq_work; 12221afaf18SBorislav Petkov 12321afaf18SBorislav Petkov /* 12421afaf18SBorislav Petkov * CPU/chipset specific EDAC code can register a notifier call here to print 12521afaf18SBorislav Petkov * MCE errors in a human-readable form. 12621afaf18SBorislav Petkov */ 12721afaf18SBorislav Petkov BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); 12821afaf18SBorislav Petkov 12921afaf18SBorislav Petkov /* Do initial initialization of a struct mce */ 130487d654dSBorislav Petkov void mce_setup(struct mce *m) 13121afaf18SBorislav Petkov { 13221afaf18SBorislav Petkov memset(m, 0, sizeof(struct mce)); 13321afaf18SBorislav Petkov m->cpu = m->extcpu = smp_processor_id(); 13421afaf18SBorislav Petkov /* need the internal __ version to avoid deadlocks */ 13521afaf18SBorislav Petkov m->time = __ktime_get_real_seconds(); 13621afaf18SBorislav Petkov m->cpuvendor = boot_cpu_data.x86_vendor; 13721afaf18SBorislav Petkov m->cpuid = cpuid_eax(1); 13821afaf18SBorislav Petkov m->socketid = cpu_data(m->extcpu).phys_proc_id; 13921afaf18SBorislav Petkov m->apicid = cpu_data(m->extcpu).initial_apicid; 140865d3a9aSThomas Gleixner m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); 14121afaf18SBorislav Petkov 14221afaf18SBorislav Petkov if (this_cpu_has(X86_FEATURE_INTEL_PPIN)) 143865d3a9aSThomas Gleixner m->ppin = __rdmsr(MSR_PPIN); 144077168e2SWei Huang else if (this_cpu_has(X86_FEATURE_AMD_PPIN)) 145865d3a9aSThomas Gleixner m->ppin = __rdmsr(MSR_AMD_PPIN); 14621afaf18SBorislav Petkov 14721afaf18SBorislav Petkov m->microcode = boot_cpu_data.microcode; 14821afaf18SBorislav Petkov } 14921afaf18SBorislav Petkov 15021afaf18SBorislav Petkov DEFINE_PER_CPU(struct mce, injectm); 15121afaf18SBorislav Petkov EXPORT_PER_CPU_SYMBOL_GPL(injectm); 15221afaf18SBorislav Petkov 15321afaf18SBorislav Petkov void mce_log(struct mce *m) 15421afaf18SBorislav Petkov { 15521afaf18SBorislav Petkov if (!mce_gen_pool_add(m)) 15621afaf18SBorislav Petkov irq_work_queue(&mce_irq_work); 15721afaf18SBorislav Petkov } 15881736abdSJan H. Schönherr EXPORT_SYMBOL_GPL(mce_log); 15921afaf18SBorislav Petkov 16021afaf18SBorislav Petkov void mce_register_decode_chain(struct notifier_block *nb) 16121afaf18SBorislav Petkov { 16215af3659SZhen Lei if (WARN_ON(nb->priority < MCE_PRIO_LOWEST || 16315af3659SZhen Lei nb->priority > MCE_PRIO_HIGHEST)) 16421afaf18SBorislav Petkov return; 16521afaf18SBorislav Petkov 16621afaf18SBorislav Petkov blocking_notifier_chain_register(&x86_mce_decoder_chain, nb); 16721afaf18SBorislav Petkov } 16821afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_register_decode_chain); 16921afaf18SBorislav Petkov 17021afaf18SBorislav Petkov void mce_unregister_decode_chain(struct notifier_block *nb) 17121afaf18SBorislav Petkov { 17221afaf18SBorislav Petkov blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb); 17321afaf18SBorislav Petkov } 17421afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); 17521afaf18SBorislav Petkov 1768121b8f9SBorislav Petkov u32 mca_msr_reg(int bank, enum mca_msr reg) 17721afaf18SBorislav Petkov { 1788121b8f9SBorislav Petkov if (mce_flags.smca) { 1798121b8f9SBorislav Petkov switch (reg) { 1808121b8f9SBorislav Petkov case MCA_CTL: return MSR_AMD64_SMCA_MCx_CTL(bank); 1818121b8f9SBorislav Petkov case MCA_ADDR: return MSR_AMD64_SMCA_MCx_ADDR(bank); 1828121b8f9SBorislav Petkov case MCA_MISC: return MSR_AMD64_SMCA_MCx_MISC(bank); 1838121b8f9SBorislav Petkov case MCA_STATUS: return MSR_AMD64_SMCA_MCx_STATUS(bank); 1848121b8f9SBorislav Petkov } 18521afaf18SBorislav Petkov } 18621afaf18SBorislav Petkov 1878121b8f9SBorislav Petkov switch (reg) { 1888121b8f9SBorislav Petkov case MCA_CTL: return MSR_IA32_MCx_CTL(bank); 1898121b8f9SBorislav Petkov case MCA_ADDR: return MSR_IA32_MCx_ADDR(bank); 1908121b8f9SBorislav Petkov case MCA_MISC: return MSR_IA32_MCx_MISC(bank); 1918121b8f9SBorislav Petkov case MCA_STATUS: return MSR_IA32_MCx_STATUS(bank); 19221afaf18SBorislav Petkov } 19321afaf18SBorislav Petkov 1948121b8f9SBorislav Petkov return 0; 19521afaf18SBorislav Petkov } 19621afaf18SBorislav Petkov 19721afaf18SBorislav Petkov static void __print_mce(struct mce *m) 19821afaf18SBorislav Petkov { 19921afaf18SBorislav Petkov pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", 20021afaf18SBorislav Petkov m->extcpu, 20121afaf18SBorislav Petkov (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""), 20221afaf18SBorislav Petkov m->mcgstatus, m->bank, m->status); 20321afaf18SBorislav Petkov 20421afaf18SBorislav Petkov if (m->ip) { 20521afaf18SBorislav Petkov pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", 20621afaf18SBorislav Petkov !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", 20721afaf18SBorislav Petkov m->cs, m->ip); 20821afaf18SBorislav Petkov 20921afaf18SBorislav Petkov if (m->cs == __KERNEL_CS) 21021afaf18SBorislav Petkov pr_cont("{%pS}", (void *)(unsigned long)m->ip); 21121afaf18SBorislav Petkov pr_cont("\n"); 21221afaf18SBorislav Petkov } 21321afaf18SBorislav Petkov 21421afaf18SBorislav Petkov pr_emerg(HW_ERR "TSC %llx ", m->tsc); 21521afaf18SBorislav Petkov if (m->addr) 21621afaf18SBorislav Petkov pr_cont("ADDR %llx ", m->addr); 21721afaf18SBorislav Petkov if (m->misc) 21821afaf18SBorislav Petkov pr_cont("MISC %llx ", m->misc); 219bb2de0adSSmita Koralahalli if (m->ppin) 220bb2de0adSSmita Koralahalli pr_cont("PPIN %llx ", m->ppin); 22121afaf18SBorislav Petkov 22221afaf18SBorislav Petkov if (mce_flags.smca) { 22321afaf18SBorislav Petkov if (m->synd) 22421afaf18SBorislav Petkov pr_cont("SYND %llx ", m->synd); 22521afaf18SBorislav Petkov if (m->ipid) 22621afaf18SBorislav Petkov pr_cont("IPID %llx ", m->ipid); 22721afaf18SBorislav Petkov } 22821afaf18SBorislav Petkov 22921afaf18SBorislav Petkov pr_cont("\n"); 230925946cfSTony Luck 23121afaf18SBorislav Petkov /* 23221afaf18SBorislav Petkov * Note this output is parsed by external tools and old fields 23321afaf18SBorislav Petkov * should not be changed. 23421afaf18SBorislav Petkov */ 23521afaf18SBorislav Petkov pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", 23621afaf18SBorislav Petkov m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, 23721afaf18SBorislav Petkov m->microcode); 23821afaf18SBorislav Petkov } 23921afaf18SBorislav Petkov 24021afaf18SBorislav Petkov static void print_mce(struct mce *m) 24121afaf18SBorislav Petkov { 24221afaf18SBorislav Petkov __print_mce(m); 24321afaf18SBorislav Petkov 24421afaf18SBorislav Petkov if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON) 24521afaf18SBorislav Petkov pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); 24621afaf18SBorislav Petkov } 24721afaf18SBorislav Petkov 24821afaf18SBorislav Petkov #define PANIC_TIMEOUT 5 /* 5 seconds */ 24921afaf18SBorislav Petkov 25021afaf18SBorislav Petkov static atomic_t mce_panicked; 25121afaf18SBorislav Petkov 25221afaf18SBorislav Petkov static int fake_panic; 25321afaf18SBorislav Petkov static atomic_t mce_fake_panicked; 25421afaf18SBorislav Petkov 25521afaf18SBorislav Petkov /* Panic in progress. Enable interrupts and wait for final IPI */ 25621afaf18SBorislav Petkov static void wait_for_panic(void) 25721afaf18SBorislav Petkov { 25821afaf18SBorislav Petkov long timeout = PANIC_TIMEOUT*USEC_PER_SEC; 25921afaf18SBorislav Petkov 26021afaf18SBorislav Petkov preempt_disable(); 26121afaf18SBorislav Petkov local_irq_enable(); 26221afaf18SBorislav Petkov while (timeout-- > 0) 26321afaf18SBorislav Petkov udelay(1); 26421afaf18SBorislav Petkov if (panic_timeout == 0) 26521afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 26621afaf18SBorislav Petkov panic("Panicing machine check CPU died"); 26721afaf18SBorislav Petkov } 26821afaf18SBorislav Petkov 2693c7ce80aSBorislav Petkov static noinstr void mce_panic(const char *msg, struct mce *final, char *exp) 27021afaf18SBorislav Petkov { 27121afaf18SBorislav Petkov struct llist_node *pending; 27221afaf18SBorislav Petkov struct mce_evt_llist *l; 2733c7ce80aSBorislav Petkov int apei_err = 0; 2743c7ce80aSBorislav Petkov 2753c7ce80aSBorislav Petkov /* 2763c7ce80aSBorislav Petkov * Allow instrumentation around external facilities usage. Not that it 2773c7ce80aSBorislav Petkov * matters a whole lot since the machine is going to panic anyway. 2783c7ce80aSBorislav Petkov */ 2793c7ce80aSBorislav Petkov instrumentation_begin(); 28021afaf18SBorislav Petkov 28121afaf18SBorislav Petkov if (!fake_panic) { 28221afaf18SBorislav Petkov /* 28321afaf18SBorislav Petkov * Make sure only one CPU runs in machine check panic 28421afaf18SBorislav Petkov */ 28521afaf18SBorislav Petkov if (atomic_inc_return(&mce_panicked) > 1) 28621afaf18SBorislav Petkov wait_for_panic(); 28721afaf18SBorislav Petkov barrier(); 28821afaf18SBorislav Petkov 28921afaf18SBorislav Petkov bust_spinlocks(1); 29021afaf18SBorislav Petkov console_verbose(); 29121afaf18SBorislav Petkov } else { 29221afaf18SBorislav Petkov /* Don't log too much for fake panic */ 29321afaf18SBorislav Petkov if (atomic_inc_return(&mce_fake_panicked) > 1) 2943c7ce80aSBorislav Petkov goto out; 29521afaf18SBorislav Petkov } 29621afaf18SBorislav Petkov pending = mce_gen_pool_prepare_records(); 29721afaf18SBorislav Petkov /* First print corrected ones that are still unlogged */ 29821afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 29921afaf18SBorislav Petkov struct mce *m = &l->mce; 30021afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) { 30121afaf18SBorislav Petkov print_mce(m); 30221afaf18SBorislav Petkov if (!apei_err) 30321afaf18SBorislav Petkov apei_err = apei_write_mce(m); 30421afaf18SBorislav Petkov } 30521afaf18SBorislav Petkov } 30621afaf18SBorislav Petkov /* Now print uncorrected but with the final one last */ 30721afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 30821afaf18SBorislav Petkov struct mce *m = &l->mce; 30921afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) 31021afaf18SBorislav Petkov continue; 31121afaf18SBorislav Petkov if (!final || mce_cmp(m, final)) { 31221afaf18SBorislav Petkov print_mce(m); 31321afaf18SBorislav Petkov if (!apei_err) 31421afaf18SBorislav Petkov apei_err = apei_write_mce(m); 31521afaf18SBorislav Petkov } 31621afaf18SBorislav Petkov } 31721afaf18SBorislav Petkov if (final) { 31821afaf18SBorislav Petkov print_mce(final); 31921afaf18SBorislav Petkov if (!apei_err) 32021afaf18SBorislav Petkov apei_err = apei_write_mce(final); 32121afaf18SBorislav Petkov } 32221afaf18SBorislav Petkov if (exp) 32321afaf18SBorislav Petkov pr_emerg(HW_ERR "Machine check: %s\n", exp); 32421afaf18SBorislav Petkov if (!fake_panic) { 32521afaf18SBorislav Petkov if (panic_timeout == 0) 32621afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 32721afaf18SBorislav Petkov panic(msg); 32821afaf18SBorislav Petkov } else 32921afaf18SBorislav Petkov pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); 3303c7ce80aSBorislav Petkov 3313c7ce80aSBorislav Petkov out: 3323c7ce80aSBorislav Petkov instrumentation_end(); 33321afaf18SBorislav Petkov } 33421afaf18SBorislav Petkov 33521afaf18SBorislav Petkov /* Support code for software error injection */ 33621afaf18SBorislav Petkov 33721afaf18SBorislav Petkov static int msr_to_offset(u32 msr) 33821afaf18SBorislav Petkov { 33921afaf18SBorislav Petkov unsigned bank = __this_cpu_read(injectm.bank); 34021afaf18SBorislav Petkov 34121afaf18SBorislav Petkov if (msr == mca_cfg.rip_msr) 34221afaf18SBorislav Petkov return offsetof(struct mce, ip); 3438121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_STATUS)) 34421afaf18SBorislav Petkov return offsetof(struct mce, status); 3458121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_ADDR)) 34621afaf18SBorislav Petkov return offsetof(struct mce, addr); 3478121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_MISC)) 34821afaf18SBorislav Petkov return offsetof(struct mce, misc); 34921afaf18SBorislav Petkov if (msr == MSR_IA32_MCG_STATUS) 35021afaf18SBorislav Petkov return offsetof(struct mce, mcgstatus); 35121afaf18SBorislav Petkov return -1; 35221afaf18SBorislav Petkov } 35321afaf18SBorislav Petkov 35446d28947SThomas Gleixner void ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr) 355e2def7d4SBorislav Petkov { 356e42404afSThomas Gleixner if (wrmsr) { 357e42404afSThomas Gleixner pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n", 358e42404afSThomas Gleixner (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax, 359e42404afSThomas Gleixner regs->ip, (void *)regs->ip); 360e42404afSThomas Gleixner } else { 361e2def7d4SBorislav Petkov pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n", 362e2def7d4SBorislav Petkov (unsigned int)regs->cx, regs->ip, (void *)regs->ip); 363e42404afSThomas Gleixner } 364e2def7d4SBorislav Petkov 365e2def7d4SBorislav Petkov show_stack_regs(regs); 366e2def7d4SBorislav Petkov 367e2def7d4SBorislav Petkov panic("MCA architectural violation!\n"); 368e2def7d4SBorislav Petkov 369e2def7d4SBorislav Petkov while (true) 370e2def7d4SBorislav Petkov cpu_relax(); 371e42404afSThomas Gleixner } 372e2def7d4SBorislav Petkov 37321afaf18SBorislav Petkov /* MSR access wrappers used for error injection */ 37488f66a42SBorislav Petkov noinstr u64 mce_rdmsrl(u32 msr) 37521afaf18SBorislav Petkov { 376e2def7d4SBorislav Petkov DECLARE_ARGS(val, low, high); 37721afaf18SBorislav Petkov 37821afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 379e1007770SBorislav Petkov int offset; 380e1007770SBorislav Petkov u64 ret; 38121afaf18SBorislav Petkov 382e1007770SBorislav Petkov instrumentation_begin(); 383e1007770SBorislav Petkov 384e1007770SBorislav Petkov offset = msr_to_offset(msr); 38521afaf18SBorislav Petkov if (offset < 0) 386e1007770SBorislav Petkov ret = 0; 387e1007770SBorislav Petkov else 388e1007770SBorislav Petkov ret = *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); 389e1007770SBorislav Petkov 390e1007770SBorislav Petkov instrumentation_end(); 391e1007770SBorislav Petkov 392e1007770SBorislav Petkov return ret; 39321afaf18SBorislav Petkov } 39421afaf18SBorislav Petkov 39521afaf18SBorislav Petkov /* 396e2def7d4SBorislav Petkov * RDMSR on MCA MSRs should not fault. If they do, this is very much an 397e2def7d4SBorislav Petkov * architectural violation and needs to be reported to hw vendor. Panic 398e2def7d4SBorislav Petkov * the box to not allow any further progress. 39921afaf18SBorislav Petkov */ 400e2def7d4SBorislav Petkov asm volatile("1: rdmsr\n" 401e2def7d4SBorislav Petkov "2:\n" 40246d28947SThomas Gleixner _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR_IN_MCE) 403e2def7d4SBorislav Petkov : EAX_EDX_RET(val, low, high) : "c" (msr)); 404e2def7d4SBorislav Petkov 405e2def7d4SBorislav Petkov 406e2def7d4SBorislav Petkov return EAX_EDX_VAL(val, low, high); 40721afaf18SBorislav Petkov } 40821afaf18SBorislav Petkov 409e1007770SBorislav Petkov static noinstr void mce_wrmsrl(u32 msr, u64 v) 41021afaf18SBorislav Petkov { 411e2def7d4SBorislav Petkov u32 low, high; 412e2def7d4SBorislav Petkov 41321afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 414e1007770SBorislav Petkov int offset; 41521afaf18SBorislav Petkov 416e1007770SBorislav Petkov instrumentation_begin(); 417e1007770SBorislav Petkov 418e1007770SBorislav Petkov offset = msr_to_offset(msr); 41921afaf18SBorislav Petkov if (offset >= 0) 42021afaf18SBorislav Petkov *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; 421e1007770SBorislav Petkov 422e1007770SBorislav Petkov instrumentation_end(); 423e1007770SBorislav Petkov 42421afaf18SBorislav Petkov return; 42521afaf18SBorislav Petkov } 426e2def7d4SBorislav Petkov 427e2def7d4SBorislav Petkov low = (u32)v; 428e2def7d4SBorislav Petkov high = (u32)(v >> 32); 429e2def7d4SBorislav Petkov 430e2def7d4SBorislav Petkov /* See comment in mce_rdmsrl() */ 431e2def7d4SBorislav Petkov asm volatile("1: wrmsr\n" 432e2def7d4SBorislav Petkov "2:\n" 43346d28947SThomas Gleixner _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR_IN_MCE) 434e2def7d4SBorislav Petkov : : "c" (msr), "a"(low), "d" (high) : "memory"); 43521afaf18SBorislav Petkov } 43621afaf18SBorislav Petkov 43721afaf18SBorislav Petkov /* 43821afaf18SBorislav Petkov * Collect all global (w.r.t. this processor) status about this machine 43921afaf18SBorislav Petkov * check into our "mce" struct so that we can use it later to assess 44021afaf18SBorislav Petkov * the severity of the problem as we read per-bank specific details. 44121afaf18SBorislav Petkov */ 442487d654dSBorislav Petkov static noinstr void mce_gather_info(struct mce *m, struct pt_regs *regs) 44321afaf18SBorislav Petkov { 444487d654dSBorislav Petkov /* 445487d654dSBorislav Petkov * Enable instrumentation around mce_setup() which calls external 446487d654dSBorislav Petkov * facilities. 447487d654dSBorislav Petkov */ 448487d654dSBorislav Petkov instrumentation_begin(); 44921afaf18SBorislav Petkov mce_setup(m); 450487d654dSBorislav Petkov instrumentation_end(); 45121afaf18SBorislav Petkov 45221afaf18SBorislav Petkov m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 45321afaf18SBorislav Petkov if (regs) { 45421afaf18SBorislav Petkov /* 45521afaf18SBorislav Petkov * Get the address of the instruction at the time of 45621afaf18SBorislav Petkov * the machine check error. 45721afaf18SBorislav Petkov */ 45821afaf18SBorislav Petkov if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { 45921afaf18SBorislav Petkov m->ip = regs->ip; 46021afaf18SBorislav Petkov m->cs = regs->cs; 46121afaf18SBorislav Petkov 46221afaf18SBorislav Petkov /* 46321afaf18SBorislav Petkov * When in VM86 mode make the cs look like ring 3 46421afaf18SBorislav Petkov * always. This is a lie, but it's better than passing 46521afaf18SBorislav Petkov * the additional vm86 bit around everywhere. 46621afaf18SBorislav Petkov */ 46721afaf18SBorislav Petkov if (v8086_mode(regs)) 46821afaf18SBorislav Petkov m->cs |= 3; 46921afaf18SBorislav Petkov } 47021afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 47121afaf18SBorislav Petkov if (mca_cfg.rip_msr) 47221afaf18SBorislav Petkov m->ip = mce_rdmsrl(mca_cfg.rip_msr); 47321afaf18SBorislav Petkov } 47421afaf18SBorislav Petkov } 47521afaf18SBorislav Petkov 47621afaf18SBorislav Petkov int mce_available(struct cpuinfo_x86 *c) 47721afaf18SBorislav Petkov { 47821afaf18SBorislav Petkov if (mca_cfg.disabled) 47921afaf18SBorislav Petkov return 0; 48021afaf18SBorislav Petkov return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); 48121afaf18SBorislav Petkov } 48221afaf18SBorislav Petkov 48321afaf18SBorislav Petkov static void mce_schedule_work(void) 48421afaf18SBorislav Petkov { 48521afaf18SBorislav Petkov if (!mce_gen_pool_empty()) 48621afaf18SBorislav Petkov schedule_work(&mce_work); 48721afaf18SBorislav Petkov } 48821afaf18SBorislav Petkov 48921afaf18SBorislav Petkov static void mce_irq_work_cb(struct irq_work *entry) 49021afaf18SBorislav Petkov { 49121afaf18SBorislav Petkov mce_schedule_work(); 49221afaf18SBorislav Petkov } 49321afaf18SBorislav Petkov 49421afaf18SBorislav Petkov /* 49521afaf18SBorislav Petkov * Check if the address reported by the CPU is in a format we can parse. 49621afaf18SBorislav Petkov * It would be possible to add code for most other cases, but all would 49721afaf18SBorislav Petkov * be somewhat complicated (e.g. segment offset would require an instruction 498d9f6e12fSIngo Molnar * parser). So only support physical addresses up to page granularity for now. 49921afaf18SBorislav Petkov */ 50021afaf18SBorislav Petkov int mce_usable_address(struct mce *m) 50121afaf18SBorislav Petkov { 50221afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_ADDRV)) 50321afaf18SBorislav Petkov return 0; 50421afaf18SBorislav Petkov 5056e898d2bSTony W Wang-oc /* Checks after this one are Intel/Zhaoxin-specific: */ 5066e898d2bSTony W Wang-oc if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && 5076e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) 50821afaf18SBorislav Petkov return 1; 50921afaf18SBorislav Petkov 51021afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_MISCV)) 51121afaf18SBorislav Petkov return 0; 51221afaf18SBorislav Petkov 51321afaf18SBorislav Petkov if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) 51421afaf18SBorislav Petkov return 0; 51521afaf18SBorislav Petkov 51621afaf18SBorislav Petkov if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) 51721afaf18SBorislav Petkov return 0; 51821afaf18SBorislav Petkov 51921afaf18SBorislav Petkov return 1; 52021afaf18SBorislav Petkov } 52121afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_usable_address); 52221afaf18SBorislav Petkov 52321afaf18SBorislav Petkov bool mce_is_memory_error(struct mce *m) 52421afaf18SBorislav Petkov { 5256e898d2bSTony W Wang-oc switch (m->cpuvendor) { 5266e898d2bSTony W Wang-oc case X86_VENDOR_AMD: 5276e898d2bSTony W Wang-oc case X86_VENDOR_HYGON: 52821afaf18SBorislav Petkov return amd_mce_is_memory_error(m); 5296e898d2bSTony W Wang-oc 5306e898d2bSTony W Wang-oc case X86_VENDOR_INTEL: 5316e898d2bSTony W Wang-oc case X86_VENDOR_ZHAOXIN: 53221afaf18SBorislav Petkov /* 53321afaf18SBorislav Petkov * Intel SDM Volume 3B - 15.9.2 Compound Error Codes 53421afaf18SBorislav Petkov * 53521afaf18SBorislav Petkov * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for 53621afaf18SBorislav Petkov * indicating a memory error. Bit 8 is used for indicating a 53721afaf18SBorislav Petkov * cache hierarchy error. The combination of bit 2 and bit 3 53821afaf18SBorislav Petkov * is used for indicating a `generic' cache hierarchy error 53921afaf18SBorislav Petkov * But we can't just blindly check the above bits, because if 54021afaf18SBorislav Petkov * bit 11 is set, then it is a bus/interconnect error - and 54121afaf18SBorislav Petkov * either way the above bits just gives more detail on what 54221afaf18SBorislav Petkov * bus/interconnect error happened. Note that bit 12 can be 54321afaf18SBorislav Petkov * ignored, as it's the "filter" bit. 54421afaf18SBorislav Petkov */ 54521afaf18SBorislav Petkov return (m->status & 0xef80) == BIT(7) || 54621afaf18SBorislav Petkov (m->status & 0xef00) == BIT(8) || 54721afaf18SBorislav Petkov (m->status & 0xeffc) == 0xc; 54821afaf18SBorislav Petkov 5496e898d2bSTony W Wang-oc default: 55021afaf18SBorislav Petkov return false; 55121afaf18SBorislav Petkov } 5526e898d2bSTony W Wang-oc } 55321afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_memory_error); 55421afaf18SBorislav Petkov 55517fae129STony Luck static bool whole_page(struct mce *m) 55617fae129STony Luck { 55717fae129STony Luck if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV)) 55817fae129STony Luck return true; 55917fae129STony Luck 56017fae129STony Luck return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT; 56117fae129STony Luck } 56217fae129STony Luck 56321afaf18SBorislav Petkov bool mce_is_correctable(struct mce *m) 56421afaf18SBorislav Petkov { 56521afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED) 56621afaf18SBorislav Petkov return false; 56721afaf18SBorislav Petkov 56821afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED) 56921afaf18SBorislav Petkov return false; 57021afaf18SBorislav Petkov 57121afaf18SBorislav Petkov if (m->status & MCI_STATUS_UC) 57221afaf18SBorislav Petkov return false; 57321afaf18SBorislav Petkov 57421afaf18SBorislav Petkov return true; 57521afaf18SBorislav Petkov } 57621afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_correctable); 57721afaf18SBorislav Petkov 578c9c6d216STony Luck static int mce_early_notifier(struct notifier_block *nb, unsigned long val, 57921afaf18SBorislav Petkov void *data) 58021afaf18SBorislav Petkov { 58121afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 58221afaf18SBorislav Petkov 58321afaf18SBorislav Petkov if (!m) 58421afaf18SBorislav Petkov return NOTIFY_DONE; 58521afaf18SBorislav Petkov 58621afaf18SBorislav Petkov /* Emit the trace record: */ 58721afaf18SBorislav Petkov trace_mce_record(m); 58821afaf18SBorislav Petkov 58921afaf18SBorislav Petkov set_bit(0, &mce_need_notify); 59021afaf18SBorislav Petkov 59121afaf18SBorislav Petkov mce_notify_irq(); 59221afaf18SBorislav Petkov 59321afaf18SBorislav Petkov return NOTIFY_DONE; 59421afaf18SBorislav Petkov } 59521afaf18SBorislav Petkov 596c9c6d216STony Luck static struct notifier_block early_nb = { 597c9c6d216STony Luck .notifier_call = mce_early_notifier, 598c9c6d216STony Luck .priority = MCE_PRIO_EARLY, 59921afaf18SBorislav Petkov }; 60021afaf18SBorislav Petkov 6018438b84aSJan H. Schönherr static int uc_decode_notifier(struct notifier_block *nb, unsigned long val, 60221afaf18SBorislav Petkov void *data) 60321afaf18SBorislav Petkov { 60421afaf18SBorislav Petkov struct mce *mce = (struct mce *)data; 60521afaf18SBorislav Petkov unsigned long pfn; 60621afaf18SBorislav Petkov 6078438b84aSJan H. Schönherr if (!mce || !mce_usable_address(mce)) 60821afaf18SBorislav Petkov return NOTIFY_DONE; 60921afaf18SBorislav Petkov 6108438b84aSJan H. Schönherr if (mce->severity != MCE_AO_SEVERITY && 6118438b84aSJan H. Schönherr mce->severity != MCE_DEFERRED_SEVERITY) 6128438b84aSJan H. Schönherr return NOTIFY_DONE; 6138438b84aSJan H. Schönherr 61421afaf18SBorislav Petkov pfn = mce->addr >> PAGE_SHIFT; 61523ba710aSTony Luck if (!memory_failure(pfn, 0)) { 61617fae129STony Luck set_mce_nospec(pfn, whole_page(mce)); 61723ba710aSTony Luck mce->kflags |= MCE_HANDLED_UC; 61823ba710aSTony Luck } 61921afaf18SBorislav Petkov 62021afaf18SBorislav Petkov return NOTIFY_OK; 62121afaf18SBorislav Petkov } 6228438b84aSJan H. Schönherr 6238438b84aSJan H. Schönherr static struct notifier_block mce_uc_nb = { 6248438b84aSJan H. Schönherr .notifier_call = uc_decode_notifier, 6258438b84aSJan H. Schönherr .priority = MCE_PRIO_UC, 62621afaf18SBorislav Petkov }; 62721afaf18SBorislav Petkov 62821afaf18SBorislav Petkov static int mce_default_notifier(struct notifier_block *nb, unsigned long val, 62921afaf18SBorislav Petkov void *data) 63021afaf18SBorislav Petkov { 63121afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 63221afaf18SBorislav Petkov 63321afaf18SBorislav Petkov if (!m) 63421afaf18SBorislav Petkov return NOTIFY_DONE; 63521afaf18SBorislav Petkov 63643505646STony Luck if (mca_cfg.print_all || !m->kflags) 63721afaf18SBorislav Petkov __print_mce(m); 63821afaf18SBorislav Petkov 63921afaf18SBorislav Petkov return NOTIFY_DONE; 64021afaf18SBorislav Petkov } 64121afaf18SBorislav Petkov 64221afaf18SBorislav Petkov static struct notifier_block mce_default_nb = { 64321afaf18SBorislav Petkov .notifier_call = mce_default_notifier, 64421afaf18SBorislav Petkov /* lowest prio, we want it to run last. */ 64521afaf18SBorislav Petkov .priority = MCE_PRIO_LOWEST, 64621afaf18SBorislav Petkov }; 64721afaf18SBorislav Petkov 64821afaf18SBorislav Petkov /* 64921afaf18SBorislav Petkov * Read ADDR and MISC registers. 65021afaf18SBorislav Petkov */ 651db6c996dSBorislav Petkov static noinstr void mce_read_aux(struct mce *m, int i) 65221afaf18SBorislav Petkov { 65321afaf18SBorislav Petkov if (m->status & MCI_STATUS_MISCV) 6548121b8f9SBorislav Petkov m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC)); 65521afaf18SBorislav Petkov 65621afaf18SBorislav Petkov if (m->status & MCI_STATUS_ADDRV) { 6578121b8f9SBorislav Petkov m->addr = mce_rdmsrl(mca_msr_reg(i, MCA_ADDR)); 65821afaf18SBorislav Petkov 65921afaf18SBorislav Petkov /* 66021afaf18SBorislav Petkov * Mask the reported address by the reported granularity. 66121afaf18SBorislav Petkov */ 66221afaf18SBorislav Petkov if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { 66321afaf18SBorislav Petkov u8 shift = MCI_MISC_ADDR_LSB(m->misc); 66421afaf18SBorislav Petkov m->addr >>= shift; 66521afaf18SBorislav Petkov m->addr <<= shift; 66621afaf18SBorislav Petkov } 66721afaf18SBorislav Petkov 66821afaf18SBorislav Petkov /* 66921afaf18SBorislav Petkov * Extract [55:<lsb>] where lsb is the least significant 67021afaf18SBorislav Petkov * *valid* bit of the address bits. 67121afaf18SBorislav Petkov */ 67221afaf18SBorislav Petkov if (mce_flags.smca) { 67321afaf18SBorislav Petkov u8 lsb = (m->addr >> 56) & 0x3f; 67421afaf18SBorislav Petkov 67521afaf18SBorislav Petkov m->addr &= GENMASK_ULL(55, lsb); 67621afaf18SBorislav Petkov } 67721afaf18SBorislav Petkov } 67821afaf18SBorislav Petkov 67921afaf18SBorislav Petkov if (mce_flags.smca) { 68021afaf18SBorislav Petkov m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); 68121afaf18SBorislav Petkov 68221afaf18SBorislav Petkov if (m->status & MCI_STATUS_SYNDV) 68321afaf18SBorislav Petkov m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); 68421afaf18SBorislav Petkov } 68521afaf18SBorislav Petkov } 68621afaf18SBorislav Petkov 68721afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_poll_count); 68821afaf18SBorislav Petkov 68921afaf18SBorislav Petkov /* 69021afaf18SBorislav Petkov * Poll for corrected events or events that happened before reset. 69121afaf18SBorislav Petkov * Those are just logged through /dev/mcelog. 69221afaf18SBorislav Petkov * 69321afaf18SBorislav Petkov * This is executed in standard interrupt context. 69421afaf18SBorislav Petkov * 69521afaf18SBorislav Petkov * Note: spec recommends to panic for fatal unsignalled 69621afaf18SBorislav Petkov * errors here. However this would be quite problematic -- 69721afaf18SBorislav Petkov * we would need to reimplement the Monarch handling and 69821afaf18SBorislav Petkov * it would mess up the exclusion between exception handler 699312a4661SLinus Torvalds * and poll handler -- * so we skip this for now. 70021afaf18SBorislav Petkov * These cases should not happen anyways, or only when the CPU 70121afaf18SBorislav Petkov * is already totally * confused. In this case it's likely it will 70221afaf18SBorislav Petkov * not fully execute the machine check handler either. 70321afaf18SBorislav Petkov */ 70421afaf18SBorislav Petkov bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) 70521afaf18SBorislav Petkov { 706b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 70721afaf18SBorislav Petkov bool error_seen = false; 70821afaf18SBorislav Petkov struct mce m; 70921afaf18SBorislav Petkov int i; 71021afaf18SBorislav Petkov 71121afaf18SBorislav Petkov this_cpu_inc(mce_poll_count); 71221afaf18SBorislav Petkov 71321afaf18SBorislav Petkov mce_gather_info(&m, NULL); 71421afaf18SBorislav Petkov 71521afaf18SBorislav Petkov if (flags & MCP_TIMESTAMP) 71621afaf18SBorislav Petkov m.tsc = rdtsc(); 71721afaf18SBorislav Petkov 718c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 71921afaf18SBorislav Petkov if (!mce_banks[i].ctl || !test_bit(i, *b)) 72021afaf18SBorislav Petkov continue; 72121afaf18SBorislav Petkov 72221afaf18SBorislav Petkov m.misc = 0; 72321afaf18SBorislav Petkov m.addr = 0; 72421afaf18SBorislav Petkov m.bank = i; 72521afaf18SBorislav Petkov 72621afaf18SBorislav Petkov barrier(); 7278121b8f9SBorislav Petkov m.status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 728f19501aaSTony Luck 729f19501aaSTony Luck /* If this entry is not valid, ignore it */ 73021afaf18SBorislav Petkov if (!(m.status & MCI_STATUS_VAL)) 73121afaf18SBorislav Petkov continue; 73221afaf18SBorislav Petkov 73321afaf18SBorislav Petkov /* 734f19501aaSTony Luck * If we are logging everything (at CPU online) or this 735f19501aaSTony Luck * is a corrected error, then we must log it. 73621afaf18SBorislav Petkov */ 737f19501aaSTony Luck if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC)) 738f19501aaSTony Luck goto log_it; 739f19501aaSTony Luck 740f19501aaSTony Luck /* 741f19501aaSTony Luck * Newer Intel systems that support software error 742f19501aaSTony Luck * recovery need to make additional checks. Other 743f19501aaSTony Luck * CPUs should skip over uncorrected errors, but log 744f19501aaSTony Luck * everything else. 745f19501aaSTony Luck */ 746f19501aaSTony Luck if (!mca_cfg.ser) { 747f19501aaSTony Luck if (m.status & MCI_STATUS_UC) 748f19501aaSTony Luck continue; 749f19501aaSTony Luck goto log_it; 750f19501aaSTony Luck } 751f19501aaSTony Luck 752f19501aaSTony Luck /* Log "not enabled" (speculative) errors */ 753f19501aaSTony Luck if (!(m.status & MCI_STATUS_EN)) 754f19501aaSTony Luck goto log_it; 755f19501aaSTony Luck 756f19501aaSTony Luck /* 757f19501aaSTony Luck * Log UCNA (SDM: 15.6.3 "UCR Error Classification") 758f19501aaSTony Luck * UC == 1 && PCC == 0 && S == 0 759f19501aaSTony Luck */ 760f19501aaSTony Luck if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S)) 761f19501aaSTony Luck goto log_it; 762f19501aaSTony Luck 763f19501aaSTony Luck /* 764f19501aaSTony Luck * Skip anything else. Presumption is that our read of this 765f19501aaSTony Luck * bank is racing with a machine check. Leave the log alone 766f19501aaSTony Luck * for do_machine_check() to deal with it. 767f19501aaSTony Luck */ 76821afaf18SBorislav Petkov continue; 76921afaf18SBorislav Petkov 770f19501aaSTony Luck log_it: 77121afaf18SBorislav Petkov error_seen = true; 77221afaf18SBorislav Petkov 77390454e49SJan H. Schönherr if (flags & MCP_DONTLOG) 77490454e49SJan H. Schönherr goto clear_it; 77590454e49SJan H. Schönherr 77621afaf18SBorislav Petkov mce_read_aux(&m, i); 77741ce0564SYouquan Song m.severity = mce_severity(&m, NULL, mca_cfg.tolerant, NULL, false); 77821afaf18SBorislav Petkov /* 77921afaf18SBorislav Petkov * Don't get the IP here because it's unlikely to 78021afaf18SBorislav Petkov * have anything to do with the actual error location. 78121afaf18SBorislav Petkov */ 78221afaf18SBorislav Petkov 78390454e49SJan H. Schönherr if (mca_cfg.dont_log_ce && !mce_usable_address(&m)) 78490454e49SJan H. Schönherr goto clear_it; 78590454e49SJan H. Schönherr 7863bff147bSBorislav Petkov if (flags & MCP_QUEUE_LOG) 7873bff147bSBorislav Petkov mce_gen_pool_add(&m); 7883bff147bSBorislav Petkov else 78990454e49SJan H. Schönherr mce_log(&m); 79090454e49SJan H. Schönherr 79190454e49SJan H. Schönherr clear_it: 79221afaf18SBorislav Petkov /* 79321afaf18SBorislav Petkov * Clear state for this bank. 79421afaf18SBorislav Petkov */ 7958121b8f9SBorislav Petkov mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 79621afaf18SBorislav Petkov } 79721afaf18SBorislav Petkov 79821afaf18SBorislav Petkov /* 79921afaf18SBorislav Petkov * Don't clear MCG_STATUS here because it's only defined for 80021afaf18SBorislav Petkov * exceptions. 80121afaf18SBorislav Petkov */ 80221afaf18SBorislav Petkov 80321afaf18SBorislav Petkov sync_core(); 80421afaf18SBorislav Petkov 80521afaf18SBorislav Petkov return error_seen; 80621afaf18SBorislav Petkov } 80721afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(machine_check_poll); 80821afaf18SBorislav Petkov 80921afaf18SBorislav Petkov /* 810cc466666SBorislav Petkov * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and 811cc466666SBorislav Petkov * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM 812cc466666SBorislav Petkov * Vol 3B Table 15-20). But this confuses both the code that determines 813cc466666SBorislav Petkov * whether the machine check occurred in kernel or user mode, and also 814cc466666SBorislav Petkov * the severity assessment code. Pretend that EIPV was set, and take the 815cc466666SBorislav Petkov * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. 816cc466666SBorislav Petkov */ 817cc466666SBorislav Petkov static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) 818cc466666SBorislav Petkov { 819cc466666SBorislav Petkov if (bank != 0) 820cc466666SBorislav Petkov return; 821cc466666SBorislav Petkov if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) 822cc466666SBorislav Petkov return; 823cc466666SBorislav Petkov if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| 824cc466666SBorislav Petkov MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| 825cc466666SBorislav Petkov MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| 826cc466666SBorislav Petkov MCACOD)) != 827cc466666SBorislav Petkov (MCI_STATUS_UC|MCI_STATUS_EN| 828cc466666SBorislav Petkov MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| 829cc466666SBorislav Petkov MCI_STATUS_AR|MCACOD_INSTR)) 830cc466666SBorislav Petkov return; 831cc466666SBorislav Petkov 832cc466666SBorislav Petkov m->mcgstatus |= MCG_STATUS_EIPV; 833cc466666SBorislav Petkov m->ip = regs->ip; 834cc466666SBorislav Petkov m->cs = regs->cs; 835cc466666SBorislav Petkov } 836cc466666SBorislav Petkov 837cc466666SBorislav Petkov /* 83821afaf18SBorislav Petkov * Do a quick check if any of the events requires a panic. 83921afaf18SBorislav Petkov * This decides if we keep the events around or clear them. 84021afaf18SBorislav Petkov */ 84121afaf18SBorislav Petkov static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, 84221afaf18SBorislav Petkov struct pt_regs *regs) 84321afaf18SBorislav Petkov { 8447a8bc2b0SJan H. Schönherr char *tmp = *msg; 84521afaf18SBorislav Petkov int i; 84621afaf18SBorislav Petkov 847c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 8488121b8f9SBorislav Petkov m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 84921afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 85021afaf18SBorislav Petkov continue; 85121afaf18SBorislav Petkov 85221afaf18SBorislav Petkov __set_bit(i, validp); 853cc466666SBorislav Petkov if (mce_flags.snb_ifu_quirk) 854cc466666SBorislav Petkov quirk_sandybridge_ifu(i, m, regs); 85521afaf18SBorislav Petkov 856d28af26fSTony Luck m->bank = i; 85741ce0564SYouquan Song if (mce_severity(m, regs, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) { 85821afaf18SBorislav Petkov mce_read_aux(m, i); 85921afaf18SBorislav Petkov *msg = tmp; 86021afaf18SBorislav Petkov return 1; 86121afaf18SBorislav Petkov } 86221afaf18SBorislav Petkov } 86321afaf18SBorislav Petkov return 0; 86421afaf18SBorislav Petkov } 86521afaf18SBorislav Petkov 86621afaf18SBorislav Petkov /* 86721afaf18SBorislav Petkov * Variable to establish order between CPUs while scanning. 86821afaf18SBorislav Petkov * Each CPU spins initially until executing is equal its number. 86921afaf18SBorislav Petkov */ 87021afaf18SBorislav Petkov static atomic_t mce_executing; 87121afaf18SBorislav Petkov 87221afaf18SBorislav Petkov /* 87321afaf18SBorislav Petkov * Defines order of CPUs on entry. First CPU becomes Monarch. 87421afaf18SBorislav Petkov */ 87521afaf18SBorislav Petkov static atomic_t mce_callin; 87621afaf18SBorislav Petkov 87721afaf18SBorislav Petkov /* 8787bb39313SPaul E. McKenney * Track which CPUs entered the MCA broadcast synchronization and which not in 8797bb39313SPaul E. McKenney * order to print holdouts. 8807bb39313SPaul E. McKenney */ 8817bb39313SPaul E. McKenney static cpumask_t mce_missing_cpus = CPU_MASK_ALL; 8827bb39313SPaul E. McKenney 8837bb39313SPaul E. McKenney /* 88421afaf18SBorislav Petkov * Check if a timeout waiting for other CPUs happened. 88521afaf18SBorislav Petkov */ 886*edb3d07eSBorislav Petkov static noinstr int mce_timed_out(u64 *t, const char *msg) 88721afaf18SBorislav Petkov { 888*edb3d07eSBorislav Petkov int ret = 0; 889*edb3d07eSBorislav Petkov 890*edb3d07eSBorislav Petkov /* Enable instrumentation around calls to external facilities */ 891*edb3d07eSBorislav Petkov instrumentation_begin(); 892*edb3d07eSBorislav Petkov 89321afaf18SBorislav Petkov /* 89421afaf18SBorislav Petkov * The others already did panic for some reason. 89521afaf18SBorislav Petkov * Bail out like in a timeout. 89621afaf18SBorislav Petkov * rmb() to tell the compiler that system_state 89721afaf18SBorislav Petkov * might have been modified by someone else. 89821afaf18SBorislav Petkov */ 89921afaf18SBorislav Petkov rmb(); 90021afaf18SBorislav Petkov if (atomic_read(&mce_panicked)) 90121afaf18SBorislav Petkov wait_for_panic(); 90221afaf18SBorislav Petkov if (!mca_cfg.monarch_timeout) 90321afaf18SBorislav Petkov goto out; 90421afaf18SBorislav Petkov if ((s64)*t < SPINUNIT) { 9057bb39313SPaul E. McKenney if (mca_cfg.tolerant <= 1) { 9067bb39313SPaul E. McKenney if (cpumask_and(&mce_missing_cpus, cpu_online_mask, &mce_missing_cpus)) 9077bb39313SPaul E. McKenney pr_emerg("CPUs not responding to MCE broadcast (may include false positives): %*pbl\n", 9087bb39313SPaul E. McKenney cpumask_pr_args(&mce_missing_cpus)); 90921afaf18SBorislav Petkov mce_panic(msg, NULL, NULL); 9107bb39313SPaul E. McKenney } 911*edb3d07eSBorislav Petkov ret = 1; 912*edb3d07eSBorislav Petkov goto out; 91321afaf18SBorislav Petkov } 91421afaf18SBorislav Petkov *t -= SPINUNIT; 915*edb3d07eSBorislav Petkov 91621afaf18SBorislav Petkov out: 91721afaf18SBorislav Petkov touch_nmi_watchdog(); 918*edb3d07eSBorislav Petkov 919*edb3d07eSBorislav Petkov instrumentation_end(); 920*edb3d07eSBorislav Petkov 921*edb3d07eSBorislav Petkov return ret; 92221afaf18SBorislav Petkov } 92321afaf18SBorislav Petkov 92421afaf18SBorislav Petkov /* 92521afaf18SBorislav Petkov * The Monarch's reign. The Monarch is the CPU who entered 92621afaf18SBorislav Petkov * the machine check handler first. It waits for the others to 92721afaf18SBorislav Petkov * raise the exception too and then grades them. When any 92821afaf18SBorislav Petkov * error is fatal panic. Only then let the others continue. 92921afaf18SBorislav Petkov * 93021afaf18SBorislav Petkov * The other CPUs entering the MCE handler will be controlled by the 93121afaf18SBorislav Petkov * Monarch. They are called Subjects. 93221afaf18SBorislav Petkov * 93321afaf18SBorislav Petkov * This way we prevent any potential data corruption in a unrecoverable case 93421afaf18SBorislav Petkov * and also makes sure always all CPU's errors are examined. 93521afaf18SBorislav Petkov * 93621afaf18SBorislav Petkov * Also this detects the case of a machine check event coming from outer 93721afaf18SBorislav Petkov * space (not detected by any CPUs) In this case some external agent wants 93821afaf18SBorislav Petkov * us to shut down, so panic too. 93921afaf18SBorislav Petkov * 94021afaf18SBorislav Petkov * The other CPUs might still decide to panic if the handler happens 94121afaf18SBorislav Petkov * in a unrecoverable place, but in this case the system is in a semi-stable 94221afaf18SBorislav Petkov * state and won't corrupt anything by itself. It's ok to let the others 94321afaf18SBorislav Petkov * continue for a bit first. 94421afaf18SBorislav Petkov * 94521afaf18SBorislav Petkov * All the spin loops have timeouts; when a timeout happens a CPU 94621afaf18SBorislav Petkov * typically elects itself to be Monarch. 94721afaf18SBorislav Petkov */ 94821afaf18SBorislav Petkov static void mce_reign(void) 94921afaf18SBorislav Petkov { 95021afaf18SBorislav Petkov int cpu; 95121afaf18SBorislav Petkov struct mce *m = NULL; 95221afaf18SBorislav Petkov int global_worst = 0; 95321afaf18SBorislav Petkov char *msg = NULL; 95421afaf18SBorislav Petkov 95521afaf18SBorislav Petkov /* 95621afaf18SBorislav Petkov * This CPU is the Monarch and the other CPUs have run 95721afaf18SBorislav Petkov * through their handlers. 95821afaf18SBorislav Petkov * Grade the severity of the errors of all the CPUs. 95921afaf18SBorislav Petkov */ 96021afaf18SBorislav Petkov for_each_possible_cpu(cpu) { 96113c877f4STony Luck struct mce *mtmp = &per_cpu(mces_seen, cpu); 96213c877f4STony Luck 96313c877f4STony Luck if (mtmp->severity > global_worst) { 96413c877f4STony Luck global_worst = mtmp->severity; 96521afaf18SBorislav Petkov m = &per_cpu(mces_seen, cpu); 96621afaf18SBorislav Petkov } 96721afaf18SBorislav Petkov } 96821afaf18SBorislav Petkov 96921afaf18SBorislav Petkov /* 97021afaf18SBorislav Petkov * Cannot recover? Panic here then. 97121afaf18SBorislav Petkov * This dumps all the mces in the log buffer and stops the 97221afaf18SBorislav Petkov * other CPUs. 97321afaf18SBorislav Petkov */ 97413c877f4STony Luck if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) { 97513c877f4STony Luck /* call mce_severity() to get "msg" for panic */ 97641ce0564SYouquan Song mce_severity(m, NULL, mca_cfg.tolerant, &msg, true); 97721afaf18SBorislav Petkov mce_panic("Fatal machine check", m, msg); 97813c877f4STony Luck } 97921afaf18SBorislav Petkov 98021afaf18SBorislav Petkov /* 98121afaf18SBorislav Petkov * For UC somewhere we let the CPU who detects it handle it. 98221afaf18SBorislav Petkov * Also must let continue the others, otherwise the handling 98321afaf18SBorislav Petkov * CPU could deadlock on a lock. 98421afaf18SBorislav Petkov */ 98521afaf18SBorislav Petkov 98621afaf18SBorislav Petkov /* 98721afaf18SBorislav Petkov * No machine check event found. Must be some external 98821afaf18SBorislav Petkov * source or one CPU is hung. Panic. 98921afaf18SBorislav Petkov */ 99021afaf18SBorislav Petkov if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) 99121afaf18SBorislav Petkov mce_panic("Fatal machine check from unknown source", NULL, NULL); 99221afaf18SBorislav Petkov 99321afaf18SBorislav Petkov /* 99421afaf18SBorislav Petkov * Now clear all the mces_seen so that they don't reappear on 99521afaf18SBorislav Petkov * the next mce. 99621afaf18SBorislav Petkov */ 99721afaf18SBorislav Petkov for_each_possible_cpu(cpu) 99821afaf18SBorislav Petkov memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); 99921afaf18SBorislav Petkov } 100021afaf18SBorislav Petkov 100121afaf18SBorislav Petkov static atomic_t global_nwo; 100221afaf18SBorislav Petkov 100321afaf18SBorislav Petkov /* 100421afaf18SBorislav Petkov * Start of Monarch synchronization. This waits until all CPUs have 100521afaf18SBorislav Petkov * entered the exception handler and then determines if any of them 100621afaf18SBorislav Petkov * saw a fatal event that requires panic. Then it executes them 100721afaf18SBorislav Petkov * in the entry order. 100821afaf18SBorislav Petkov * TBD double check parallel CPU hotunplug 100921afaf18SBorislav Petkov */ 101021afaf18SBorislav Petkov static int mce_start(int *no_way_out) 101121afaf18SBorislav Petkov { 101221afaf18SBorislav Petkov int order; 101321afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 101421afaf18SBorislav Petkov 101521afaf18SBorislav Petkov if (!timeout) 101621afaf18SBorislav Petkov return -1; 101721afaf18SBorislav Petkov 101821afaf18SBorislav Petkov atomic_add(*no_way_out, &global_nwo); 101921afaf18SBorislav Petkov /* 102021afaf18SBorislav Petkov * Rely on the implied barrier below, such that global_nwo 102121afaf18SBorislav Petkov * is updated before mce_callin. 102221afaf18SBorislav Petkov */ 102321afaf18SBorislav Petkov order = atomic_inc_return(&mce_callin); 10247bb39313SPaul E. McKenney cpumask_clear_cpu(smp_processor_id(), &mce_missing_cpus); 102521afaf18SBorislav Petkov 102621afaf18SBorislav Petkov /* 102721afaf18SBorislav Petkov * Wait for everyone. 102821afaf18SBorislav Petkov */ 1029ad669ec1SBorislav Petkov while (atomic_read(&mce_callin) != num_online_cpus()) { 103021afaf18SBorislav Petkov if (mce_timed_out(&timeout, 103121afaf18SBorislav Petkov "Timeout: Not all CPUs entered broadcast exception handler")) { 103221afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 103321afaf18SBorislav Petkov return -1; 103421afaf18SBorislav Petkov } 103521afaf18SBorislav Petkov ndelay(SPINUNIT); 103621afaf18SBorislav Petkov } 103721afaf18SBorislav Petkov 103821afaf18SBorislav Petkov /* 103921afaf18SBorislav Petkov * mce_callin should be read before global_nwo 104021afaf18SBorislav Petkov */ 104121afaf18SBorislav Petkov smp_rmb(); 104221afaf18SBorislav Petkov 104321afaf18SBorislav Petkov if (order == 1) { 104421afaf18SBorislav Petkov /* 104521afaf18SBorislav Petkov * Monarch: Starts executing now, the others wait. 104621afaf18SBorislav Petkov */ 104721afaf18SBorislav Petkov atomic_set(&mce_executing, 1); 104821afaf18SBorislav Petkov } else { 104921afaf18SBorislav Petkov /* 105021afaf18SBorislav Petkov * Subject: Now start the scanning loop one by one in 105121afaf18SBorislav Petkov * the original callin order. 105221afaf18SBorislav Petkov * This way when there are any shared banks it will be 105321afaf18SBorislav Petkov * only seen by one CPU before cleared, avoiding duplicates. 105421afaf18SBorislav Petkov */ 105521afaf18SBorislav Petkov while (atomic_read(&mce_executing) < order) { 105621afaf18SBorislav Petkov if (mce_timed_out(&timeout, 105721afaf18SBorislav Petkov "Timeout: Subject CPUs unable to finish machine check processing")) { 105821afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 105921afaf18SBorislav Petkov return -1; 106021afaf18SBorislav Petkov } 106121afaf18SBorislav Petkov ndelay(SPINUNIT); 106221afaf18SBorislav Petkov } 106321afaf18SBorislav Petkov } 106421afaf18SBorislav Petkov 106521afaf18SBorislav Petkov /* 106621afaf18SBorislav Petkov * Cache the global no_way_out state. 106721afaf18SBorislav Petkov */ 106821afaf18SBorislav Petkov *no_way_out = atomic_read(&global_nwo); 106921afaf18SBorislav Petkov 107021afaf18SBorislav Petkov return order; 107121afaf18SBorislav Petkov } 107221afaf18SBorislav Petkov 107321afaf18SBorislav Petkov /* 107421afaf18SBorislav Petkov * Synchronize between CPUs after main scanning loop. 107521afaf18SBorislav Petkov * This invokes the bulk of the Monarch processing. 107621afaf18SBorislav Petkov */ 1077b4813539SBorislav Petkov static noinstr int mce_end(int order) 107821afaf18SBorislav Petkov { 107921afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 1080b4813539SBorislav Petkov int ret = -1; 1081b4813539SBorislav Petkov 1082b4813539SBorislav Petkov /* Allow instrumentation around external facilities. */ 1083b4813539SBorislav Petkov instrumentation_begin(); 108421afaf18SBorislav Petkov 108521afaf18SBorislav Petkov if (!timeout) 108621afaf18SBorislav Petkov goto reset; 108721afaf18SBorislav Petkov if (order < 0) 108821afaf18SBorislav Petkov goto reset; 108921afaf18SBorislav Petkov 109021afaf18SBorislav Petkov /* 109121afaf18SBorislav Petkov * Allow others to run. 109221afaf18SBorislav Petkov */ 109321afaf18SBorislav Petkov atomic_inc(&mce_executing); 109421afaf18SBorislav Petkov 109521afaf18SBorislav Petkov if (order == 1) { 109621afaf18SBorislav Petkov /* 109721afaf18SBorislav Petkov * Monarch: Wait for everyone to go through their scanning 109821afaf18SBorislav Petkov * loops. 109921afaf18SBorislav Petkov */ 1100ad669ec1SBorislav Petkov while (atomic_read(&mce_executing) <= num_online_cpus()) { 110121afaf18SBorislav Petkov if (mce_timed_out(&timeout, 110221afaf18SBorislav Petkov "Timeout: Monarch CPU unable to finish machine check processing")) 110321afaf18SBorislav Petkov goto reset; 110421afaf18SBorislav Petkov ndelay(SPINUNIT); 110521afaf18SBorislav Petkov } 110621afaf18SBorislav Petkov 110721afaf18SBorislav Petkov mce_reign(); 110821afaf18SBorislav Petkov barrier(); 110921afaf18SBorislav Petkov ret = 0; 111021afaf18SBorislav Petkov } else { 111121afaf18SBorislav Petkov /* 111221afaf18SBorislav Petkov * Subject: Wait for Monarch to finish. 111321afaf18SBorislav Petkov */ 111421afaf18SBorislav Petkov while (atomic_read(&mce_executing) != 0) { 111521afaf18SBorislav Petkov if (mce_timed_out(&timeout, 111621afaf18SBorislav Petkov "Timeout: Monarch CPU did not finish machine check processing")) 111721afaf18SBorislav Petkov goto reset; 111821afaf18SBorislav Petkov ndelay(SPINUNIT); 111921afaf18SBorislav Petkov } 112021afaf18SBorislav Petkov 112121afaf18SBorislav Petkov /* 112221afaf18SBorislav Petkov * Don't reset anything. That's done by the Monarch. 112321afaf18SBorislav Petkov */ 1124b4813539SBorislav Petkov ret = 0; 1125b4813539SBorislav Petkov goto out; 112621afaf18SBorislav Petkov } 112721afaf18SBorislav Petkov 112821afaf18SBorislav Petkov /* 112921afaf18SBorislav Petkov * Reset all global state. 113021afaf18SBorislav Petkov */ 113121afaf18SBorislav Petkov reset: 113221afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 113321afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 11347bb39313SPaul E. McKenney cpumask_setall(&mce_missing_cpus); 113521afaf18SBorislav Petkov barrier(); 113621afaf18SBorislav Petkov 113721afaf18SBorislav Petkov /* 113821afaf18SBorislav Petkov * Let others run again. 113921afaf18SBorislav Petkov */ 114021afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 1141b4813539SBorislav Petkov 1142b4813539SBorislav Petkov out: 1143b4813539SBorislav Petkov instrumentation_end(); 1144b4813539SBorislav Petkov 114521afaf18SBorislav Petkov return ret; 114621afaf18SBorislav Petkov } 114721afaf18SBorislav Petkov 114821afaf18SBorislav Petkov static void mce_clear_state(unsigned long *toclear) 114921afaf18SBorislav Petkov { 115021afaf18SBorislav Petkov int i; 115121afaf18SBorislav Petkov 1152c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 115321afaf18SBorislav Petkov if (test_bit(i, toclear)) 11548121b8f9SBorislav Petkov mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 115521afaf18SBorislav Petkov } 115621afaf18SBorislav Petkov } 115721afaf18SBorislav Petkov 115821afaf18SBorislav Petkov /* 115921afaf18SBorislav Petkov * Cases where we avoid rendezvous handler timeout: 116021afaf18SBorislav Petkov * 1) If this CPU is offline. 116121afaf18SBorislav Petkov * 116221afaf18SBorislav Petkov * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to 116321afaf18SBorislav Petkov * skip those CPUs which remain looping in the 1st kernel - see 116421afaf18SBorislav Petkov * crash_nmi_callback(). 116521afaf18SBorislav Petkov * 116621afaf18SBorislav Petkov * Note: there still is a small window between kexec-ing and the new, 116721afaf18SBorislav Petkov * kdump kernel establishing a new #MC handler where a broadcasted MCE 116821afaf18SBorislav Petkov * might not get handled properly. 116921afaf18SBorislav Petkov */ 117094a46d31SThomas Gleixner static noinstr bool mce_check_crashing_cpu(void) 117121afaf18SBorislav Petkov { 117294a46d31SThomas Gleixner unsigned int cpu = smp_processor_id(); 117394a46d31SThomas Gleixner 117414d3b376SPeter Zijlstra if (arch_cpu_is_offline(cpu) || 117521afaf18SBorislav Petkov (crashing_cpu != -1 && crashing_cpu != cpu)) { 117621afaf18SBorislav Petkov u64 mcgstatus; 117721afaf18SBorislav Petkov 1178aedbdeabSThomas Gleixner mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS); 117970f0c230STony W Wang-oc 118070f0c230STony W Wang-oc if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { 118170f0c230STony W Wang-oc if (mcgstatus & MCG_STATUS_LMCES) 118270f0c230STony W Wang-oc return false; 118370f0c230STony W Wang-oc } 118470f0c230STony W Wang-oc 118521afaf18SBorislav Petkov if (mcgstatus & MCG_STATUS_RIPV) { 1186aedbdeabSThomas Gleixner __wrmsr(MSR_IA32_MCG_STATUS, 0, 0); 118721afaf18SBorislav Petkov return true; 118821afaf18SBorislav Petkov } 118921afaf18SBorislav Petkov } 119021afaf18SBorislav Petkov return false; 119121afaf18SBorislav Petkov } 119221afaf18SBorislav Petkov 119375581a20SBorislav Petkov static __always_inline int 119475581a20SBorislav Petkov __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final, 119575581a20SBorislav Petkov unsigned long *toclear, unsigned long *valid_banks, int no_way_out, 119675581a20SBorislav Petkov int *worst) 119721afaf18SBorislav Petkov { 1198b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 119921afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 120075581a20SBorislav Petkov int severity, i, taint = 0; 120121afaf18SBorislav Petkov 1202c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 120321afaf18SBorislav Petkov __clear_bit(i, toclear); 120421afaf18SBorislav Petkov if (!test_bit(i, valid_banks)) 120521afaf18SBorislav Petkov continue; 120621afaf18SBorislav Petkov 120721afaf18SBorislav Petkov if (!mce_banks[i].ctl) 120821afaf18SBorislav Petkov continue; 120921afaf18SBorislav Petkov 121021afaf18SBorislav Petkov m->misc = 0; 121121afaf18SBorislav Petkov m->addr = 0; 121221afaf18SBorislav Petkov m->bank = i; 121321afaf18SBorislav Petkov 12148121b8f9SBorislav Petkov m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 121521afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 121621afaf18SBorislav Petkov continue; 121721afaf18SBorislav Petkov 121821afaf18SBorislav Petkov /* 121921afaf18SBorislav Petkov * Corrected or non-signaled errors are handled by 122021afaf18SBorislav Petkov * machine_check_poll(). Leave them alone, unless this panics. 122121afaf18SBorislav Petkov */ 122221afaf18SBorislav Petkov if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && 122321afaf18SBorislav Petkov !no_way_out) 122421afaf18SBorislav Petkov continue; 122521afaf18SBorislav Petkov 122621afaf18SBorislav Petkov /* Set taint even when machine check was not enabled. */ 122775581a20SBorislav Petkov taint++; 122821afaf18SBorislav Petkov 122941ce0564SYouquan Song severity = mce_severity(m, regs, cfg->tolerant, NULL, true); 123021afaf18SBorislav Petkov 123121afaf18SBorislav Petkov /* 123221afaf18SBorislav Petkov * When machine check was for corrected/deferred handler don't 123321afaf18SBorislav Petkov * touch, unless we're panicking. 123421afaf18SBorislav Petkov */ 123521afaf18SBorislav Petkov if ((severity == MCE_KEEP_SEVERITY || 123621afaf18SBorislav Petkov severity == MCE_UCNA_SEVERITY) && !no_way_out) 123721afaf18SBorislav Petkov continue; 123821afaf18SBorislav Petkov 123921afaf18SBorislav Petkov __set_bit(i, toclear); 124021afaf18SBorislav Petkov 124121afaf18SBorislav Petkov /* Machine check event was not enabled. Clear, but ignore. */ 124221afaf18SBorislav Petkov if (severity == MCE_NO_SEVERITY) 124321afaf18SBorislav Petkov continue; 124421afaf18SBorislav Petkov 124521afaf18SBorislav Petkov mce_read_aux(m, i); 124621afaf18SBorislav Petkov 124721afaf18SBorislav Petkov /* assuming valid severity level != 0 */ 124821afaf18SBorislav Petkov m->severity = severity; 124921afaf18SBorislav Petkov 125075581a20SBorislav Petkov /* 125175581a20SBorislav Petkov * Enable instrumentation around the mce_log() call which is 125275581a20SBorislav Petkov * done in #MC context, where instrumentation is disabled. 125375581a20SBorislav Petkov */ 125475581a20SBorislav Petkov instrumentation_begin(); 125521afaf18SBorislav Petkov mce_log(m); 125675581a20SBorislav Petkov instrumentation_end(); 125721afaf18SBorislav Petkov 125821afaf18SBorislav Petkov if (severity > *worst) { 125921afaf18SBorislav Petkov *final = *m; 126021afaf18SBorislav Petkov *worst = severity; 126121afaf18SBorislav Petkov } 126221afaf18SBorislav Petkov } 126321afaf18SBorislav Petkov 126421afaf18SBorislav Petkov /* mce_clear_state will clear *final, save locally for use later */ 126521afaf18SBorislav Petkov *m = *final; 126675581a20SBorislav Petkov 126775581a20SBorislav Petkov return taint; 126821afaf18SBorislav Petkov } 126921afaf18SBorislav Petkov 12705567d11cSPeter Zijlstra static void kill_me_now(struct callback_head *ch) 12715567d11cSPeter Zijlstra { 127281065b35STony Luck struct task_struct *p = container_of(ch, struct task_struct, mce_kill_me); 127381065b35STony Luck 127481065b35STony Luck p->mce_count = 0; 12755567d11cSPeter Zijlstra force_sig(SIGBUS); 12765567d11cSPeter Zijlstra } 12775567d11cSPeter Zijlstra 12785567d11cSPeter Zijlstra static void kill_me_maybe(struct callback_head *cb) 12795567d11cSPeter Zijlstra { 12805567d11cSPeter Zijlstra struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me); 12815567d11cSPeter Zijlstra int flags = MF_ACTION_REQUIRED; 1282a3f5d80eSNaoya Horiguchi int ret; 12835567d11cSPeter Zijlstra 128481065b35STony Luck p->mce_count = 0; 12855567d11cSPeter Zijlstra pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr); 128617fae129STony Luck 128717fae129STony Luck if (!p->mce_ripv) 12885567d11cSPeter Zijlstra flags |= MF_MUST_KILL; 12895567d11cSPeter Zijlstra 1290a3f5d80eSNaoya Horiguchi ret = memory_failure(p->mce_addr >> PAGE_SHIFT, flags); 1291a6e3cf70STony Luck if (!ret) { 129217fae129STony Luck set_mce_nospec(p->mce_addr >> PAGE_SHIFT, p->mce_whole_page); 12931e36d9c6STony Luck sync_core(); 12945567d11cSPeter Zijlstra return; 12955567d11cSPeter Zijlstra } 12965567d11cSPeter Zijlstra 1297a3f5d80eSNaoya Horiguchi /* 1298a3f5d80eSNaoya Horiguchi * -EHWPOISON from memory_failure() means that it already sent SIGBUS 1299a3f5d80eSNaoya Horiguchi * to the current process with the proper error info, so no need to 1300a3f5d80eSNaoya Horiguchi * send SIGBUS here again. 1301a3f5d80eSNaoya Horiguchi */ 1302a3f5d80eSNaoya Horiguchi if (ret == -EHWPOISON) 1303a3f5d80eSNaoya Horiguchi return; 1304a3f5d80eSNaoya Horiguchi 13055567d11cSPeter Zijlstra pr_err("Memory error not recovered"); 13065567d11cSPeter Zijlstra kill_me_now(cb); 13075567d11cSPeter Zijlstra } 1308a6e3cf70STony Luck 1309a6e3cf70STony Luck static void kill_me_never(struct callback_head *cb) 1310a6e3cf70STony Luck { 1311a6e3cf70STony Luck struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me); 1312a6e3cf70STony Luck 1313a6e3cf70STony Luck p->mce_count = 0; 1314a6e3cf70STony Luck pr_err("Kernel accessed poison in user space at %llx\n", p->mce_addr); 1315a6e3cf70STony Luck if (!memory_failure(p->mce_addr >> PAGE_SHIFT, 0)) 1316a6e3cf70STony Luck set_mce_nospec(p->mce_addr >> PAGE_SHIFT, p->mce_whole_page); 131730063810STony Luck } 13185567d11cSPeter Zijlstra 1319a6e3cf70STony Luck static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callback_head *)) 1320c0ab7ffcSTony Luck { 132181065b35STony Luck int count = ++current->mce_count; 132281065b35STony Luck 132381065b35STony Luck /* First call, save all the details */ 132481065b35STony Luck if (count == 1) { 1325c0ab7ffcSTony Luck current->mce_addr = m->addr; 1326c0ab7ffcSTony Luck current->mce_kflags = m->kflags; 1327c0ab7ffcSTony Luck current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV); 1328c0ab7ffcSTony Luck current->mce_whole_page = whole_page(m); 1329a6e3cf70STony Luck current->mce_kill_me.func = func; 133081065b35STony Luck } 133181065b35STony Luck 133281065b35STony Luck /* Ten is likely overkill. Don't expect more than two faults before task_work() */ 133381065b35STony Luck if (count > 10) 133481065b35STony Luck mce_panic("Too many consecutive machine checks while accessing user data", m, msg); 133581065b35STony Luck 133681065b35STony Luck /* Second or later call, make sure page address matches the one from first call */ 133781065b35STony Luck if (count > 1 && (current->mce_addr >> PAGE_SHIFT) != (m->addr >> PAGE_SHIFT)) 133881065b35STony Luck mce_panic("Consecutive machine checks to different user pages", m, msg); 133981065b35STony Luck 134081065b35STony Luck /* Do not call task_work_add() more than once */ 134181065b35STony Luck if (count > 1) 134281065b35STony Luck return; 1343c0ab7ffcSTony Luck 134491989c70SJens Axboe task_work_add(current, ¤t->mce_kill_me, TWA_RESUME); 1345c0ab7ffcSTony Luck } 134621afaf18SBorislav Petkov 1347cbe1de16SBorislav Petkov /* Handle unconfigured int18 (should never happen) */ 1348cbe1de16SBorislav Petkov static noinstr void unexpected_machine_check(struct pt_regs *regs) 1349cbe1de16SBorislav Petkov { 1350cbe1de16SBorislav Petkov instrumentation_begin(); 1351cbe1de16SBorislav Petkov pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", 1352cbe1de16SBorislav Petkov smp_processor_id()); 1353cbe1de16SBorislav Petkov instrumentation_end(); 1354cbe1de16SBorislav Petkov } 1355cbe1de16SBorislav Petkov 135621afaf18SBorislav Petkov /* 1357487d654dSBorislav Petkov * The actual machine check handler. This only handles real exceptions when 1358487d654dSBorislav Petkov * something got corrupted coming in through int 18. 135921afaf18SBorislav Petkov * 1360487d654dSBorislav Petkov * This is executed in #MC context not subject to normal locking rules. 1361487d654dSBorislav Petkov * This implies that most kernel services cannot be safely used. Don't even 136221afaf18SBorislav Petkov * think about putting a printk in there! 136321afaf18SBorislav Petkov * 136421afaf18SBorislav Petkov * On Intel systems this is entered on all CPUs in parallel through 136521afaf18SBorislav Petkov * MCE broadcast. However some CPUs might be broken beyond repair, 136621afaf18SBorislav Petkov * so be always careful when synchronizing with others. 136755ba18d6SAndy Lutomirski * 136855ba18d6SAndy Lutomirski * Tracing and kprobes are disabled: if we interrupted a kernel context 136955ba18d6SAndy Lutomirski * with IF=1, we need to minimize stack usage. There are also recursion 137055ba18d6SAndy Lutomirski * issues: if the machine check was due to a failure of the memory 137155ba18d6SAndy Lutomirski * backing the user stack, tracing that reads the user stack will cause 137255ba18d6SAndy Lutomirski * potentially infinite recursion. 1373487d654dSBorislav Petkov * 1374487d654dSBorislav Petkov * Currently, the #MC handler calls out to a number of external facilities 1375487d654dSBorislav Petkov * and, therefore, allows instrumentation around them. The optimal thing to 1376487d654dSBorislav Petkov * have would be to do the absolutely minimal work required in #MC context 1377487d654dSBorislav Petkov * and have instrumentation disabled only around that. Further processing can 1378487d654dSBorislav Petkov * then happen in process context where instrumentation is allowed. Achieving 1379487d654dSBorislav Petkov * that requires careful auditing and modifications. Until then, the code 1380487d654dSBorislav Petkov * allows instrumentation temporarily, where required. * 138121afaf18SBorislav Petkov */ 13827f6fa101SIra Weiny noinstr void do_machine_check(struct pt_regs *regs) 138321afaf18SBorislav Petkov { 138475581a20SBorislav Petkov int worst = 0, order, no_way_out, kill_current_task, lmce, taint = 0; 1385cd5e0d1fSBorislav Petkov DECLARE_BITMAP(valid_banks, MAX_NR_BANKS) = { 0 }; 1386cd5e0d1fSBorislav Petkov DECLARE_BITMAP(toclear, MAX_NR_BANKS) = { 0 }; 138721afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 138821afaf18SBorislav Petkov struct mce m, *final; 13897a8bc2b0SJan H. Schönherr char *msg = NULL; 1390cbe1de16SBorislav Petkov 1391cbe1de16SBorislav Petkov if (unlikely(mce_flags.p5)) 1392cbe1de16SBorislav Petkov return pentium_machine_check(regs); 1393cbe1de16SBorislav Petkov else if (unlikely(mce_flags.winchip)) 1394cbe1de16SBorislav Petkov return winchip_machine_check(regs); 1395cbe1de16SBorislav Petkov else if (unlikely(!mca_cfg.initialized)) 1396cbe1de16SBorislav Petkov return unexpected_machine_check(regs); 139721afaf18SBorislav Petkov 139821afaf18SBorislav Petkov /* 139921afaf18SBorislav Petkov * Establish sequential order between the CPUs entering the machine 140021afaf18SBorislav Petkov * check handler. 140121afaf18SBorislav Petkov */ 1402cbe1de16SBorislav Petkov order = -1; 140321afaf18SBorislav Petkov 140421afaf18SBorislav Petkov /* 140521afaf18SBorislav Petkov * If no_way_out gets set, there is no safe way to recover from this 140621afaf18SBorislav Petkov * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. 140721afaf18SBorislav Petkov */ 1408cbe1de16SBorislav Petkov no_way_out = 0; 140921afaf18SBorislav Petkov 141021afaf18SBorislav Petkov /* 1411e1c06d23SGabriele Paoloni * If kill_current_task is not set, there might be a way to recover from this 141221afaf18SBorislav Petkov * error. 141321afaf18SBorislav Petkov */ 1414cbe1de16SBorislav Petkov kill_current_task = 0; 141521afaf18SBorislav Petkov 141621afaf18SBorislav Petkov /* 141721afaf18SBorislav Petkov * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES 141821afaf18SBorislav Petkov * on Intel. 141921afaf18SBorislav Petkov */ 1420cbe1de16SBorislav Petkov lmce = 1; 142121afaf18SBorislav Petkov 142221afaf18SBorislav Petkov this_cpu_inc(mce_exception_count); 142321afaf18SBorislav Petkov 142421afaf18SBorislav Petkov mce_gather_info(&m, regs); 142521afaf18SBorislav Petkov m.tsc = rdtsc(); 142621afaf18SBorislav Petkov 142721afaf18SBorislav Petkov final = this_cpu_ptr(&mces_seen); 142821afaf18SBorislav Petkov *final = m; 142921afaf18SBorislav Petkov 143021afaf18SBorislav Petkov no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); 143121afaf18SBorislav Petkov 143221afaf18SBorislav Petkov barrier(); 143321afaf18SBorislav Petkov 143421afaf18SBorislav Petkov /* 143521afaf18SBorislav Petkov * When no restart IP might need to kill or panic. 143621afaf18SBorislav Petkov * Assume the worst for now, but if we find the 143721afaf18SBorislav Petkov * severity is MCE_AR_SEVERITY we have other options. 143821afaf18SBorislav Petkov */ 143921afaf18SBorislav Petkov if (!(m.mcgstatus & MCG_STATUS_RIPV)) 1440e1c06d23SGabriele Paoloni kill_current_task = (cfg->tolerant == 3) ? 0 : 1; 144121afaf18SBorislav Petkov /* 144221afaf18SBorislav Petkov * Check if this MCE is signaled to only this logical processor, 144370f0c230STony W Wang-oc * on Intel, Zhaoxin only. 144421afaf18SBorislav Petkov */ 144570f0c230STony W Wang-oc if (m.cpuvendor == X86_VENDOR_INTEL || 144670f0c230STony W Wang-oc m.cpuvendor == X86_VENDOR_ZHAOXIN) 144721afaf18SBorislav Petkov lmce = m.mcgstatus & MCG_STATUS_LMCES; 144821afaf18SBorislav Petkov 144921afaf18SBorislav Petkov /* 145021afaf18SBorislav Petkov * Local machine check may already know that we have to panic. 145121afaf18SBorislav Petkov * Broadcast machine check begins rendezvous in mce_start() 145221afaf18SBorislav Petkov * Go through all banks in exclusion of the other CPUs. This way we 145321afaf18SBorislav Petkov * don't report duplicated events on shared banks because the first one 145421afaf18SBorislav Petkov * to see it will clear it. 145521afaf18SBorislav Petkov */ 145621afaf18SBorislav Petkov if (lmce) { 14573a866b16SGabriele Paoloni if (no_way_out && cfg->tolerant < 3) 145821afaf18SBorislav Petkov mce_panic("Fatal local machine check", &m, msg); 145921afaf18SBorislav Petkov } else { 146021afaf18SBorislav Petkov order = mce_start(&no_way_out); 146121afaf18SBorislav Petkov } 146221afaf18SBorislav Petkov 146375581a20SBorislav Petkov taint = __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst); 146421afaf18SBorislav Petkov 146521afaf18SBorislav Petkov if (!no_way_out) 146621afaf18SBorislav Petkov mce_clear_state(toclear); 146721afaf18SBorislav Petkov 146821afaf18SBorislav Petkov /* 146921afaf18SBorislav Petkov * Do most of the synchronization with other CPUs. 147021afaf18SBorislav Petkov * When there's any problem use only local no_way_out state. 147121afaf18SBorislav Petkov */ 147221afaf18SBorislav Petkov if (!lmce) { 147325bc65d8SGabriele Paoloni if (mce_end(order) < 0) { 147425bc65d8SGabriele Paoloni if (!no_way_out) 147521afaf18SBorislav Petkov no_way_out = worst >= MCE_PANIC_SEVERITY; 1476e273e6e1SGabriele Paoloni 1477e273e6e1SGabriele Paoloni if (no_way_out && cfg->tolerant < 3) 1478e273e6e1SGabriele Paoloni mce_panic("Fatal machine check on current CPU", &m, msg); 147925bc65d8SGabriele Paoloni } 148021afaf18SBorislav Petkov } else { 148121afaf18SBorislav Petkov /* 148221afaf18SBorislav Petkov * If there was a fatal machine check we should have 148321afaf18SBorislav Petkov * already called mce_panic earlier in this function. 148421afaf18SBorislav Petkov * Since we re-read the banks, we might have found 148521afaf18SBorislav Petkov * something new. Check again to see if we found a 148621afaf18SBorislav Petkov * fatal error. We call "mce_severity()" again to 148721afaf18SBorislav Petkov * make sure we have the right "msg". 148821afaf18SBorislav Petkov */ 148921afaf18SBorislav Petkov if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) { 149041ce0564SYouquan Song mce_severity(&m, regs, cfg->tolerant, &msg, true); 149121afaf18SBorislav Petkov mce_panic("Local fatal machine check!", &m, msg); 149221afaf18SBorislav Petkov } 149321afaf18SBorislav Petkov } 149421afaf18SBorislav Petkov 14954fbce464SBorislav Petkov /* 149675581a20SBorislav Petkov * Enable instrumentation around the external facilities like task_work_add() 149775581a20SBorislav Petkov * (via queue_task_work()), fixup_exception() etc. For now, that is. Fixing this 149875581a20SBorislav Petkov * properly would need a lot more involved reorganization. 14994fbce464SBorislav Petkov */ 15004fbce464SBorislav Petkov instrumentation_begin(); 15014fbce464SBorislav Petkov 150275581a20SBorislav Petkov if (taint) 150375581a20SBorislav Petkov add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 150475581a20SBorislav Petkov 150575581a20SBorislav Petkov if (worst != MCE_AR_SEVERITY && !kill_current_task) 150675581a20SBorislav Petkov goto out; 150775581a20SBorislav Petkov 150821afaf18SBorislav Petkov /* Fault was in user mode and we need to take some action */ 150921afaf18SBorislav Petkov if ((m.cs & 3) == 3) { 1510b052df3dSThomas Gleixner /* If this triggers there is no way to recover. Die hard. */ 1511b052df3dSThomas Gleixner BUG_ON(!on_thread_stack() || !user_mode(regs)); 151221afaf18SBorislav Petkov 1513a6e3cf70STony Luck if (kill_current_task) 1514a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_now); 1515a6e3cf70STony Luck else 1516a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_maybe); 1517c0ab7ffcSTony Luck 151821afaf18SBorislav Petkov } else { 15191df73b21SBorislav Petkov /* 15201df73b21SBorislav Petkov * Handle an MCE which has happened in kernel space but from 15211df73b21SBorislav Petkov * which the kernel can recover: ex_has_fault_handler() has 15221df73b21SBorislav Petkov * already verified that the rIP at which the error happened is 15231df73b21SBorislav Petkov * a rIP from which the kernel can recover (by jumping to 15241df73b21SBorislav Petkov * recovery code specified in _ASM_EXTABLE_FAULT()) and the 15251df73b21SBorislav Petkov * corresponding exception handler which would do that is the 15261df73b21SBorislav Petkov * proper one. 15271df73b21SBorislav Petkov */ 15281df73b21SBorislav Petkov if (m.kflags & MCE_IN_KERNEL_RECOV) { 15298cd501c1SThomas Gleixner if (!fixup_exception(regs, X86_TRAP_MC, 0, 0)) 15302d806d07SJan H. Schönherr mce_panic("Failed kernel mode recovery", &m, msg); 153121afaf18SBorislav Petkov } 1532c0ab7ffcSTony Luck 1533c0ab7ffcSTony Luck if (m.kflags & MCE_IN_KERNEL_COPYIN) 1534a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_never); 15351df73b21SBorislav Petkov } 15364fbce464SBorislav Petkov 153775581a20SBorislav Petkov out: 15384fbce464SBorislav Petkov instrumentation_end(); 15394fbce464SBorislav Petkov 15401e36d9c6STony Luck mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); 154121afaf18SBorislav Petkov } 154221afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(do_machine_check); 154321afaf18SBorislav Petkov 154421afaf18SBorislav Petkov #ifndef CONFIG_MEMORY_FAILURE 154521afaf18SBorislav Petkov int memory_failure(unsigned long pfn, int flags) 154621afaf18SBorislav Petkov { 154721afaf18SBorislav Petkov /* mce_severity() should not hand us an ACTION_REQUIRED error */ 154821afaf18SBorislav Petkov BUG_ON(flags & MF_ACTION_REQUIRED); 154921afaf18SBorislav Petkov pr_err("Uncorrected memory error in page 0x%lx ignored\n" 155021afaf18SBorislav Petkov "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", 155121afaf18SBorislav Petkov pfn); 155221afaf18SBorislav Petkov 155321afaf18SBorislav Petkov return 0; 155421afaf18SBorislav Petkov } 155521afaf18SBorislav Petkov #endif 155621afaf18SBorislav Petkov 155721afaf18SBorislav Petkov /* 155821afaf18SBorislav Petkov * Periodic polling timer for "silent" machine check errors. If the 155921afaf18SBorislav Petkov * poller finds an MCE, poll 2x faster. When the poller finds no more 156021afaf18SBorislav Petkov * errors, poll 2x slower (up to check_interval seconds). 156121afaf18SBorislav Petkov */ 156221afaf18SBorislav Petkov static unsigned long check_interval = INITIAL_CHECK_INTERVAL; 156321afaf18SBorislav Petkov 156421afaf18SBorislav Petkov static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ 156521afaf18SBorislav Petkov static DEFINE_PER_CPU(struct timer_list, mce_timer); 156621afaf18SBorislav Petkov 156721afaf18SBorislav Petkov static unsigned long mce_adjust_timer_default(unsigned long interval) 156821afaf18SBorislav Petkov { 156921afaf18SBorislav Petkov return interval; 157021afaf18SBorislav Petkov } 157121afaf18SBorislav Petkov 157221afaf18SBorislav Petkov static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; 157321afaf18SBorislav Petkov 157421afaf18SBorislav Petkov static void __start_timer(struct timer_list *t, unsigned long interval) 157521afaf18SBorislav Petkov { 157621afaf18SBorislav Petkov unsigned long when = jiffies + interval; 157721afaf18SBorislav Petkov unsigned long flags; 157821afaf18SBorislav Petkov 157921afaf18SBorislav Petkov local_irq_save(flags); 158021afaf18SBorislav Petkov 158121afaf18SBorislav Petkov if (!timer_pending(t) || time_before(when, t->expires)) 158221afaf18SBorislav Petkov mod_timer(t, round_jiffies(when)); 158321afaf18SBorislav Petkov 158421afaf18SBorislav Petkov local_irq_restore(flags); 158521afaf18SBorislav Petkov } 158621afaf18SBorislav Petkov 158721afaf18SBorislav Petkov static void mce_timer_fn(struct timer_list *t) 158821afaf18SBorislav Petkov { 158921afaf18SBorislav Petkov struct timer_list *cpu_t = this_cpu_ptr(&mce_timer); 159021afaf18SBorislav Petkov unsigned long iv; 159121afaf18SBorislav Petkov 159221afaf18SBorislav Petkov WARN_ON(cpu_t != t); 159321afaf18SBorislav Petkov 159421afaf18SBorislav Petkov iv = __this_cpu_read(mce_next_interval); 159521afaf18SBorislav Petkov 159621afaf18SBorislav Petkov if (mce_available(this_cpu_ptr(&cpu_info))) { 159721afaf18SBorislav Petkov machine_check_poll(0, this_cpu_ptr(&mce_poll_banks)); 159821afaf18SBorislav Petkov 159921afaf18SBorislav Petkov if (mce_intel_cmci_poll()) { 160021afaf18SBorislav Petkov iv = mce_adjust_timer(iv); 160121afaf18SBorislav Petkov goto done; 160221afaf18SBorislav Petkov } 160321afaf18SBorislav Petkov } 160421afaf18SBorislav Petkov 160521afaf18SBorislav Petkov /* 160621afaf18SBorislav Petkov * Alert userspace if needed. If we logged an MCE, reduce the polling 160721afaf18SBorislav Petkov * interval, otherwise increase the polling interval. 160821afaf18SBorislav Petkov */ 160921afaf18SBorislav Petkov if (mce_notify_irq()) 161021afaf18SBorislav Petkov iv = max(iv / 2, (unsigned long) HZ/100); 161121afaf18SBorislav Petkov else 161221afaf18SBorislav Petkov iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); 161321afaf18SBorislav Petkov 161421afaf18SBorislav Petkov done: 161521afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, iv); 161621afaf18SBorislav Petkov __start_timer(t, iv); 161721afaf18SBorislav Petkov } 161821afaf18SBorislav Petkov 161921afaf18SBorislav Petkov /* 162021afaf18SBorislav Petkov * Ensure that the timer is firing in @interval from now. 162121afaf18SBorislav Petkov */ 162221afaf18SBorislav Petkov void mce_timer_kick(unsigned long interval) 162321afaf18SBorislav Petkov { 162421afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 162521afaf18SBorislav Petkov unsigned long iv = __this_cpu_read(mce_next_interval); 162621afaf18SBorislav Petkov 162721afaf18SBorislav Petkov __start_timer(t, interval); 162821afaf18SBorislav Petkov 162921afaf18SBorislav Petkov if (interval < iv) 163021afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, interval); 163121afaf18SBorislav Petkov } 163221afaf18SBorislav Petkov 163321afaf18SBorislav Petkov /* Must not be called in IRQ context where del_timer_sync() can deadlock */ 163421afaf18SBorislav Petkov static void mce_timer_delete_all(void) 163521afaf18SBorislav Petkov { 163621afaf18SBorislav Petkov int cpu; 163721afaf18SBorislav Petkov 163821afaf18SBorislav Petkov for_each_online_cpu(cpu) 163921afaf18SBorislav Petkov del_timer_sync(&per_cpu(mce_timer, cpu)); 164021afaf18SBorislav Petkov } 164121afaf18SBorislav Petkov 164221afaf18SBorislav Petkov /* 164321afaf18SBorislav Petkov * Notify the user(s) about new machine check events. 164421afaf18SBorislav Petkov * Can be called from interrupt context, but not from machine check/NMI 164521afaf18SBorislav Petkov * context. 164621afaf18SBorislav Petkov */ 164721afaf18SBorislav Petkov int mce_notify_irq(void) 164821afaf18SBorislav Petkov { 164921afaf18SBorislav Petkov /* Not more than two messages every minute */ 165021afaf18SBorislav Petkov static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); 165121afaf18SBorislav Petkov 165221afaf18SBorislav Petkov if (test_and_clear_bit(0, &mce_need_notify)) { 165321afaf18SBorislav Petkov mce_work_trigger(); 165421afaf18SBorislav Petkov 165521afaf18SBorislav Petkov if (__ratelimit(&ratelimit)) 165621afaf18SBorislav Petkov pr_info(HW_ERR "Machine check events logged\n"); 165721afaf18SBorislav Petkov 165821afaf18SBorislav Petkov return 1; 165921afaf18SBorislav Petkov } 166021afaf18SBorislav Petkov return 0; 166121afaf18SBorislav Petkov } 166221afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_notify_irq); 166321afaf18SBorislav Petkov 1664b4914508SYazen Ghannam static void __mcheck_cpu_mce_banks_init(void) 166521afaf18SBorislav Petkov { 1666b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1667c7d314f3SYazen Ghannam u8 n_banks = this_cpu_read(mce_num_banks); 166821afaf18SBorislav Petkov int i; 166921afaf18SBorislav Petkov 1670c7d314f3SYazen Ghannam for (i = 0; i < n_banks; i++) { 167121afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 167221afaf18SBorislav Petkov 1673068b053dSYazen Ghannam /* 1674068b053dSYazen Ghannam * Init them all, __mcheck_cpu_apply_quirks() is going to apply 1675068b053dSYazen Ghannam * the required vendor quirks before 1676068b053dSYazen Ghannam * __mcheck_cpu_init_clear_banks() does the final bank setup. 1677068b053dSYazen Ghannam */ 167821afaf18SBorislav Petkov b->ctl = -1ULL; 167977080929SKaixu Xia b->init = true; 168021afaf18SBorislav Petkov } 168121afaf18SBorislav Petkov } 168221afaf18SBorislav Petkov 168321afaf18SBorislav Petkov /* 168421afaf18SBorislav Petkov * Initialize Machine Checks for a CPU. 168521afaf18SBorislav Petkov */ 1686b4914508SYazen Ghannam static void __mcheck_cpu_cap_init(void) 168721afaf18SBorislav Petkov { 168821afaf18SBorislav Petkov u64 cap; 1689006c0770SYazen Ghannam u8 b; 169021afaf18SBorislav Petkov 169121afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 169221afaf18SBorislav Petkov 169321afaf18SBorislav Petkov b = cap & MCG_BANKCNT_MASK; 169421afaf18SBorislav Petkov 1695c7d314f3SYazen Ghannam if (b > MAX_NR_BANKS) { 1696c7d314f3SYazen Ghannam pr_warn("CPU%d: Using only %u machine check banks out of %u\n", 1697c7d314f3SYazen Ghannam smp_processor_id(), MAX_NR_BANKS, b); 1698c7d314f3SYazen Ghannam b = MAX_NR_BANKS; 1699c7d314f3SYazen Ghannam } 1700c7d314f3SYazen Ghannam 1701c7d314f3SYazen Ghannam this_cpu_write(mce_num_banks, b); 170221afaf18SBorislav Petkov 1703b4914508SYazen Ghannam __mcheck_cpu_mce_banks_init(); 170421afaf18SBorislav Petkov 170521afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 170621afaf18SBorislav Petkov if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) 170721afaf18SBorislav Petkov mca_cfg.rip_msr = MSR_IA32_MCG_EIP; 170821afaf18SBorislav Petkov 170921afaf18SBorislav Petkov if (cap & MCG_SER_P) 171021afaf18SBorislav Petkov mca_cfg.ser = 1; 171121afaf18SBorislav Petkov } 171221afaf18SBorislav Petkov 171321afaf18SBorislav Petkov static void __mcheck_cpu_init_generic(void) 171421afaf18SBorislav Petkov { 171521afaf18SBorislav Petkov enum mcp_flags m_fl = 0; 171621afaf18SBorislav Petkov mce_banks_t all_banks; 171721afaf18SBorislav Petkov u64 cap; 171821afaf18SBorislav Petkov 171921afaf18SBorislav Petkov if (!mca_cfg.bootlog) 172021afaf18SBorislav Petkov m_fl = MCP_DONTLOG; 172121afaf18SBorislav Petkov 172221afaf18SBorislav Petkov /* 17233bff147bSBorislav Petkov * Log the machine checks left over from the previous reset. Log them 17243bff147bSBorislav Petkov * only, do not start processing them. That will happen in mcheck_late_init() 17253bff147bSBorislav Petkov * when all consumers have been registered on the notifier chain. 172621afaf18SBorislav Petkov */ 172721afaf18SBorislav Petkov bitmap_fill(all_banks, MAX_NR_BANKS); 17283bff147bSBorislav Petkov machine_check_poll(MCP_UC | MCP_QUEUE_LOG | m_fl, &all_banks); 172921afaf18SBorislav Petkov 173021afaf18SBorislav Petkov cr4_set_bits(X86_CR4_MCE); 173121afaf18SBorislav Petkov 173221afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 173321afaf18SBorislav Petkov if (cap & MCG_CTL_P) 173421afaf18SBorislav Petkov wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); 173521afaf18SBorislav Petkov } 173621afaf18SBorislav Petkov 173721afaf18SBorislav Petkov static void __mcheck_cpu_init_clear_banks(void) 173821afaf18SBorislav Petkov { 1739b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 174021afaf18SBorislav Petkov int i; 174121afaf18SBorislav Petkov 1742c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 174321afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 174421afaf18SBorislav Petkov 174521afaf18SBorislav Petkov if (!b->init) 174621afaf18SBorislav Petkov continue; 17478121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); 17488121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 174921afaf18SBorislav Petkov } 175021afaf18SBorislav Petkov } 175121afaf18SBorislav Petkov 175221afaf18SBorislav Petkov /* 1753068b053dSYazen Ghannam * Do a final check to see if there are any unused/RAZ banks. 1754068b053dSYazen Ghannam * 1755068b053dSYazen Ghannam * This must be done after the banks have been initialized and any quirks have 1756068b053dSYazen Ghannam * been applied. 1757068b053dSYazen Ghannam * 1758068b053dSYazen Ghannam * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs. 1759068b053dSYazen Ghannam * Otherwise, a user who disables a bank will not be able to re-enable it 1760068b053dSYazen Ghannam * without a system reboot. 1761068b053dSYazen Ghannam */ 1762068b053dSYazen Ghannam static void __mcheck_cpu_check_banks(void) 1763068b053dSYazen Ghannam { 1764068b053dSYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1765068b053dSYazen Ghannam u64 msrval; 1766068b053dSYazen Ghannam int i; 1767068b053dSYazen Ghannam 1768068b053dSYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1769068b053dSYazen Ghannam struct mce_bank *b = &mce_banks[i]; 1770068b053dSYazen Ghannam 1771068b053dSYazen Ghannam if (!b->init) 1772068b053dSYazen Ghannam continue; 1773068b053dSYazen Ghannam 17748121b8f9SBorislav Petkov rdmsrl(mca_msr_reg(i, MCA_CTL), msrval); 1775068b053dSYazen Ghannam b->init = !!msrval; 1776068b053dSYazen Ghannam } 1777068b053dSYazen Ghannam } 1778068b053dSYazen Ghannam 177921afaf18SBorislav Petkov /* Add per CPU specific workarounds here */ 178021afaf18SBorislav Petkov static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) 178121afaf18SBorislav Petkov { 1782b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 178321afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 178421afaf18SBorislav Petkov 178521afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_UNKNOWN) { 178621afaf18SBorislav Petkov pr_info("unknown CPU type - not enabling MCE support\n"); 178721afaf18SBorislav Petkov return -EOPNOTSUPP; 178821afaf18SBorislav Petkov } 178921afaf18SBorislav Petkov 179021afaf18SBorislav Petkov /* This should be disabled by the BIOS, but isn't always */ 179121afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD) { 1792c7d314f3SYazen Ghannam if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { 179321afaf18SBorislav Petkov /* 179421afaf18SBorislav Petkov * disable GART TBL walk error reporting, which 179521afaf18SBorislav Petkov * trips off incorrectly with the IOMMU & 3ware 179621afaf18SBorislav Petkov * & Cerberus: 179721afaf18SBorislav Petkov */ 179821afaf18SBorislav Petkov clear_bit(10, (unsigned long *)&mce_banks[4].ctl); 179921afaf18SBorislav Petkov } 180021afaf18SBorislav Petkov if (c->x86 < 0x11 && cfg->bootlog < 0) { 180121afaf18SBorislav Petkov /* 180221afaf18SBorislav Petkov * Lots of broken BIOS around that don't clear them 180321afaf18SBorislav Petkov * by default and leave crap in there. Don't log: 180421afaf18SBorislav Petkov */ 180521afaf18SBorislav Petkov cfg->bootlog = 0; 180621afaf18SBorislav Petkov } 180721afaf18SBorislav Petkov /* 180821afaf18SBorislav Petkov * Various K7s with broken bank 0 around. Always disable 180921afaf18SBorislav Petkov * by default. 181021afaf18SBorislav Petkov */ 1811c7d314f3SYazen Ghannam if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0) 181221afaf18SBorislav Petkov mce_banks[0].ctl = 0; 181321afaf18SBorislav Petkov 181421afaf18SBorislav Petkov /* 181521afaf18SBorislav Petkov * overflow_recov is supported for F15h Models 00h-0fh 181621afaf18SBorislav Petkov * even though we don't have a CPUID bit for it. 181721afaf18SBorislav Petkov */ 181821afaf18SBorislav Petkov if (c->x86 == 0x15 && c->x86_model <= 0xf) 181921afaf18SBorislav Petkov mce_flags.overflow_recov = 1; 182021afaf18SBorislav Petkov 182121afaf18SBorislav Petkov } 182221afaf18SBorislav Petkov 182321afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_INTEL) { 182421afaf18SBorislav Petkov /* 182521afaf18SBorislav Petkov * SDM documents that on family 6 bank 0 should not be written 182621afaf18SBorislav Petkov * because it aliases to another special BIOS controlled 182721afaf18SBorislav Petkov * register. 182821afaf18SBorislav Petkov * But it's not aliased anymore on model 0x1a+ 182921afaf18SBorislav Petkov * Don't ignore bank 0 completely because there could be a 183021afaf18SBorislav Petkov * valid event later, merely don't write CTL0. 183121afaf18SBorislav Petkov */ 183221afaf18SBorislav Petkov 1833c7d314f3SYazen Ghannam if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) 183477080929SKaixu Xia mce_banks[0].init = false; 183521afaf18SBorislav Petkov 183621afaf18SBorislav Petkov /* 183721afaf18SBorislav Petkov * All newer Intel systems support MCE broadcasting. Enable 183821afaf18SBorislav Petkov * synchronization with a one second timeout. 183921afaf18SBorislav Petkov */ 184021afaf18SBorislav Petkov if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && 184121afaf18SBorislav Petkov cfg->monarch_timeout < 0) 184221afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 184321afaf18SBorislav Petkov 184421afaf18SBorislav Petkov /* 184521afaf18SBorislav Petkov * There are also broken BIOSes on some Pentium M and 184621afaf18SBorislav Petkov * earlier systems: 184721afaf18SBorislav Petkov */ 184821afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) 184921afaf18SBorislav Petkov cfg->bootlog = 0; 185021afaf18SBorislav Petkov 185121afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model == 45) 1852cc466666SBorislav Petkov mce_flags.snb_ifu_quirk = 1; 185321afaf18SBorislav Petkov } 18546e898d2bSTony W Wang-oc 18556e898d2bSTony W Wang-oc if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { 18566e898d2bSTony W Wang-oc /* 18576e898d2bSTony W Wang-oc * All newer Zhaoxin CPUs support MCE broadcasting. Enable 18586e898d2bSTony W Wang-oc * synchronization with a one second timeout. 18596e898d2bSTony W Wang-oc */ 18606e898d2bSTony W Wang-oc if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 18616e898d2bSTony W Wang-oc if (cfg->monarch_timeout < 0) 18626e898d2bSTony W Wang-oc cfg->monarch_timeout = USEC_PER_SEC; 18636e898d2bSTony W Wang-oc } 18646e898d2bSTony W Wang-oc } 18656e898d2bSTony W Wang-oc 186621afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 186721afaf18SBorislav Petkov cfg->monarch_timeout = 0; 186821afaf18SBorislav Petkov if (cfg->bootlog != 0) 186921afaf18SBorislav Petkov cfg->panic_timeout = 30; 187021afaf18SBorislav Petkov 187121afaf18SBorislav Petkov return 0; 187221afaf18SBorislav Petkov } 187321afaf18SBorislav Petkov 187421afaf18SBorislav Petkov static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) 187521afaf18SBorislav Petkov { 187621afaf18SBorislav Petkov if (c->x86 != 5) 187721afaf18SBorislav Petkov return 0; 187821afaf18SBorislav Petkov 187921afaf18SBorislav Petkov switch (c->x86_vendor) { 188021afaf18SBorislav Petkov case X86_VENDOR_INTEL: 188121afaf18SBorislav Petkov intel_p5_mcheck_init(c); 1882cbe1de16SBorislav Petkov mce_flags.p5 = 1; 188321afaf18SBorislav Petkov return 1; 188421afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 188521afaf18SBorislav Petkov winchip_mcheck_init(c); 1886cbe1de16SBorislav Petkov mce_flags.winchip = 1; 188721afaf18SBorislav Petkov return 1; 188821afaf18SBorislav Petkov default: 188921afaf18SBorislav Petkov return 0; 189021afaf18SBorislav Petkov } 189121afaf18SBorislav Petkov 189221afaf18SBorislav Petkov return 0; 189321afaf18SBorislav Petkov } 189421afaf18SBorislav Petkov 189521afaf18SBorislav Petkov /* 189621afaf18SBorislav Petkov * Init basic CPU features needed for early decoding of MCEs. 189721afaf18SBorislav Petkov */ 189821afaf18SBorislav Petkov static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) 189921afaf18SBorislav Petkov { 190021afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) { 190121afaf18SBorislav Petkov mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); 190221afaf18SBorislav Petkov mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); 190321afaf18SBorislav Petkov mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); 1904c9bf318fSThomas Gleixner mce_flags.amd_threshold = 1; 190521afaf18SBorislav Petkov } 190621afaf18SBorislav Petkov } 190721afaf18SBorislav Petkov 190821afaf18SBorislav Petkov static void mce_centaur_feature_init(struct cpuinfo_x86 *c) 190921afaf18SBorislav Petkov { 191021afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 191121afaf18SBorislav Petkov 191221afaf18SBorislav Petkov /* 191321afaf18SBorislav Petkov * All newer Centaur CPUs support MCE broadcasting. Enable 191421afaf18SBorislav Petkov * synchronization with a one second timeout. 191521afaf18SBorislav Petkov */ 191621afaf18SBorislav Petkov if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) || 191721afaf18SBorislav Petkov c->x86 > 6) { 191821afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 191921afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 192021afaf18SBorislav Petkov } 192121afaf18SBorislav Petkov } 192221afaf18SBorislav Petkov 19235a3d56a0STony W Wang-oc static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) 19245a3d56a0STony W Wang-oc { 19255a3d56a0STony W Wang-oc struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 19265a3d56a0STony W Wang-oc 19275a3d56a0STony W Wang-oc /* 19285a3d56a0STony W Wang-oc * These CPUs have MCA bank 8 which reports only one error type called 19295a3d56a0STony W Wang-oc * SVAD (System View Address Decoder). The reporting of that error is 19305a3d56a0STony W Wang-oc * controlled by IA32_MC8.CTL.0. 19315a3d56a0STony W Wang-oc * 19325a3d56a0STony W Wang-oc * If enabled, prefetching on these CPUs will cause SVAD MCE when 19335a3d56a0STony W Wang-oc * virtual machines start and result in a system panic. Always disable 19345a3d56a0STony W Wang-oc * bank 8 SVAD error by default. 19355a3d56a0STony W Wang-oc */ 19365a3d56a0STony W Wang-oc if ((c->x86 == 7 && c->x86_model == 0x1b) || 19375a3d56a0STony W Wang-oc (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 19385a3d56a0STony W Wang-oc if (this_cpu_read(mce_num_banks) > 8) 19395a3d56a0STony W Wang-oc mce_banks[8].ctl = 0; 19405a3d56a0STony W Wang-oc } 19415a3d56a0STony W Wang-oc 19425a3d56a0STony W Wang-oc intel_init_cmci(); 194370f0c230STony W Wang-oc intel_init_lmce(); 19445a3d56a0STony W Wang-oc mce_adjust_timer = cmci_intel_adjust_timer; 19455a3d56a0STony W Wang-oc } 19465a3d56a0STony W Wang-oc 194770f0c230STony W Wang-oc static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) 194870f0c230STony W Wang-oc { 194970f0c230STony W Wang-oc intel_clear_lmce(); 195070f0c230STony W Wang-oc } 195170f0c230STony W Wang-oc 195221afaf18SBorislav Petkov static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) 195321afaf18SBorislav Petkov { 195421afaf18SBorislav Petkov switch (c->x86_vendor) { 195521afaf18SBorislav Petkov case X86_VENDOR_INTEL: 195621afaf18SBorislav Petkov mce_intel_feature_init(c); 195721afaf18SBorislav Petkov mce_adjust_timer = cmci_intel_adjust_timer; 195821afaf18SBorislav Petkov break; 195921afaf18SBorislav Petkov 196021afaf18SBorislav Petkov case X86_VENDOR_AMD: { 196121afaf18SBorislav Petkov mce_amd_feature_init(c); 196221afaf18SBorislav Petkov break; 196321afaf18SBorislav Petkov } 196421afaf18SBorislav Petkov 196521afaf18SBorislav Petkov case X86_VENDOR_HYGON: 196621afaf18SBorislav Petkov mce_hygon_feature_init(c); 196721afaf18SBorislav Petkov break; 196821afaf18SBorislav Petkov 196921afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 197021afaf18SBorislav Petkov mce_centaur_feature_init(c); 197121afaf18SBorislav Petkov break; 197221afaf18SBorislav Petkov 19735a3d56a0STony W Wang-oc case X86_VENDOR_ZHAOXIN: 19745a3d56a0STony W Wang-oc mce_zhaoxin_feature_init(c); 19755a3d56a0STony W Wang-oc break; 19765a3d56a0STony W Wang-oc 197721afaf18SBorislav Petkov default: 197821afaf18SBorislav Petkov break; 197921afaf18SBorislav Petkov } 198021afaf18SBorislav Petkov } 198121afaf18SBorislav Petkov 198221afaf18SBorislav Petkov static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) 198321afaf18SBorislav Petkov { 198421afaf18SBorislav Petkov switch (c->x86_vendor) { 198521afaf18SBorislav Petkov case X86_VENDOR_INTEL: 198621afaf18SBorislav Petkov mce_intel_feature_clear(c); 198721afaf18SBorislav Petkov break; 198870f0c230STony W Wang-oc 198970f0c230STony W Wang-oc case X86_VENDOR_ZHAOXIN: 199070f0c230STony W Wang-oc mce_zhaoxin_feature_clear(c); 199170f0c230STony W Wang-oc break; 199270f0c230STony W Wang-oc 199321afaf18SBorislav Petkov default: 199421afaf18SBorislav Petkov break; 199521afaf18SBorislav Petkov } 199621afaf18SBorislav Petkov } 199721afaf18SBorislav Petkov 199821afaf18SBorislav Petkov static void mce_start_timer(struct timer_list *t) 199921afaf18SBorislav Petkov { 200021afaf18SBorislav Petkov unsigned long iv = check_interval * HZ; 200121afaf18SBorislav Petkov 200221afaf18SBorislav Petkov if (mca_cfg.ignore_ce || !iv) 200321afaf18SBorislav Petkov return; 200421afaf18SBorislav Petkov 200521afaf18SBorislav Petkov this_cpu_write(mce_next_interval, iv); 200621afaf18SBorislav Petkov __start_timer(t, iv); 200721afaf18SBorislav Petkov } 200821afaf18SBorislav Petkov 200921afaf18SBorislav Petkov static void __mcheck_cpu_setup_timer(void) 201021afaf18SBorislav Petkov { 201121afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 201221afaf18SBorislav Petkov 201321afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 201421afaf18SBorislav Petkov } 201521afaf18SBorislav Petkov 201621afaf18SBorislav Petkov static void __mcheck_cpu_init_timer(void) 201721afaf18SBorislav Petkov { 201821afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 201921afaf18SBorislav Petkov 202021afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 202121afaf18SBorislav Petkov mce_start_timer(t); 202221afaf18SBorislav Petkov } 202321afaf18SBorislav Petkov 202445d4b7b9SYazen Ghannam bool filter_mce(struct mce *m) 202545d4b7b9SYazen Ghannam { 202671a84402SYazen Ghannam if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 202771a84402SYazen Ghannam return amd_filter_mce(m); 20282976908eSPrarit Bhargava if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 20292976908eSPrarit Bhargava return intel_filter_mce(m); 203071a84402SYazen Ghannam 203145d4b7b9SYazen Ghannam return false; 203245d4b7b9SYazen Ghannam } 203345d4b7b9SYazen Ghannam 20344c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_kernel(struct pt_regs *regs) 203521afaf18SBorislav Petkov { 2036b6be002bSThomas Gleixner irqentry_state_t irq_state; 2037bc21a291SThomas Gleixner 203813cbc0cdSAndy Lutomirski WARN_ON_ONCE(user_mode(regs)); 203913cbc0cdSAndy Lutomirski 20404c0dcd83SThomas Gleixner /* 20414c0dcd83SThomas Gleixner * Only required when from kernel mode. See 20424c0dcd83SThomas Gleixner * mce_check_crashing_cpu() for details. 20434c0dcd83SThomas Gleixner */ 2044cbe1de16SBorislav Petkov if (mca_cfg.initialized && mce_check_crashing_cpu()) 204594a46d31SThomas Gleixner return; 204694a46d31SThomas Gleixner 2047b6be002bSThomas Gleixner irq_state = irqentry_nmi_enter(regs); 204873749536SPeter Zijlstra 2049cbe1de16SBorislav Petkov do_machine_check(regs); 205073749536SPeter Zijlstra 2051b6be002bSThomas Gleixner irqentry_nmi_exit(regs, irq_state); 205221afaf18SBorislav Petkov } 205321afaf18SBorislav Petkov 20544c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_user(struct pt_regs *regs) 20554c0dcd83SThomas Gleixner { 2056517e4992SThomas Gleixner irqentry_enter_from_user_mode(regs); 205773749536SPeter Zijlstra 2058cbe1de16SBorislav Petkov do_machine_check(regs); 205973749536SPeter Zijlstra 2060517e4992SThomas Gleixner irqentry_exit_to_user_mode(regs); 20614c0dcd83SThomas Gleixner } 20624c0dcd83SThomas Gleixner 20634c0dcd83SThomas Gleixner #ifdef CONFIG_X86_64 20644c0dcd83SThomas Gleixner /* MCE hit kernel mode */ 20654c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE(exc_machine_check) 20664c0dcd83SThomas Gleixner { 2067cd840e42SPeter Zijlstra unsigned long dr7; 2068cd840e42SPeter Zijlstra 2069cd840e42SPeter Zijlstra dr7 = local_db_save(); 20704c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 2071cd840e42SPeter Zijlstra local_db_restore(dr7); 20724c0dcd83SThomas Gleixner } 20734c0dcd83SThomas Gleixner 20744c0dcd83SThomas Gleixner /* The user mode variant. */ 20754c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE_USER(exc_machine_check) 20764c0dcd83SThomas Gleixner { 2077cd840e42SPeter Zijlstra unsigned long dr7; 2078cd840e42SPeter Zijlstra 2079cd840e42SPeter Zijlstra dr7 = local_db_save(); 20804c0dcd83SThomas Gleixner exc_machine_check_user(regs); 2081cd840e42SPeter Zijlstra local_db_restore(dr7); 20824c0dcd83SThomas Gleixner } 20834c0dcd83SThomas Gleixner #else 20844c0dcd83SThomas Gleixner /* 32bit unified entry point */ 208513cbc0cdSAndy Lutomirski DEFINE_IDTENTRY_RAW(exc_machine_check) 20864c0dcd83SThomas Gleixner { 2087cd840e42SPeter Zijlstra unsigned long dr7; 2088cd840e42SPeter Zijlstra 2089cd840e42SPeter Zijlstra dr7 = local_db_save(); 20904c0dcd83SThomas Gleixner if (user_mode(regs)) 20914c0dcd83SThomas Gleixner exc_machine_check_user(regs); 20924c0dcd83SThomas Gleixner else 20934c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 2094cd840e42SPeter Zijlstra local_db_restore(dr7); 20954c0dcd83SThomas Gleixner } 20964c0dcd83SThomas Gleixner #endif 209721afaf18SBorislav Petkov 209821afaf18SBorislav Petkov /* 209921afaf18SBorislav Petkov * Called for each booted CPU to set up machine checks. 210021afaf18SBorislav Petkov * Must be called with preempt off: 210121afaf18SBorislav Petkov */ 210221afaf18SBorislav Petkov void mcheck_cpu_init(struct cpuinfo_x86 *c) 210321afaf18SBorislav Petkov { 210421afaf18SBorislav Petkov if (mca_cfg.disabled) 210521afaf18SBorislav Petkov return; 210621afaf18SBorislav Petkov 210721afaf18SBorislav Petkov if (__mcheck_cpu_ancient_init(c)) 210821afaf18SBorislav Petkov return; 210921afaf18SBorislav Petkov 211021afaf18SBorislav Petkov if (!mce_available(c)) 211121afaf18SBorislav Petkov return; 211221afaf18SBorislav Petkov 2113b4914508SYazen Ghannam __mcheck_cpu_cap_init(); 2114b4914508SYazen Ghannam 2115b4914508SYazen Ghannam if (__mcheck_cpu_apply_quirks(c) < 0) { 211621afaf18SBorislav Petkov mca_cfg.disabled = 1; 211721afaf18SBorislav Petkov return; 211821afaf18SBorislav Petkov } 211921afaf18SBorislav Petkov 212021afaf18SBorislav Petkov if (mce_gen_pool_init()) { 212121afaf18SBorislav Petkov mca_cfg.disabled = 1; 212221afaf18SBorislav Petkov pr_emerg("Couldn't allocate MCE records pool!\n"); 212321afaf18SBorislav Petkov return; 212421afaf18SBorislav Petkov } 212521afaf18SBorislav Petkov 2126cbe1de16SBorislav Petkov mca_cfg.initialized = 1; 212721afaf18SBorislav Petkov 212821afaf18SBorislav Petkov __mcheck_cpu_init_early(c); 212921afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 213021afaf18SBorislav Petkov __mcheck_cpu_init_vendor(c); 213121afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 2132068b053dSYazen Ghannam __mcheck_cpu_check_banks(); 213321afaf18SBorislav Petkov __mcheck_cpu_setup_timer(); 213421afaf18SBorislav Petkov } 213521afaf18SBorislav Petkov 213621afaf18SBorislav Petkov /* 213721afaf18SBorislav Petkov * Called for each booted CPU to clear some machine checks opt-ins 213821afaf18SBorislav Petkov */ 213921afaf18SBorislav Petkov void mcheck_cpu_clear(struct cpuinfo_x86 *c) 214021afaf18SBorislav Petkov { 214121afaf18SBorislav Petkov if (mca_cfg.disabled) 214221afaf18SBorislav Petkov return; 214321afaf18SBorislav Petkov 214421afaf18SBorislav Petkov if (!mce_available(c)) 214521afaf18SBorislav Petkov return; 214621afaf18SBorislav Petkov 214721afaf18SBorislav Petkov /* 214821afaf18SBorislav Petkov * Possibly to clear general settings generic to x86 214921afaf18SBorislav Petkov * __mcheck_cpu_clear_generic(c); 215021afaf18SBorislav Petkov */ 215121afaf18SBorislav Petkov __mcheck_cpu_clear_vendor(c); 215221afaf18SBorislav Petkov 215321afaf18SBorislav Petkov } 215421afaf18SBorislav Petkov 215521afaf18SBorislav Petkov static void __mce_disable_bank(void *arg) 215621afaf18SBorislav Petkov { 215721afaf18SBorislav Petkov int bank = *((int *)arg); 215821afaf18SBorislav Petkov __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); 215921afaf18SBorislav Petkov cmci_disable_bank(bank); 216021afaf18SBorislav Petkov } 216121afaf18SBorislav Petkov 216221afaf18SBorislav Petkov void mce_disable_bank(int bank) 216321afaf18SBorislav Petkov { 2164c7d314f3SYazen Ghannam if (bank >= this_cpu_read(mce_num_banks)) { 216521afaf18SBorislav Petkov pr_warn(FW_BUG 216621afaf18SBorislav Petkov "Ignoring request to disable invalid MCA bank %d.\n", 216721afaf18SBorislav Petkov bank); 216821afaf18SBorislav Petkov return; 216921afaf18SBorislav Petkov } 217021afaf18SBorislav Petkov set_bit(bank, mce_banks_ce_disabled); 217121afaf18SBorislav Petkov on_each_cpu(__mce_disable_bank, &bank, 1); 217221afaf18SBorislav Petkov } 217321afaf18SBorislav Petkov 217421afaf18SBorislav Petkov /* 217521afaf18SBorislav Petkov * mce=off Disables machine check 217621afaf18SBorislav Petkov * mce=no_cmci Disables CMCI 217721afaf18SBorislav Petkov * mce=no_lmce Disables LMCE 217821afaf18SBorislav Petkov * mce=dont_log_ce Clears corrected events silently, no log created for CEs. 217943505646STony Luck * mce=print_all Print all machine check logs to console 218021afaf18SBorislav Petkov * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. 218121afaf18SBorislav Petkov * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) 218221afaf18SBorislav Petkov * monarchtimeout is how long to wait for other CPUs on machine 218321afaf18SBorislav Petkov * check, or 0 to not wait 218421afaf18SBorislav Petkov * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h 218521afaf18SBorislav Petkov and older. 218621afaf18SBorislav Petkov * mce=nobootlog Don't log MCEs from before booting. 218721afaf18SBorislav Petkov * mce=bios_cmci_threshold Don't program the CMCI threshold 2188ec6347bbSDan Williams * mce=recovery force enable copy_mc_fragile() 218921afaf18SBorislav Petkov */ 219021afaf18SBorislav Petkov static int __init mcheck_enable(char *str) 219121afaf18SBorislav Petkov { 219221afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 219321afaf18SBorislav Petkov 219421afaf18SBorislav Petkov if (*str == 0) { 219521afaf18SBorislav Petkov enable_p5_mce(); 219621afaf18SBorislav Petkov return 1; 219721afaf18SBorislav Petkov } 219821afaf18SBorislav Petkov if (*str == '=') 219921afaf18SBorislav Petkov str++; 220021afaf18SBorislav Petkov if (!strcmp(str, "off")) 220121afaf18SBorislav Petkov cfg->disabled = 1; 220221afaf18SBorislav Petkov else if (!strcmp(str, "no_cmci")) 220321afaf18SBorislav Petkov cfg->cmci_disabled = true; 220421afaf18SBorislav Petkov else if (!strcmp(str, "no_lmce")) 220521afaf18SBorislav Petkov cfg->lmce_disabled = 1; 220621afaf18SBorislav Petkov else if (!strcmp(str, "dont_log_ce")) 220721afaf18SBorislav Petkov cfg->dont_log_ce = true; 220843505646STony Luck else if (!strcmp(str, "print_all")) 220943505646STony Luck cfg->print_all = true; 221021afaf18SBorislav Petkov else if (!strcmp(str, "ignore_ce")) 221121afaf18SBorislav Petkov cfg->ignore_ce = true; 221221afaf18SBorislav Petkov else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) 221321afaf18SBorislav Petkov cfg->bootlog = (str[0] == 'b'); 221421afaf18SBorislav Petkov else if (!strcmp(str, "bios_cmci_threshold")) 221521afaf18SBorislav Petkov cfg->bios_cmci_threshold = 1; 221621afaf18SBorislav Petkov else if (!strcmp(str, "recovery")) 221721afaf18SBorislav Petkov cfg->recovery = 1; 221821afaf18SBorislav Petkov else if (isdigit(str[0])) { 221921afaf18SBorislav Petkov if (get_option(&str, &cfg->tolerant) == 2) 222021afaf18SBorislav Petkov get_option(&str, &(cfg->monarch_timeout)); 222121afaf18SBorislav Petkov } else { 222221afaf18SBorislav Petkov pr_info("mce argument %s ignored. Please use /sys\n", str); 222321afaf18SBorislav Petkov return 0; 222421afaf18SBorislav Petkov } 222521afaf18SBorislav Petkov return 1; 222621afaf18SBorislav Petkov } 222721afaf18SBorislav Petkov __setup("mce", mcheck_enable); 222821afaf18SBorislav Petkov 222921afaf18SBorislav Petkov int __init mcheck_init(void) 223021afaf18SBorislav Petkov { 2231c9c6d216STony Luck mce_register_decode_chain(&early_nb); 22328438b84aSJan H. Schönherr mce_register_decode_chain(&mce_uc_nb); 223321afaf18SBorislav Petkov mce_register_decode_chain(&mce_default_nb); 223421afaf18SBorislav Petkov 223521afaf18SBorislav Petkov INIT_WORK(&mce_work, mce_gen_pool_process); 223621afaf18SBorislav Petkov init_irq_work(&mce_irq_work, mce_irq_work_cb); 223721afaf18SBorislav Petkov 223821afaf18SBorislav Petkov return 0; 223921afaf18SBorislav Petkov } 224021afaf18SBorislav Petkov 224121afaf18SBorislav Petkov /* 224221afaf18SBorislav Petkov * mce_syscore: PM support 224321afaf18SBorislav Petkov */ 224421afaf18SBorislav Petkov 224521afaf18SBorislav Petkov /* 224621afaf18SBorislav Petkov * Disable machine checks on suspend and shutdown. We can't really handle 224721afaf18SBorislav Petkov * them later. 224821afaf18SBorislav Petkov */ 224921afaf18SBorislav Petkov static void mce_disable_error_reporting(void) 225021afaf18SBorislav Petkov { 2251b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 225221afaf18SBorislav Petkov int i; 225321afaf18SBorislav Petkov 2254c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 225521afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 225621afaf18SBorislav Petkov 225721afaf18SBorislav Petkov if (b->init) 22588121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), 0); 225921afaf18SBorislav Petkov } 226021afaf18SBorislav Petkov return; 226121afaf18SBorislav Petkov } 226221afaf18SBorislav Petkov 226321afaf18SBorislav Petkov static void vendor_disable_error_reporting(void) 226421afaf18SBorislav Petkov { 226521afaf18SBorislav Petkov /* 22666e898d2bSTony W Wang-oc * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these 22676e898d2bSTony W Wang-oc * MSRs are socket-wide. Disabling them for just a single offlined CPU 22686e898d2bSTony W Wang-oc * is bad, since it will inhibit reporting for all shared resources on 22696e898d2bSTony W Wang-oc * the socket like the last level cache (LLC), the integrated memory 22706e898d2bSTony W Wang-oc * controller (iMC), etc. 227121afaf18SBorislav Petkov */ 227221afaf18SBorislav Petkov if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || 227321afaf18SBorislav Petkov boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || 22746e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 22756e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) 227621afaf18SBorislav Petkov return; 227721afaf18SBorislav Petkov 227821afaf18SBorislav Petkov mce_disable_error_reporting(); 227921afaf18SBorislav Petkov } 228021afaf18SBorislav Petkov 228121afaf18SBorislav Petkov static int mce_syscore_suspend(void) 228221afaf18SBorislav Petkov { 228321afaf18SBorislav Petkov vendor_disable_error_reporting(); 228421afaf18SBorislav Petkov return 0; 228521afaf18SBorislav Petkov } 228621afaf18SBorislav Petkov 228721afaf18SBorislav Petkov static void mce_syscore_shutdown(void) 228821afaf18SBorislav Petkov { 228921afaf18SBorislav Petkov vendor_disable_error_reporting(); 229021afaf18SBorislav Petkov } 229121afaf18SBorislav Petkov 229221afaf18SBorislav Petkov /* 229321afaf18SBorislav Petkov * On resume clear all MCE state. Don't want to see leftovers from the BIOS. 229421afaf18SBorislav Petkov * Only one CPU is active at this time, the others get re-added later using 229521afaf18SBorislav Petkov * CPU hotplug: 229621afaf18SBorislav Petkov */ 229721afaf18SBorislav Petkov static void mce_syscore_resume(void) 229821afaf18SBorislav Petkov { 229921afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 230021afaf18SBorislav Petkov __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); 230121afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 230221afaf18SBorislav Petkov } 230321afaf18SBorislav Petkov 230421afaf18SBorislav Petkov static struct syscore_ops mce_syscore_ops = { 230521afaf18SBorislav Petkov .suspend = mce_syscore_suspend, 230621afaf18SBorislav Petkov .shutdown = mce_syscore_shutdown, 230721afaf18SBorislav Petkov .resume = mce_syscore_resume, 230821afaf18SBorislav Petkov }; 230921afaf18SBorislav Petkov 231021afaf18SBorislav Petkov /* 231121afaf18SBorislav Petkov * mce_device: Sysfs support 231221afaf18SBorislav Petkov */ 231321afaf18SBorislav Petkov 231421afaf18SBorislav Petkov static void mce_cpu_restart(void *data) 231521afaf18SBorislav Petkov { 231621afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 231721afaf18SBorislav Petkov return; 231821afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 231921afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 232021afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 232121afaf18SBorislav Petkov } 232221afaf18SBorislav Petkov 232321afaf18SBorislav Petkov /* Reinit MCEs after user configuration changes */ 232421afaf18SBorislav Petkov static void mce_restart(void) 232521afaf18SBorislav Petkov { 232621afaf18SBorislav Petkov mce_timer_delete_all(); 232721afaf18SBorislav Petkov on_each_cpu(mce_cpu_restart, NULL, 1); 232821afaf18SBorislav Petkov } 232921afaf18SBorislav Petkov 233021afaf18SBorislav Petkov /* Toggle features for corrected errors */ 233121afaf18SBorislav Petkov static void mce_disable_cmci(void *data) 233221afaf18SBorislav Petkov { 233321afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 233421afaf18SBorislav Petkov return; 233521afaf18SBorislav Petkov cmci_clear(); 233621afaf18SBorislav Petkov } 233721afaf18SBorislav Petkov 233821afaf18SBorislav Petkov static void mce_enable_ce(void *all) 233921afaf18SBorislav Petkov { 234021afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 234121afaf18SBorislav Petkov return; 234221afaf18SBorislav Petkov cmci_reenable(); 234321afaf18SBorislav Petkov cmci_recheck(); 234421afaf18SBorislav Petkov if (all) 234521afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 234621afaf18SBorislav Petkov } 234721afaf18SBorislav Petkov 234821afaf18SBorislav Petkov static struct bus_type mce_subsys = { 234921afaf18SBorislav Petkov .name = "machinecheck", 235021afaf18SBorislav Petkov .dev_name = "machinecheck", 235121afaf18SBorislav Petkov }; 235221afaf18SBorislav Petkov 235321afaf18SBorislav Petkov DEFINE_PER_CPU(struct device *, mce_device); 235421afaf18SBorislav Petkov 2355b4914508SYazen Ghannam static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr) 235621afaf18SBorislav Petkov { 2357b4914508SYazen Ghannam return container_of(attr, struct mce_bank_dev, attr); 235821afaf18SBorislav Petkov } 235921afaf18SBorislav Petkov 236021afaf18SBorislav Petkov static ssize_t show_bank(struct device *s, struct device_attribute *attr, 236121afaf18SBorislav Petkov char *buf) 236221afaf18SBorislav Petkov { 2363b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2364b4914508SYazen Ghannam struct mce_bank *b; 2365b4914508SYazen Ghannam 2366c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2367b4914508SYazen Ghannam return -EINVAL; 2368b4914508SYazen Ghannam 2369b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2370b4914508SYazen Ghannam 2371068b053dSYazen Ghannam if (!b->init) 2372068b053dSYazen Ghannam return -ENODEV; 2373068b053dSYazen Ghannam 2374b4914508SYazen Ghannam return sprintf(buf, "%llx\n", b->ctl); 237521afaf18SBorislav Petkov } 237621afaf18SBorislav Petkov 237721afaf18SBorislav Petkov static ssize_t set_bank(struct device *s, struct device_attribute *attr, 237821afaf18SBorislav Petkov const char *buf, size_t size) 237921afaf18SBorislav Petkov { 2380b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2381b4914508SYazen Ghannam struct mce_bank *b; 238221afaf18SBorislav Petkov u64 new; 238321afaf18SBorislav Petkov 238421afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 238521afaf18SBorislav Petkov return -EINVAL; 238621afaf18SBorislav Petkov 2387c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2388b4914508SYazen Ghannam return -EINVAL; 2389b4914508SYazen Ghannam 2390b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2391b4914508SYazen Ghannam 2392068b053dSYazen Ghannam if (!b->init) 2393068b053dSYazen Ghannam return -ENODEV; 2394068b053dSYazen Ghannam 2395b4914508SYazen Ghannam b->ctl = new; 239621afaf18SBorislav Petkov mce_restart(); 239721afaf18SBorislav Petkov 239821afaf18SBorislav Petkov return size; 239921afaf18SBorislav Petkov } 240021afaf18SBorislav Petkov 240121afaf18SBorislav Petkov static ssize_t set_ignore_ce(struct device *s, 240221afaf18SBorislav Petkov struct device_attribute *attr, 240321afaf18SBorislav Petkov const char *buf, size_t size) 240421afaf18SBorislav Petkov { 240521afaf18SBorislav Petkov u64 new; 240621afaf18SBorislav Petkov 240721afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 240821afaf18SBorislav Petkov return -EINVAL; 240921afaf18SBorislav Petkov 241021afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 241121afaf18SBorislav Petkov if (mca_cfg.ignore_ce ^ !!new) { 241221afaf18SBorislav Petkov if (new) { 241321afaf18SBorislav Petkov /* disable ce features */ 241421afaf18SBorislav Petkov mce_timer_delete_all(); 241521afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 241621afaf18SBorislav Petkov mca_cfg.ignore_ce = true; 241721afaf18SBorislav Petkov } else { 241821afaf18SBorislav Petkov /* enable ce features */ 241921afaf18SBorislav Petkov mca_cfg.ignore_ce = false; 242021afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, (void *)1, 1); 242121afaf18SBorislav Petkov } 242221afaf18SBorislav Petkov } 242321afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 242421afaf18SBorislav Petkov 242521afaf18SBorislav Petkov return size; 242621afaf18SBorislav Petkov } 242721afaf18SBorislav Petkov 242821afaf18SBorislav Petkov static ssize_t set_cmci_disabled(struct device *s, 242921afaf18SBorislav Petkov struct device_attribute *attr, 243021afaf18SBorislav Petkov const char *buf, size_t size) 243121afaf18SBorislav Petkov { 243221afaf18SBorislav Petkov u64 new; 243321afaf18SBorislav Petkov 243421afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 243521afaf18SBorislav Petkov return -EINVAL; 243621afaf18SBorislav Petkov 243721afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 243821afaf18SBorislav Petkov if (mca_cfg.cmci_disabled ^ !!new) { 243921afaf18SBorislav Petkov if (new) { 244021afaf18SBorislav Petkov /* disable cmci */ 244121afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 244221afaf18SBorislav Petkov mca_cfg.cmci_disabled = true; 244321afaf18SBorislav Petkov } else { 244421afaf18SBorislav Petkov /* enable cmci */ 244521afaf18SBorislav Petkov mca_cfg.cmci_disabled = false; 244621afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, NULL, 1); 244721afaf18SBorislav Petkov } 244821afaf18SBorislav Petkov } 244921afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 245021afaf18SBorislav Petkov 245121afaf18SBorislav Petkov return size; 245221afaf18SBorislav Petkov } 245321afaf18SBorislav Petkov 245421afaf18SBorislav Petkov static ssize_t store_int_with_restart(struct device *s, 245521afaf18SBorislav Petkov struct device_attribute *attr, 245621afaf18SBorislav Petkov const char *buf, size_t size) 245721afaf18SBorislav Petkov { 245821afaf18SBorislav Petkov unsigned long old_check_interval = check_interval; 245921afaf18SBorislav Petkov ssize_t ret = device_store_ulong(s, attr, buf, size); 246021afaf18SBorislav Petkov 246121afaf18SBorislav Petkov if (check_interval == old_check_interval) 246221afaf18SBorislav Petkov return ret; 246321afaf18SBorislav Petkov 246421afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 246521afaf18SBorislav Petkov mce_restart(); 246621afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 246721afaf18SBorislav Petkov 246821afaf18SBorislav Petkov return ret; 246921afaf18SBorislav Petkov } 247021afaf18SBorislav Petkov 247121afaf18SBorislav Petkov static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); 247221afaf18SBorislav Petkov static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); 247321afaf18SBorislav Petkov static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); 247443505646STony Luck static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all); 247521afaf18SBorislav Petkov 247621afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_check_interval = { 247721afaf18SBorislav Petkov __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), 247821afaf18SBorislav Petkov &check_interval 247921afaf18SBorislav Petkov }; 248021afaf18SBorislav Petkov 248121afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_ignore_ce = { 248221afaf18SBorislav Petkov __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), 248321afaf18SBorislav Petkov &mca_cfg.ignore_ce 248421afaf18SBorislav Petkov }; 248521afaf18SBorislav Petkov 248621afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_cmci_disabled = { 248721afaf18SBorislav Petkov __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), 248821afaf18SBorislav Petkov &mca_cfg.cmci_disabled 248921afaf18SBorislav Petkov }; 249021afaf18SBorislav Petkov 249121afaf18SBorislav Petkov static struct device_attribute *mce_device_attrs[] = { 249221afaf18SBorislav Petkov &dev_attr_tolerant.attr, 249321afaf18SBorislav Petkov &dev_attr_check_interval.attr, 249421afaf18SBorislav Petkov #ifdef CONFIG_X86_MCELOG_LEGACY 249521afaf18SBorislav Petkov &dev_attr_trigger, 249621afaf18SBorislav Petkov #endif 249721afaf18SBorislav Petkov &dev_attr_monarch_timeout.attr, 249821afaf18SBorislav Petkov &dev_attr_dont_log_ce.attr, 249943505646STony Luck &dev_attr_print_all.attr, 250021afaf18SBorislav Petkov &dev_attr_ignore_ce.attr, 250121afaf18SBorislav Petkov &dev_attr_cmci_disabled.attr, 250221afaf18SBorislav Petkov NULL 250321afaf18SBorislav Petkov }; 250421afaf18SBorislav Petkov 250521afaf18SBorislav Petkov static cpumask_var_t mce_device_initialized; 250621afaf18SBorislav Petkov 250721afaf18SBorislav Petkov static void mce_device_release(struct device *dev) 250821afaf18SBorislav Petkov { 250921afaf18SBorislav Petkov kfree(dev); 251021afaf18SBorislav Petkov } 251121afaf18SBorislav Petkov 2512b4914508SYazen Ghannam /* Per CPU device init. All of the CPUs still share the same bank device: */ 251321afaf18SBorislav Petkov static int mce_device_create(unsigned int cpu) 251421afaf18SBorislav Petkov { 251521afaf18SBorislav Petkov struct device *dev; 251621afaf18SBorislav Petkov int err; 251721afaf18SBorislav Petkov int i, j; 251821afaf18SBorislav Petkov 251921afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) 252021afaf18SBorislav Petkov return -EIO; 252121afaf18SBorislav Petkov 252221afaf18SBorislav Petkov dev = per_cpu(mce_device, cpu); 252321afaf18SBorislav Petkov if (dev) 252421afaf18SBorislav Petkov return 0; 252521afaf18SBorislav Petkov 252621afaf18SBorislav Petkov dev = kzalloc(sizeof(*dev), GFP_KERNEL); 252721afaf18SBorislav Petkov if (!dev) 252821afaf18SBorislav Petkov return -ENOMEM; 252921afaf18SBorislav Petkov dev->id = cpu; 253021afaf18SBorislav Petkov dev->bus = &mce_subsys; 253121afaf18SBorislav Petkov dev->release = &mce_device_release; 253221afaf18SBorislav Petkov 253321afaf18SBorislav Petkov err = device_register(dev); 253421afaf18SBorislav Petkov if (err) { 253521afaf18SBorislav Petkov put_device(dev); 253621afaf18SBorislav Petkov return err; 253721afaf18SBorislav Petkov } 253821afaf18SBorislav Petkov 253921afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) { 254021afaf18SBorislav Petkov err = device_create_file(dev, mce_device_attrs[i]); 254121afaf18SBorislav Petkov if (err) 254221afaf18SBorislav Petkov goto error; 254321afaf18SBorislav Petkov } 2544c7d314f3SYazen Ghannam for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) { 2545b4914508SYazen Ghannam err = device_create_file(dev, &mce_bank_devs[j].attr); 254621afaf18SBorislav Petkov if (err) 254721afaf18SBorislav Petkov goto error2; 254821afaf18SBorislav Petkov } 254921afaf18SBorislav Petkov cpumask_set_cpu(cpu, mce_device_initialized); 255021afaf18SBorislav Petkov per_cpu(mce_device, cpu) = dev; 255121afaf18SBorislav Petkov 255221afaf18SBorislav Petkov return 0; 255321afaf18SBorislav Petkov error2: 255421afaf18SBorislav Petkov while (--j >= 0) 2555b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[j].attr); 255621afaf18SBorislav Petkov error: 255721afaf18SBorislav Petkov while (--i >= 0) 255821afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 255921afaf18SBorislav Petkov 256021afaf18SBorislav Petkov device_unregister(dev); 256121afaf18SBorislav Petkov 256221afaf18SBorislav Petkov return err; 256321afaf18SBorislav Petkov } 256421afaf18SBorislav Petkov 256521afaf18SBorislav Petkov static void mce_device_remove(unsigned int cpu) 256621afaf18SBorislav Petkov { 256721afaf18SBorislav Petkov struct device *dev = per_cpu(mce_device, cpu); 256821afaf18SBorislav Petkov int i; 256921afaf18SBorislav Petkov 257021afaf18SBorislav Petkov if (!cpumask_test_cpu(cpu, mce_device_initialized)) 257121afaf18SBorislav Petkov return; 257221afaf18SBorislav Petkov 257321afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) 257421afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 257521afaf18SBorislav Petkov 2576c7d314f3SYazen Ghannam for (i = 0; i < per_cpu(mce_num_banks, cpu); i++) 2577b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[i].attr); 257821afaf18SBorislav Petkov 257921afaf18SBorislav Petkov device_unregister(dev); 258021afaf18SBorislav Petkov cpumask_clear_cpu(cpu, mce_device_initialized); 258121afaf18SBorislav Petkov per_cpu(mce_device, cpu) = NULL; 258221afaf18SBorislav Petkov } 258321afaf18SBorislav Petkov 258421afaf18SBorislav Petkov /* Make sure there are no machine checks on offlined CPUs. */ 258521afaf18SBorislav Petkov static void mce_disable_cpu(void) 258621afaf18SBorislav Petkov { 258721afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 258821afaf18SBorislav Petkov return; 258921afaf18SBorislav Petkov 259021afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 259121afaf18SBorislav Petkov cmci_clear(); 259221afaf18SBorislav Petkov 259321afaf18SBorislav Petkov vendor_disable_error_reporting(); 259421afaf18SBorislav Petkov } 259521afaf18SBorislav Petkov 259621afaf18SBorislav Petkov static void mce_reenable_cpu(void) 259721afaf18SBorislav Petkov { 2598b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 259921afaf18SBorislav Petkov int i; 260021afaf18SBorislav Petkov 260121afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 260221afaf18SBorislav Petkov return; 260321afaf18SBorislav Petkov 260421afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 260521afaf18SBorislav Petkov cmci_reenable(); 2606c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 260721afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 260821afaf18SBorislav Petkov 260921afaf18SBorislav Petkov if (b->init) 26108121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); 261121afaf18SBorislav Petkov } 261221afaf18SBorislav Petkov } 261321afaf18SBorislav Petkov 261421afaf18SBorislav Petkov static int mce_cpu_dead(unsigned int cpu) 261521afaf18SBorislav Petkov { 261621afaf18SBorislav Petkov mce_intel_hcpu_update(cpu); 261721afaf18SBorislav Petkov 261821afaf18SBorislav Petkov /* intentionally ignoring frozen here */ 261921afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 262021afaf18SBorislav Petkov cmci_rediscover(); 262121afaf18SBorislav Petkov return 0; 262221afaf18SBorislav Petkov } 262321afaf18SBorislav Petkov 262421afaf18SBorislav Petkov static int mce_cpu_online(unsigned int cpu) 262521afaf18SBorislav Petkov { 262621afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 262721afaf18SBorislav Petkov int ret; 262821afaf18SBorislav Petkov 262921afaf18SBorislav Petkov mce_device_create(cpu); 263021afaf18SBorislav Petkov 263121afaf18SBorislav Petkov ret = mce_threshold_create_device(cpu); 263221afaf18SBorislav Petkov if (ret) { 263321afaf18SBorislav Petkov mce_device_remove(cpu); 263421afaf18SBorislav Petkov return ret; 263521afaf18SBorislav Petkov } 263621afaf18SBorislav Petkov mce_reenable_cpu(); 263721afaf18SBorislav Petkov mce_start_timer(t); 263821afaf18SBorislav Petkov return 0; 263921afaf18SBorislav Petkov } 264021afaf18SBorislav Petkov 264121afaf18SBorislav Petkov static int mce_cpu_pre_down(unsigned int cpu) 264221afaf18SBorislav Petkov { 264321afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 264421afaf18SBorislav Petkov 264521afaf18SBorislav Petkov mce_disable_cpu(); 264621afaf18SBorislav Petkov del_timer_sync(t); 264721afaf18SBorislav Petkov mce_threshold_remove_device(cpu); 264821afaf18SBorislav Petkov mce_device_remove(cpu); 264921afaf18SBorislav Petkov return 0; 265021afaf18SBorislav Petkov } 265121afaf18SBorislav Petkov 265221afaf18SBorislav Petkov static __init void mce_init_banks(void) 265321afaf18SBorislav Petkov { 265421afaf18SBorislav Petkov int i; 265521afaf18SBorislav Petkov 2656b4914508SYazen Ghannam for (i = 0; i < MAX_NR_BANKS; i++) { 2657b4914508SYazen Ghannam struct mce_bank_dev *b = &mce_bank_devs[i]; 265821afaf18SBorislav Petkov struct device_attribute *a = &b->attr; 265921afaf18SBorislav Petkov 2660b4914508SYazen Ghannam b->bank = i; 2661b4914508SYazen Ghannam 266221afaf18SBorislav Petkov sysfs_attr_init(&a->attr); 266321afaf18SBorislav Petkov a->attr.name = b->attrname; 266421afaf18SBorislav Petkov snprintf(b->attrname, ATTR_LEN, "bank%d", i); 266521afaf18SBorislav Petkov 266621afaf18SBorislav Petkov a->attr.mode = 0644; 266721afaf18SBorislav Petkov a->show = show_bank; 266821afaf18SBorislav Petkov a->store = set_bank; 266921afaf18SBorislav Petkov } 267021afaf18SBorislav Petkov } 267121afaf18SBorislav Petkov 26726e7a41c6SThomas Gleixner /* 26736e7a41c6SThomas Gleixner * When running on XEN, this initcall is ordered against the XEN mcelog 26746e7a41c6SThomas Gleixner * initcall: 26756e7a41c6SThomas Gleixner * 26766e7a41c6SThomas Gleixner * device_initcall(xen_late_init_mcelog); 26776e7a41c6SThomas Gleixner * device_initcall_sync(mcheck_init_device); 26786e7a41c6SThomas Gleixner */ 267921afaf18SBorislav Petkov static __init int mcheck_init_device(void) 268021afaf18SBorislav Petkov { 268121afaf18SBorislav Petkov int err; 268221afaf18SBorislav Petkov 268321afaf18SBorislav Petkov /* 268421afaf18SBorislav Petkov * Check if we have a spare virtual bit. This will only become 268521afaf18SBorislav Petkov * a problem if/when we move beyond 5-level page tables. 268621afaf18SBorislav Petkov */ 268721afaf18SBorislav Petkov MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63); 268821afaf18SBorislav Petkov 268921afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) { 269021afaf18SBorislav Petkov err = -EIO; 269121afaf18SBorislav Petkov goto err_out; 269221afaf18SBorislav Petkov } 269321afaf18SBorislav Petkov 269421afaf18SBorislav Petkov if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { 269521afaf18SBorislav Petkov err = -ENOMEM; 269621afaf18SBorislav Petkov goto err_out; 269721afaf18SBorislav Petkov } 269821afaf18SBorislav Petkov 269921afaf18SBorislav Petkov mce_init_banks(); 270021afaf18SBorislav Petkov 270121afaf18SBorislav Petkov err = subsys_system_register(&mce_subsys, NULL); 270221afaf18SBorislav Petkov if (err) 270321afaf18SBorislav Petkov goto err_out_mem; 270421afaf18SBorislav Petkov 270521afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL, 270621afaf18SBorislav Petkov mce_cpu_dead); 270721afaf18SBorislav Petkov if (err) 270821afaf18SBorislav Petkov goto err_out_mem; 270921afaf18SBorislav Petkov 27106e7a41c6SThomas Gleixner /* 27116e7a41c6SThomas Gleixner * Invokes mce_cpu_online() on all CPUs which are online when 27126e7a41c6SThomas Gleixner * the state is installed. 27136e7a41c6SThomas Gleixner */ 271421afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online", 271521afaf18SBorislav Petkov mce_cpu_online, mce_cpu_pre_down); 271621afaf18SBorislav Petkov if (err < 0) 271721afaf18SBorislav Petkov goto err_out_online; 271821afaf18SBorislav Petkov 271921afaf18SBorislav Petkov register_syscore_ops(&mce_syscore_ops); 272021afaf18SBorislav Petkov 272121afaf18SBorislav Petkov return 0; 272221afaf18SBorislav Petkov 272321afaf18SBorislav Petkov err_out_online: 272421afaf18SBorislav Petkov cpuhp_remove_state(CPUHP_X86_MCE_DEAD); 272521afaf18SBorislav Petkov 272621afaf18SBorislav Petkov err_out_mem: 272721afaf18SBorislav Petkov free_cpumask_var(mce_device_initialized); 272821afaf18SBorislav Petkov 272921afaf18SBorislav Petkov err_out: 273021afaf18SBorislav Petkov pr_err("Unable to init MCE device (rc: %d)\n", err); 273121afaf18SBorislav Petkov 273221afaf18SBorislav Petkov return err; 273321afaf18SBorislav Petkov } 273421afaf18SBorislav Petkov device_initcall_sync(mcheck_init_device); 273521afaf18SBorislav Petkov 273621afaf18SBorislav Petkov /* 273721afaf18SBorislav Petkov * Old style boot options parsing. Only for compatibility. 273821afaf18SBorislav Petkov */ 273921afaf18SBorislav Petkov static int __init mcheck_disable(char *str) 274021afaf18SBorislav Petkov { 274121afaf18SBorislav Petkov mca_cfg.disabled = 1; 274221afaf18SBorislav Petkov return 1; 274321afaf18SBorislav Petkov } 274421afaf18SBorislav Petkov __setup("nomce", mcheck_disable); 274521afaf18SBorislav Petkov 274621afaf18SBorislav Petkov #ifdef CONFIG_DEBUG_FS 274721afaf18SBorislav Petkov struct dentry *mce_get_debugfs_dir(void) 274821afaf18SBorislav Petkov { 274921afaf18SBorislav Petkov static struct dentry *dmce; 275021afaf18SBorislav Petkov 275121afaf18SBorislav Petkov if (!dmce) 275221afaf18SBorislav Petkov dmce = debugfs_create_dir("mce", NULL); 275321afaf18SBorislav Petkov 275421afaf18SBorislav Petkov return dmce; 275521afaf18SBorislav Petkov } 275621afaf18SBorislav Petkov 275721afaf18SBorislav Petkov static void mce_reset(void) 275821afaf18SBorislav Petkov { 275921afaf18SBorislav Petkov atomic_set(&mce_fake_panicked, 0); 276021afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 276121afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 276221afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 27637bb39313SPaul E. McKenney cpumask_setall(&mce_missing_cpus); 276421afaf18SBorislav Petkov } 276521afaf18SBorislav Petkov 276621afaf18SBorislav Petkov static int fake_panic_get(void *data, u64 *val) 276721afaf18SBorislav Petkov { 276821afaf18SBorislav Petkov *val = fake_panic; 276921afaf18SBorislav Petkov return 0; 277021afaf18SBorislav Petkov } 277121afaf18SBorislav Petkov 277221afaf18SBorislav Petkov static int fake_panic_set(void *data, u64 val) 277321afaf18SBorislav Petkov { 277421afaf18SBorislav Petkov mce_reset(); 277521afaf18SBorislav Petkov fake_panic = val; 277621afaf18SBorislav Petkov return 0; 277721afaf18SBorislav Petkov } 277821afaf18SBorislav Petkov 277928156d76SYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set, 278028156d76SYueHaibing "%llu\n"); 278121afaf18SBorislav Petkov 27826e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) 278321afaf18SBorislav Petkov { 27846e4f929eSGreg Kroah-Hartman struct dentry *dmce; 278521afaf18SBorislav Petkov 278621afaf18SBorislav Petkov dmce = mce_get_debugfs_dir(); 27876e4f929eSGreg Kroah-Hartman debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL, 27886e4f929eSGreg Kroah-Hartman &fake_panic_fops); 278921afaf18SBorislav Petkov } 279021afaf18SBorislav Petkov #else 27916e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) { } 279221afaf18SBorislav Petkov #endif 279321afaf18SBorislav Petkov 279421afaf18SBorislav Petkov static int __init mcheck_late_init(void) 279521afaf18SBorislav Petkov { 279621afaf18SBorislav Petkov if (mca_cfg.recovery) 2797ec6347bbSDan Williams enable_copy_mc_fragile(); 279821afaf18SBorislav Petkov 279921afaf18SBorislav Petkov mcheck_debugfs_init(); 280021afaf18SBorislav Petkov 280121afaf18SBorislav Petkov /* 280221afaf18SBorislav Petkov * Flush out everything that has been logged during early boot, now that 280321afaf18SBorislav Petkov * everything has been initialized (workqueues, decoders, ...). 280421afaf18SBorislav Petkov */ 280521afaf18SBorislav Petkov mce_schedule_work(); 280621afaf18SBorislav Petkov 280721afaf18SBorislav Petkov return 0; 280821afaf18SBorislav Petkov } 280921afaf18SBorislav Petkov late_initcall(mcheck_late_init); 2810