1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 221afaf18SBorislav Petkov /* 321afaf18SBorislav Petkov * Machine check handler. 421afaf18SBorislav Petkov * 521afaf18SBorislav Petkov * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. 621afaf18SBorislav Petkov * Rest from unknown author(s). 721afaf18SBorislav Petkov * 2004 Andi Kleen. Rewrote most of it. 821afaf18SBorislav Petkov * Copyright 2008 Intel Corporation 921afaf18SBorislav Petkov * Author: Andi Kleen 1021afaf18SBorislav Petkov */ 1121afaf18SBorislav Petkov 1221afaf18SBorislav Petkov #include <linux/thread_info.h> 1321afaf18SBorislav Petkov #include <linux/capability.h> 1421afaf18SBorislav Petkov #include <linux/miscdevice.h> 1521afaf18SBorislav Petkov #include <linux/ratelimit.h> 1621afaf18SBorislav Petkov #include <linux/rcupdate.h> 1721afaf18SBorislav Petkov #include <linux/kobject.h> 1821afaf18SBorislav Petkov #include <linux/uaccess.h> 1921afaf18SBorislav Petkov #include <linux/kdebug.h> 2021afaf18SBorislav Petkov #include <linux/kernel.h> 2121afaf18SBorislav Petkov #include <linux/percpu.h> 2221afaf18SBorislav Petkov #include <linux/string.h> 2321afaf18SBorislav Petkov #include <linux/device.h> 2421afaf18SBorislav Petkov #include <linux/syscore_ops.h> 2521afaf18SBorislav Petkov #include <linux/delay.h> 2621afaf18SBorislav Petkov #include <linux/ctype.h> 2721afaf18SBorislav Petkov #include <linux/sched.h> 2821afaf18SBorislav Petkov #include <linux/sysfs.h> 2921afaf18SBorislav Petkov #include <linux/types.h> 3021afaf18SBorislav Petkov #include <linux/slab.h> 3121afaf18SBorislav Petkov #include <linux/init.h> 3221afaf18SBorislav Petkov #include <linux/kmod.h> 3321afaf18SBorislav Petkov #include <linux/poll.h> 3421afaf18SBorislav Petkov #include <linux/nmi.h> 3521afaf18SBorislav Petkov #include <linux/cpu.h> 3621afaf18SBorislav Petkov #include <linux/ras.h> 3721afaf18SBorislav Petkov #include <linux/smp.h> 3821afaf18SBorislav Petkov #include <linux/fs.h> 3921afaf18SBorislav Petkov #include <linux/mm.h> 4021afaf18SBorislav Petkov #include <linux/debugfs.h> 4121afaf18SBorislav Petkov #include <linux/irq_work.h> 4221afaf18SBorislav Petkov #include <linux/export.h> 4321afaf18SBorislav Petkov #include <linux/set_memory.h> 449998a983SRicardo Neri #include <linux/sync_core.h> 455567d11cSPeter Zijlstra #include <linux/task_work.h> 460d00449cSPeter Zijlstra #include <linux/hardirq.h> 4721afaf18SBorislav Petkov 4821afaf18SBorislav Petkov #include <asm/intel-family.h> 4921afaf18SBorislav Petkov #include <asm/processor.h> 5021afaf18SBorislav Petkov #include <asm/traps.h> 5121afaf18SBorislav Petkov #include <asm/tlbflush.h> 5221afaf18SBorislav Petkov #include <asm/mce.h> 5321afaf18SBorislav Petkov #include <asm/msr.h> 5421afaf18SBorislav Petkov #include <asm/reboot.h> 5521afaf18SBorislav Petkov 5621afaf18SBorislav Petkov #include "internal.h" 5721afaf18SBorislav Petkov 5821afaf18SBorislav Petkov /* sysfs synchronization */ 5921afaf18SBorislav Petkov static DEFINE_MUTEX(mce_sysfs_mutex); 6021afaf18SBorislav Petkov 6121afaf18SBorislav Petkov #define CREATE_TRACE_POINTS 6221afaf18SBorislav Petkov #include <trace/events/mce.h> 6321afaf18SBorislav Petkov 6421afaf18SBorislav Petkov #define SPINUNIT 100 /* 100ns */ 6521afaf18SBorislav Petkov 6621afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_exception_count); 6721afaf18SBorislav Petkov 68c7d314f3SYazen Ghannam DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks); 69c7d314f3SYazen Ghannam 7095fdce6bSYazen Ghannam struct mce_bank { 7195fdce6bSYazen Ghannam u64 ctl; /* subevents to enable */ 7295fdce6bSYazen Ghannam bool init; /* initialise bank? */ 73b4914508SYazen Ghannam }; 74b4914508SYazen Ghannam static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); 75b4914508SYazen Ghannam 76b4914508SYazen Ghannam #define ATTR_LEN 16 77b4914508SYazen Ghannam /* One object for each MCE bank, shared by all CPUs */ 78b4914508SYazen Ghannam struct mce_bank_dev { 7995fdce6bSYazen Ghannam struct device_attribute attr; /* device attribute */ 8095fdce6bSYazen Ghannam char attrname[ATTR_LEN]; /* attribute name */ 81b4914508SYazen Ghannam u8 bank; /* bank number */ 8295fdce6bSYazen Ghannam }; 83b4914508SYazen Ghannam static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS]; 8495fdce6bSYazen Ghannam 8521afaf18SBorislav Petkov struct mce_vendor_flags mce_flags __read_mostly; 8621afaf18SBorislav Petkov 8721afaf18SBorislav Petkov struct mca_config mca_cfg __read_mostly = { 8821afaf18SBorislav Petkov .bootlog = -1, 8921afaf18SBorislav Petkov /* 9021afaf18SBorislav Petkov * Tolerant levels: 9121afaf18SBorislav Petkov * 0: always panic on uncorrected errors, log corrected errors 9221afaf18SBorislav Petkov * 1: panic or SIGBUS on uncorrected errors, log corrected errors 9321afaf18SBorislav Petkov * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors 9421afaf18SBorislav Petkov * 3: never panic or SIGBUS, log all errors (for testing only) 9521afaf18SBorislav Petkov */ 9621afaf18SBorislav Petkov .tolerant = 1, 9721afaf18SBorislav Petkov .monarch_timeout = -1 9821afaf18SBorislav Petkov }; 9921afaf18SBorislav Petkov 10021afaf18SBorislav Petkov static DEFINE_PER_CPU(struct mce, mces_seen); 10121afaf18SBorislav Petkov static unsigned long mce_need_notify; 10221afaf18SBorislav Petkov 10321afaf18SBorislav Petkov /* 10421afaf18SBorislav Petkov * MCA banks polled by the period polling timer for corrected events. 10521afaf18SBorislav Petkov * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). 10621afaf18SBorislav Petkov */ 10721afaf18SBorislav Petkov DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { 10821afaf18SBorislav Petkov [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL 10921afaf18SBorislav Petkov }; 11021afaf18SBorislav Petkov 11121afaf18SBorislav Petkov /* 11221afaf18SBorislav Petkov * MCA banks controlled through firmware first for corrected errors. 11321afaf18SBorislav Petkov * This is a global list of banks for which we won't enable CMCI and we 11421afaf18SBorislav Petkov * won't poll. Firmware controls these banks and is responsible for 11521afaf18SBorislav Petkov * reporting corrected errors through GHES. Uncorrected/recoverable 11621afaf18SBorislav Petkov * errors are still notified through a machine check. 11721afaf18SBorislav Petkov */ 11821afaf18SBorislav Petkov mce_banks_t mce_banks_ce_disabled; 11921afaf18SBorislav Petkov 12021afaf18SBorislav Petkov static struct work_struct mce_work; 12121afaf18SBorislav Petkov static struct irq_work mce_irq_work; 12221afaf18SBorislav Petkov 12321afaf18SBorislav Petkov /* 12421afaf18SBorislav Petkov * CPU/chipset specific EDAC code can register a notifier call here to print 12521afaf18SBorislav Petkov * MCE errors in a human-readable form. 12621afaf18SBorislav Petkov */ 12721afaf18SBorislav Petkov BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); 12821afaf18SBorislav Petkov 12921afaf18SBorislav Petkov /* Do initial initialization of a struct mce */ 130865d3a9aSThomas Gleixner noinstr void mce_setup(struct mce *m) 13121afaf18SBorislav Petkov { 13221afaf18SBorislav Petkov memset(m, 0, sizeof(struct mce)); 13321afaf18SBorislav Petkov m->cpu = m->extcpu = smp_processor_id(); 13421afaf18SBorislav Petkov /* need the internal __ version to avoid deadlocks */ 13521afaf18SBorislav Petkov m->time = __ktime_get_real_seconds(); 13621afaf18SBorislav Petkov m->cpuvendor = boot_cpu_data.x86_vendor; 13721afaf18SBorislav Petkov m->cpuid = cpuid_eax(1); 13821afaf18SBorislav Petkov m->socketid = cpu_data(m->extcpu).phys_proc_id; 13921afaf18SBorislav Petkov m->apicid = cpu_data(m->extcpu).initial_apicid; 140865d3a9aSThomas Gleixner m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); 14121afaf18SBorislav Petkov 14221afaf18SBorislav Petkov if (this_cpu_has(X86_FEATURE_INTEL_PPIN)) 143865d3a9aSThomas Gleixner m->ppin = __rdmsr(MSR_PPIN); 144077168e2SWei Huang else if (this_cpu_has(X86_FEATURE_AMD_PPIN)) 145865d3a9aSThomas Gleixner m->ppin = __rdmsr(MSR_AMD_PPIN); 14621afaf18SBorislav Petkov 14721afaf18SBorislav Petkov m->microcode = boot_cpu_data.microcode; 14821afaf18SBorislav Petkov } 14921afaf18SBorislav Petkov 15021afaf18SBorislav Petkov DEFINE_PER_CPU(struct mce, injectm); 15121afaf18SBorislav Petkov EXPORT_PER_CPU_SYMBOL_GPL(injectm); 15221afaf18SBorislav Petkov 15321afaf18SBorislav Petkov void mce_log(struct mce *m) 15421afaf18SBorislav Petkov { 15521afaf18SBorislav Petkov if (!mce_gen_pool_add(m)) 15621afaf18SBorislav Petkov irq_work_queue(&mce_irq_work); 15721afaf18SBorislav Petkov } 15881736abdSJan H. Schönherr EXPORT_SYMBOL_GPL(mce_log); 15921afaf18SBorislav Petkov 16021afaf18SBorislav Petkov void mce_register_decode_chain(struct notifier_block *nb) 16121afaf18SBorislav Petkov { 16215af3659SZhen Lei if (WARN_ON(nb->priority < MCE_PRIO_LOWEST || 16315af3659SZhen Lei nb->priority > MCE_PRIO_HIGHEST)) 16421afaf18SBorislav Petkov return; 16521afaf18SBorislav Petkov 16621afaf18SBorislav Petkov blocking_notifier_chain_register(&x86_mce_decoder_chain, nb); 16721afaf18SBorislav Petkov } 16821afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_register_decode_chain); 16921afaf18SBorislav Petkov 17021afaf18SBorislav Petkov void mce_unregister_decode_chain(struct notifier_block *nb) 17121afaf18SBorislav Petkov { 17221afaf18SBorislav Petkov blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb); 17321afaf18SBorislav Petkov } 17421afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); 17521afaf18SBorislav Petkov 1768121b8f9SBorislav Petkov u32 mca_msr_reg(int bank, enum mca_msr reg) 17721afaf18SBorislav Petkov { 1788121b8f9SBorislav Petkov if (mce_flags.smca) { 1798121b8f9SBorislav Petkov switch (reg) { 1808121b8f9SBorislav Petkov case MCA_CTL: return MSR_AMD64_SMCA_MCx_CTL(bank); 1818121b8f9SBorislav Petkov case MCA_ADDR: return MSR_AMD64_SMCA_MCx_ADDR(bank); 1828121b8f9SBorislav Petkov case MCA_MISC: return MSR_AMD64_SMCA_MCx_MISC(bank); 1838121b8f9SBorislav Petkov case MCA_STATUS: return MSR_AMD64_SMCA_MCx_STATUS(bank); 1848121b8f9SBorislav Petkov } 18521afaf18SBorislav Petkov } 18621afaf18SBorislav Petkov 1878121b8f9SBorislav Petkov switch (reg) { 1888121b8f9SBorislav Petkov case MCA_CTL: return MSR_IA32_MCx_CTL(bank); 1898121b8f9SBorislav Petkov case MCA_ADDR: return MSR_IA32_MCx_ADDR(bank); 1908121b8f9SBorislav Petkov case MCA_MISC: return MSR_IA32_MCx_MISC(bank); 1918121b8f9SBorislav Petkov case MCA_STATUS: return MSR_IA32_MCx_STATUS(bank); 19221afaf18SBorislav Petkov } 19321afaf18SBorislav Petkov 1948121b8f9SBorislav Petkov return 0; 19521afaf18SBorislav Petkov } 19621afaf18SBorislav Petkov 19721afaf18SBorislav Petkov static void __print_mce(struct mce *m) 19821afaf18SBorislav Petkov { 19921afaf18SBorislav Petkov pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", 20021afaf18SBorislav Petkov m->extcpu, 20121afaf18SBorislav Petkov (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""), 20221afaf18SBorislav Petkov m->mcgstatus, m->bank, m->status); 20321afaf18SBorislav Petkov 20421afaf18SBorislav Petkov if (m->ip) { 20521afaf18SBorislav Petkov pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", 20621afaf18SBorislav Petkov !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", 20721afaf18SBorislav Petkov m->cs, m->ip); 20821afaf18SBorislav Petkov 20921afaf18SBorislav Petkov if (m->cs == __KERNEL_CS) 21021afaf18SBorislav Petkov pr_cont("{%pS}", (void *)(unsigned long)m->ip); 21121afaf18SBorislav Petkov pr_cont("\n"); 21221afaf18SBorislav Petkov } 21321afaf18SBorislav Petkov 21421afaf18SBorislav Petkov pr_emerg(HW_ERR "TSC %llx ", m->tsc); 21521afaf18SBorislav Petkov if (m->addr) 21621afaf18SBorislav Petkov pr_cont("ADDR %llx ", m->addr); 21721afaf18SBorislav Petkov if (m->misc) 21821afaf18SBorislav Petkov pr_cont("MISC %llx ", m->misc); 219bb2de0adSSmita Koralahalli if (m->ppin) 220bb2de0adSSmita Koralahalli pr_cont("PPIN %llx ", m->ppin); 22121afaf18SBorislav Petkov 22221afaf18SBorislav Petkov if (mce_flags.smca) { 22321afaf18SBorislav Petkov if (m->synd) 22421afaf18SBorislav Petkov pr_cont("SYND %llx ", m->synd); 22521afaf18SBorislav Petkov if (m->ipid) 22621afaf18SBorislav Petkov pr_cont("IPID %llx ", m->ipid); 22721afaf18SBorislav Petkov } 22821afaf18SBorislav Petkov 22921afaf18SBorislav Petkov pr_cont("\n"); 230925946cfSTony Luck 23121afaf18SBorislav Petkov /* 23221afaf18SBorislav Petkov * Note this output is parsed by external tools and old fields 23321afaf18SBorislav Petkov * should not be changed. 23421afaf18SBorislav Petkov */ 23521afaf18SBorislav Petkov pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", 23621afaf18SBorislav Petkov m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, 23721afaf18SBorislav Petkov m->microcode); 23821afaf18SBorislav Petkov } 23921afaf18SBorislav Petkov 24021afaf18SBorislav Petkov static void print_mce(struct mce *m) 24121afaf18SBorislav Petkov { 24221afaf18SBorislav Petkov __print_mce(m); 24321afaf18SBorislav Petkov 24421afaf18SBorislav Petkov if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON) 24521afaf18SBorislav Petkov pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); 24621afaf18SBorislav Petkov } 24721afaf18SBorislav Petkov 24821afaf18SBorislav Petkov #define PANIC_TIMEOUT 5 /* 5 seconds */ 24921afaf18SBorislav Petkov 25021afaf18SBorislav Petkov static atomic_t mce_panicked; 25121afaf18SBorislav Petkov 25221afaf18SBorislav Petkov static int fake_panic; 25321afaf18SBorislav Petkov static atomic_t mce_fake_panicked; 25421afaf18SBorislav Petkov 25521afaf18SBorislav Petkov /* Panic in progress. Enable interrupts and wait for final IPI */ 25621afaf18SBorislav Petkov static void wait_for_panic(void) 25721afaf18SBorislav Petkov { 25821afaf18SBorislav Petkov long timeout = PANIC_TIMEOUT*USEC_PER_SEC; 25921afaf18SBorislav Petkov 26021afaf18SBorislav Petkov preempt_disable(); 26121afaf18SBorislav Petkov local_irq_enable(); 26221afaf18SBorislav Petkov while (timeout-- > 0) 26321afaf18SBorislav Petkov udelay(1); 26421afaf18SBorislav Petkov if (panic_timeout == 0) 26521afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 26621afaf18SBorislav Petkov panic("Panicing machine check CPU died"); 26721afaf18SBorislav Petkov } 26821afaf18SBorislav Petkov 26921afaf18SBorislav Petkov static void mce_panic(const char *msg, struct mce *final, char *exp) 27021afaf18SBorislav Petkov { 27121afaf18SBorislav Petkov int apei_err = 0; 27221afaf18SBorislav Petkov struct llist_node *pending; 27321afaf18SBorislav Petkov struct mce_evt_llist *l; 27421afaf18SBorislav Petkov 27521afaf18SBorislav Petkov if (!fake_panic) { 27621afaf18SBorislav Petkov /* 27721afaf18SBorislav Petkov * Make sure only one CPU runs in machine check panic 27821afaf18SBorislav Petkov */ 27921afaf18SBorislav Petkov if (atomic_inc_return(&mce_panicked) > 1) 28021afaf18SBorislav Petkov wait_for_panic(); 28121afaf18SBorislav Petkov barrier(); 28221afaf18SBorislav Petkov 28321afaf18SBorislav Petkov bust_spinlocks(1); 28421afaf18SBorislav Petkov console_verbose(); 28521afaf18SBorislav Petkov } else { 28621afaf18SBorislav Petkov /* Don't log too much for fake panic */ 28721afaf18SBorislav Petkov if (atomic_inc_return(&mce_fake_panicked) > 1) 28821afaf18SBorislav Petkov return; 28921afaf18SBorislav Petkov } 29021afaf18SBorislav Petkov pending = mce_gen_pool_prepare_records(); 29121afaf18SBorislav Petkov /* First print corrected ones that are still unlogged */ 29221afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 29321afaf18SBorislav Petkov struct mce *m = &l->mce; 29421afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) { 29521afaf18SBorislav Petkov print_mce(m); 29621afaf18SBorislav Petkov if (!apei_err) 29721afaf18SBorislav Petkov apei_err = apei_write_mce(m); 29821afaf18SBorislav Petkov } 29921afaf18SBorislav Petkov } 30021afaf18SBorislav Petkov /* Now print uncorrected but with the final one last */ 30121afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 30221afaf18SBorislav Petkov struct mce *m = &l->mce; 30321afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) 30421afaf18SBorislav Petkov continue; 30521afaf18SBorislav Petkov if (!final || mce_cmp(m, final)) { 30621afaf18SBorislav Petkov print_mce(m); 30721afaf18SBorislav Petkov if (!apei_err) 30821afaf18SBorislav Petkov apei_err = apei_write_mce(m); 30921afaf18SBorislav Petkov } 31021afaf18SBorislav Petkov } 31121afaf18SBorislav Petkov if (final) { 31221afaf18SBorislav Petkov print_mce(final); 31321afaf18SBorislav Petkov if (!apei_err) 31421afaf18SBorislav Petkov apei_err = apei_write_mce(final); 31521afaf18SBorislav Petkov } 31621afaf18SBorislav Petkov if (exp) 31721afaf18SBorislav Petkov pr_emerg(HW_ERR "Machine check: %s\n", exp); 31821afaf18SBorislav Petkov if (!fake_panic) { 31921afaf18SBorislav Petkov if (panic_timeout == 0) 32021afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 32121afaf18SBorislav Petkov panic(msg); 32221afaf18SBorislav Petkov } else 32321afaf18SBorislav Petkov pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); 32421afaf18SBorislav Petkov } 32521afaf18SBorislav Petkov 32621afaf18SBorislav Petkov /* Support code for software error injection */ 32721afaf18SBorislav Petkov 32821afaf18SBorislav Petkov static int msr_to_offset(u32 msr) 32921afaf18SBorislav Petkov { 33021afaf18SBorislav Petkov unsigned bank = __this_cpu_read(injectm.bank); 33121afaf18SBorislav Petkov 33221afaf18SBorislav Petkov if (msr == mca_cfg.rip_msr) 33321afaf18SBorislav Petkov return offsetof(struct mce, ip); 3348121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_STATUS)) 33521afaf18SBorislav Petkov return offsetof(struct mce, status); 3368121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_ADDR)) 33721afaf18SBorislav Petkov return offsetof(struct mce, addr); 3388121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_MISC)) 33921afaf18SBorislav Petkov return offsetof(struct mce, misc); 34021afaf18SBorislav Petkov if (msr == MSR_IA32_MCG_STATUS) 34121afaf18SBorislav Petkov return offsetof(struct mce, mcgstatus); 34221afaf18SBorislav Petkov return -1; 34321afaf18SBorislav Petkov } 34421afaf18SBorislav Petkov 34546d28947SThomas Gleixner void ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr) 346e2def7d4SBorislav Petkov { 347e42404afSThomas Gleixner if (wrmsr) { 348e42404afSThomas Gleixner pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n", 349e42404afSThomas Gleixner (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax, 350e42404afSThomas Gleixner regs->ip, (void *)regs->ip); 351e42404afSThomas Gleixner } else { 352e2def7d4SBorislav Petkov pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n", 353e2def7d4SBorislav Petkov (unsigned int)regs->cx, regs->ip, (void *)regs->ip); 354e42404afSThomas Gleixner } 355e2def7d4SBorislav Petkov 356e2def7d4SBorislav Petkov show_stack_regs(regs); 357e2def7d4SBorislav Petkov 358e2def7d4SBorislav Petkov panic("MCA architectural violation!\n"); 359e2def7d4SBorislav Petkov 360e2def7d4SBorislav Petkov while (true) 361e2def7d4SBorislav Petkov cpu_relax(); 362e42404afSThomas Gleixner } 363e2def7d4SBorislav Petkov 36421afaf18SBorislav Petkov /* MSR access wrappers used for error injection */ 365e1007770SBorislav Petkov static noinstr u64 mce_rdmsrl(u32 msr) 36621afaf18SBorislav Petkov { 367e2def7d4SBorislav Petkov DECLARE_ARGS(val, low, high); 36821afaf18SBorislav Petkov 36921afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 370e1007770SBorislav Petkov int offset; 371e1007770SBorislav Petkov u64 ret; 37221afaf18SBorislav Petkov 373e1007770SBorislav Petkov instrumentation_begin(); 374e1007770SBorislav Petkov 375e1007770SBorislav Petkov offset = msr_to_offset(msr); 37621afaf18SBorislav Petkov if (offset < 0) 377e1007770SBorislav Petkov ret = 0; 378e1007770SBorislav Petkov else 379e1007770SBorislav Petkov ret = *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); 380e1007770SBorislav Petkov 381e1007770SBorislav Petkov instrumentation_end(); 382e1007770SBorislav Petkov 383e1007770SBorislav Petkov return ret; 38421afaf18SBorislav Petkov } 38521afaf18SBorislav Petkov 38621afaf18SBorislav Petkov /* 387e2def7d4SBorislav Petkov * RDMSR on MCA MSRs should not fault. If they do, this is very much an 388e2def7d4SBorislav Petkov * architectural violation and needs to be reported to hw vendor. Panic 389e2def7d4SBorislav Petkov * the box to not allow any further progress. 39021afaf18SBorislav Petkov */ 391e2def7d4SBorislav Petkov asm volatile("1: rdmsr\n" 392e2def7d4SBorislav Petkov "2:\n" 39346d28947SThomas Gleixner _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR_IN_MCE) 394e2def7d4SBorislav Petkov : EAX_EDX_RET(val, low, high) : "c" (msr)); 395e2def7d4SBorislav Petkov 396e2def7d4SBorislav Petkov 397e2def7d4SBorislav Petkov return EAX_EDX_VAL(val, low, high); 39821afaf18SBorislav Petkov } 39921afaf18SBorislav Petkov 400e1007770SBorislav Petkov static noinstr void mce_wrmsrl(u32 msr, u64 v) 40121afaf18SBorislav Petkov { 402e2def7d4SBorislav Petkov u32 low, high; 403e2def7d4SBorislav Petkov 40421afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 405e1007770SBorislav Petkov int offset; 40621afaf18SBorislav Petkov 407e1007770SBorislav Petkov instrumentation_begin(); 408e1007770SBorislav Petkov 409e1007770SBorislav Petkov offset = msr_to_offset(msr); 41021afaf18SBorislav Petkov if (offset >= 0) 41121afaf18SBorislav Petkov *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; 412e1007770SBorislav Petkov 413e1007770SBorislav Petkov instrumentation_end(); 414e1007770SBorislav Petkov 41521afaf18SBorislav Petkov return; 41621afaf18SBorislav Petkov } 417e2def7d4SBorislav Petkov 418e2def7d4SBorislav Petkov low = (u32)v; 419e2def7d4SBorislav Petkov high = (u32)(v >> 32); 420e2def7d4SBorislav Petkov 421e2def7d4SBorislav Petkov /* See comment in mce_rdmsrl() */ 422e2def7d4SBorislav Petkov asm volatile("1: wrmsr\n" 423e2def7d4SBorislav Petkov "2:\n" 42446d28947SThomas Gleixner _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR_IN_MCE) 425e2def7d4SBorislav Petkov : : "c" (msr), "a"(low), "d" (high) : "memory"); 42621afaf18SBorislav Petkov } 42721afaf18SBorislav Petkov 42821afaf18SBorislav Petkov /* 42921afaf18SBorislav Petkov * Collect all global (w.r.t. this processor) status about this machine 43021afaf18SBorislav Petkov * check into our "mce" struct so that we can use it later to assess 43121afaf18SBorislav Petkov * the severity of the problem as we read per-bank specific details. 43221afaf18SBorislav Petkov */ 43321afaf18SBorislav Petkov static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) 43421afaf18SBorislav Petkov { 43521afaf18SBorislav Petkov mce_setup(m); 43621afaf18SBorislav Petkov 43721afaf18SBorislav Petkov m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 43821afaf18SBorislav Petkov if (regs) { 43921afaf18SBorislav Petkov /* 44021afaf18SBorislav Petkov * Get the address of the instruction at the time of 44121afaf18SBorislav Petkov * the machine check error. 44221afaf18SBorislav Petkov */ 44321afaf18SBorislav Petkov if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { 44421afaf18SBorislav Petkov m->ip = regs->ip; 44521afaf18SBorislav Petkov m->cs = regs->cs; 44621afaf18SBorislav Petkov 44721afaf18SBorislav Petkov /* 44821afaf18SBorislav Petkov * When in VM86 mode make the cs look like ring 3 44921afaf18SBorislav Petkov * always. This is a lie, but it's better than passing 45021afaf18SBorislav Petkov * the additional vm86 bit around everywhere. 45121afaf18SBorislav Petkov */ 45221afaf18SBorislav Petkov if (v8086_mode(regs)) 45321afaf18SBorislav Petkov m->cs |= 3; 45421afaf18SBorislav Petkov } 45521afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 45621afaf18SBorislav Petkov if (mca_cfg.rip_msr) 45721afaf18SBorislav Petkov m->ip = mce_rdmsrl(mca_cfg.rip_msr); 45821afaf18SBorislav Petkov } 45921afaf18SBorislav Petkov } 46021afaf18SBorislav Petkov 46121afaf18SBorislav Petkov int mce_available(struct cpuinfo_x86 *c) 46221afaf18SBorislav Petkov { 46321afaf18SBorislav Petkov if (mca_cfg.disabled) 46421afaf18SBorislav Petkov return 0; 46521afaf18SBorislav Petkov return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); 46621afaf18SBorislav Petkov } 46721afaf18SBorislav Petkov 46821afaf18SBorislav Petkov static void mce_schedule_work(void) 46921afaf18SBorislav Petkov { 47021afaf18SBorislav Petkov if (!mce_gen_pool_empty()) 47121afaf18SBorislav Petkov schedule_work(&mce_work); 47221afaf18SBorislav Petkov } 47321afaf18SBorislav Petkov 47421afaf18SBorislav Petkov static void mce_irq_work_cb(struct irq_work *entry) 47521afaf18SBorislav Petkov { 47621afaf18SBorislav Petkov mce_schedule_work(); 47721afaf18SBorislav Petkov } 47821afaf18SBorislav Petkov 47921afaf18SBorislav Petkov /* 48021afaf18SBorislav Petkov * Check if the address reported by the CPU is in a format we can parse. 48121afaf18SBorislav Petkov * It would be possible to add code for most other cases, but all would 48221afaf18SBorislav Petkov * be somewhat complicated (e.g. segment offset would require an instruction 483d9f6e12fSIngo Molnar * parser). So only support physical addresses up to page granularity for now. 48421afaf18SBorislav Petkov */ 48521afaf18SBorislav Petkov int mce_usable_address(struct mce *m) 48621afaf18SBorislav Petkov { 48721afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_ADDRV)) 48821afaf18SBorislav Petkov return 0; 48921afaf18SBorislav Petkov 4906e898d2bSTony W Wang-oc /* Checks after this one are Intel/Zhaoxin-specific: */ 4916e898d2bSTony W Wang-oc if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && 4926e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) 49321afaf18SBorislav Petkov return 1; 49421afaf18SBorislav Petkov 49521afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_MISCV)) 49621afaf18SBorislav Petkov return 0; 49721afaf18SBorislav Petkov 49821afaf18SBorislav Petkov if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) 49921afaf18SBorislav Petkov return 0; 50021afaf18SBorislav Petkov 50121afaf18SBorislav Petkov if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) 50221afaf18SBorislav Petkov return 0; 50321afaf18SBorislav Petkov 50421afaf18SBorislav Petkov return 1; 50521afaf18SBorislav Petkov } 50621afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_usable_address); 50721afaf18SBorislav Petkov 50821afaf18SBorislav Petkov bool mce_is_memory_error(struct mce *m) 50921afaf18SBorislav Petkov { 5106e898d2bSTony W Wang-oc switch (m->cpuvendor) { 5116e898d2bSTony W Wang-oc case X86_VENDOR_AMD: 5126e898d2bSTony W Wang-oc case X86_VENDOR_HYGON: 51321afaf18SBorislav Petkov return amd_mce_is_memory_error(m); 5146e898d2bSTony W Wang-oc 5156e898d2bSTony W Wang-oc case X86_VENDOR_INTEL: 5166e898d2bSTony W Wang-oc case X86_VENDOR_ZHAOXIN: 51721afaf18SBorislav Petkov /* 51821afaf18SBorislav Petkov * Intel SDM Volume 3B - 15.9.2 Compound Error Codes 51921afaf18SBorislav Petkov * 52021afaf18SBorislav Petkov * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for 52121afaf18SBorislav Petkov * indicating a memory error. Bit 8 is used for indicating a 52221afaf18SBorislav Petkov * cache hierarchy error. The combination of bit 2 and bit 3 52321afaf18SBorislav Petkov * is used for indicating a `generic' cache hierarchy error 52421afaf18SBorislav Petkov * But we can't just blindly check the above bits, because if 52521afaf18SBorislav Petkov * bit 11 is set, then it is a bus/interconnect error - and 52621afaf18SBorislav Petkov * either way the above bits just gives more detail on what 52721afaf18SBorislav Petkov * bus/interconnect error happened. Note that bit 12 can be 52821afaf18SBorislav Petkov * ignored, as it's the "filter" bit. 52921afaf18SBorislav Petkov */ 53021afaf18SBorislav Petkov return (m->status & 0xef80) == BIT(7) || 53121afaf18SBorislav Petkov (m->status & 0xef00) == BIT(8) || 53221afaf18SBorislav Petkov (m->status & 0xeffc) == 0xc; 53321afaf18SBorislav Petkov 5346e898d2bSTony W Wang-oc default: 53521afaf18SBorislav Petkov return false; 53621afaf18SBorislav Petkov } 5376e898d2bSTony W Wang-oc } 53821afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_memory_error); 53921afaf18SBorislav Petkov 54017fae129STony Luck static bool whole_page(struct mce *m) 54117fae129STony Luck { 54217fae129STony Luck if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV)) 54317fae129STony Luck return true; 54417fae129STony Luck 54517fae129STony Luck return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT; 54617fae129STony Luck } 54717fae129STony Luck 54821afaf18SBorislav Petkov bool mce_is_correctable(struct mce *m) 54921afaf18SBorislav Petkov { 55021afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED) 55121afaf18SBorislav Petkov return false; 55221afaf18SBorislav Petkov 55321afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED) 55421afaf18SBorislav Petkov return false; 55521afaf18SBorislav Petkov 55621afaf18SBorislav Petkov if (m->status & MCI_STATUS_UC) 55721afaf18SBorislav Petkov return false; 55821afaf18SBorislav Petkov 55921afaf18SBorislav Petkov return true; 56021afaf18SBorislav Petkov } 56121afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_correctable); 56221afaf18SBorislav Petkov 563c9c6d216STony Luck static int mce_early_notifier(struct notifier_block *nb, unsigned long val, 56421afaf18SBorislav Petkov void *data) 56521afaf18SBorislav Petkov { 56621afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 56721afaf18SBorislav Petkov 56821afaf18SBorislav Petkov if (!m) 56921afaf18SBorislav Petkov return NOTIFY_DONE; 57021afaf18SBorislav Petkov 57121afaf18SBorislav Petkov /* Emit the trace record: */ 57221afaf18SBorislav Petkov trace_mce_record(m); 57321afaf18SBorislav Petkov 57421afaf18SBorislav Petkov set_bit(0, &mce_need_notify); 57521afaf18SBorislav Petkov 57621afaf18SBorislav Petkov mce_notify_irq(); 57721afaf18SBorislav Petkov 57821afaf18SBorislav Petkov return NOTIFY_DONE; 57921afaf18SBorislav Petkov } 58021afaf18SBorislav Petkov 581c9c6d216STony Luck static struct notifier_block early_nb = { 582c9c6d216STony Luck .notifier_call = mce_early_notifier, 583c9c6d216STony Luck .priority = MCE_PRIO_EARLY, 58421afaf18SBorislav Petkov }; 58521afaf18SBorislav Petkov 5868438b84aSJan H. Schönherr static int uc_decode_notifier(struct notifier_block *nb, unsigned long val, 58721afaf18SBorislav Petkov void *data) 58821afaf18SBorislav Petkov { 58921afaf18SBorislav Petkov struct mce *mce = (struct mce *)data; 59021afaf18SBorislav Petkov unsigned long pfn; 59121afaf18SBorislav Petkov 5928438b84aSJan H. Schönherr if (!mce || !mce_usable_address(mce)) 59321afaf18SBorislav Petkov return NOTIFY_DONE; 59421afaf18SBorislav Petkov 5958438b84aSJan H. Schönherr if (mce->severity != MCE_AO_SEVERITY && 5968438b84aSJan H. Schönherr mce->severity != MCE_DEFERRED_SEVERITY) 5978438b84aSJan H. Schönherr return NOTIFY_DONE; 5988438b84aSJan H. Schönherr 59921afaf18SBorislav Petkov pfn = mce->addr >> PAGE_SHIFT; 60023ba710aSTony Luck if (!memory_failure(pfn, 0)) { 60117fae129STony Luck set_mce_nospec(pfn, whole_page(mce)); 60223ba710aSTony Luck mce->kflags |= MCE_HANDLED_UC; 60323ba710aSTony Luck } 60421afaf18SBorislav Petkov 60521afaf18SBorislav Petkov return NOTIFY_OK; 60621afaf18SBorislav Petkov } 6078438b84aSJan H. Schönherr 6088438b84aSJan H. Schönherr static struct notifier_block mce_uc_nb = { 6098438b84aSJan H. Schönherr .notifier_call = uc_decode_notifier, 6108438b84aSJan H. Schönherr .priority = MCE_PRIO_UC, 61121afaf18SBorislav Petkov }; 61221afaf18SBorislav Petkov 61321afaf18SBorislav Petkov static int mce_default_notifier(struct notifier_block *nb, unsigned long val, 61421afaf18SBorislav Petkov void *data) 61521afaf18SBorislav Petkov { 61621afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 61721afaf18SBorislav Petkov 61821afaf18SBorislav Petkov if (!m) 61921afaf18SBorislav Petkov return NOTIFY_DONE; 62021afaf18SBorislav Petkov 62143505646STony Luck if (mca_cfg.print_all || !m->kflags) 62221afaf18SBorislav Petkov __print_mce(m); 62321afaf18SBorislav Petkov 62421afaf18SBorislav Petkov return NOTIFY_DONE; 62521afaf18SBorislav Petkov } 62621afaf18SBorislav Petkov 62721afaf18SBorislav Petkov static struct notifier_block mce_default_nb = { 62821afaf18SBorislav Petkov .notifier_call = mce_default_notifier, 62921afaf18SBorislav Petkov /* lowest prio, we want it to run last. */ 63021afaf18SBorislav Petkov .priority = MCE_PRIO_LOWEST, 63121afaf18SBorislav Petkov }; 63221afaf18SBorislav Petkov 63321afaf18SBorislav Petkov /* 63421afaf18SBorislav Petkov * Read ADDR and MISC registers. 63521afaf18SBorislav Petkov */ 63621afaf18SBorislav Petkov static void mce_read_aux(struct mce *m, int i) 63721afaf18SBorislav Petkov { 63821afaf18SBorislav Petkov if (m->status & MCI_STATUS_MISCV) 6398121b8f9SBorislav Petkov m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC)); 64021afaf18SBorislav Petkov 64121afaf18SBorislav Petkov if (m->status & MCI_STATUS_ADDRV) { 6428121b8f9SBorislav Petkov m->addr = mce_rdmsrl(mca_msr_reg(i, MCA_ADDR)); 64321afaf18SBorislav Petkov 64421afaf18SBorislav Petkov /* 64521afaf18SBorislav Petkov * Mask the reported address by the reported granularity. 64621afaf18SBorislav Petkov */ 64721afaf18SBorislav Petkov if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { 64821afaf18SBorislav Petkov u8 shift = MCI_MISC_ADDR_LSB(m->misc); 64921afaf18SBorislav Petkov m->addr >>= shift; 65021afaf18SBorislav Petkov m->addr <<= shift; 65121afaf18SBorislav Petkov } 65221afaf18SBorislav Petkov 65321afaf18SBorislav Petkov /* 65421afaf18SBorislav Petkov * Extract [55:<lsb>] where lsb is the least significant 65521afaf18SBorislav Petkov * *valid* bit of the address bits. 65621afaf18SBorislav Petkov */ 65721afaf18SBorislav Petkov if (mce_flags.smca) { 65821afaf18SBorislav Petkov u8 lsb = (m->addr >> 56) & 0x3f; 65921afaf18SBorislav Petkov 66021afaf18SBorislav Petkov m->addr &= GENMASK_ULL(55, lsb); 66121afaf18SBorislav Petkov } 66221afaf18SBorislav Petkov } 66321afaf18SBorislav Petkov 66421afaf18SBorislav Petkov if (mce_flags.smca) { 66521afaf18SBorislav Petkov m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); 66621afaf18SBorislav Petkov 66721afaf18SBorislav Petkov if (m->status & MCI_STATUS_SYNDV) 66821afaf18SBorislav Petkov m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); 66921afaf18SBorislav Petkov } 67021afaf18SBorislav Petkov } 67121afaf18SBorislav Petkov 67221afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_poll_count); 67321afaf18SBorislav Petkov 67421afaf18SBorislav Petkov /* 67521afaf18SBorislav Petkov * Poll for corrected events or events that happened before reset. 67621afaf18SBorislav Petkov * Those are just logged through /dev/mcelog. 67721afaf18SBorislav Petkov * 67821afaf18SBorislav Petkov * This is executed in standard interrupt context. 67921afaf18SBorislav Petkov * 68021afaf18SBorislav Petkov * Note: spec recommends to panic for fatal unsignalled 68121afaf18SBorislav Petkov * errors here. However this would be quite problematic -- 68221afaf18SBorislav Petkov * we would need to reimplement the Monarch handling and 68321afaf18SBorislav Petkov * it would mess up the exclusion between exception handler 684312a4661SLinus Torvalds * and poll handler -- * so we skip this for now. 68521afaf18SBorislav Petkov * These cases should not happen anyways, or only when the CPU 68621afaf18SBorislav Petkov * is already totally * confused. In this case it's likely it will 68721afaf18SBorislav Petkov * not fully execute the machine check handler either. 68821afaf18SBorislav Petkov */ 68921afaf18SBorislav Petkov bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) 69021afaf18SBorislav Petkov { 691b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 69221afaf18SBorislav Petkov bool error_seen = false; 69321afaf18SBorislav Petkov struct mce m; 69421afaf18SBorislav Petkov int i; 69521afaf18SBorislav Petkov 69621afaf18SBorislav Petkov this_cpu_inc(mce_poll_count); 69721afaf18SBorislav Petkov 69821afaf18SBorislav Petkov mce_gather_info(&m, NULL); 69921afaf18SBorislav Petkov 70021afaf18SBorislav Petkov if (flags & MCP_TIMESTAMP) 70121afaf18SBorislav Petkov m.tsc = rdtsc(); 70221afaf18SBorislav Petkov 703c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 70421afaf18SBorislav Petkov if (!mce_banks[i].ctl || !test_bit(i, *b)) 70521afaf18SBorislav Petkov continue; 70621afaf18SBorislav Petkov 70721afaf18SBorislav Petkov m.misc = 0; 70821afaf18SBorislav Petkov m.addr = 0; 70921afaf18SBorislav Petkov m.bank = i; 71021afaf18SBorislav Petkov 71121afaf18SBorislav Petkov barrier(); 7128121b8f9SBorislav Petkov m.status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 713f19501aaSTony Luck 714f19501aaSTony Luck /* If this entry is not valid, ignore it */ 71521afaf18SBorislav Petkov if (!(m.status & MCI_STATUS_VAL)) 71621afaf18SBorislav Petkov continue; 71721afaf18SBorislav Petkov 71821afaf18SBorislav Petkov /* 719f19501aaSTony Luck * If we are logging everything (at CPU online) or this 720f19501aaSTony Luck * is a corrected error, then we must log it. 72121afaf18SBorislav Petkov */ 722f19501aaSTony Luck if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC)) 723f19501aaSTony Luck goto log_it; 724f19501aaSTony Luck 725f19501aaSTony Luck /* 726f19501aaSTony Luck * Newer Intel systems that support software error 727f19501aaSTony Luck * recovery need to make additional checks. Other 728f19501aaSTony Luck * CPUs should skip over uncorrected errors, but log 729f19501aaSTony Luck * everything else. 730f19501aaSTony Luck */ 731f19501aaSTony Luck if (!mca_cfg.ser) { 732f19501aaSTony Luck if (m.status & MCI_STATUS_UC) 733f19501aaSTony Luck continue; 734f19501aaSTony Luck goto log_it; 735f19501aaSTony Luck } 736f19501aaSTony Luck 737f19501aaSTony Luck /* Log "not enabled" (speculative) errors */ 738f19501aaSTony Luck if (!(m.status & MCI_STATUS_EN)) 739f19501aaSTony Luck goto log_it; 740f19501aaSTony Luck 741f19501aaSTony Luck /* 742f19501aaSTony Luck * Log UCNA (SDM: 15.6.3 "UCR Error Classification") 743f19501aaSTony Luck * UC == 1 && PCC == 0 && S == 0 744f19501aaSTony Luck */ 745f19501aaSTony Luck if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S)) 746f19501aaSTony Luck goto log_it; 747f19501aaSTony Luck 748f19501aaSTony Luck /* 749f19501aaSTony Luck * Skip anything else. Presumption is that our read of this 750f19501aaSTony Luck * bank is racing with a machine check. Leave the log alone 751f19501aaSTony Luck * for do_machine_check() to deal with it. 752f19501aaSTony Luck */ 75321afaf18SBorislav Petkov continue; 75421afaf18SBorislav Petkov 755f19501aaSTony Luck log_it: 75621afaf18SBorislav Petkov error_seen = true; 75721afaf18SBorislav Petkov 75890454e49SJan H. Schönherr if (flags & MCP_DONTLOG) 75990454e49SJan H. Schönherr goto clear_it; 76090454e49SJan H. Schönherr 76121afaf18SBorislav Petkov mce_read_aux(&m, i); 76241ce0564SYouquan Song m.severity = mce_severity(&m, NULL, mca_cfg.tolerant, NULL, false); 76321afaf18SBorislav Petkov /* 76421afaf18SBorislav Petkov * Don't get the IP here because it's unlikely to 76521afaf18SBorislav Petkov * have anything to do with the actual error location. 76621afaf18SBorislav Petkov */ 76721afaf18SBorislav Petkov 76890454e49SJan H. Schönherr if (mca_cfg.dont_log_ce && !mce_usable_address(&m)) 76990454e49SJan H. Schönherr goto clear_it; 77090454e49SJan H. Schönherr 7713bff147bSBorislav Petkov if (flags & MCP_QUEUE_LOG) 7723bff147bSBorislav Petkov mce_gen_pool_add(&m); 7733bff147bSBorislav Petkov else 77490454e49SJan H. Schönherr mce_log(&m); 77590454e49SJan H. Schönherr 77690454e49SJan H. Schönherr clear_it: 77721afaf18SBorislav Petkov /* 77821afaf18SBorislav Petkov * Clear state for this bank. 77921afaf18SBorislav Petkov */ 7808121b8f9SBorislav Petkov mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 78121afaf18SBorislav Petkov } 78221afaf18SBorislav Petkov 78321afaf18SBorislav Petkov /* 78421afaf18SBorislav Petkov * Don't clear MCG_STATUS here because it's only defined for 78521afaf18SBorislav Petkov * exceptions. 78621afaf18SBorislav Petkov */ 78721afaf18SBorislav Petkov 78821afaf18SBorislav Petkov sync_core(); 78921afaf18SBorislav Petkov 79021afaf18SBorislav Petkov return error_seen; 79121afaf18SBorislav Petkov } 79221afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(machine_check_poll); 79321afaf18SBorislav Petkov 79421afaf18SBorislav Petkov /* 795cc466666SBorislav Petkov * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and 796cc466666SBorislav Petkov * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM 797cc466666SBorislav Petkov * Vol 3B Table 15-20). But this confuses both the code that determines 798cc466666SBorislav Petkov * whether the machine check occurred in kernel or user mode, and also 799cc466666SBorislav Petkov * the severity assessment code. Pretend that EIPV was set, and take the 800cc466666SBorislav Petkov * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. 801cc466666SBorislav Petkov */ 802cc466666SBorislav Petkov static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) 803cc466666SBorislav Petkov { 804cc466666SBorislav Petkov if (bank != 0) 805cc466666SBorislav Petkov return; 806cc466666SBorislav Petkov if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) 807cc466666SBorislav Petkov return; 808cc466666SBorislav Petkov if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| 809cc466666SBorislav Petkov MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| 810cc466666SBorislav Petkov MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| 811cc466666SBorislav Petkov MCACOD)) != 812cc466666SBorislav Petkov (MCI_STATUS_UC|MCI_STATUS_EN| 813cc466666SBorislav Petkov MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| 814cc466666SBorislav Petkov MCI_STATUS_AR|MCACOD_INSTR)) 815cc466666SBorislav Petkov return; 816cc466666SBorislav Petkov 817cc466666SBorislav Petkov m->mcgstatus |= MCG_STATUS_EIPV; 818cc466666SBorislav Petkov m->ip = regs->ip; 819cc466666SBorislav Petkov m->cs = regs->cs; 820cc466666SBorislav Petkov } 821cc466666SBorislav Petkov 822cc466666SBorislav Petkov /* 82321afaf18SBorislav Petkov * Do a quick check if any of the events requires a panic. 82421afaf18SBorislav Petkov * This decides if we keep the events around or clear them. 82521afaf18SBorislav Petkov */ 82621afaf18SBorislav Petkov static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, 82721afaf18SBorislav Petkov struct pt_regs *regs) 82821afaf18SBorislav Petkov { 8297a8bc2b0SJan H. Schönherr char *tmp = *msg; 83021afaf18SBorislav Petkov int i; 83121afaf18SBorislav Petkov 832c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 8338121b8f9SBorislav Petkov m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 83421afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 83521afaf18SBorislav Petkov continue; 83621afaf18SBorislav Petkov 83721afaf18SBorislav Petkov __set_bit(i, validp); 838cc466666SBorislav Petkov if (mce_flags.snb_ifu_quirk) 839cc466666SBorislav Petkov quirk_sandybridge_ifu(i, m, regs); 84021afaf18SBorislav Petkov 841d28af26fSTony Luck m->bank = i; 84241ce0564SYouquan Song if (mce_severity(m, regs, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) { 84321afaf18SBorislav Petkov mce_read_aux(m, i); 84421afaf18SBorislav Petkov *msg = tmp; 84521afaf18SBorislav Petkov return 1; 84621afaf18SBorislav Petkov } 84721afaf18SBorislav Petkov } 84821afaf18SBorislav Petkov return 0; 84921afaf18SBorislav Petkov } 85021afaf18SBorislav Petkov 85121afaf18SBorislav Petkov /* 85221afaf18SBorislav Petkov * Variable to establish order between CPUs while scanning. 85321afaf18SBorislav Petkov * Each CPU spins initially until executing is equal its number. 85421afaf18SBorislav Petkov */ 85521afaf18SBorislav Petkov static atomic_t mce_executing; 85621afaf18SBorislav Petkov 85721afaf18SBorislav Petkov /* 85821afaf18SBorislav Petkov * Defines order of CPUs on entry. First CPU becomes Monarch. 85921afaf18SBorislav Petkov */ 86021afaf18SBorislav Petkov static atomic_t mce_callin; 86121afaf18SBorislav Petkov 86221afaf18SBorislav Petkov /* 8637bb39313SPaul E. McKenney * Track which CPUs entered the MCA broadcast synchronization and which not in 8647bb39313SPaul E. McKenney * order to print holdouts. 8657bb39313SPaul E. McKenney */ 8667bb39313SPaul E. McKenney static cpumask_t mce_missing_cpus = CPU_MASK_ALL; 8677bb39313SPaul E. McKenney 8687bb39313SPaul E. McKenney /* 86921afaf18SBorislav Petkov * Check if a timeout waiting for other CPUs happened. 87021afaf18SBorislav Petkov */ 87121afaf18SBorislav Petkov static int mce_timed_out(u64 *t, const char *msg) 87221afaf18SBorislav Petkov { 87321afaf18SBorislav Petkov /* 87421afaf18SBorislav Petkov * The others already did panic for some reason. 87521afaf18SBorislav Petkov * Bail out like in a timeout. 87621afaf18SBorislav Petkov * rmb() to tell the compiler that system_state 87721afaf18SBorislav Petkov * might have been modified by someone else. 87821afaf18SBorislav Petkov */ 87921afaf18SBorislav Petkov rmb(); 88021afaf18SBorislav Petkov if (atomic_read(&mce_panicked)) 88121afaf18SBorislav Petkov wait_for_panic(); 88221afaf18SBorislav Petkov if (!mca_cfg.monarch_timeout) 88321afaf18SBorislav Petkov goto out; 88421afaf18SBorislav Petkov if ((s64)*t < SPINUNIT) { 8857bb39313SPaul E. McKenney if (mca_cfg.tolerant <= 1) { 8867bb39313SPaul E. McKenney if (cpumask_and(&mce_missing_cpus, cpu_online_mask, &mce_missing_cpus)) 8877bb39313SPaul E. McKenney pr_emerg("CPUs not responding to MCE broadcast (may include false positives): %*pbl\n", 8887bb39313SPaul E. McKenney cpumask_pr_args(&mce_missing_cpus)); 88921afaf18SBorislav Petkov mce_panic(msg, NULL, NULL); 8907bb39313SPaul E. McKenney } 89121afaf18SBorislav Petkov return 1; 89221afaf18SBorislav Petkov } 89321afaf18SBorislav Petkov *t -= SPINUNIT; 89421afaf18SBorislav Petkov out: 89521afaf18SBorislav Petkov touch_nmi_watchdog(); 89621afaf18SBorislav Petkov return 0; 89721afaf18SBorislav Petkov } 89821afaf18SBorislav Petkov 89921afaf18SBorislav Petkov /* 90021afaf18SBorislav Petkov * The Monarch's reign. The Monarch is the CPU who entered 90121afaf18SBorislav Petkov * the machine check handler first. It waits for the others to 90221afaf18SBorislav Petkov * raise the exception too and then grades them. When any 90321afaf18SBorislav Petkov * error is fatal panic. Only then let the others continue. 90421afaf18SBorislav Petkov * 90521afaf18SBorislav Petkov * The other CPUs entering the MCE handler will be controlled by the 90621afaf18SBorislav Petkov * Monarch. They are called Subjects. 90721afaf18SBorislav Petkov * 90821afaf18SBorislav Petkov * This way we prevent any potential data corruption in a unrecoverable case 90921afaf18SBorislav Petkov * and also makes sure always all CPU's errors are examined. 91021afaf18SBorislav Petkov * 91121afaf18SBorislav Petkov * Also this detects the case of a machine check event coming from outer 91221afaf18SBorislav Petkov * space (not detected by any CPUs) In this case some external agent wants 91321afaf18SBorislav Petkov * us to shut down, so panic too. 91421afaf18SBorislav Petkov * 91521afaf18SBorislav Petkov * The other CPUs might still decide to panic if the handler happens 91621afaf18SBorislav Petkov * in a unrecoverable place, but in this case the system is in a semi-stable 91721afaf18SBorislav Petkov * state and won't corrupt anything by itself. It's ok to let the others 91821afaf18SBorislav Petkov * continue for a bit first. 91921afaf18SBorislav Petkov * 92021afaf18SBorislav Petkov * All the spin loops have timeouts; when a timeout happens a CPU 92121afaf18SBorislav Petkov * typically elects itself to be Monarch. 92221afaf18SBorislav Petkov */ 92321afaf18SBorislav Petkov static void mce_reign(void) 92421afaf18SBorislav Petkov { 92521afaf18SBorislav Petkov int cpu; 92621afaf18SBorislav Petkov struct mce *m = NULL; 92721afaf18SBorislav Petkov int global_worst = 0; 92821afaf18SBorislav Petkov char *msg = NULL; 92921afaf18SBorislav Petkov 93021afaf18SBorislav Petkov /* 93121afaf18SBorislav Petkov * This CPU is the Monarch and the other CPUs have run 93221afaf18SBorislav Petkov * through their handlers. 93321afaf18SBorislav Petkov * Grade the severity of the errors of all the CPUs. 93421afaf18SBorislav Petkov */ 93521afaf18SBorislav Petkov for_each_possible_cpu(cpu) { 93613c877f4STony Luck struct mce *mtmp = &per_cpu(mces_seen, cpu); 93713c877f4STony Luck 93813c877f4STony Luck if (mtmp->severity > global_worst) { 93913c877f4STony Luck global_worst = mtmp->severity; 94021afaf18SBorislav Petkov m = &per_cpu(mces_seen, cpu); 94121afaf18SBorislav Petkov } 94221afaf18SBorislav Petkov } 94321afaf18SBorislav Petkov 94421afaf18SBorislav Petkov /* 94521afaf18SBorislav Petkov * Cannot recover? Panic here then. 94621afaf18SBorislav Petkov * This dumps all the mces in the log buffer and stops the 94721afaf18SBorislav Petkov * other CPUs. 94821afaf18SBorislav Petkov */ 94913c877f4STony Luck if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) { 95013c877f4STony Luck /* call mce_severity() to get "msg" for panic */ 95141ce0564SYouquan Song mce_severity(m, NULL, mca_cfg.tolerant, &msg, true); 95221afaf18SBorislav Petkov mce_panic("Fatal machine check", m, msg); 95313c877f4STony Luck } 95421afaf18SBorislav Petkov 95521afaf18SBorislav Petkov /* 95621afaf18SBorislav Petkov * For UC somewhere we let the CPU who detects it handle it. 95721afaf18SBorislav Petkov * Also must let continue the others, otherwise the handling 95821afaf18SBorislav Petkov * CPU could deadlock on a lock. 95921afaf18SBorislav Petkov */ 96021afaf18SBorislav Petkov 96121afaf18SBorislav Petkov /* 96221afaf18SBorislav Petkov * No machine check event found. Must be some external 96321afaf18SBorislav Petkov * source or one CPU is hung. Panic. 96421afaf18SBorislav Petkov */ 96521afaf18SBorislav Petkov if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) 96621afaf18SBorislav Petkov mce_panic("Fatal machine check from unknown source", NULL, NULL); 96721afaf18SBorislav Petkov 96821afaf18SBorislav Petkov /* 96921afaf18SBorislav Petkov * Now clear all the mces_seen so that they don't reappear on 97021afaf18SBorislav Petkov * the next mce. 97121afaf18SBorislav Petkov */ 97221afaf18SBorislav Petkov for_each_possible_cpu(cpu) 97321afaf18SBorislav Petkov memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); 97421afaf18SBorislav Petkov } 97521afaf18SBorislav Petkov 97621afaf18SBorislav Petkov static atomic_t global_nwo; 97721afaf18SBorislav Petkov 97821afaf18SBorislav Petkov /* 97921afaf18SBorislav Petkov * Start of Monarch synchronization. This waits until all CPUs have 98021afaf18SBorislav Petkov * entered the exception handler and then determines if any of them 98121afaf18SBorislav Petkov * saw a fatal event that requires panic. Then it executes them 98221afaf18SBorislav Petkov * in the entry order. 98321afaf18SBorislav Petkov * TBD double check parallel CPU hotunplug 98421afaf18SBorislav Petkov */ 98521afaf18SBorislav Petkov static int mce_start(int *no_way_out) 98621afaf18SBorislav Petkov { 98721afaf18SBorislav Petkov int order; 98821afaf18SBorislav Petkov int cpus = num_online_cpus(); 98921afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 99021afaf18SBorislav Petkov 99121afaf18SBorislav Petkov if (!timeout) 99221afaf18SBorislav Petkov return -1; 99321afaf18SBorislav Petkov 99421afaf18SBorislav Petkov atomic_add(*no_way_out, &global_nwo); 99521afaf18SBorislav Petkov /* 99621afaf18SBorislav Petkov * Rely on the implied barrier below, such that global_nwo 99721afaf18SBorislav Petkov * is updated before mce_callin. 99821afaf18SBorislav Petkov */ 99921afaf18SBorislav Petkov order = atomic_inc_return(&mce_callin); 10007bb39313SPaul E. McKenney cpumask_clear_cpu(smp_processor_id(), &mce_missing_cpus); 100121afaf18SBorislav Petkov 100221afaf18SBorislav Petkov /* 100321afaf18SBorislav Petkov * Wait for everyone. 100421afaf18SBorislav Petkov */ 100521afaf18SBorislav Petkov while (atomic_read(&mce_callin) != cpus) { 100621afaf18SBorislav Petkov if (mce_timed_out(&timeout, 100721afaf18SBorislav Petkov "Timeout: Not all CPUs entered broadcast exception handler")) { 100821afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 100921afaf18SBorislav Petkov return -1; 101021afaf18SBorislav Petkov } 101121afaf18SBorislav Petkov ndelay(SPINUNIT); 101221afaf18SBorislav Petkov } 101321afaf18SBorislav Petkov 101421afaf18SBorislav Petkov /* 101521afaf18SBorislav Petkov * mce_callin should be read before global_nwo 101621afaf18SBorislav Petkov */ 101721afaf18SBorislav Petkov smp_rmb(); 101821afaf18SBorislav Petkov 101921afaf18SBorislav Petkov if (order == 1) { 102021afaf18SBorislav Petkov /* 102121afaf18SBorislav Petkov * Monarch: Starts executing now, the others wait. 102221afaf18SBorislav Petkov */ 102321afaf18SBorislav Petkov atomic_set(&mce_executing, 1); 102421afaf18SBorislav Petkov } else { 102521afaf18SBorislav Petkov /* 102621afaf18SBorislav Petkov * Subject: Now start the scanning loop one by one in 102721afaf18SBorislav Petkov * the original callin order. 102821afaf18SBorislav Petkov * This way when there are any shared banks it will be 102921afaf18SBorislav Petkov * only seen by one CPU before cleared, avoiding duplicates. 103021afaf18SBorislav Petkov */ 103121afaf18SBorislav Petkov while (atomic_read(&mce_executing) < order) { 103221afaf18SBorislav Petkov if (mce_timed_out(&timeout, 103321afaf18SBorislav Petkov "Timeout: Subject CPUs unable to finish machine check processing")) { 103421afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 103521afaf18SBorislav Petkov return -1; 103621afaf18SBorislav Petkov } 103721afaf18SBorislav Petkov ndelay(SPINUNIT); 103821afaf18SBorislav Petkov } 103921afaf18SBorislav Petkov } 104021afaf18SBorislav Petkov 104121afaf18SBorislav Petkov /* 104221afaf18SBorislav Petkov * Cache the global no_way_out state. 104321afaf18SBorislav Petkov */ 104421afaf18SBorislav Petkov *no_way_out = atomic_read(&global_nwo); 104521afaf18SBorislav Petkov 104621afaf18SBorislav Petkov return order; 104721afaf18SBorislav Petkov } 104821afaf18SBorislav Petkov 104921afaf18SBorislav Petkov /* 105021afaf18SBorislav Petkov * Synchronize between CPUs after main scanning loop. 105121afaf18SBorislav Petkov * This invokes the bulk of the Monarch processing. 105221afaf18SBorislav Petkov */ 105321afaf18SBorislav Petkov static int mce_end(int order) 105421afaf18SBorislav Petkov { 105521afaf18SBorislav Petkov int ret = -1; 105621afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 105721afaf18SBorislav Petkov 105821afaf18SBorislav Petkov if (!timeout) 105921afaf18SBorislav Petkov goto reset; 106021afaf18SBorislav Petkov if (order < 0) 106121afaf18SBorislav Petkov goto reset; 106221afaf18SBorislav Petkov 106321afaf18SBorislav Petkov /* 106421afaf18SBorislav Petkov * Allow others to run. 106521afaf18SBorislav Petkov */ 106621afaf18SBorislav Petkov atomic_inc(&mce_executing); 106721afaf18SBorislav Petkov 106821afaf18SBorislav Petkov if (order == 1) { 106921afaf18SBorislav Petkov /* CHECKME: Can this race with a parallel hotplug? */ 107021afaf18SBorislav Petkov int cpus = num_online_cpus(); 107121afaf18SBorislav Petkov 107221afaf18SBorislav Petkov /* 107321afaf18SBorislav Petkov * Monarch: Wait for everyone to go through their scanning 107421afaf18SBorislav Petkov * loops. 107521afaf18SBorislav Petkov */ 107621afaf18SBorislav Petkov while (atomic_read(&mce_executing) <= cpus) { 107721afaf18SBorislav Petkov if (mce_timed_out(&timeout, 107821afaf18SBorislav Petkov "Timeout: Monarch CPU unable to finish machine check processing")) 107921afaf18SBorislav Petkov goto reset; 108021afaf18SBorislav Petkov ndelay(SPINUNIT); 108121afaf18SBorislav Petkov } 108221afaf18SBorislav Petkov 108321afaf18SBorislav Petkov mce_reign(); 108421afaf18SBorislav Petkov barrier(); 108521afaf18SBorislav Petkov ret = 0; 108621afaf18SBorislav Petkov } else { 108721afaf18SBorislav Petkov /* 108821afaf18SBorislav Petkov * Subject: Wait for Monarch to finish. 108921afaf18SBorislav Petkov */ 109021afaf18SBorislav Petkov while (atomic_read(&mce_executing) != 0) { 109121afaf18SBorislav Petkov if (mce_timed_out(&timeout, 109221afaf18SBorislav Petkov "Timeout: Monarch CPU did not finish machine check processing")) 109321afaf18SBorislav Petkov goto reset; 109421afaf18SBorislav Petkov ndelay(SPINUNIT); 109521afaf18SBorislav Petkov } 109621afaf18SBorislav Petkov 109721afaf18SBorislav Petkov /* 109821afaf18SBorislav Petkov * Don't reset anything. That's done by the Monarch. 109921afaf18SBorislav Petkov */ 110021afaf18SBorislav Petkov return 0; 110121afaf18SBorislav Petkov } 110221afaf18SBorislav Petkov 110321afaf18SBorislav Petkov /* 110421afaf18SBorislav Petkov * Reset all global state. 110521afaf18SBorislav Petkov */ 110621afaf18SBorislav Petkov reset: 110721afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 110821afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 11097bb39313SPaul E. McKenney cpumask_setall(&mce_missing_cpus); 111021afaf18SBorislav Petkov barrier(); 111121afaf18SBorislav Petkov 111221afaf18SBorislav Petkov /* 111321afaf18SBorislav Petkov * Let others run again. 111421afaf18SBorislav Petkov */ 111521afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 111621afaf18SBorislav Petkov return ret; 111721afaf18SBorislav Petkov } 111821afaf18SBorislav Petkov 111921afaf18SBorislav Petkov static void mce_clear_state(unsigned long *toclear) 112021afaf18SBorislav Petkov { 112121afaf18SBorislav Petkov int i; 112221afaf18SBorislav Petkov 1123c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 112421afaf18SBorislav Petkov if (test_bit(i, toclear)) 11258121b8f9SBorislav Petkov mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 112621afaf18SBorislav Petkov } 112721afaf18SBorislav Petkov } 112821afaf18SBorislav Petkov 112921afaf18SBorislav Petkov /* 113021afaf18SBorislav Petkov * Cases where we avoid rendezvous handler timeout: 113121afaf18SBorislav Petkov * 1) If this CPU is offline. 113221afaf18SBorislav Petkov * 113321afaf18SBorislav Petkov * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to 113421afaf18SBorislav Petkov * skip those CPUs which remain looping in the 1st kernel - see 113521afaf18SBorislav Petkov * crash_nmi_callback(). 113621afaf18SBorislav Petkov * 113721afaf18SBorislav Petkov * Note: there still is a small window between kexec-ing and the new, 113821afaf18SBorislav Petkov * kdump kernel establishing a new #MC handler where a broadcasted MCE 113921afaf18SBorislav Petkov * might not get handled properly. 114021afaf18SBorislav Petkov */ 114194a46d31SThomas Gleixner static noinstr bool mce_check_crashing_cpu(void) 114221afaf18SBorislav Petkov { 114394a46d31SThomas Gleixner unsigned int cpu = smp_processor_id(); 114494a46d31SThomas Gleixner 114514d3b376SPeter Zijlstra if (arch_cpu_is_offline(cpu) || 114621afaf18SBorislav Petkov (crashing_cpu != -1 && crashing_cpu != cpu)) { 114721afaf18SBorislav Petkov u64 mcgstatus; 114821afaf18SBorislav Petkov 1149aedbdeabSThomas Gleixner mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS); 115070f0c230STony W Wang-oc 115170f0c230STony W Wang-oc if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { 115270f0c230STony W Wang-oc if (mcgstatus & MCG_STATUS_LMCES) 115370f0c230STony W Wang-oc return false; 115470f0c230STony W Wang-oc } 115570f0c230STony W Wang-oc 115621afaf18SBorislav Petkov if (mcgstatus & MCG_STATUS_RIPV) { 1157aedbdeabSThomas Gleixner __wrmsr(MSR_IA32_MCG_STATUS, 0, 0); 115821afaf18SBorislav Petkov return true; 115921afaf18SBorislav Petkov } 116021afaf18SBorislav Petkov } 116121afaf18SBorislav Petkov return false; 116221afaf18SBorislav Petkov } 116321afaf18SBorislav Petkov 116441ce0564SYouquan Song static void __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final, 116521afaf18SBorislav Petkov unsigned long *toclear, unsigned long *valid_banks, 116621afaf18SBorislav Petkov int no_way_out, int *worst) 116721afaf18SBorislav Petkov { 1168b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 116921afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 117021afaf18SBorislav Petkov int severity, i; 117121afaf18SBorislav Petkov 1172c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 117321afaf18SBorislav Petkov __clear_bit(i, toclear); 117421afaf18SBorislav Petkov if (!test_bit(i, valid_banks)) 117521afaf18SBorislav Petkov continue; 117621afaf18SBorislav Petkov 117721afaf18SBorislav Petkov if (!mce_banks[i].ctl) 117821afaf18SBorislav Petkov continue; 117921afaf18SBorislav Petkov 118021afaf18SBorislav Petkov m->misc = 0; 118121afaf18SBorislav Petkov m->addr = 0; 118221afaf18SBorislav Petkov m->bank = i; 118321afaf18SBorislav Petkov 11848121b8f9SBorislav Petkov m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 118521afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 118621afaf18SBorislav Petkov continue; 118721afaf18SBorislav Petkov 118821afaf18SBorislav Petkov /* 118921afaf18SBorislav Petkov * Corrected or non-signaled errors are handled by 119021afaf18SBorislav Petkov * machine_check_poll(). Leave them alone, unless this panics. 119121afaf18SBorislav Petkov */ 119221afaf18SBorislav Petkov if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && 119321afaf18SBorislav Petkov !no_way_out) 119421afaf18SBorislav Petkov continue; 119521afaf18SBorislav Petkov 119621afaf18SBorislav Petkov /* Set taint even when machine check was not enabled. */ 119721afaf18SBorislav Petkov add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 119821afaf18SBorislav Petkov 119941ce0564SYouquan Song severity = mce_severity(m, regs, cfg->tolerant, NULL, true); 120021afaf18SBorislav Petkov 120121afaf18SBorislav Petkov /* 120221afaf18SBorislav Petkov * When machine check was for corrected/deferred handler don't 120321afaf18SBorislav Petkov * touch, unless we're panicking. 120421afaf18SBorislav Petkov */ 120521afaf18SBorislav Petkov if ((severity == MCE_KEEP_SEVERITY || 120621afaf18SBorislav Petkov severity == MCE_UCNA_SEVERITY) && !no_way_out) 120721afaf18SBorislav Petkov continue; 120821afaf18SBorislav Petkov 120921afaf18SBorislav Petkov __set_bit(i, toclear); 121021afaf18SBorislav Petkov 121121afaf18SBorislav Petkov /* Machine check event was not enabled. Clear, but ignore. */ 121221afaf18SBorislav Petkov if (severity == MCE_NO_SEVERITY) 121321afaf18SBorislav Petkov continue; 121421afaf18SBorislav Petkov 121521afaf18SBorislav Petkov mce_read_aux(m, i); 121621afaf18SBorislav Petkov 121721afaf18SBorislav Petkov /* assuming valid severity level != 0 */ 121821afaf18SBorislav Petkov m->severity = severity; 121921afaf18SBorislav Petkov 122021afaf18SBorislav Petkov mce_log(m); 122121afaf18SBorislav Petkov 122221afaf18SBorislav Petkov if (severity > *worst) { 122321afaf18SBorislav Petkov *final = *m; 122421afaf18SBorislav Petkov *worst = severity; 122521afaf18SBorislav Petkov } 122621afaf18SBorislav Petkov } 122721afaf18SBorislav Petkov 122821afaf18SBorislav Petkov /* mce_clear_state will clear *final, save locally for use later */ 122921afaf18SBorislav Petkov *m = *final; 123021afaf18SBorislav Petkov } 123121afaf18SBorislav Petkov 12325567d11cSPeter Zijlstra static void kill_me_now(struct callback_head *ch) 12335567d11cSPeter Zijlstra { 123481065b35STony Luck struct task_struct *p = container_of(ch, struct task_struct, mce_kill_me); 123581065b35STony Luck 123681065b35STony Luck p->mce_count = 0; 12375567d11cSPeter Zijlstra force_sig(SIGBUS); 12385567d11cSPeter Zijlstra } 12395567d11cSPeter Zijlstra 12405567d11cSPeter Zijlstra static void kill_me_maybe(struct callback_head *cb) 12415567d11cSPeter Zijlstra { 12425567d11cSPeter Zijlstra struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me); 12435567d11cSPeter Zijlstra int flags = MF_ACTION_REQUIRED; 1244a3f5d80eSNaoya Horiguchi int ret; 12455567d11cSPeter Zijlstra 124681065b35STony Luck p->mce_count = 0; 12475567d11cSPeter Zijlstra pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr); 124817fae129STony Luck 124917fae129STony Luck if (!p->mce_ripv) 12505567d11cSPeter Zijlstra flags |= MF_MUST_KILL; 12515567d11cSPeter Zijlstra 1252a3f5d80eSNaoya Horiguchi ret = memory_failure(p->mce_addr >> PAGE_SHIFT, flags); 1253a6e3cf70STony Luck if (!ret) { 125417fae129STony Luck set_mce_nospec(p->mce_addr >> PAGE_SHIFT, p->mce_whole_page); 12551e36d9c6STony Luck sync_core(); 12565567d11cSPeter Zijlstra return; 12575567d11cSPeter Zijlstra } 12585567d11cSPeter Zijlstra 1259a3f5d80eSNaoya Horiguchi /* 1260a3f5d80eSNaoya Horiguchi * -EHWPOISON from memory_failure() means that it already sent SIGBUS 1261a3f5d80eSNaoya Horiguchi * to the current process with the proper error info, so no need to 1262a3f5d80eSNaoya Horiguchi * send SIGBUS here again. 1263a3f5d80eSNaoya Horiguchi */ 1264a3f5d80eSNaoya Horiguchi if (ret == -EHWPOISON) 1265a3f5d80eSNaoya Horiguchi return; 1266a3f5d80eSNaoya Horiguchi 12675567d11cSPeter Zijlstra pr_err("Memory error not recovered"); 12685567d11cSPeter Zijlstra kill_me_now(cb); 12695567d11cSPeter Zijlstra } 1270a6e3cf70STony Luck 1271a6e3cf70STony Luck static void kill_me_never(struct callback_head *cb) 1272a6e3cf70STony Luck { 1273a6e3cf70STony Luck struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me); 1274a6e3cf70STony Luck 1275a6e3cf70STony Luck p->mce_count = 0; 1276a6e3cf70STony Luck pr_err("Kernel accessed poison in user space at %llx\n", p->mce_addr); 1277a6e3cf70STony Luck if (!memory_failure(p->mce_addr >> PAGE_SHIFT, 0)) 1278a6e3cf70STony Luck set_mce_nospec(p->mce_addr >> PAGE_SHIFT, p->mce_whole_page); 127930063810STony Luck } 12805567d11cSPeter Zijlstra 1281a6e3cf70STony Luck static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callback_head *)) 1282c0ab7ffcSTony Luck { 128381065b35STony Luck int count = ++current->mce_count; 128481065b35STony Luck 128581065b35STony Luck /* First call, save all the details */ 128681065b35STony Luck if (count == 1) { 1287c0ab7ffcSTony Luck current->mce_addr = m->addr; 1288c0ab7ffcSTony Luck current->mce_kflags = m->kflags; 1289c0ab7ffcSTony Luck current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV); 1290c0ab7ffcSTony Luck current->mce_whole_page = whole_page(m); 1291a6e3cf70STony Luck current->mce_kill_me.func = func; 129281065b35STony Luck } 129381065b35STony Luck 129481065b35STony Luck /* Ten is likely overkill. Don't expect more than two faults before task_work() */ 129581065b35STony Luck if (count > 10) 129681065b35STony Luck mce_panic("Too many consecutive machine checks while accessing user data", m, msg); 129781065b35STony Luck 129881065b35STony Luck /* Second or later call, make sure page address matches the one from first call */ 129981065b35STony Luck if (count > 1 && (current->mce_addr >> PAGE_SHIFT) != (m->addr >> PAGE_SHIFT)) 130081065b35STony Luck mce_panic("Consecutive machine checks to different user pages", m, msg); 130181065b35STony Luck 130281065b35STony Luck /* Do not call task_work_add() more than once */ 130381065b35STony Luck if (count > 1) 130481065b35STony Luck return; 1305c0ab7ffcSTony Luck 130691989c70SJens Axboe task_work_add(current, ¤t->mce_kill_me, TWA_RESUME); 1307c0ab7ffcSTony Luck } 130821afaf18SBorislav Petkov 1309cbe1de16SBorislav Petkov /* Handle unconfigured int18 (should never happen) */ 1310cbe1de16SBorislav Petkov static noinstr void unexpected_machine_check(struct pt_regs *regs) 1311cbe1de16SBorislav Petkov { 1312cbe1de16SBorislav Petkov instrumentation_begin(); 1313cbe1de16SBorislav Petkov pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", 1314cbe1de16SBorislav Petkov smp_processor_id()); 1315cbe1de16SBorislav Petkov instrumentation_end(); 1316cbe1de16SBorislav Petkov } 1317cbe1de16SBorislav Petkov 131821afaf18SBorislav Petkov /* 131921afaf18SBorislav Petkov * The actual machine check handler. This only handles real 132021afaf18SBorislav Petkov * exceptions when something got corrupted coming in through int 18. 132121afaf18SBorislav Petkov * 132221afaf18SBorislav Petkov * This is executed in NMI context not subject to normal locking rules. This 132321afaf18SBorislav Petkov * implies that most kernel services cannot be safely used. Don't even 132421afaf18SBorislav Petkov * think about putting a printk in there! 132521afaf18SBorislav Petkov * 132621afaf18SBorislav Petkov * On Intel systems this is entered on all CPUs in parallel through 132721afaf18SBorislav Petkov * MCE broadcast. However some CPUs might be broken beyond repair, 132821afaf18SBorislav Petkov * so be always careful when synchronizing with others. 132955ba18d6SAndy Lutomirski * 133055ba18d6SAndy Lutomirski * Tracing and kprobes are disabled: if we interrupted a kernel context 133155ba18d6SAndy Lutomirski * with IF=1, we need to minimize stack usage. There are also recursion 133255ba18d6SAndy Lutomirski * issues: if the machine check was due to a failure of the memory 133355ba18d6SAndy Lutomirski * backing the user stack, tracing that reads the user stack will cause 133455ba18d6SAndy Lutomirski * potentially infinite recursion. 133521afaf18SBorislav Petkov */ 13367f6fa101SIra Weiny noinstr void do_machine_check(struct pt_regs *regs) 133721afaf18SBorislav Petkov { 1338cbe1de16SBorislav Petkov int worst = 0, order, no_way_out, kill_current_task, lmce; 1339*cd5e0d1fSBorislav Petkov DECLARE_BITMAP(valid_banks, MAX_NR_BANKS) = { 0 }; 1340*cd5e0d1fSBorislav Petkov DECLARE_BITMAP(toclear, MAX_NR_BANKS) = { 0 }; 134121afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 134221afaf18SBorislav Petkov struct mce m, *final; 13437a8bc2b0SJan H. Schönherr char *msg = NULL; 1344cbe1de16SBorislav Petkov 1345cbe1de16SBorislav Petkov if (unlikely(mce_flags.p5)) 1346cbe1de16SBorislav Petkov return pentium_machine_check(regs); 1347cbe1de16SBorislav Petkov else if (unlikely(mce_flags.winchip)) 1348cbe1de16SBorislav Petkov return winchip_machine_check(regs); 1349cbe1de16SBorislav Petkov else if (unlikely(!mca_cfg.initialized)) 1350cbe1de16SBorislav Petkov return unexpected_machine_check(regs); 135121afaf18SBorislav Petkov 135221afaf18SBorislav Petkov /* 135321afaf18SBorislav Petkov * Establish sequential order between the CPUs entering the machine 135421afaf18SBorislav Petkov * check handler. 135521afaf18SBorislav Petkov */ 1356cbe1de16SBorislav Petkov order = -1; 135721afaf18SBorislav Petkov 135821afaf18SBorislav Petkov /* 135921afaf18SBorislav Petkov * If no_way_out gets set, there is no safe way to recover from this 136021afaf18SBorislav Petkov * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. 136121afaf18SBorislav Petkov */ 1362cbe1de16SBorislav Petkov no_way_out = 0; 136321afaf18SBorislav Petkov 136421afaf18SBorislav Petkov /* 1365e1c06d23SGabriele Paoloni * If kill_current_task is not set, there might be a way to recover from this 136621afaf18SBorislav Petkov * error. 136721afaf18SBorislav Petkov */ 1368cbe1de16SBorislav Petkov kill_current_task = 0; 136921afaf18SBorislav Petkov 137021afaf18SBorislav Petkov /* 137121afaf18SBorislav Petkov * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES 137221afaf18SBorislav Petkov * on Intel. 137321afaf18SBorislav Petkov */ 1374cbe1de16SBorislav Petkov lmce = 1; 137521afaf18SBorislav Petkov 137621afaf18SBorislav Petkov this_cpu_inc(mce_exception_count); 137721afaf18SBorislav Petkov 137821afaf18SBorislav Petkov mce_gather_info(&m, regs); 137921afaf18SBorislav Petkov m.tsc = rdtsc(); 138021afaf18SBorislav Petkov 138121afaf18SBorislav Petkov final = this_cpu_ptr(&mces_seen); 138221afaf18SBorislav Petkov *final = m; 138321afaf18SBorislav Petkov 138421afaf18SBorislav Petkov no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); 138521afaf18SBorislav Petkov 138621afaf18SBorislav Petkov barrier(); 138721afaf18SBorislav Petkov 138821afaf18SBorislav Petkov /* 138921afaf18SBorislav Petkov * When no restart IP might need to kill or panic. 139021afaf18SBorislav Petkov * Assume the worst for now, but if we find the 139121afaf18SBorislav Petkov * severity is MCE_AR_SEVERITY we have other options. 139221afaf18SBorislav Petkov */ 139321afaf18SBorislav Petkov if (!(m.mcgstatus & MCG_STATUS_RIPV)) 1394e1c06d23SGabriele Paoloni kill_current_task = (cfg->tolerant == 3) ? 0 : 1; 139521afaf18SBorislav Petkov /* 139621afaf18SBorislav Petkov * Check if this MCE is signaled to only this logical processor, 139770f0c230STony W Wang-oc * on Intel, Zhaoxin only. 139821afaf18SBorislav Petkov */ 139970f0c230STony W Wang-oc if (m.cpuvendor == X86_VENDOR_INTEL || 140070f0c230STony W Wang-oc m.cpuvendor == X86_VENDOR_ZHAOXIN) 140121afaf18SBorislav Petkov lmce = m.mcgstatus & MCG_STATUS_LMCES; 140221afaf18SBorislav Petkov 140321afaf18SBorislav Petkov /* 140421afaf18SBorislav Petkov * Local machine check may already know that we have to panic. 140521afaf18SBorislav Petkov * Broadcast machine check begins rendezvous in mce_start() 140621afaf18SBorislav Petkov * Go through all banks in exclusion of the other CPUs. This way we 140721afaf18SBorislav Petkov * don't report duplicated events on shared banks because the first one 140821afaf18SBorislav Petkov * to see it will clear it. 140921afaf18SBorislav Petkov */ 141021afaf18SBorislav Petkov if (lmce) { 14113a866b16SGabriele Paoloni if (no_way_out && cfg->tolerant < 3) 141221afaf18SBorislav Petkov mce_panic("Fatal local machine check", &m, msg); 141321afaf18SBorislav Petkov } else { 141421afaf18SBorislav Petkov order = mce_start(&no_way_out); 141521afaf18SBorislav Petkov } 141621afaf18SBorislav Petkov 141741ce0564SYouquan Song __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst); 141821afaf18SBorislav Petkov 141921afaf18SBorislav Petkov if (!no_way_out) 142021afaf18SBorislav Petkov mce_clear_state(toclear); 142121afaf18SBorislav Petkov 142221afaf18SBorislav Petkov /* 142321afaf18SBorislav Petkov * Do most of the synchronization with other CPUs. 142421afaf18SBorislav Petkov * When there's any problem use only local no_way_out state. 142521afaf18SBorislav Petkov */ 142621afaf18SBorislav Petkov if (!lmce) { 142725bc65d8SGabriele Paoloni if (mce_end(order) < 0) { 142825bc65d8SGabriele Paoloni if (!no_way_out) 142921afaf18SBorislav Petkov no_way_out = worst >= MCE_PANIC_SEVERITY; 1430e273e6e1SGabriele Paoloni 1431e273e6e1SGabriele Paoloni if (no_way_out && cfg->tolerant < 3) 1432e273e6e1SGabriele Paoloni mce_panic("Fatal machine check on current CPU", &m, msg); 143325bc65d8SGabriele Paoloni } 143421afaf18SBorislav Petkov } else { 143521afaf18SBorislav Petkov /* 143621afaf18SBorislav Petkov * If there was a fatal machine check we should have 143721afaf18SBorislav Petkov * already called mce_panic earlier in this function. 143821afaf18SBorislav Petkov * Since we re-read the banks, we might have found 143921afaf18SBorislav Petkov * something new. Check again to see if we found a 144021afaf18SBorislav Petkov * fatal error. We call "mce_severity()" again to 144121afaf18SBorislav Petkov * make sure we have the right "msg". 144221afaf18SBorislav Petkov */ 144321afaf18SBorislav Petkov if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) { 144441ce0564SYouquan Song mce_severity(&m, regs, cfg->tolerant, &msg, true); 144521afaf18SBorislav Petkov mce_panic("Local fatal machine check!", &m, msg); 144621afaf18SBorislav Petkov } 144721afaf18SBorislav Petkov } 144821afaf18SBorislav Petkov 1449e1c06d23SGabriele Paoloni if (worst != MCE_AR_SEVERITY && !kill_current_task) 14501e36d9c6STony Luck goto out; 145121afaf18SBorislav Petkov 145221afaf18SBorislav Petkov /* Fault was in user mode and we need to take some action */ 145321afaf18SBorislav Petkov if ((m.cs & 3) == 3) { 1454b052df3dSThomas Gleixner /* If this triggers there is no way to recover. Die hard. */ 1455b052df3dSThomas Gleixner BUG_ON(!on_thread_stack() || !user_mode(regs)); 145621afaf18SBorislav Petkov 1457a6e3cf70STony Luck if (kill_current_task) 1458a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_now); 1459a6e3cf70STony Luck else 1460a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_maybe); 1461c0ab7ffcSTony Luck 146221afaf18SBorislav Petkov } else { 14631df73b21SBorislav Petkov /* 14641df73b21SBorislav Petkov * Handle an MCE which has happened in kernel space but from 14651df73b21SBorislav Petkov * which the kernel can recover: ex_has_fault_handler() has 14661df73b21SBorislav Petkov * already verified that the rIP at which the error happened is 14671df73b21SBorislav Petkov * a rIP from which the kernel can recover (by jumping to 14681df73b21SBorislav Petkov * recovery code specified in _ASM_EXTABLE_FAULT()) and the 14691df73b21SBorislav Petkov * corresponding exception handler which would do that is the 14701df73b21SBorislav Petkov * proper one. 14711df73b21SBorislav Petkov */ 14721df73b21SBorislav Petkov if (m.kflags & MCE_IN_KERNEL_RECOV) { 14738cd501c1SThomas Gleixner if (!fixup_exception(regs, X86_TRAP_MC, 0, 0)) 14742d806d07SJan H. Schönherr mce_panic("Failed kernel mode recovery", &m, msg); 147521afaf18SBorislav Petkov } 1476c0ab7ffcSTony Luck 1477c0ab7ffcSTony Luck if (m.kflags & MCE_IN_KERNEL_COPYIN) 1478a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_never); 14791df73b21SBorislav Petkov } 14801e36d9c6STony Luck out: 14811e36d9c6STony Luck mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); 148221afaf18SBorislav Petkov } 148321afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(do_machine_check); 148421afaf18SBorislav Petkov 148521afaf18SBorislav Petkov #ifndef CONFIG_MEMORY_FAILURE 148621afaf18SBorislav Petkov int memory_failure(unsigned long pfn, int flags) 148721afaf18SBorislav Petkov { 148821afaf18SBorislav Petkov /* mce_severity() should not hand us an ACTION_REQUIRED error */ 148921afaf18SBorislav Petkov BUG_ON(flags & MF_ACTION_REQUIRED); 149021afaf18SBorislav Petkov pr_err("Uncorrected memory error in page 0x%lx ignored\n" 149121afaf18SBorislav Petkov "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", 149221afaf18SBorislav Petkov pfn); 149321afaf18SBorislav Petkov 149421afaf18SBorislav Petkov return 0; 149521afaf18SBorislav Petkov } 149621afaf18SBorislav Petkov #endif 149721afaf18SBorislav Petkov 149821afaf18SBorislav Petkov /* 149921afaf18SBorislav Petkov * Periodic polling timer for "silent" machine check errors. If the 150021afaf18SBorislav Petkov * poller finds an MCE, poll 2x faster. When the poller finds no more 150121afaf18SBorislav Petkov * errors, poll 2x slower (up to check_interval seconds). 150221afaf18SBorislav Petkov */ 150321afaf18SBorislav Petkov static unsigned long check_interval = INITIAL_CHECK_INTERVAL; 150421afaf18SBorislav Petkov 150521afaf18SBorislav Petkov static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ 150621afaf18SBorislav Petkov static DEFINE_PER_CPU(struct timer_list, mce_timer); 150721afaf18SBorislav Petkov 150821afaf18SBorislav Petkov static unsigned long mce_adjust_timer_default(unsigned long interval) 150921afaf18SBorislav Petkov { 151021afaf18SBorislav Petkov return interval; 151121afaf18SBorislav Petkov } 151221afaf18SBorislav Petkov 151321afaf18SBorislav Petkov static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; 151421afaf18SBorislav Petkov 151521afaf18SBorislav Petkov static void __start_timer(struct timer_list *t, unsigned long interval) 151621afaf18SBorislav Petkov { 151721afaf18SBorislav Petkov unsigned long when = jiffies + interval; 151821afaf18SBorislav Petkov unsigned long flags; 151921afaf18SBorislav Petkov 152021afaf18SBorislav Petkov local_irq_save(flags); 152121afaf18SBorislav Petkov 152221afaf18SBorislav Petkov if (!timer_pending(t) || time_before(when, t->expires)) 152321afaf18SBorislav Petkov mod_timer(t, round_jiffies(when)); 152421afaf18SBorislav Petkov 152521afaf18SBorislav Petkov local_irq_restore(flags); 152621afaf18SBorislav Petkov } 152721afaf18SBorislav Petkov 152821afaf18SBorislav Petkov static void mce_timer_fn(struct timer_list *t) 152921afaf18SBorislav Petkov { 153021afaf18SBorislav Petkov struct timer_list *cpu_t = this_cpu_ptr(&mce_timer); 153121afaf18SBorislav Petkov unsigned long iv; 153221afaf18SBorislav Petkov 153321afaf18SBorislav Petkov WARN_ON(cpu_t != t); 153421afaf18SBorislav Petkov 153521afaf18SBorislav Petkov iv = __this_cpu_read(mce_next_interval); 153621afaf18SBorislav Petkov 153721afaf18SBorislav Petkov if (mce_available(this_cpu_ptr(&cpu_info))) { 153821afaf18SBorislav Petkov machine_check_poll(0, this_cpu_ptr(&mce_poll_banks)); 153921afaf18SBorislav Petkov 154021afaf18SBorislav Petkov if (mce_intel_cmci_poll()) { 154121afaf18SBorislav Petkov iv = mce_adjust_timer(iv); 154221afaf18SBorislav Petkov goto done; 154321afaf18SBorislav Petkov } 154421afaf18SBorislav Petkov } 154521afaf18SBorislav Petkov 154621afaf18SBorislav Petkov /* 154721afaf18SBorislav Petkov * Alert userspace if needed. If we logged an MCE, reduce the polling 154821afaf18SBorislav Petkov * interval, otherwise increase the polling interval. 154921afaf18SBorislav Petkov */ 155021afaf18SBorislav Petkov if (mce_notify_irq()) 155121afaf18SBorislav Petkov iv = max(iv / 2, (unsigned long) HZ/100); 155221afaf18SBorislav Petkov else 155321afaf18SBorislav Petkov iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); 155421afaf18SBorislav Petkov 155521afaf18SBorislav Petkov done: 155621afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, iv); 155721afaf18SBorislav Petkov __start_timer(t, iv); 155821afaf18SBorislav Petkov } 155921afaf18SBorislav Petkov 156021afaf18SBorislav Petkov /* 156121afaf18SBorislav Petkov * Ensure that the timer is firing in @interval from now. 156221afaf18SBorislav Petkov */ 156321afaf18SBorislav Petkov void mce_timer_kick(unsigned long interval) 156421afaf18SBorislav Petkov { 156521afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 156621afaf18SBorislav Petkov unsigned long iv = __this_cpu_read(mce_next_interval); 156721afaf18SBorislav Petkov 156821afaf18SBorislav Petkov __start_timer(t, interval); 156921afaf18SBorislav Petkov 157021afaf18SBorislav Petkov if (interval < iv) 157121afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, interval); 157221afaf18SBorislav Petkov } 157321afaf18SBorislav Petkov 157421afaf18SBorislav Petkov /* Must not be called in IRQ context where del_timer_sync() can deadlock */ 157521afaf18SBorislav Petkov static void mce_timer_delete_all(void) 157621afaf18SBorislav Petkov { 157721afaf18SBorislav Petkov int cpu; 157821afaf18SBorislav Petkov 157921afaf18SBorislav Petkov for_each_online_cpu(cpu) 158021afaf18SBorislav Petkov del_timer_sync(&per_cpu(mce_timer, cpu)); 158121afaf18SBorislav Petkov } 158221afaf18SBorislav Petkov 158321afaf18SBorislav Petkov /* 158421afaf18SBorislav Petkov * Notify the user(s) about new machine check events. 158521afaf18SBorislav Petkov * Can be called from interrupt context, but not from machine check/NMI 158621afaf18SBorislav Petkov * context. 158721afaf18SBorislav Petkov */ 158821afaf18SBorislav Petkov int mce_notify_irq(void) 158921afaf18SBorislav Petkov { 159021afaf18SBorislav Petkov /* Not more than two messages every minute */ 159121afaf18SBorislav Petkov static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); 159221afaf18SBorislav Petkov 159321afaf18SBorislav Petkov if (test_and_clear_bit(0, &mce_need_notify)) { 159421afaf18SBorislav Petkov mce_work_trigger(); 159521afaf18SBorislav Petkov 159621afaf18SBorislav Petkov if (__ratelimit(&ratelimit)) 159721afaf18SBorislav Petkov pr_info(HW_ERR "Machine check events logged\n"); 159821afaf18SBorislav Petkov 159921afaf18SBorislav Petkov return 1; 160021afaf18SBorislav Petkov } 160121afaf18SBorislav Petkov return 0; 160221afaf18SBorislav Petkov } 160321afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_notify_irq); 160421afaf18SBorislav Petkov 1605b4914508SYazen Ghannam static void __mcheck_cpu_mce_banks_init(void) 160621afaf18SBorislav Petkov { 1607b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1608c7d314f3SYazen Ghannam u8 n_banks = this_cpu_read(mce_num_banks); 160921afaf18SBorislav Petkov int i; 161021afaf18SBorislav Petkov 1611c7d314f3SYazen Ghannam for (i = 0; i < n_banks; i++) { 161221afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 161321afaf18SBorislav Petkov 1614068b053dSYazen Ghannam /* 1615068b053dSYazen Ghannam * Init them all, __mcheck_cpu_apply_quirks() is going to apply 1616068b053dSYazen Ghannam * the required vendor quirks before 1617068b053dSYazen Ghannam * __mcheck_cpu_init_clear_banks() does the final bank setup. 1618068b053dSYazen Ghannam */ 161921afaf18SBorislav Petkov b->ctl = -1ULL; 162077080929SKaixu Xia b->init = true; 162121afaf18SBorislav Petkov } 162221afaf18SBorislav Petkov } 162321afaf18SBorislav Petkov 162421afaf18SBorislav Petkov /* 162521afaf18SBorislav Petkov * Initialize Machine Checks for a CPU. 162621afaf18SBorislav Petkov */ 1627b4914508SYazen Ghannam static void __mcheck_cpu_cap_init(void) 162821afaf18SBorislav Petkov { 162921afaf18SBorislav Petkov u64 cap; 1630006c0770SYazen Ghannam u8 b; 163121afaf18SBorislav Petkov 163221afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 163321afaf18SBorislav Petkov 163421afaf18SBorislav Petkov b = cap & MCG_BANKCNT_MASK; 163521afaf18SBorislav Petkov 1636c7d314f3SYazen Ghannam if (b > MAX_NR_BANKS) { 1637c7d314f3SYazen Ghannam pr_warn("CPU%d: Using only %u machine check banks out of %u\n", 1638c7d314f3SYazen Ghannam smp_processor_id(), MAX_NR_BANKS, b); 1639c7d314f3SYazen Ghannam b = MAX_NR_BANKS; 1640c7d314f3SYazen Ghannam } 1641c7d314f3SYazen Ghannam 1642c7d314f3SYazen Ghannam this_cpu_write(mce_num_banks, b); 164321afaf18SBorislav Petkov 1644b4914508SYazen Ghannam __mcheck_cpu_mce_banks_init(); 164521afaf18SBorislav Petkov 164621afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 164721afaf18SBorislav Petkov if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) 164821afaf18SBorislav Petkov mca_cfg.rip_msr = MSR_IA32_MCG_EIP; 164921afaf18SBorislav Petkov 165021afaf18SBorislav Petkov if (cap & MCG_SER_P) 165121afaf18SBorislav Petkov mca_cfg.ser = 1; 165221afaf18SBorislav Petkov } 165321afaf18SBorislav Petkov 165421afaf18SBorislav Petkov static void __mcheck_cpu_init_generic(void) 165521afaf18SBorislav Petkov { 165621afaf18SBorislav Petkov enum mcp_flags m_fl = 0; 165721afaf18SBorislav Petkov mce_banks_t all_banks; 165821afaf18SBorislav Petkov u64 cap; 165921afaf18SBorislav Petkov 166021afaf18SBorislav Petkov if (!mca_cfg.bootlog) 166121afaf18SBorislav Petkov m_fl = MCP_DONTLOG; 166221afaf18SBorislav Petkov 166321afaf18SBorislav Petkov /* 16643bff147bSBorislav Petkov * Log the machine checks left over from the previous reset. Log them 16653bff147bSBorislav Petkov * only, do not start processing them. That will happen in mcheck_late_init() 16663bff147bSBorislav Petkov * when all consumers have been registered on the notifier chain. 166721afaf18SBorislav Petkov */ 166821afaf18SBorislav Petkov bitmap_fill(all_banks, MAX_NR_BANKS); 16693bff147bSBorislav Petkov machine_check_poll(MCP_UC | MCP_QUEUE_LOG | m_fl, &all_banks); 167021afaf18SBorislav Petkov 167121afaf18SBorislav Petkov cr4_set_bits(X86_CR4_MCE); 167221afaf18SBorislav Petkov 167321afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 167421afaf18SBorislav Petkov if (cap & MCG_CTL_P) 167521afaf18SBorislav Petkov wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); 167621afaf18SBorislav Petkov } 167721afaf18SBorislav Petkov 167821afaf18SBorislav Petkov static void __mcheck_cpu_init_clear_banks(void) 167921afaf18SBorislav Petkov { 1680b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 168121afaf18SBorislav Petkov int i; 168221afaf18SBorislav Petkov 1683c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 168421afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 168521afaf18SBorislav Petkov 168621afaf18SBorislav Petkov if (!b->init) 168721afaf18SBorislav Petkov continue; 16888121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); 16898121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 169021afaf18SBorislav Petkov } 169121afaf18SBorislav Petkov } 169221afaf18SBorislav Petkov 169321afaf18SBorislav Petkov /* 1694068b053dSYazen Ghannam * Do a final check to see if there are any unused/RAZ banks. 1695068b053dSYazen Ghannam * 1696068b053dSYazen Ghannam * This must be done after the banks have been initialized and any quirks have 1697068b053dSYazen Ghannam * been applied. 1698068b053dSYazen Ghannam * 1699068b053dSYazen Ghannam * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs. 1700068b053dSYazen Ghannam * Otherwise, a user who disables a bank will not be able to re-enable it 1701068b053dSYazen Ghannam * without a system reboot. 1702068b053dSYazen Ghannam */ 1703068b053dSYazen Ghannam static void __mcheck_cpu_check_banks(void) 1704068b053dSYazen Ghannam { 1705068b053dSYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1706068b053dSYazen Ghannam u64 msrval; 1707068b053dSYazen Ghannam int i; 1708068b053dSYazen Ghannam 1709068b053dSYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1710068b053dSYazen Ghannam struct mce_bank *b = &mce_banks[i]; 1711068b053dSYazen Ghannam 1712068b053dSYazen Ghannam if (!b->init) 1713068b053dSYazen Ghannam continue; 1714068b053dSYazen Ghannam 17158121b8f9SBorislav Petkov rdmsrl(mca_msr_reg(i, MCA_CTL), msrval); 1716068b053dSYazen Ghannam b->init = !!msrval; 1717068b053dSYazen Ghannam } 1718068b053dSYazen Ghannam } 1719068b053dSYazen Ghannam 172021afaf18SBorislav Petkov /* Add per CPU specific workarounds here */ 172121afaf18SBorislav Petkov static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) 172221afaf18SBorislav Petkov { 1723b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 172421afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 172521afaf18SBorislav Petkov 172621afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_UNKNOWN) { 172721afaf18SBorislav Petkov pr_info("unknown CPU type - not enabling MCE support\n"); 172821afaf18SBorislav Petkov return -EOPNOTSUPP; 172921afaf18SBorislav Petkov } 173021afaf18SBorislav Petkov 173121afaf18SBorislav Petkov /* This should be disabled by the BIOS, but isn't always */ 173221afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD) { 1733c7d314f3SYazen Ghannam if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { 173421afaf18SBorislav Petkov /* 173521afaf18SBorislav Petkov * disable GART TBL walk error reporting, which 173621afaf18SBorislav Petkov * trips off incorrectly with the IOMMU & 3ware 173721afaf18SBorislav Petkov * & Cerberus: 173821afaf18SBorislav Petkov */ 173921afaf18SBorislav Petkov clear_bit(10, (unsigned long *)&mce_banks[4].ctl); 174021afaf18SBorislav Petkov } 174121afaf18SBorislav Petkov if (c->x86 < 0x11 && cfg->bootlog < 0) { 174221afaf18SBorislav Petkov /* 174321afaf18SBorislav Petkov * Lots of broken BIOS around that don't clear them 174421afaf18SBorislav Petkov * by default and leave crap in there. Don't log: 174521afaf18SBorislav Petkov */ 174621afaf18SBorislav Petkov cfg->bootlog = 0; 174721afaf18SBorislav Petkov } 174821afaf18SBorislav Petkov /* 174921afaf18SBorislav Petkov * Various K7s with broken bank 0 around. Always disable 175021afaf18SBorislav Petkov * by default. 175121afaf18SBorislav Petkov */ 1752c7d314f3SYazen Ghannam if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0) 175321afaf18SBorislav Petkov mce_banks[0].ctl = 0; 175421afaf18SBorislav Petkov 175521afaf18SBorislav Petkov /* 175621afaf18SBorislav Petkov * overflow_recov is supported for F15h Models 00h-0fh 175721afaf18SBorislav Petkov * even though we don't have a CPUID bit for it. 175821afaf18SBorislav Petkov */ 175921afaf18SBorislav Petkov if (c->x86 == 0x15 && c->x86_model <= 0xf) 176021afaf18SBorislav Petkov mce_flags.overflow_recov = 1; 176121afaf18SBorislav Petkov 176221afaf18SBorislav Petkov } 176321afaf18SBorislav Petkov 176421afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_INTEL) { 176521afaf18SBorislav Petkov /* 176621afaf18SBorislav Petkov * SDM documents that on family 6 bank 0 should not be written 176721afaf18SBorislav Petkov * because it aliases to another special BIOS controlled 176821afaf18SBorislav Petkov * register. 176921afaf18SBorislav Petkov * But it's not aliased anymore on model 0x1a+ 177021afaf18SBorislav Petkov * Don't ignore bank 0 completely because there could be a 177121afaf18SBorislav Petkov * valid event later, merely don't write CTL0. 177221afaf18SBorislav Petkov */ 177321afaf18SBorislav Petkov 1774c7d314f3SYazen Ghannam if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) 177577080929SKaixu Xia mce_banks[0].init = false; 177621afaf18SBorislav Petkov 177721afaf18SBorislav Petkov /* 177821afaf18SBorislav Petkov * All newer Intel systems support MCE broadcasting. Enable 177921afaf18SBorislav Petkov * synchronization with a one second timeout. 178021afaf18SBorislav Petkov */ 178121afaf18SBorislav Petkov if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && 178221afaf18SBorislav Petkov cfg->monarch_timeout < 0) 178321afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 178421afaf18SBorislav Petkov 178521afaf18SBorislav Petkov /* 178621afaf18SBorislav Petkov * There are also broken BIOSes on some Pentium M and 178721afaf18SBorislav Petkov * earlier systems: 178821afaf18SBorislav Petkov */ 178921afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) 179021afaf18SBorislav Petkov cfg->bootlog = 0; 179121afaf18SBorislav Petkov 179221afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model == 45) 1793cc466666SBorislav Petkov mce_flags.snb_ifu_quirk = 1; 179421afaf18SBorislav Petkov } 17956e898d2bSTony W Wang-oc 17966e898d2bSTony W Wang-oc if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { 17976e898d2bSTony W Wang-oc /* 17986e898d2bSTony W Wang-oc * All newer Zhaoxin CPUs support MCE broadcasting. Enable 17996e898d2bSTony W Wang-oc * synchronization with a one second timeout. 18006e898d2bSTony W Wang-oc */ 18016e898d2bSTony W Wang-oc if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 18026e898d2bSTony W Wang-oc if (cfg->monarch_timeout < 0) 18036e898d2bSTony W Wang-oc cfg->monarch_timeout = USEC_PER_SEC; 18046e898d2bSTony W Wang-oc } 18056e898d2bSTony W Wang-oc } 18066e898d2bSTony W Wang-oc 180721afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 180821afaf18SBorislav Petkov cfg->monarch_timeout = 0; 180921afaf18SBorislav Petkov if (cfg->bootlog != 0) 181021afaf18SBorislav Petkov cfg->panic_timeout = 30; 181121afaf18SBorislav Petkov 181221afaf18SBorislav Petkov return 0; 181321afaf18SBorislav Petkov } 181421afaf18SBorislav Petkov 181521afaf18SBorislav Petkov static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) 181621afaf18SBorislav Petkov { 181721afaf18SBorislav Petkov if (c->x86 != 5) 181821afaf18SBorislav Petkov return 0; 181921afaf18SBorislav Petkov 182021afaf18SBorislav Petkov switch (c->x86_vendor) { 182121afaf18SBorislav Petkov case X86_VENDOR_INTEL: 182221afaf18SBorislav Petkov intel_p5_mcheck_init(c); 1823cbe1de16SBorislav Petkov mce_flags.p5 = 1; 182421afaf18SBorislav Petkov return 1; 182521afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 182621afaf18SBorislav Petkov winchip_mcheck_init(c); 1827cbe1de16SBorislav Petkov mce_flags.winchip = 1; 182821afaf18SBorislav Petkov return 1; 182921afaf18SBorislav Petkov default: 183021afaf18SBorislav Petkov return 0; 183121afaf18SBorislav Petkov } 183221afaf18SBorislav Petkov 183321afaf18SBorislav Petkov return 0; 183421afaf18SBorislav Petkov } 183521afaf18SBorislav Petkov 183621afaf18SBorislav Petkov /* 183721afaf18SBorislav Petkov * Init basic CPU features needed for early decoding of MCEs. 183821afaf18SBorislav Petkov */ 183921afaf18SBorislav Petkov static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) 184021afaf18SBorislav Petkov { 184121afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) { 184221afaf18SBorislav Petkov mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); 184321afaf18SBorislav Petkov mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); 184421afaf18SBorislav Petkov mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); 1845c9bf318fSThomas Gleixner mce_flags.amd_threshold = 1; 184621afaf18SBorislav Petkov } 184721afaf18SBorislav Petkov } 184821afaf18SBorislav Petkov 184921afaf18SBorislav Petkov static void mce_centaur_feature_init(struct cpuinfo_x86 *c) 185021afaf18SBorislav Petkov { 185121afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 185221afaf18SBorislav Petkov 185321afaf18SBorislav Petkov /* 185421afaf18SBorislav Petkov * All newer Centaur CPUs support MCE broadcasting. Enable 185521afaf18SBorislav Petkov * synchronization with a one second timeout. 185621afaf18SBorislav Petkov */ 185721afaf18SBorislav Petkov if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) || 185821afaf18SBorislav Petkov c->x86 > 6) { 185921afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 186021afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 186121afaf18SBorislav Petkov } 186221afaf18SBorislav Petkov } 186321afaf18SBorislav Petkov 18645a3d56a0STony W Wang-oc static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) 18655a3d56a0STony W Wang-oc { 18665a3d56a0STony W Wang-oc struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 18675a3d56a0STony W Wang-oc 18685a3d56a0STony W Wang-oc /* 18695a3d56a0STony W Wang-oc * These CPUs have MCA bank 8 which reports only one error type called 18705a3d56a0STony W Wang-oc * SVAD (System View Address Decoder). The reporting of that error is 18715a3d56a0STony W Wang-oc * controlled by IA32_MC8.CTL.0. 18725a3d56a0STony W Wang-oc * 18735a3d56a0STony W Wang-oc * If enabled, prefetching on these CPUs will cause SVAD MCE when 18745a3d56a0STony W Wang-oc * virtual machines start and result in a system panic. Always disable 18755a3d56a0STony W Wang-oc * bank 8 SVAD error by default. 18765a3d56a0STony W Wang-oc */ 18775a3d56a0STony W Wang-oc if ((c->x86 == 7 && c->x86_model == 0x1b) || 18785a3d56a0STony W Wang-oc (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 18795a3d56a0STony W Wang-oc if (this_cpu_read(mce_num_banks) > 8) 18805a3d56a0STony W Wang-oc mce_banks[8].ctl = 0; 18815a3d56a0STony W Wang-oc } 18825a3d56a0STony W Wang-oc 18835a3d56a0STony W Wang-oc intel_init_cmci(); 188470f0c230STony W Wang-oc intel_init_lmce(); 18855a3d56a0STony W Wang-oc mce_adjust_timer = cmci_intel_adjust_timer; 18865a3d56a0STony W Wang-oc } 18875a3d56a0STony W Wang-oc 188870f0c230STony W Wang-oc static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) 188970f0c230STony W Wang-oc { 189070f0c230STony W Wang-oc intel_clear_lmce(); 189170f0c230STony W Wang-oc } 189270f0c230STony W Wang-oc 189321afaf18SBorislav Petkov static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) 189421afaf18SBorislav Petkov { 189521afaf18SBorislav Petkov switch (c->x86_vendor) { 189621afaf18SBorislav Petkov case X86_VENDOR_INTEL: 189721afaf18SBorislav Petkov mce_intel_feature_init(c); 189821afaf18SBorislav Petkov mce_adjust_timer = cmci_intel_adjust_timer; 189921afaf18SBorislav Petkov break; 190021afaf18SBorislav Petkov 190121afaf18SBorislav Petkov case X86_VENDOR_AMD: { 190221afaf18SBorislav Petkov mce_amd_feature_init(c); 190321afaf18SBorislav Petkov break; 190421afaf18SBorislav Petkov } 190521afaf18SBorislav Petkov 190621afaf18SBorislav Petkov case X86_VENDOR_HYGON: 190721afaf18SBorislav Petkov mce_hygon_feature_init(c); 190821afaf18SBorislav Petkov break; 190921afaf18SBorislav Petkov 191021afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 191121afaf18SBorislav Petkov mce_centaur_feature_init(c); 191221afaf18SBorislav Petkov break; 191321afaf18SBorislav Petkov 19145a3d56a0STony W Wang-oc case X86_VENDOR_ZHAOXIN: 19155a3d56a0STony W Wang-oc mce_zhaoxin_feature_init(c); 19165a3d56a0STony W Wang-oc break; 19175a3d56a0STony W Wang-oc 191821afaf18SBorislav Petkov default: 191921afaf18SBorislav Petkov break; 192021afaf18SBorislav Petkov } 192121afaf18SBorislav Petkov } 192221afaf18SBorislav Petkov 192321afaf18SBorislav Petkov static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) 192421afaf18SBorislav Petkov { 192521afaf18SBorislav Petkov switch (c->x86_vendor) { 192621afaf18SBorislav Petkov case X86_VENDOR_INTEL: 192721afaf18SBorislav Petkov mce_intel_feature_clear(c); 192821afaf18SBorislav Petkov break; 192970f0c230STony W Wang-oc 193070f0c230STony W Wang-oc case X86_VENDOR_ZHAOXIN: 193170f0c230STony W Wang-oc mce_zhaoxin_feature_clear(c); 193270f0c230STony W Wang-oc break; 193370f0c230STony W Wang-oc 193421afaf18SBorislav Petkov default: 193521afaf18SBorislav Petkov break; 193621afaf18SBorislav Petkov } 193721afaf18SBorislav Petkov } 193821afaf18SBorislav Petkov 193921afaf18SBorislav Petkov static void mce_start_timer(struct timer_list *t) 194021afaf18SBorislav Petkov { 194121afaf18SBorislav Petkov unsigned long iv = check_interval * HZ; 194221afaf18SBorislav Petkov 194321afaf18SBorislav Petkov if (mca_cfg.ignore_ce || !iv) 194421afaf18SBorislav Petkov return; 194521afaf18SBorislav Petkov 194621afaf18SBorislav Petkov this_cpu_write(mce_next_interval, iv); 194721afaf18SBorislav Petkov __start_timer(t, iv); 194821afaf18SBorislav Petkov } 194921afaf18SBorislav Petkov 195021afaf18SBorislav Petkov static void __mcheck_cpu_setup_timer(void) 195121afaf18SBorislav Petkov { 195221afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 195321afaf18SBorislav Petkov 195421afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 195521afaf18SBorislav Petkov } 195621afaf18SBorislav Petkov 195721afaf18SBorislav Petkov static void __mcheck_cpu_init_timer(void) 195821afaf18SBorislav Petkov { 195921afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 196021afaf18SBorislav Petkov 196121afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 196221afaf18SBorislav Petkov mce_start_timer(t); 196321afaf18SBorislav Petkov } 196421afaf18SBorislav Petkov 196545d4b7b9SYazen Ghannam bool filter_mce(struct mce *m) 196645d4b7b9SYazen Ghannam { 196771a84402SYazen Ghannam if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 196871a84402SYazen Ghannam return amd_filter_mce(m); 19692976908eSPrarit Bhargava if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 19702976908eSPrarit Bhargava return intel_filter_mce(m); 197171a84402SYazen Ghannam 197245d4b7b9SYazen Ghannam return false; 197345d4b7b9SYazen Ghannam } 197445d4b7b9SYazen Ghannam 19754c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_kernel(struct pt_regs *regs) 197621afaf18SBorislav Petkov { 1977b6be002bSThomas Gleixner irqentry_state_t irq_state; 1978bc21a291SThomas Gleixner 197913cbc0cdSAndy Lutomirski WARN_ON_ONCE(user_mode(regs)); 198013cbc0cdSAndy Lutomirski 19814c0dcd83SThomas Gleixner /* 19824c0dcd83SThomas Gleixner * Only required when from kernel mode. See 19834c0dcd83SThomas Gleixner * mce_check_crashing_cpu() for details. 19844c0dcd83SThomas Gleixner */ 1985cbe1de16SBorislav Petkov if (mca_cfg.initialized && mce_check_crashing_cpu()) 198694a46d31SThomas Gleixner return; 198794a46d31SThomas Gleixner 1988b6be002bSThomas Gleixner irq_state = irqentry_nmi_enter(regs); 198973749536SPeter Zijlstra 1990cbe1de16SBorislav Petkov do_machine_check(regs); 199173749536SPeter Zijlstra 1992b6be002bSThomas Gleixner irqentry_nmi_exit(regs, irq_state); 199321afaf18SBorislav Petkov } 199421afaf18SBorislav Petkov 19954c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_user(struct pt_regs *regs) 19964c0dcd83SThomas Gleixner { 1997517e4992SThomas Gleixner irqentry_enter_from_user_mode(regs); 199873749536SPeter Zijlstra 1999cbe1de16SBorislav Petkov do_machine_check(regs); 200073749536SPeter Zijlstra 2001517e4992SThomas Gleixner irqentry_exit_to_user_mode(regs); 20024c0dcd83SThomas Gleixner } 20034c0dcd83SThomas Gleixner 20044c0dcd83SThomas Gleixner #ifdef CONFIG_X86_64 20054c0dcd83SThomas Gleixner /* MCE hit kernel mode */ 20064c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE(exc_machine_check) 20074c0dcd83SThomas Gleixner { 2008cd840e42SPeter Zijlstra unsigned long dr7; 2009cd840e42SPeter Zijlstra 2010cd840e42SPeter Zijlstra dr7 = local_db_save(); 20114c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 2012cd840e42SPeter Zijlstra local_db_restore(dr7); 20134c0dcd83SThomas Gleixner } 20144c0dcd83SThomas Gleixner 20154c0dcd83SThomas Gleixner /* The user mode variant. */ 20164c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE_USER(exc_machine_check) 20174c0dcd83SThomas Gleixner { 2018cd840e42SPeter Zijlstra unsigned long dr7; 2019cd840e42SPeter Zijlstra 2020cd840e42SPeter Zijlstra dr7 = local_db_save(); 20214c0dcd83SThomas Gleixner exc_machine_check_user(regs); 2022cd840e42SPeter Zijlstra local_db_restore(dr7); 20234c0dcd83SThomas Gleixner } 20244c0dcd83SThomas Gleixner #else 20254c0dcd83SThomas Gleixner /* 32bit unified entry point */ 202613cbc0cdSAndy Lutomirski DEFINE_IDTENTRY_RAW(exc_machine_check) 20274c0dcd83SThomas Gleixner { 2028cd840e42SPeter Zijlstra unsigned long dr7; 2029cd840e42SPeter Zijlstra 2030cd840e42SPeter Zijlstra dr7 = local_db_save(); 20314c0dcd83SThomas Gleixner if (user_mode(regs)) 20324c0dcd83SThomas Gleixner exc_machine_check_user(regs); 20334c0dcd83SThomas Gleixner else 20344c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 2035cd840e42SPeter Zijlstra local_db_restore(dr7); 20364c0dcd83SThomas Gleixner } 20374c0dcd83SThomas Gleixner #endif 203821afaf18SBorislav Petkov 203921afaf18SBorislav Petkov /* 204021afaf18SBorislav Petkov * Called for each booted CPU to set up machine checks. 204121afaf18SBorislav Petkov * Must be called with preempt off: 204221afaf18SBorislav Petkov */ 204321afaf18SBorislav Petkov void mcheck_cpu_init(struct cpuinfo_x86 *c) 204421afaf18SBorislav Petkov { 204521afaf18SBorislav Petkov if (mca_cfg.disabled) 204621afaf18SBorislav Petkov return; 204721afaf18SBorislav Petkov 204821afaf18SBorislav Petkov if (__mcheck_cpu_ancient_init(c)) 204921afaf18SBorislav Petkov return; 205021afaf18SBorislav Petkov 205121afaf18SBorislav Petkov if (!mce_available(c)) 205221afaf18SBorislav Petkov return; 205321afaf18SBorislav Petkov 2054b4914508SYazen Ghannam __mcheck_cpu_cap_init(); 2055b4914508SYazen Ghannam 2056b4914508SYazen Ghannam if (__mcheck_cpu_apply_quirks(c) < 0) { 205721afaf18SBorislav Petkov mca_cfg.disabled = 1; 205821afaf18SBorislav Petkov return; 205921afaf18SBorislav Petkov } 206021afaf18SBorislav Petkov 206121afaf18SBorislav Petkov if (mce_gen_pool_init()) { 206221afaf18SBorislav Petkov mca_cfg.disabled = 1; 206321afaf18SBorislav Petkov pr_emerg("Couldn't allocate MCE records pool!\n"); 206421afaf18SBorislav Petkov return; 206521afaf18SBorislav Petkov } 206621afaf18SBorislav Petkov 2067cbe1de16SBorislav Petkov mca_cfg.initialized = 1; 206821afaf18SBorislav Petkov 206921afaf18SBorislav Petkov __mcheck_cpu_init_early(c); 207021afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 207121afaf18SBorislav Petkov __mcheck_cpu_init_vendor(c); 207221afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 2073068b053dSYazen Ghannam __mcheck_cpu_check_banks(); 207421afaf18SBorislav Petkov __mcheck_cpu_setup_timer(); 207521afaf18SBorislav Petkov } 207621afaf18SBorislav Petkov 207721afaf18SBorislav Petkov /* 207821afaf18SBorislav Petkov * Called for each booted CPU to clear some machine checks opt-ins 207921afaf18SBorislav Petkov */ 208021afaf18SBorislav Petkov void mcheck_cpu_clear(struct cpuinfo_x86 *c) 208121afaf18SBorislav Petkov { 208221afaf18SBorislav Petkov if (mca_cfg.disabled) 208321afaf18SBorislav Petkov return; 208421afaf18SBorislav Petkov 208521afaf18SBorislav Petkov if (!mce_available(c)) 208621afaf18SBorislav Petkov return; 208721afaf18SBorislav Petkov 208821afaf18SBorislav Petkov /* 208921afaf18SBorislav Petkov * Possibly to clear general settings generic to x86 209021afaf18SBorislav Petkov * __mcheck_cpu_clear_generic(c); 209121afaf18SBorislav Petkov */ 209221afaf18SBorislav Petkov __mcheck_cpu_clear_vendor(c); 209321afaf18SBorislav Petkov 209421afaf18SBorislav Petkov } 209521afaf18SBorislav Petkov 209621afaf18SBorislav Petkov static void __mce_disable_bank(void *arg) 209721afaf18SBorislav Petkov { 209821afaf18SBorislav Petkov int bank = *((int *)arg); 209921afaf18SBorislav Petkov __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); 210021afaf18SBorislav Petkov cmci_disable_bank(bank); 210121afaf18SBorislav Petkov } 210221afaf18SBorislav Petkov 210321afaf18SBorislav Petkov void mce_disable_bank(int bank) 210421afaf18SBorislav Petkov { 2105c7d314f3SYazen Ghannam if (bank >= this_cpu_read(mce_num_banks)) { 210621afaf18SBorislav Petkov pr_warn(FW_BUG 210721afaf18SBorislav Petkov "Ignoring request to disable invalid MCA bank %d.\n", 210821afaf18SBorislav Petkov bank); 210921afaf18SBorislav Petkov return; 211021afaf18SBorislav Petkov } 211121afaf18SBorislav Petkov set_bit(bank, mce_banks_ce_disabled); 211221afaf18SBorislav Petkov on_each_cpu(__mce_disable_bank, &bank, 1); 211321afaf18SBorislav Petkov } 211421afaf18SBorislav Petkov 211521afaf18SBorislav Petkov /* 211621afaf18SBorislav Petkov * mce=off Disables machine check 211721afaf18SBorislav Petkov * mce=no_cmci Disables CMCI 211821afaf18SBorislav Petkov * mce=no_lmce Disables LMCE 211921afaf18SBorislav Petkov * mce=dont_log_ce Clears corrected events silently, no log created for CEs. 212043505646STony Luck * mce=print_all Print all machine check logs to console 212121afaf18SBorislav Petkov * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. 212221afaf18SBorislav Petkov * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) 212321afaf18SBorislav Petkov * monarchtimeout is how long to wait for other CPUs on machine 212421afaf18SBorislav Petkov * check, or 0 to not wait 212521afaf18SBorislav Petkov * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h 212621afaf18SBorislav Petkov and older. 212721afaf18SBorislav Petkov * mce=nobootlog Don't log MCEs from before booting. 212821afaf18SBorislav Petkov * mce=bios_cmci_threshold Don't program the CMCI threshold 2129ec6347bbSDan Williams * mce=recovery force enable copy_mc_fragile() 213021afaf18SBorislav Petkov */ 213121afaf18SBorislav Petkov static int __init mcheck_enable(char *str) 213221afaf18SBorislav Petkov { 213321afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 213421afaf18SBorislav Petkov 213521afaf18SBorislav Petkov if (*str == 0) { 213621afaf18SBorislav Petkov enable_p5_mce(); 213721afaf18SBorislav Petkov return 1; 213821afaf18SBorislav Petkov } 213921afaf18SBorislav Petkov if (*str == '=') 214021afaf18SBorislav Petkov str++; 214121afaf18SBorislav Petkov if (!strcmp(str, "off")) 214221afaf18SBorislav Petkov cfg->disabled = 1; 214321afaf18SBorislav Petkov else if (!strcmp(str, "no_cmci")) 214421afaf18SBorislav Petkov cfg->cmci_disabled = true; 214521afaf18SBorislav Petkov else if (!strcmp(str, "no_lmce")) 214621afaf18SBorislav Petkov cfg->lmce_disabled = 1; 214721afaf18SBorislav Petkov else if (!strcmp(str, "dont_log_ce")) 214821afaf18SBorislav Petkov cfg->dont_log_ce = true; 214943505646STony Luck else if (!strcmp(str, "print_all")) 215043505646STony Luck cfg->print_all = true; 215121afaf18SBorislav Petkov else if (!strcmp(str, "ignore_ce")) 215221afaf18SBorislav Petkov cfg->ignore_ce = true; 215321afaf18SBorislav Petkov else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) 215421afaf18SBorislav Petkov cfg->bootlog = (str[0] == 'b'); 215521afaf18SBorislav Petkov else if (!strcmp(str, "bios_cmci_threshold")) 215621afaf18SBorislav Petkov cfg->bios_cmci_threshold = 1; 215721afaf18SBorislav Petkov else if (!strcmp(str, "recovery")) 215821afaf18SBorislav Petkov cfg->recovery = 1; 215921afaf18SBorislav Petkov else if (isdigit(str[0])) { 216021afaf18SBorislav Petkov if (get_option(&str, &cfg->tolerant) == 2) 216121afaf18SBorislav Petkov get_option(&str, &(cfg->monarch_timeout)); 216221afaf18SBorislav Petkov } else { 216321afaf18SBorislav Petkov pr_info("mce argument %s ignored. Please use /sys\n", str); 216421afaf18SBorislav Petkov return 0; 216521afaf18SBorislav Petkov } 216621afaf18SBorislav Petkov return 1; 216721afaf18SBorislav Petkov } 216821afaf18SBorislav Petkov __setup("mce", mcheck_enable); 216921afaf18SBorislav Petkov 217021afaf18SBorislav Petkov int __init mcheck_init(void) 217121afaf18SBorislav Petkov { 2172c9c6d216STony Luck mce_register_decode_chain(&early_nb); 21738438b84aSJan H. Schönherr mce_register_decode_chain(&mce_uc_nb); 217421afaf18SBorislav Petkov mce_register_decode_chain(&mce_default_nb); 217521afaf18SBorislav Petkov 217621afaf18SBorislav Petkov INIT_WORK(&mce_work, mce_gen_pool_process); 217721afaf18SBorislav Petkov init_irq_work(&mce_irq_work, mce_irq_work_cb); 217821afaf18SBorislav Petkov 217921afaf18SBorislav Petkov return 0; 218021afaf18SBorislav Petkov } 218121afaf18SBorislav Petkov 218221afaf18SBorislav Petkov /* 218321afaf18SBorislav Petkov * mce_syscore: PM support 218421afaf18SBorislav Petkov */ 218521afaf18SBorislav Petkov 218621afaf18SBorislav Petkov /* 218721afaf18SBorislav Petkov * Disable machine checks on suspend and shutdown. We can't really handle 218821afaf18SBorislav Petkov * them later. 218921afaf18SBorislav Petkov */ 219021afaf18SBorislav Petkov static void mce_disable_error_reporting(void) 219121afaf18SBorislav Petkov { 2192b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 219321afaf18SBorislav Petkov int i; 219421afaf18SBorislav Petkov 2195c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 219621afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 219721afaf18SBorislav Petkov 219821afaf18SBorislav Petkov if (b->init) 21998121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), 0); 220021afaf18SBorislav Petkov } 220121afaf18SBorislav Petkov return; 220221afaf18SBorislav Petkov } 220321afaf18SBorislav Petkov 220421afaf18SBorislav Petkov static void vendor_disable_error_reporting(void) 220521afaf18SBorislav Petkov { 220621afaf18SBorislav Petkov /* 22076e898d2bSTony W Wang-oc * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these 22086e898d2bSTony W Wang-oc * MSRs are socket-wide. Disabling them for just a single offlined CPU 22096e898d2bSTony W Wang-oc * is bad, since it will inhibit reporting for all shared resources on 22106e898d2bSTony W Wang-oc * the socket like the last level cache (LLC), the integrated memory 22116e898d2bSTony W Wang-oc * controller (iMC), etc. 221221afaf18SBorislav Petkov */ 221321afaf18SBorislav Petkov if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || 221421afaf18SBorislav Petkov boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || 22156e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 22166e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) 221721afaf18SBorislav Petkov return; 221821afaf18SBorislav Petkov 221921afaf18SBorislav Petkov mce_disable_error_reporting(); 222021afaf18SBorislav Petkov } 222121afaf18SBorislav Petkov 222221afaf18SBorislav Petkov static int mce_syscore_suspend(void) 222321afaf18SBorislav Petkov { 222421afaf18SBorislav Petkov vendor_disable_error_reporting(); 222521afaf18SBorislav Petkov return 0; 222621afaf18SBorislav Petkov } 222721afaf18SBorislav Petkov 222821afaf18SBorislav Petkov static void mce_syscore_shutdown(void) 222921afaf18SBorislav Petkov { 223021afaf18SBorislav Petkov vendor_disable_error_reporting(); 223121afaf18SBorislav Petkov } 223221afaf18SBorislav Petkov 223321afaf18SBorislav Petkov /* 223421afaf18SBorislav Petkov * On resume clear all MCE state. Don't want to see leftovers from the BIOS. 223521afaf18SBorislav Petkov * Only one CPU is active at this time, the others get re-added later using 223621afaf18SBorislav Petkov * CPU hotplug: 223721afaf18SBorislav Petkov */ 223821afaf18SBorislav Petkov static void mce_syscore_resume(void) 223921afaf18SBorislav Petkov { 224021afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 224121afaf18SBorislav Petkov __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); 224221afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 224321afaf18SBorislav Petkov } 224421afaf18SBorislav Petkov 224521afaf18SBorislav Petkov static struct syscore_ops mce_syscore_ops = { 224621afaf18SBorislav Petkov .suspend = mce_syscore_suspend, 224721afaf18SBorislav Petkov .shutdown = mce_syscore_shutdown, 224821afaf18SBorislav Petkov .resume = mce_syscore_resume, 224921afaf18SBorislav Petkov }; 225021afaf18SBorislav Petkov 225121afaf18SBorislav Petkov /* 225221afaf18SBorislav Petkov * mce_device: Sysfs support 225321afaf18SBorislav Petkov */ 225421afaf18SBorislav Petkov 225521afaf18SBorislav Petkov static void mce_cpu_restart(void *data) 225621afaf18SBorislav Petkov { 225721afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 225821afaf18SBorislav Petkov return; 225921afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 226021afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 226121afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 226221afaf18SBorislav Petkov } 226321afaf18SBorislav Petkov 226421afaf18SBorislav Petkov /* Reinit MCEs after user configuration changes */ 226521afaf18SBorislav Petkov static void mce_restart(void) 226621afaf18SBorislav Petkov { 226721afaf18SBorislav Petkov mce_timer_delete_all(); 226821afaf18SBorislav Petkov on_each_cpu(mce_cpu_restart, NULL, 1); 226921afaf18SBorislav Petkov } 227021afaf18SBorislav Petkov 227121afaf18SBorislav Petkov /* Toggle features for corrected errors */ 227221afaf18SBorislav Petkov static void mce_disable_cmci(void *data) 227321afaf18SBorislav Petkov { 227421afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 227521afaf18SBorislav Petkov return; 227621afaf18SBorislav Petkov cmci_clear(); 227721afaf18SBorislav Petkov } 227821afaf18SBorislav Petkov 227921afaf18SBorislav Petkov static void mce_enable_ce(void *all) 228021afaf18SBorislav Petkov { 228121afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 228221afaf18SBorislav Petkov return; 228321afaf18SBorislav Petkov cmci_reenable(); 228421afaf18SBorislav Petkov cmci_recheck(); 228521afaf18SBorislav Petkov if (all) 228621afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 228721afaf18SBorislav Petkov } 228821afaf18SBorislav Petkov 228921afaf18SBorislav Petkov static struct bus_type mce_subsys = { 229021afaf18SBorislav Petkov .name = "machinecheck", 229121afaf18SBorislav Petkov .dev_name = "machinecheck", 229221afaf18SBorislav Petkov }; 229321afaf18SBorislav Petkov 229421afaf18SBorislav Petkov DEFINE_PER_CPU(struct device *, mce_device); 229521afaf18SBorislav Petkov 2296b4914508SYazen Ghannam static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr) 229721afaf18SBorislav Petkov { 2298b4914508SYazen Ghannam return container_of(attr, struct mce_bank_dev, attr); 229921afaf18SBorislav Petkov } 230021afaf18SBorislav Petkov 230121afaf18SBorislav Petkov static ssize_t show_bank(struct device *s, struct device_attribute *attr, 230221afaf18SBorislav Petkov char *buf) 230321afaf18SBorislav Petkov { 2304b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2305b4914508SYazen Ghannam struct mce_bank *b; 2306b4914508SYazen Ghannam 2307c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2308b4914508SYazen Ghannam return -EINVAL; 2309b4914508SYazen Ghannam 2310b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2311b4914508SYazen Ghannam 2312068b053dSYazen Ghannam if (!b->init) 2313068b053dSYazen Ghannam return -ENODEV; 2314068b053dSYazen Ghannam 2315b4914508SYazen Ghannam return sprintf(buf, "%llx\n", b->ctl); 231621afaf18SBorislav Petkov } 231721afaf18SBorislav Petkov 231821afaf18SBorislav Petkov static ssize_t set_bank(struct device *s, struct device_attribute *attr, 231921afaf18SBorislav Petkov const char *buf, size_t size) 232021afaf18SBorislav Petkov { 2321b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2322b4914508SYazen Ghannam struct mce_bank *b; 232321afaf18SBorislav Petkov u64 new; 232421afaf18SBorislav Petkov 232521afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 232621afaf18SBorislav Petkov return -EINVAL; 232721afaf18SBorislav Petkov 2328c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2329b4914508SYazen Ghannam return -EINVAL; 2330b4914508SYazen Ghannam 2331b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2332b4914508SYazen Ghannam 2333068b053dSYazen Ghannam if (!b->init) 2334068b053dSYazen Ghannam return -ENODEV; 2335068b053dSYazen Ghannam 2336b4914508SYazen Ghannam b->ctl = new; 233721afaf18SBorislav Petkov mce_restart(); 233821afaf18SBorislav Petkov 233921afaf18SBorislav Petkov return size; 234021afaf18SBorislav Petkov } 234121afaf18SBorislav Petkov 234221afaf18SBorislav Petkov static ssize_t set_ignore_ce(struct device *s, 234321afaf18SBorislav Petkov struct device_attribute *attr, 234421afaf18SBorislav Petkov const char *buf, size_t size) 234521afaf18SBorislav Petkov { 234621afaf18SBorislav Petkov u64 new; 234721afaf18SBorislav Petkov 234821afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 234921afaf18SBorislav Petkov return -EINVAL; 235021afaf18SBorislav Petkov 235121afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 235221afaf18SBorislav Petkov if (mca_cfg.ignore_ce ^ !!new) { 235321afaf18SBorislav Petkov if (new) { 235421afaf18SBorislav Petkov /* disable ce features */ 235521afaf18SBorislav Petkov mce_timer_delete_all(); 235621afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 235721afaf18SBorislav Petkov mca_cfg.ignore_ce = true; 235821afaf18SBorislav Petkov } else { 235921afaf18SBorislav Petkov /* enable ce features */ 236021afaf18SBorislav Petkov mca_cfg.ignore_ce = false; 236121afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, (void *)1, 1); 236221afaf18SBorislav Petkov } 236321afaf18SBorislav Petkov } 236421afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 236521afaf18SBorislav Petkov 236621afaf18SBorislav Petkov return size; 236721afaf18SBorislav Petkov } 236821afaf18SBorislav Petkov 236921afaf18SBorislav Petkov static ssize_t set_cmci_disabled(struct device *s, 237021afaf18SBorislav Petkov struct device_attribute *attr, 237121afaf18SBorislav Petkov const char *buf, size_t size) 237221afaf18SBorislav Petkov { 237321afaf18SBorislav Petkov u64 new; 237421afaf18SBorislav Petkov 237521afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 237621afaf18SBorislav Petkov return -EINVAL; 237721afaf18SBorislav Petkov 237821afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 237921afaf18SBorislav Petkov if (mca_cfg.cmci_disabled ^ !!new) { 238021afaf18SBorislav Petkov if (new) { 238121afaf18SBorislav Petkov /* disable cmci */ 238221afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 238321afaf18SBorislav Petkov mca_cfg.cmci_disabled = true; 238421afaf18SBorislav Petkov } else { 238521afaf18SBorislav Petkov /* enable cmci */ 238621afaf18SBorislav Petkov mca_cfg.cmci_disabled = false; 238721afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, NULL, 1); 238821afaf18SBorislav Petkov } 238921afaf18SBorislav Petkov } 239021afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 239121afaf18SBorislav Petkov 239221afaf18SBorislav Petkov return size; 239321afaf18SBorislav Petkov } 239421afaf18SBorislav Petkov 239521afaf18SBorislav Petkov static ssize_t store_int_with_restart(struct device *s, 239621afaf18SBorislav Petkov struct device_attribute *attr, 239721afaf18SBorislav Petkov const char *buf, size_t size) 239821afaf18SBorislav Petkov { 239921afaf18SBorislav Petkov unsigned long old_check_interval = check_interval; 240021afaf18SBorislav Petkov ssize_t ret = device_store_ulong(s, attr, buf, size); 240121afaf18SBorislav Petkov 240221afaf18SBorislav Petkov if (check_interval == old_check_interval) 240321afaf18SBorislav Petkov return ret; 240421afaf18SBorislav Petkov 240521afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 240621afaf18SBorislav Petkov mce_restart(); 240721afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 240821afaf18SBorislav Petkov 240921afaf18SBorislav Petkov return ret; 241021afaf18SBorislav Petkov } 241121afaf18SBorislav Petkov 241221afaf18SBorislav Petkov static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); 241321afaf18SBorislav Petkov static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); 241421afaf18SBorislav Petkov static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); 241543505646STony Luck static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all); 241621afaf18SBorislav Petkov 241721afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_check_interval = { 241821afaf18SBorislav Petkov __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), 241921afaf18SBorislav Petkov &check_interval 242021afaf18SBorislav Petkov }; 242121afaf18SBorislav Petkov 242221afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_ignore_ce = { 242321afaf18SBorislav Petkov __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), 242421afaf18SBorislav Petkov &mca_cfg.ignore_ce 242521afaf18SBorislav Petkov }; 242621afaf18SBorislav Petkov 242721afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_cmci_disabled = { 242821afaf18SBorislav Petkov __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), 242921afaf18SBorislav Petkov &mca_cfg.cmci_disabled 243021afaf18SBorislav Petkov }; 243121afaf18SBorislav Petkov 243221afaf18SBorislav Petkov static struct device_attribute *mce_device_attrs[] = { 243321afaf18SBorislav Petkov &dev_attr_tolerant.attr, 243421afaf18SBorislav Petkov &dev_attr_check_interval.attr, 243521afaf18SBorislav Petkov #ifdef CONFIG_X86_MCELOG_LEGACY 243621afaf18SBorislav Petkov &dev_attr_trigger, 243721afaf18SBorislav Petkov #endif 243821afaf18SBorislav Petkov &dev_attr_monarch_timeout.attr, 243921afaf18SBorislav Petkov &dev_attr_dont_log_ce.attr, 244043505646STony Luck &dev_attr_print_all.attr, 244121afaf18SBorislav Petkov &dev_attr_ignore_ce.attr, 244221afaf18SBorislav Petkov &dev_attr_cmci_disabled.attr, 244321afaf18SBorislav Petkov NULL 244421afaf18SBorislav Petkov }; 244521afaf18SBorislav Petkov 244621afaf18SBorislav Petkov static cpumask_var_t mce_device_initialized; 244721afaf18SBorislav Petkov 244821afaf18SBorislav Petkov static void mce_device_release(struct device *dev) 244921afaf18SBorislav Petkov { 245021afaf18SBorislav Petkov kfree(dev); 245121afaf18SBorislav Petkov } 245221afaf18SBorislav Petkov 2453b4914508SYazen Ghannam /* Per CPU device init. All of the CPUs still share the same bank device: */ 245421afaf18SBorislav Petkov static int mce_device_create(unsigned int cpu) 245521afaf18SBorislav Petkov { 245621afaf18SBorislav Petkov struct device *dev; 245721afaf18SBorislav Petkov int err; 245821afaf18SBorislav Petkov int i, j; 245921afaf18SBorislav Petkov 246021afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) 246121afaf18SBorislav Petkov return -EIO; 246221afaf18SBorislav Petkov 246321afaf18SBorislav Petkov dev = per_cpu(mce_device, cpu); 246421afaf18SBorislav Petkov if (dev) 246521afaf18SBorislav Petkov return 0; 246621afaf18SBorislav Petkov 246721afaf18SBorislav Petkov dev = kzalloc(sizeof(*dev), GFP_KERNEL); 246821afaf18SBorislav Petkov if (!dev) 246921afaf18SBorislav Petkov return -ENOMEM; 247021afaf18SBorislav Petkov dev->id = cpu; 247121afaf18SBorislav Petkov dev->bus = &mce_subsys; 247221afaf18SBorislav Petkov dev->release = &mce_device_release; 247321afaf18SBorislav Petkov 247421afaf18SBorislav Petkov err = device_register(dev); 247521afaf18SBorislav Petkov if (err) { 247621afaf18SBorislav Petkov put_device(dev); 247721afaf18SBorislav Petkov return err; 247821afaf18SBorislav Petkov } 247921afaf18SBorislav Petkov 248021afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) { 248121afaf18SBorislav Petkov err = device_create_file(dev, mce_device_attrs[i]); 248221afaf18SBorislav Petkov if (err) 248321afaf18SBorislav Petkov goto error; 248421afaf18SBorislav Petkov } 2485c7d314f3SYazen Ghannam for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) { 2486b4914508SYazen Ghannam err = device_create_file(dev, &mce_bank_devs[j].attr); 248721afaf18SBorislav Petkov if (err) 248821afaf18SBorislav Petkov goto error2; 248921afaf18SBorislav Petkov } 249021afaf18SBorislav Petkov cpumask_set_cpu(cpu, mce_device_initialized); 249121afaf18SBorislav Petkov per_cpu(mce_device, cpu) = dev; 249221afaf18SBorislav Petkov 249321afaf18SBorislav Petkov return 0; 249421afaf18SBorislav Petkov error2: 249521afaf18SBorislav Petkov while (--j >= 0) 2496b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[j].attr); 249721afaf18SBorislav Petkov error: 249821afaf18SBorislav Petkov while (--i >= 0) 249921afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 250021afaf18SBorislav Petkov 250121afaf18SBorislav Petkov device_unregister(dev); 250221afaf18SBorislav Petkov 250321afaf18SBorislav Petkov return err; 250421afaf18SBorislav Petkov } 250521afaf18SBorislav Petkov 250621afaf18SBorislav Petkov static void mce_device_remove(unsigned int cpu) 250721afaf18SBorislav Petkov { 250821afaf18SBorislav Petkov struct device *dev = per_cpu(mce_device, cpu); 250921afaf18SBorislav Petkov int i; 251021afaf18SBorislav Petkov 251121afaf18SBorislav Petkov if (!cpumask_test_cpu(cpu, mce_device_initialized)) 251221afaf18SBorislav Petkov return; 251321afaf18SBorislav Petkov 251421afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) 251521afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 251621afaf18SBorislav Petkov 2517c7d314f3SYazen Ghannam for (i = 0; i < per_cpu(mce_num_banks, cpu); i++) 2518b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[i].attr); 251921afaf18SBorislav Petkov 252021afaf18SBorislav Petkov device_unregister(dev); 252121afaf18SBorislav Petkov cpumask_clear_cpu(cpu, mce_device_initialized); 252221afaf18SBorislav Petkov per_cpu(mce_device, cpu) = NULL; 252321afaf18SBorislav Petkov } 252421afaf18SBorislav Petkov 252521afaf18SBorislav Petkov /* Make sure there are no machine checks on offlined CPUs. */ 252621afaf18SBorislav Petkov static void mce_disable_cpu(void) 252721afaf18SBorislav Petkov { 252821afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 252921afaf18SBorislav Petkov return; 253021afaf18SBorislav Petkov 253121afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 253221afaf18SBorislav Petkov cmci_clear(); 253321afaf18SBorislav Petkov 253421afaf18SBorislav Petkov vendor_disable_error_reporting(); 253521afaf18SBorislav Petkov } 253621afaf18SBorislav Petkov 253721afaf18SBorislav Petkov static void mce_reenable_cpu(void) 253821afaf18SBorislav Petkov { 2539b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 254021afaf18SBorislav Petkov int i; 254121afaf18SBorislav Petkov 254221afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 254321afaf18SBorislav Petkov return; 254421afaf18SBorislav Petkov 254521afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 254621afaf18SBorislav Petkov cmci_reenable(); 2547c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 254821afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 254921afaf18SBorislav Petkov 255021afaf18SBorislav Petkov if (b->init) 25518121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); 255221afaf18SBorislav Petkov } 255321afaf18SBorislav Petkov } 255421afaf18SBorislav Petkov 255521afaf18SBorislav Petkov static int mce_cpu_dead(unsigned int cpu) 255621afaf18SBorislav Petkov { 255721afaf18SBorislav Petkov mce_intel_hcpu_update(cpu); 255821afaf18SBorislav Petkov 255921afaf18SBorislav Petkov /* intentionally ignoring frozen here */ 256021afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 256121afaf18SBorislav Petkov cmci_rediscover(); 256221afaf18SBorislav Petkov return 0; 256321afaf18SBorislav Petkov } 256421afaf18SBorislav Petkov 256521afaf18SBorislav Petkov static int mce_cpu_online(unsigned int cpu) 256621afaf18SBorislav Petkov { 256721afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 256821afaf18SBorislav Petkov int ret; 256921afaf18SBorislav Petkov 257021afaf18SBorislav Petkov mce_device_create(cpu); 257121afaf18SBorislav Petkov 257221afaf18SBorislav Petkov ret = mce_threshold_create_device(cpu); 257321afaf18SBorislav Petkov if (ret) { 257421afaf18SBorislav Petkov mce_device_remove(cpu); 257521afaf18SBorislav Petkov return ret; 257621afaf18SBorislav Petkov } 257721afaf18SBorislav Petkov mce_reenable_cpu(); 257821afaf18SBorislav Petkov mce_start_timer(t); 257921afaf18SBorislav Petkov return 0; 258021afaf18SBorislav Petkov } 258121afaf18SBorislav Petkov 258221afaf18SBorislav Petkov static int mce_cpu_pre_down(unsigned int cpu) 258321afaf18SBorislav Petkov { 258421afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 258521afaf18SBorislav Petkov 258621afaf18SBorislav Petkov mce_disable_cpu(); 258721afaf18SBorislav Petkov del_timer_sync(t); 258821afaf18SBorislav Petkov mce_threshold_remove_device(cpu); 258921afaf18SBorislav Petkov mce_device_remove(cpu); 259021afaf18SBorislav Petkov return 0; 259121afaf18SBorislav Petkov } 259221afaf18SBorislav Petkov 259321afaf18SBorislav Petkov static __init void mce_init_banks(void) 259421afaf18SBorislav Petkov { 259521afaf18SBorislav Petkov int i; 259621afaf18SBorislav Petkov 2597b4914508SYazen Ghannam for (i = 0; i < MAX_NR_BANKS; i++) { 2598b4914508SYazen Ghannam struct mce_bank_dev *b = &mce_bank_devs[i]; 259921afaf18SBorislav Petkov struct device_attribute *a = &b->attr; 260021afaf18SBorislav Petkov 2601b4914508SYazen Ghannam b->bank = i; 2602b4914508SYazen Ghannam 260321afaf18SBorislav Petkov sysfs_attr_init(&a->attr); 260421afaf18SBorislav Petkov a->attr.name = b->attrname; 260521afaf18SBorislav Petkov snprintf(b->attrname, ATTR_LEN, "bank%d", i); 260621afaf18SBorislav Petkov 260721afaf18SBorislav Petkov a->attr.mode = 0644; 260821afaf18SBorislav Petkov a->show = show_bank; 260921afaf18SBorislav Petkov a->store = set_bank; 261021afaf18SBorislav Petkov } 261121afaf18SBorislav Petkov } 261221afaf18SBorislav Petkov 26136e7a41c6SThomas Gleixner /* 26146e7a41c6SThomas Gleixner * When running on XEN, this initcall is ordered against the XEN mcelog 26156e7a41c6SThomas Gleixner * initcall: 26166e7a41c6SThomas Gleixner * 26176e7a41c6SThomas Gleixner * device_initcall(xen_late_init_mcelog); 26186e7a41c6SThomas Gleixner * device_initcall_sync(mcheck_init_device); 26196e7a41c6SThomas Gleixner */ 262021afaf18SBorislav Petkov static __init int mcheck_init_device(void) 262121afaf18SBorislav Petkov { 262221afaf18SBorislav Petkov int err; 262321afaf18SBorislav Petkov 262421afaf18SBorislav Petkov /* 262521afaf18SBorislav Petkov * Check if we have a spare virtual bit. This will only become 262621afaf18SBorislav Petkov * a problem if/when we move beyond 5-level page tables. 262721afaf18SBorislav Petkov */ 262821afaf18SBorislav Petkov MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63); 262921afaf18SBorislav Petkov 263021afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) { 263121afaf18SBorislav Petkov err = -EIO; 263221afaf18SBorislav Petkov goto err_out; 263321afaf18SBorislav Petkov } 263421afaf18SBorislav Petkov 263521afaf18SBorislav Petkov if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { 263621afaf18SBorislav Petkov err = -ENOMEM; 263721afaf18SBorislav Petkov goto err_out; 263821afaf18SBorislav Petkov } 263921afaf18SBorislav Petkov 264021afaf18SBorislav Petkov mce_init_banks(); 264121afaf18SBorislav Petkov 264221afaf18SBorislav Petkov err = subsys_system_register(&mce_subsys, NULL); 264321afaf18SBorislav Petkov if (err) 264421afaf18SBorislav Petkov goto err_out_mem; 264521afaf18SBorislav Petkov 264621afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL, 264721afaf18SBorislav Petkov mce_cpu_dead); 264821afaf18SBorislav Petkov if (err) 264921afaf18SBorislav Petkov goto err_out_mem; 265021afaf18SBorislav Petkov 26516e7a41c6SThomas Gleixner /* 26526e7a41c6SThomas Gleixner * Invokes mce_cpu_online() on all CPUs which are online when 26536e7a41c6SThomas Gleixner * the state is installed. 26546e7a41c6SThomas Gleixner */ 265521afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online", 265621afaf18SBorislav Petkov mce_cpu_online, mce_cpu_pre_down); 265721afaf18SBorislav Petkov if (err < 0) 265821afaf18SBorislav Petkov goto err_out_online; 265921afaf18SBorislav Petkov 266021afaf18SBorislav Petkov register_syscore_ops(&mce_syscore_ops); 266121afaf18SBorislav Petkov 266221afaf18SBorislav Petkov return 0; 266321afaf18SBorislav Petkov 266421afaf18SBorislav Petkov err_out_online: 266521afaf18SBorislav Petkov cpuhp_remove_state(CPUHP_X86_MCE_DEAD); 266621afaf18SBorislav Petkov 266721afaf18SBorislav Petkov err_out_mem: 266821afaf18SBorislav Petkov free_cpumask_var(mce_device_initialized); 266921afaf18SBorislav Petkov 267021afaf18SBorislav Petkov err_out: 267121afaf18SBorislav Petkov pr_err("Unable to init MCE device (rc: %d)\n", err); 267221afaf18SBorislav Petkov 267321afaf18SBorislav Petkov return err; 267421afaf18SBorislav Petkov } 267521afaf18SBorislav Petkov device_initcall_sync(mcheck_init_device); 267621afaf18SBorislav Petkov 267721afaf18SBorislav Petkov /* 267821afaf18SBorislav Petkov * Old style boot options parsing. Only for compatibility. 267921afaf18SBorislav Petkov */ 268021afaf18SBorislav Petkov static int __init mcheck_disable(char *str) 268121afaf18SBorislav Petkov { 268221afaf18SBorislav Petkov mca_cfg.disabled = 1; 268321afaf18SBorislav Petkov return 1; 268421afaf18SBorislav Petkov } 268521afaf18SBorislav Petkov __setup("nomce", mcheck_disable); 268621afaf18SBorislav Petkov 268721afaf18SBorislav Petkov #ifdef CONFIG_DEBUG_FS 268821afaf18SBorislav Petkov struct dentry *mce_get_debugfs_dir(void) 268921afaf18SBorislav Petkov { 269021afaf18SBorislav Petkov static struct dentry *dmce; 269121afaf18SBorislav Petkov 269221afaf18SBorislav Petkov if (!dmce) 269321afaf18SBorislav Petkov dmce = debugfs_create_dir("mce", NULL); 269421afaf18SBorislav Petkov 269521afaf18SBorislav Petkov return dmce; 269621afaf18SBorislav Petkov } 269721afaf18SBorislav Petkov 269821afaf18SBorislav Petkov static void mce_reset(void) 269921afaf18SBorislav Petkov { 270021afaf18SBorislav Petkov atomic_set(&mce_fake_panicked, 0); 270121afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 270221afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 270321afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 27047bb39313SPaul E. McKenney cpumask_setall(&mce_missing_cpus); 270521afaf18SBorislav Petkov } 270621afaf18SBorislav Petkov 270721afaf18SBorislav Petkov static int fake_panic_get(void *data, u64 *val) 270821afaf18SBorislav Petkov { 270921afaf18SBorislav Petkov *val = fake_panic; 271021afaf18SBorislav Petkov return 0; 271121afaf18SBorislav Petkov } 271221afaf18SBorislav Petkov 271321afaf18SBorislav Petkov static int fake_panic_set(void *data, u64 val) 271421afaf18SBorislav Petkov { 271521afaf18SBorislav Petkov mce_reset(); 271621afaf18SBorislav Petkov fake_panic = val; 271721afaf18SBorislav Petkov return 0; 271821afaf18SBorislav Petkov } 271921afaf18SBorislav Petkov 272028156d76SYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set, 272128156d76SYueHaibing "%llu\n"); 272221afaf18SBorislav Petkov 27236e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) 272421afaf18SBorislav Petkov { 27256e4f929eSGreg Kroah-Hartman struct dentry *dmce; 272621afaf18SBorislav Petkov 272721afaf18SBorislav Petkov dmce = mce_get_debugfs_dir(); 27286e4f929eSGreg Kroah-Hartman debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL, 27296e4f929eSGreg Kroah-Hartman &fake_panic_fops); 273021afaf18SBorislav Petkov } 273121afaf18SBorislav Petkov #else 27326e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) { } 273321afaf18SBorislav Petkov #endif 273421afaf18SBorislav Petkov 273521afaf18SBorislav Petkov static int __init mcheck_late_init(void) 273621afaf18SBorislav Petkov { 273721afaf18SBorislav Petkov if (mca_cfg.recovery) 2738ec6347bbSDan Williams enable_copy_mc_fragile(); 273921afaf18SBorislav Petkov 274021afaf18SBorislav Petkov mcheck_debugfs_init(); 274121afaf18SBorislav Petkov 274221afaf18SBorislav Petkov /* 274321afaf18SBorislav Petkov * Flush out everything that has been logged during early boot, now that 274421afaf18SBorislav Petkov * everything has been initialized (workqueues, decoders, ...). 274521afaf18SBorislav Petkov */ 274621afaf18SBorislav Petkov mce_schedule_work(); 274721afaf18SBorislav Petkov 274821afaf18SBorislav Petkov return 0; 274921afaf18SBorislav Petkov } 275021afaf18SBorislav Petkov late_initcall(mcheck_late_init); 2751