1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 221afaf18SBorislav Petkov /* 321afaf18SBorislav Petkov * Machine check handler. 421afaf18SBorislav Petkov * 521afaf18SBorislav Petkov * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. 621afaf18SBorislav Petkov * Rest from unknown author(s). 721afaf18SBorislav Petkov * 2004 Andi Kleen. Rewrote most of it. 821afaf18SBorislav Petkov * Copyright 2008 Intel Corporation 921afaf18SBorislav Petkov * Author: Andi Kleen 1021afaf18SBorislav Petkov */ 1121afaf18SBorislav Petkov 1221afaf18SBorislav Petkov #include <linux/thread_info.h> 1321afaf18SBorislav Petkov #include <linux/capability.h> 1421afaf18SBorislav Petkov #include <linux/miscdevice.h> 1521afaf18SBorislav Petkov #include <linux/ratelimit.h> 1621afaf18SBorislav Petkov #include <linux/rcupdate.h> 1721afaf18SBorislav Petkov #include <linux/kobject.h> 1821afaf18SBorislav Petkov #include <linux/uaccess.h> 1921afaf18SBorislav Petkov #include <linux/kdebug.h> 2021afaf18SBorislav Petkov #include <linux/kernel.h> 2121afaf18SBorislav Petkov #include <linux/percpu.h> 2221afaf18SBorislav Petkov #include <linux/string.h> 2321afaf18SBorislav Petkov #include <linux/device.h> 2421afaf18SBorislav Petkov #include <linux/syscore_ops.h> 2521afaf18SBorislav Petkov #include <linux/delay.h> 2621afaf18SBorislav Petkov #include <linux/ctype.h> 2721afaf18SBorislav Petkov #include <linux/sched.h> 2821afaf18SBorislav Petkov #include <linux/sysfs.h> 2921afaf18SBorislav Petkov #include <linux/types.h> 3021afaf18SBorislav Petkov #include <linux/slab.h> 3121afaf18SBorislav Petkov #include <linux/init.h> 3221afaf18SBorislav Petkov #include <linux/kmod.h> 3321afaf18SBorislav Petkov #include <linux/poll.h> 3421afaf18SBorislav Petkov #include <linux/nmi.h> 3521afaf18SBorislav Petkov #include <linux/cpu.h> 3621afaf18SBorislav Petkov #include <linux/ras.h> 3721afaf18SBorislav Petkov #include <linux/smp.h> 3821afaf18SBorislav Petkov #include <linux/fs.h> 3921afaf18SBorislav Petkov #include <linux/mm.h> 4021afaf18SBorislav Petkov #include <linux/debugfs.h> 4121afaf18SBorislav Petkov #include <linux/irq_work.h> 4221afaf18SBorislav Petkov #include <linux/export.h> 4321afaf18SBorislav Petkov #include <linux/jump_label.h> 4421afaf18SBorislav Petkov #include <linux/set_memory.h> 455567d11cSPeter Zijlstra #include <linux/task_work.h> 460d00449cSPeter Zijlstra #include <linux/hardirq.h> 4721afaf18SBorislav Petkov 4821afaf18SBorislav Petkov #include <asm/intel-family.h> 4921afaf18SBorislav Petkov #include <asm/processor.h> 5021afaf18SBorislav Petkov #include <asm/traps.h> 5121afaf18SBorislav Petkov #include <asm/tlbflush.h> 5221afaf18SBorislav Petkov #include <asm/mce.h> 5321afaf18SBorislav Petkov #include <asm/msr.h> 5421afaf18SBorislav Petkov #include <asm/reboot.h> 5521afaf18SBorislav Petkov 5621afaf18SBorislav Petkov #include "internal.h" 5721afaf18SBorislav Petkov 5821afaf18SBorislav Petkov /* sysfs synchronization */ 5921afaf18SBorislav Petkov static DEFINE_MUTEX(mce_sysfs_mutex); 6021afaf18SBorislav Petkov 6121afaf18SBorislav Petkov #define CREATE_TRACE_POINTS 6221afaf18SBorislav Petkov #include <trace/events/mce.h> 6321afaf18SBorislav Petkov 6421afaf18SBorislav Petkov #define SPINUNIT 100 /* 100ns */ 6521afaf18SBorislav Petkov 6621afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_exception_count); 6721afaf18SBorislav Petkov 68c7d314f3SYazen Ghannam DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks); 69c7d314f3SYazen Ghannam 7095fdce6bSYazen Ghannam struct mce_bank { 7195fdce6bSYazen Ghannam u64 ctl; /* subevents to enable */ 7295fdce6bSYazen Ghannam bool init; /* initialise bank? */ 73b4914508SYazen Ghannam }; 74b4914508SYazen Ghannam static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); 75b4914508SYazen Ghannam 76b4914508SYazen Ghannam #define ATTR_LEN 16 77b4914508SYazen Ghannam /* One object for each MCE bank, shared by all CPUs */ 78b4914508SYazen Ghannam struct mce_bank_dev { 7995fdce6bSYazen Ghannam struct device_attribute attr; /* device attribute */ 8095fdce6bSYazen Ghannam char attrname[ATTR_LEN]; /* attribute name */ 81b4914508SYazen Ghannam u8 bank; /* bank number */ 8295fdce6bSYazen Ghannam }; 83b4914508SYazen Ghannam static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS]; 8495fdce6bSYazen Ghannam 8521afaf18SBorislav Petkov struct mce_vendor_flags mce_flags __read_mostly; 8621afaf18SBorislav Petkov 8721afaf18SBorislav Petkov struct mca_config mca_cfg __read_mostly = { 8821afaf18SBorislav Petkov .bootlog = -1, 8921afaf18SBorislav Petkov /* 9021afaf18SBorislav Petkov * Tolerant levels: 9121afaf18SBorislav Petkov * 0: always panic on uncorrected errors, log corrected errors 9221afaf18SBorislav Petkov * 1: panic or SIGBUS on uncorrected errors, log corrected errors 9321afaf18SBorislav Petkov * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors 9421afaf18SBorislav Petkov * 3: never panic or SIGBUS, log all errors (for testing only) 9521afaf18SBorislav Petkov */ 9621afaf18SBorislav Petkov .tolerant = 1, 9721afaf18SBorislav Petkov .monarch_timeout = -1 9821afaf18SBorislav Petkov }; 9921afaf18SBorislav Petkov 10021afaf18SBorislav Petkov static DEFINE_PER_CPU(struct mce, mces_seen); 10121afaf18SBorislav Petkov static unsigned long mce_need_notify; 10221afaf18SBorislav Petkov static int cpu_missing; 10321afaf18SBorislav Petkov 10421afaf18SBorislav Petkov /* 10521afaf18SBorislav Petkov * MCA banks polled by the period polling timer for corrected events. 10621afaf18SBorislav Petkov * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). 10721afaf18SBorislav Petkov */ 10821afaf18SBorislav Petkov DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { 10921afaf18SBorislav Petkov [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL 11021afaf18SBorislav Petkov }; 11121afaf18SBorislav Petkov 11221afaf18SBorislav Petkov /* 11321afaf18SBorislav Petkov * MCA banks controlled through firmware first for corrected errors. 11421afaf18SBorislav Petkov * This is a global list of banks for which we won't enable CMCI and we 11521afaf18SBorislav Petkov * won't poll. Firmware controls these banks and is responsible for 11621afaf18SBorislav Petkov * reporting corrected errors through GHES. Uncorrected/recoverable 11721afaf18SBorislav Petkov * errors are still notified through a machine check. 11821afaf18SBorislav Petkov */ 11921afaf18SBorislav Petkov mce_banks_t mce_banks_ce_disabled; 12021afaf18SBorislav Petkov 12121afaf18SBorislav Petkov static struct work_struct mce_work; 12221afaf18SBorislav Petkov static struct irq_work mce_irq_work; 12321afaf18SBorislav Petkov 12421afaf18SBorislav Petkov static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); 12521afaf18SBorislav Petkov 12621afaf18SBorislav Petkov /* 12721afaf18SBorislav Petkov * CPU/chipset specific EDAC code can register a notifier call here to print 12821afaf18SBorislav Petkov * MCE errors in a human-readable form. 12921afaf18SBorislav Petkov */ 13021afaf18SBorislav Petkov BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); 13121afaf18SBorislav Petkov 13221afaf18SBorislav Petkov /* Do initial initialization of a struct mce */ 133865d3a9aSThomas Gleixner noinstr void mce_setup(struct mce *m) 13421afaf18SBorislav Petkov { 13521afaf18SBorislav Petkov memset(m, 0, sizeof(struct mce)); 13621afaf18SBorislav Petkov m->cpu = m->extcpu = smp_processor_id(); 13721afaf18SBorislav Petkov /* need the internal __ version to avoid deadlocks */ 13821afaf18SBorislav Petkov m->time = __ktime_get_real_seconds(); 13921afaf18SBorislav Petkov m->cpuvendor = boot_cpu_data.x86_vendor; 14021afaf18SBorislav Petkov m->cpuid = cpuid_eax(1); 14121afaf18SBorislav Petkov m->socketid = cpu_data(m->extcpu).phys_proc_id; 14221afaf18SBorislav Petkov m->apicid = cpu_data(m->extcpu).initial_apicid; 143865d3a9aSThomas Gleixner m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); 14421afaf18SBorislav Petkov 14521afaf18SBorislav Petkov if (this_cpu_has(X86_FEATURE_INTEL_PPIN)) 146865d3a9aSThomas Gleixner m->ppin = __rdmsr(MSR_PPIN); 147077168e2SWei Huang else if (this_cpu_has(X86_FEATURE_AMD_PPIN)) 148865d3a9aSThomas Gleixner m->ppin = __rdmsr(MSR_AMD_PPIN); 14921afaf18SBorislav Petkov 15021afaf18SBorislav Petkov m->microcode = boot_cpu_data.microcode; 15121afaf18SBorislav Petkov } 15221afaf18SBorislav Petkov 15321afaf18SBorislav Petkov DEFINE_PER_CPU(struct mce, injectm); 15421afaf18SBorislav Petkov EXPORT_PER_CPU_SYMBOL_GPL(injectm); 15521afaf18SBorislav Petkov 15621afaf18SBorislav Petkov void mce_log(struct mce *m) 15721afaf18SBorislav Petkov { 15821afaf18SBorislav Petkov if (!mce_gen_pool_add(m)) 15921afaf18SBorislav Petkov irq_work_queue(&mce_irq_work); 16021afaf18SBorislav Petkov } 16181736abdSJan H. Schönherr EXPORT_SYMBOL_GPL(mce_log); 16221afaf18SBorislav Petkov 16321afaf18SBorislav Petkov /* 1648438b84aSJan H. Schönherr * We run the default notifier if we have only the UC, the first and the 16521afaf18SBorislav Petkov * default notifier registered. I.e., the mandatory NUM_DEFAULT_NOTIFIERS 16621afaf18SBorislav Petkov * notifiers registered on the chain. 16721afaf18SBorislav Petkov */ 16821afaf18SBorislav Petkov #define NUM_DEFAULT_NOTIFIERS 3 16921afaf18SBorislav Petkov static atomic_t num_notifiers; 17021afaf18SBorislav Petkov 17121afaf18SBorislav Petkov void mce_register_decode_chain(struct notifier_block *nb) 17221afaf18SBorislav Petkov { 17321afaf18SBorislav Petkov if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC)) 17421afaf18SBorislav Petkov return; 17521afaf18SBorislav Petkov 17621afaf18SBorislav Petkov atomic_inc(&num_notifiers); 17721afaf18SBorislav Petkov 17821afaf18SBorislav Petkov blocking_notifier_chain_register(&x86_mce_decoder_chain, nb); 17921afaf18SBorislav Petkov } 18021afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_register_decode_chain); 18121afaf18SBorislav Petkov 18221afaf18SBorislav Petkov void mce_unregister_decode_chain(struct notifier_block *nb) 18321afaf18SBorislav Petkov { 18421afaf18SBorislav Petkov atomic_dec(&num_notifiers); 18521afaf18SBorislav Petkov 18621afaf18SBorislav Petkov blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb); 18721afaf18SBorislav Petkov } 18821afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); 18921afaf18SBorislav Petkov 19021afaf18SBorislav Petkov static inline u32 ctl_reg(int bank) 19121afaf18SBorislav Petkov { 19221afaf18SBorislav Petkov return MSR_IA32_MCx_CTL(bank); 19321afaf18SBorislav Petkov } 19421afaf18SBorislav Petkov 19521afaf18SBorislav Petkov static inline u32 status_reg(int bank) 19621afaf18SBorislav Petkov { 19721afaf18SBorislav Petkov return MSR_IA32_MCx_STATUS(bank); 19821afaf18SBorislav Petkov } 19921afaf18SBorislav Petkov 20021afaf18SBorislav Petkov static inline u32 addr_reg(int bank) 20121afaf18SBorislav Petkov { 20221afaf18SBorislav Petkov return MSR_IA32_MCx_ADDR(bank); 20321afaf18SBorislav Petkov } 20421afaf18SBorislav Petkov 20521afaf18SBorislav Petkov static inline u32 misc_reg(int bank) 20621afaf18SBorislav Petkov { 20721afaf18SBorislav Petkov return MSR_IA32_MCx_MISC(bank); 20821afaf18SBorislav Petkov } 20921afaf18SBorislav Petkov 21021afaf18SBorislav Petkov static inline u32 smca_ctl_reg(int bank) 21121afaf18SBorislav Petkov { 21221afaf18SBorislav Petkov return MSR_AMD64_SMCA_MCx_CTL(bank); 21321afaf18SBorislav Petkov } 21421afaf18SBorislav Petkov 21521afaf18SBorislav Petkov static inline u32 smca_status_reg(int bank) 21621afaf18SBorislav Petkov { 21721afaf18SBorislav Petkov return MSR_AMD64_SMCA_MCx_STATUS(bank); 21821afaf18SBorislav Petkov } 21921afaf18SBorislav Petkov 22021afaf18SBorislav Petkov static inline u32 smca_addr_reg(int bank) 22121afaf18SBorislav Petkov { 22221afaf18SBorislav Petkov return MSR_AMD64_SMCA_MCx_ADDR(bank); 22321afaf18SBorislav Petkov } 22421afaf18SBorislav Petkov 22521afaf18SBorislav Petkov static inline u32 smca_misc_reg(int bank) 22621afaf18SBorislav Petkov { 22721afaf18SBorislav Petkov return MSR_AMD64_SMCA_MCx_MISC(bank); 22821afaf18SBorislav Petkov } 22921afaf18SBorislav Petkov 23021afaf18SBorislav Petkov struct mca_msr_regs msr_ops = { 23121afaf18SBorislav Petkov .ctl = ctl_reg, 23221afaf18SBorislav Petkov .status = status_reg, 23321afaf18SBorislav Petkov .addr = addr_reg, 23421afaf18SBorislav Petkov .misc = misc_reg 23521afaf18SBorislav Petkov }; 23621afaf18SBorislav Petkov 23721afaf18SBorislav Petkov static void __print_mce(struct mce *m) 23821afaf18SBorislav Petkov { 23921afaf18SBorislav Petkov pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", 24021afaf18SBorislav Petkov m->extcpu, 24121afaf18SBorislav Petkov (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""), 24221afaf18SBorislav Petkov m->mcgstatus, m->bank, m->status); 24321afaf18SBorislav Petkov 24421afaf18SBorislav Petkov if (m->ip) { 24521afaf18SBorislav Petkov pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", 24621afaf18SBorislav Petkov !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", 24721afaf18SBorislav Petkov m->cs, m->ip); 24821afaf18SBorislav Petkov 24921afaf18SBorislav Petkov if (m->cs == __KERNEL_CS) 25021afaf18SBorislav Petkov pr_cont("{%pS}", (void *)(unsigned long)m->ip); 25121afaf18SBorislav Petkov pr_cont("\n"); 25221afaf18SBorislav Petkov } 25321afaf18SBorislav Petkov 25421afaf18SBorislav Petkov pr_emerg(HW_ERR "TSC %llx ", m->tsc); 25521afaf18SBorislav Petkov if (m->addr) 25621afaf18SBorislav Petkov pr_cont("ADDR %llx ", m->addr); 25721afaf18SBorislav Petkov if (m->misc) 25821afaf18SBorislav Petkov pr_cont("MISC %llx ", m->misc); 25921afaf18SBorislav Petkov 26021afaf18SBorislav Petkov if (mce_flags.smca) { 26121afaf18SBorislav Petkov if (m->synd) 26221afaf18SBorislav Petkov pr_cont("SYND %llx ", m->synd); 26321afaf18SBorislav Petkov if (m->ipid) 26421afaf18SBorislav Petkov pr_cont("IPID %llx ", m->ipid); 26521afaf18SBorislav Petkov } 26621afaf18SBorislav Petkov 26721afaf18SBorislav Petkov pr_cont("\n"); 26821afaf18SBorislav Petkov /* 26921afaf18SBorislav Petkov * Note this output is parsed by external tools and old fields 27021afaf18SBorislav Petkov * should not be changed. 27121afaf18SBorislav Petkov */ 27221afaf18SBorislav Petkov pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", 27321afaf18SBorislav Petkov m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, 27421afaf18SBorislav Petkov m->microcode); 27521afaf18SBorislav Petkov } 27621afaf18SBorislav Petkov 27721afaf18SBorislav Petkov static void print_mce(struct mce *m) 27821afaf18SBorislav Petkov { 27921afaf18SBorislav Petkov __print_mce(m); 28021afaf18SBorislav Petkov 28121afaf18SBorislav Petkov if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON) 28221afaf18SBorislav Petkov pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); 28321afaf18SBorislav Petkov } 28421afaf18SBorislav Petkov 28521afaf18SBorislav Petkov #define PANIC_TIMEOUT 5 /* 5 seconds */ 28621afaf18SBorislav Petkov 28721afaf18SBorislav Petkov static atomic_t mce_panicked; 28821afaf18SBorislav Petkov 28921afaf18SBorislav Petkov static int fake_panic; 29021afaf18SBorislav Petkov static atomic_t mce_fake_panicked; 29121afaf18SBorislav Petkov 29221afaf18SBorislav Petkov /* Panic in progress. Enable interrupts and wait for final IPI */ 29321afaf18SBorislav Petkov static void wait_for_panic(void) 29421afaf18SBorislav Petkov { 29521afaf18SBorislav Petkov long timeout = PANIC_TIMEOUT*USEC_PER_SEC; 29621afaf18SBorislav Petkov 29721afaf18SBorislav Petkov preempt_disable(); 29821afaf18SBorislav Petkov local_irq_enable(); 29921afaf18SBorislav Petkov while (timeout-- > 0) 30021afaf18SBorislav Petkov udelay(1); 30121afaf18SBorislav Petkov if (panic_timeout == 0) 30221afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 30321afaf18SBorislav Petkov panic("Panicing machine check CPU died"); 30421afaf18SBorislav Petkov } 30521afaf18SBorislav Petkov 30621afaf18SBorislav Petkov static void mce_panic(const char *msg, struct mce *final, char *exp) 30721afaf18SBorislav Petkov { 30821afaf18SBorislav Petkov int apei_err = 0; 30921afaf18SBorislav Petkov struct llist_node *pending; 31021afaf18SBorislav Petkov struct mce_evt_llist *l; 31121afaf18SBorislav Petkov 31221afaf18SBorislav Petkov if (!fake_panic) { 31321afaf18SBorislav Petkov /* 31421afaf18SBorislav Petkov * Make sure only one CPU runs in machine check panic 31521afaf18SBorislav Petkov */ 31621afaf18SBorislav Petkov if (atomic_inc_return(&mce_panicked) > 1) 31721afaf18SBorislav Petkov wait_for_panic(); 31821afaf18SBorislav Petkov barrier(); 31921afaf18SBorislav Petkov 32021afaf18SBorislav Petkov bust_spinlocks(1); 32121afaf18SBorislav Petkov console_verbose(); 32221afaf18SBorislav Petkov } else { 32321afaf18SBorislav Petkov /* Don't log too much for fake panic */ 32421afaf18SBorislav Petkov if (atomic_inc_return(&mce_fake_panicked) > 1) 32521afaf18SBorislav Petkov return; 32621afaf18SBorislav Petkov } 32721afaf18SBorislav Petkov pending = mce_gen_pool_prepare_records(); 32821afaf18SBorislav Petkov /* First print corrected ones that are still unlogged */ 32921afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 33021afaf18SBorislav Petkov struct mce *m = &l->mce; 33121afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) { 33221afaf18SBorislav Petkov print_mce(m); 33321afaf18SBorislav Petkov if (!apei_err) 33421afaf18SBorislav Petkov apei_err = apei_write_mce(m); 33521afaf18SBorislav Petkov } 33621afaf18SBorislav Petkov } 33721afaf18SBorislav Petkov /* Now print uncorrected but with the final one last */ 33821afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 33921afaf18SBorislav Petkov struct mce *m = &l->mce; 34021afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) 34121afaf18SBorislav Petkov continue; 34221afaf18SBorislav Petkov if (!final || mce_cmp(m, final)) { 34321afaf18SBorislav Petkov print_mce(m); 34421afaf18SBorislav Petkov if (!apei_err) 34521afaf18SBorislav Petkov apei_err = apei_write_mce(m); 34621afaf18SBorislav Petkov } 34721afaf18SBorislav Petkov } 34821afaf18SBorislav Petkov if (final) { 34921afaf18SBorislav Petkov print_mce(final); 35021afaf18SBorislav Petkov if (!apei_err) 35121afaf18SBorislav Petkov apei_err = apei_write_mce(final); 35221afaf18SBorislav Petkov } 35321afaf18SBorislav Petkov if (cpu_missing) 35421afaf18SBorislav Petkov pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); 35521afaf18SBorislav Petkov if (exp) 35621afaf18SBorislav Petkov pr_emerg(HW_ERR "Machine check: %s\n", exp); 35721afaf18SBorislav Petkov if (!fake_panic) { 35821afaf18SBorislav Petkov if (panic_timeout == 0) 35921afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 36021afaf18SBorislav Petkov panic(msg); 36121afaf18SBorislav Petkov } else 36221afaf18SBorislav Petkov pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); 36321afaf18SBorislav Petkov } 36421afaf18SBorislav Petkov 36521afaf18SBorislav Petkov /* Support code for software error injection */ 36621afaf18SBorislav Petkov 36721afaf18SBorislav Petkov static int msr_to_offset(u32 msr) 36821afaf18SBorislav Petkov { 36921afaf18SBorislav Petkov unsigned bank = __this_cpu_read(injectm.bank); 37021afaf18SBorislav Petkov 37121afaf18SBorislav Petkov if (msr == mca_cfg.rip_msr) 37221afaf18SBorislav Petkov return offsetof(struct mce, ip); 37321afaf18SBorislav Petkov if (msr == msr_ops.status(bank)) 37421afaf18SBorislav Petkov return offsetof(struct mce, status); 37521afaf18SBorislav Petkov if (msr == msr_ops.addr(bank)) 37621afaf18SBorislav Petkov return offsetof(struct mce, addr); 37721afaf18SBorislav Petkov if (msr == msr_ops.misc(bank)) 37821afaf18SBorislav Petkov return offsetof(struct mce, misc); 37921afaf18SBorislav Petkov if (msr == MSR_IA32_MCG_STATUS) 38021afaf18SBorislav Petkov return offsetof(struct mce, mcgstatus); 38121afaf18SBorislav Petkov return -1; 38221afaf18SBorislav Petkov } 38321afaf18SBorislav Petkov 38421afaf18SBorislav Petkov /* MSR access wrappers used for error injection */ 38521afaf18SBorislav Petkov static u64 mce_rdmsrl(u32 msr) 38621afaf18SBorislav Petkov { 38721afaf18SBorislav Petkov u64 v; 38821afaf18SBorislav Petkov 38921afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 39021afaf18SBorislav Petkov int offset = msr_to_offset(msr); 39121afaf18SBorislav Petkov 39221afaf18SBorislav Petkov if (offset < 0) 39321afaf18SBorislav Petkov return 0; 39421afaf18SBorislav Petkov return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); 39521afaf18SBorislav Petkov } 39621afaf18SBorislav Petkov 39721afaf18SBorislav Petkov if (rdmsrl_safe(msr, &v)) { 39821afaf18SBorislav Petkov WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr); 39921afaf18SBorislav Petkov /* 40021afaf18SBorislav Petkov * Return zero in case the access faulted. This should 40121afaf18SBorislav Petkov * not happen normally but can happen if the CPU does 40221afaf18SBorislav Petkov * something weird, or if the code is buggy. 40321afaf18SBorislav Petkov */ 40421afaf18SBorislav Petkov v = 0; 40521afaf18SBorislav Petkov } 40621afaf18SBorislav Petkov 40721afaf18SBorislav Petkov return v; 40821afaf18SBorislav Petkov } 40921afaf18SBorislav Petkov 41021afaf18SBorislav Petkov static void mce_wrmsrl(u32 msr, u64 v) 41121afaf18SBorislav Petkov { 41221afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 41321afaf18SBorislav Petkov int offset = msr_to_offset(msr); 41421afaf18SBorislav Petkov 41521afaf18SBorislav Petkov if (offset >= 0) 41621afaf18SBorislav Petkov *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; 41721afaf18SBorislav Petkov return; 41821afaf18SBorislav Petkov } 41921afaf18SBorislav Petkov wrmsrl(msr, v); 42021afaf18SBorislav Petkov } 42121afaf18SBorislav Petkov 42221afaf18SBorislav Petkov /* 42321afaf18SBorislav Petkov * Collect all global (w.r.t. this processor) status about this machine 42421afaf18SBorislav Petkov * check into our "mce" struct so that we can use it later to assess 42521afaf18SBorislav Petkov * the severity of the problem as we read per-bank specific details. 42621afaf18SBorislav Petkov */ 42721afaf18SBorislav Petkov static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) 42821afaf18SBorislav Petkov { 42921afaf18SBorislav Petkov mce_setup(m); 43021afaf18SBorislav Petkov 43121afaf18SBorislav Petkov m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 43221afaf18SBorislav Petkov if (regs) { 43321afaf18SBorislav Petkov /* 43421afaf18SBorislav Petkov * Get the address of the instruction at the time of 43521afaf18SBorislav Petkov * the machine check error. 43621afaf18SBorislav Petkov */ 43721afaf18SBorislav Petkov if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { 43821afaf18SBorislav Petkov m->ip = regs->ip; 43921afaf18SBorislav Petkov m->cs = regs->cs; 44021afaf18SBorislav Petkov 44121afaf18SBorislav Petkov /* 44221afaf18SBorislav Petkov * When in VM86 mode make the cs look like ring 3 44321afaf18SBorislav Petkov * always. This is a lie, but it's better than passing 44421afaf18SBorislav Petkov * the additional vm86 bit around everywhere. 44521afaf18SBorislav Petkov */ 44621afaf18SBorislav Petkov if (v8086_mode(regs)) 44721afaf18SBorislav Petkov m->cs |= 3; 44821afaf18SBorislav Petkov } 44921afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 45021afaf18SBorislav Petkov if (mca_cfg.rip_msr) 45121afaf18SBorislav Petkov m->ip = mce_rdmsrl(mca_cfg.rip_msr); 45221afaf18SBorislav Petkov } 45321afaf18SBorislav Petkov } 45421afaf18SBorislav Petkov 45521afaf18SBorislav Petkov int mce_available(struct cpuinfo_x86 *c) 45621afaf18SBorislav Petkov { 45721afaf18SBorislav Petkov if (mca_cfg.disabled) 45821afaf18SBorislav Petkov return 0; 45921afaf18SBorislav Petkov return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); 46021afaf18SBorislav Petkov } 46121afaf18SBorislav Petkov 46221afaf18SBorislav Petkov static void mce_schedule_work(void) 46321afaf18SBorislav Petkov { 46421afaf18SBorislav Petkov if (!mce_gen_pool_empty()) 46521afaf18SBorislav Petkov schedule_work(&mce_work); 46621afaf18SBorislav Petkov } 46721afaf18SBorislav Petkov 46821afaf18SBorislav Petkov static void mce_irq_work_cb(struct irq_work *entry) 46921afaf18SBorislav Petkov { 47021afaf18SBorislav Petkov mce_schedule_work(); 47121afaf18SBorislav Petkov } 47221afaf18SBorislav Petkov 47321afaf18SBorislav Petkov /* 47421afaf18SBorislav Petkov * Check if the address reported by the CPU is in a format we can parse. 47521afaf18SBorislav Petkov * It would be possible to add code for most other cases, but all would 47621afaf18SBorislav Petkov * be somewhat complicated (e.g. segment offset would require an instruction 47721afaf18SBorislav Petkov * parser). So only support physical addresses up to page granuality for now. 47821afaf18SBorislav Petkov */ 47921afaf18SBorislav Petkov int mce_usable_address(struct mce *m) 48021afaf18SBorislav Petkov { 48121afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_ADDRV)) 48221afaf18SBorislav Petkov return 0; 48321afaf18SBorislav Petkov 4846e898d2bSTony W Wang-oc /* Checks after this one are Intel/Zhaoxin-specific: */ 4856e898d2bSTony W Wang-oc if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && 4866e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) 48721afaf18SBorislav Petkov return 1; 48821afaf18SBorislav Petkov 48921afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_MISCV)) 49021afaf18SBorislav Petkov return 0; 49121afaf18SBorislav Petkov 49221afaf18SBorislav Petkov if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) 49321afaf18SBorislav Petkov return 0; 49421afaf18SBorislav Petkov 49521afaf18SBorislav Petkov if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) 49621afaf18SBorislav Petkov return 0; 49721afaf18SBorislav Petkov 49821afaf18SBorislav Petkov return 1; 49921afaf18SBorislav Petkov } 50021afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_usable_address); 50121afaf18SBorislav Petkov 50221afaf18SBorislav Petkov bool mce_is_memory_error(struct mce *m) 50321afaf18SBorislav Petkov { 5046e898d2bSTony W Wang-oc switch (m->cpuvendor) { 5056e898d2bSTony W Wang-oc case X86_VENDOR_AMD: 5066e898d2bSTony W Wang-oc case X86_VENDOR_HYGON: 50721afaf18SBorislav Petkov return amd_mce_is_memory_error(m); 5086e898d2bSTony W Wang-oc 5096e898d2bSTony W Wang-oc case X86_VENDOR_INTEL: 5106e898d2bSTony W Wang-oc case X86_VENDOR_ZHAOXIN: 51121afaf18SBorislav Petkov /* 51221afaf18SBorislav Petkov * Intel SDM Volume 3B - 15.9.2 Compound Error Codes 51321afaf18SBorislav Petkov * 51421afaf18SBorislav Petkov * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for 51521afaf18SBorislav Petkov * indicating a memory error. Bit 8 is used for indicating a 51621afaf18SBorislav Petkov * cache hierarchy error. The combination of bit 2 and bit 3 51721afaf18SBorislav Petkov * is used for indicating a `generic' cache hierarchy error 51821afaf18SBorislav Petkov * But we can't just blindly check the above bits, because if 51921afaf18SBorislav Petkov * bit 11 is set, then it is a bus/interconnect error - and 52021afaf18SBorislav Petkov * either way the above bits just gives more detail on what 52121afaf18SBorislav Petkov * bus/interconnect error happened. Note that bit 12 can be 52221afaf18SBorislav Petkov * ignored, as it's the "filter" bit. 52321afaf18SBorislav Petkov */ 52421afaf18SBorislav Petkov return (m->status & 0xef80) == BIT(7) || 52521afaf18SBorislav Petkov (m->status & 0xef00) == BIT(8) || 52621afaf18SBorislav Petkov (m->status & 0xeffc) == 0xc; 52721afaf18SBorislav Petkov 5286e898d2bSTony W Wang-oc default: 52921afaf18SBorislav Petkov return false; 53021afaf18SBorislav Petkov } 5316e898d2bSTony W Wang-oc } 53221afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_memory_error); 53321afaf18SBorislav Petkov 53421afaf18SBorislav Petkov bool mce_is_correctable(struct mce *m) 53521afaf18SBorislav Petkov { 53621afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED) 53721afaf18SBorislav Petkov return false; 53821afaf18SBorislav Petkov 53921afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED) 54021afaf18SBorislav Petkov return false; 54121afaf18SBorislav Petkov 54221afaf18SBorislav Petkov if (m->status & MCI_STATUS_UC) 54321afaf18SBorislav Petkov return false; 54421afaf18SBorislav Petkov 54521afaf18SBorislav Petkov return true; 54621afaf18SBorislav Petkov } 54721afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_correctable); 54821afaf18SBorislav Petkov 54921afaf18SBorislav Petkov static bool cec_add_mce(struct mce *m) 55021afaf18SBorislav Petkov { 55121afaf18SBorislav Petkov if (!m) 55221afaf18SBorislav Petkov return false; 55321afaf18SBorislav Petkov 55421afaf18SBorislav Petkov /* We eat only correctable DRAM errors with usable addresses. */ 55521afaf18SBorislav Petkov if (mce_is_memory_error(m) && 55621afaf18SBorislav Petkov mce_is_correctable(m) && 55721afaf18SBorislav Petkov mce_usable_address(m)) 55821afaf18SBorislav Petkov if (!cec_add_elem(m->addr >> PAGE_SHIFT)) 55921afaf18SBorislav Petkov return true; 56021afaf18SBorislav Petkov 56121afaf18SBorislav Petkov return false; 56221afaf18SBorislav Petkov } 56321afaf18SBorislav Petkov 56421afaf18SBorislav Petkov static int mce_first_notifier(struct notifier_block *nb, unsigned long val, 56521afaf18SBorislav Petkov void *data) 56621afaf18SBorislav Petkov { 56721afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 56821afaf18SBorislav Petkov 56921afaf18SBorislav Petkov if (!m) 57021afaf18SBorislav Petkov return NOTIFY_DONE; 57121afaf18SBorislav Petkov 57221afaf18SBorislav Petkov if (cec_add_mce(m)) 57321afaf18SBorislav Petkov return NOTIFY_STOP; 57421afaf18SBorislav Petkov 57521afaf18SBorislav Petkov /* Emit the trace record: */ 57621afaf18SBorislav Petkov trace_mce_record(m); 57721afaf18SBorislav Petkov 57821afaf18SBorislav Petkov set_bit(0, &mce_need_notify); 57921afaf18SBorislav Petkov 58021afaf18SBorislav Petkov mce_notify_irq(); 58121afaf18SBorislav Petkov 58221afaf18SBorislav Petkov return NOTIFY_DONE; 58321afaf18SBorislav Petkov } 58421afaf18SBorislav Petkov 58521afaf18SBorislav Petkov static struct notifier_block first_nb = { 58621afaf18SBorislav Petkov .notifier_call = mce_first_notifier, 58721afaf18SBorislav Petkov .priority = MCE_PRIO_FIRST, 58821afaf18SBorislav Petkov }; 58921afaf18SBorislav Petkov 5908438b84aSJan H. Schönherr static int uc_decode_notifier(struct notifier_block *nb, unsigned long val, 59121afaf18SBorislav Petkov void *data) 59221afaf18SBorislav Petkov { 59321afaf18SBorislav Petkov struct mce *mce = (struct mce *)data; 59421afaf18SBorislav Petkov unsigned long pfn; 59521afaf18SBorislav Petkov 5968438b84aSJan H. Schönherr if (!mce || !mce_usable_address(mce)) 59721afaf18SBorislav Petkov return NOTIFY_DONE; 59821afaf18SBorislav Petkov 5998438b84aSJan H. Schönherr if (mce->severity != MCE_AO_SEVERITY && 6008438b84aSJan H. Schönherr mce->severity != MCE_DEFERRED_SEVERITY) 6018438b84aSJan H. Schönherr return NOTIFY_DONE; 6028438b84aSJan H. Schönherr 60321afaf18SBorislav Petkov pfn = mce->addr >> PAGE_SHIFT; 60421afaf18SBorislav Petkov if (!memory_failure(pfn, 0)) 60521afaf18SBorislav Petkov set_mce_nospec(pfn); 60621afaf18SBorislav Petkov 60721afaf18SBorislav Petkov return NOTIFY_OK; 60821afaf18SBorislav Petkov } 6098438b84aSJan H. Schönherr 6108438b84aSJan H. Schönherr static struct notifier_block mce_uc_nb = { 6118438b84aSJan H. Schönherr .notifier_call = uc_decode_notifier, 6128438b84aSJan H. Schönherr .priority = MCE_PRIO_UC, 61321afaf18SBorislav Petkov }; 61421afaf18SBorislav Petkov 61521afaf18SBorislav Petkov static int mce_default_notifier(struct notifier_block *nb, unsigned long val, 61621afaf18SBorislav Petkov void *data) 61721afaf18SBorislav Petkov { 61821afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 61921afaf18SBorislav Petkov 62021afaf18SBorislav Petkov if (!m) 62121afaf18SBorislav Petkov return NOTIFY_DONE; 62221afaf18SBorislav Petkov 62321afaf18SBorislav Petkov if (atomic_read(&num_notifiers) > NUM_DEFAULT_NOTIFIERS) 62421afaf18SBorislav Petkov return NOTIFY_DONE; 62521afaf18SBorislav Petkov 62621afaf18SBorislav Petkov __print_mce(m); 62721afaf18SBorislav Petkov 62821afaf18SBorislav Petkov return NOTIFY_DONE; 62921afaf18SBorislav Petkov } 63021afaf18SBorislav Petkov 63121afaf18SBorislav Petkov static struct notifier_block mce_default_nb = { 63221afaf18SBorislav Petkov .notifier_call = mce_default_notifier, 63321afaf18SBorislav Petkov /* lowest prio, we want it to run last. */ 63421afaf18SBorislav Petkov .priority = MCE_PRIO_LOWEST, 63521afaf18SBorislav Petkov }; 63621afaf18SBorislav Petkov 63721afaf18SBorislav Petkov /* 63821afaf18SBorislav Petkov * Read ADDR and MISC registers. 63921afaf18SBorislav Petkov */ 64021afaf18SBorislav Petkov static void mce_read_aux(struct mce *m, int i) 64121afaf18SBorislav Petkov { 64221afaf18SBorislav Petkov if (m->status & MCI_STATUS_MISCV) 64321afaf18SBorislav Petkov m->misc = mce_rdmsrl(msr_ops.misc(i)); 64421afaf18SBorislav Petkov 64521afaf18SBorislav Petkov if (m->status & MCI_STATUS_ADDRV) { 64621afaf18SBorislav Petkov m->addr = mce_rdmsrl(msr_ops.addr(i)); 64721afaf18SBorislav Petkov 64821afaf18SBorislav Petkov /* 64921afaf18SBorislav Petkov * Mask the reported address by the reported granularity. 65021afaf18SBorislav Petkov */ 65121afaf18SBorislav Petkov if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { 65221afaf18SBorislav Petkov u8 shift = MCI_MISC_ADDR_LSB(m->misc); 65321afaf18SBorislav Petkov m->addr >>= shift; 65421afaf18SBorislav Petkov m->addr <<= shift; 65521afaf18SBorislav Petkov } 65621afaf18SBorislav Petkov 65721afaf18SBorislav Petkov /* 65821afaf18SBorislav Petkov * Extract [55:<lsb>] where lsb is the least significant 65921afaf18SBorislav Petkov * *valid* bit of the address bits. 66021afaf18SBorislav Petkov */ 66121afaf18SBorislav Petkov if (mce_flags.smca) { 66221afaf18SBorislav Petkov u8 lsb = (m->addr >> 56) & 0x3f; 66321afaf18SBorislav Petkov 66421afaf18SBorislav Petkov m->addr &= GENMASK_ULL(55, lsb); 66521afaf18SBorislav Petkov } 66621afaf18SBorislav Petkov } 66721afaf18SBorislav Petkov 66821afaf18SBorislav Petkov if (mce_flags.smca) { 66921afaf18SBorislav Petkov m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); 67021afaf18SBorislav Petkov 67121afaf18SBorislav Petkov if (m->status & MCI_STATUS_SYNDV) 67221afaf18SBorislav Petkov m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); 67321afaf18SBorislav Petkov } 67421afaf18SBorislav Petkov } 67521afaf18SBorislav Petkov 67621afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_poll_count); 67721afaf18SBorislav Petkov 67821afaf18SBorislav Petkov /* 67921afaf18SBorislav Petkov * Poll for corrected events or events that happened before reset. 68021afaf18SBorislav Petkov * Those are just logged through /dev/mcelog. 68121afaf18SBorislav Petkov * 68221afaf18SBorislav Petkov * This is executed in standard interrupt context. 68321afaf18SBorislav Petkov * 68421afaf18SBorislav Petkov * Note: spec recommends to panic for fatal unsignalled 68521afaf18SBorislav Petkov * errors here. However this would be quite problematic -- 68621afaf18SBorislav Petkov * we would need to reimplement the Monarch handling and 68721afaf18SBorislav Petkov * it would mess up the exclusion between exception handler 688312a4661SLinus Torvalds * and poll handler -- * so we skip this for now. 68921afaf18SBorislav Petkov * These cases should not happen anyways, or only when the CPU 69021afaf18SBorislav Petkov * is already totally * confused. In this case it's likely it will 69121afaf18SBorislav Petkov * not fully execute the machine check handler either. 69221afaf18SBorislav Petkov */ 69321afaf18SBorislav Petkov bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) 69421afaf18SBorislav Petkov { 695b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 69621afaf18SBorislav Petkov bool error_seen = false; 69721afaf18SBorislav Petkov struct mce m; 69821afaf18SBorislav Petkov int i; 69921afaf18SBorislav Petkov 70021afaf18SBorislav Petkov this_cpu_inc(mce_poll_count); 70121afaf18SBorislav Petkov 70221afaf18SBorislav Petkov mce_gather_info(&m, NULL); 70321afaf18SBorislav Petkov 70421afaf18SBorislav Petkov if (flags & MCP_TIMESTAMP) 70521afaf18SBorislav Petkov m.tsc = rdtsc(); 70621afaf18SBorislav Petkov 707c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 70821afaf18SBorislav Petkov if (!mce_banks[i].ctl || !test_bit(i, *b)) 70921afaf18SBorislav Petkov continue; 71021afaf18SBorislav Petkov 71121afaf18SBorislav Petkov m.misc = 0; 71221afaf18SBorislav Petkov m.addr = 0; 71321afaf18SBorislav Petkov m.bank = i; 71421afaf18SBorislav Petkov 71521afaf18SBorislav Petkov barrier(); 71621afaf18SBorislav Petkov m.status = mce_rdmsrl(msr_ops.status(i)); 717f19501aaSTony Luck 718f19501aaSTony Luck /* If this entry is not valid, ignore it */ 71921afaf18SBorislav Petkov if (!(m.status & MCI_STATUS_VAL)) 72021afaf18SBorislav Petkov continue; 72121afaf18SBorislav Petkov 72221afaf18SBorislav Petkov /* 723f19501aaSTony Luck * If we are logging everything (at CPU online) or this 724f19501aaSTony Luck * is a corrected error, then we must log it. 72521afaf18SBorislav Petkov */ 726f19501aaSTony Luck if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC)) 727f19501aaSTony Luck goto log_it; 728f19501aaSTony Luck 729f19501aaSTony Luck /* 730f19501aaSTony Luck * Newer Intel systems that support software error 731f19501aaSTony Luck * recovery need to make additional checks. Other 732f19501aaSTony Luck * CPUs should skip over uncorrected errors, but log 733f19501aaSTony Luck * everything else. 734f19501aaSTony Luck */ 735f19501aaSTony Luck if (!mca_cfg.ser) { 736f19501aaSTony Luck if (m.status & MCI_STATUS_UC) 737f19501aaSTony Luck continue; 738f19501aaSTony Luck goto log_it; 739f19501aaSTony Luck } 740f19501aaSTony Luck 741f19501aaSTony Luck /* Log "not enabled" (speculative) errors */ 742f19501aaSTony Luck if (!(m.status & MCI_STATUS_EN)) 743f19501aaSTony Luck goto log_it; 744f19501aaSTony Luck 745f19501aaSTony Luck /* 746f19501aaSTony Luck * Log UCNA (SDM: 15.6.3 "UCR Error Classification") 747f19501aaSTony Luck * UC == 1 && PCC == 0 && S == 0 748f19501aaSTony Luck */ 749f19501aaSTony Luck if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S)) 750f19501aaSTony Luck goto log_it; 751f19501aaSTony Luck 752f19501aaSTony Luck /* 753f19501aaSTony Luck * Skip anything else. Presumption is that our read of this 754f19501aaSTony Luck * bank is racing with a machine check. Leave the log alone 755f19501aaSTony Luck * for do_machine_check() to deal with it. 756f19501aaSTony Luck */ 75721afaf18SBorislav Petkov continue; 75821afaf18SBorislav Petkov 759f19501aaSTony Luck log_it: 76021afaf18SBorislav Petkov error_seen = true; 76121afaf18SBorislav Petkov 76290454e49SJan H. Schönherr if (flags & MCP_DONTLOG) 76390454e49SJan H. Schönherr goto clear_it; 76490454e49SJan H. Schönherr 76521afaf18SBorislav Petkov mce_read_aux(&m, i); 76621afaf18SBorislav Petkov m.severity = mce_severity(&m, mca_cfg.tolerant, NULL, false); 76721afaf18SBorislav Petkov /* 76821afaf18SBorislav Petkov * Don't get the IP here because it's unlikely to 76921afaf18SBorislav Petkov * have anything to do with the actual error location. 77021afaf18SBorislav Petkov */ 77121afaf18SBorislav Petkov 77290454e49SJan H. Schönherr if (mca_cfg.dont_log_ce && !mce_usable_address(&m)) 77390454e49SJan H. Schönherr goto clear_it; 77490454e49SJan H. Schönherr 77590454e49SJan H. Schönherr mce_log(&m); 77690454e49SJan H. Schönherr 77790454e49SJan H. Schönherr clear_it: 77821afaf18SBorislav Petkov /* 77921afaf18SBorislav Petkov * Clear state for this bank. 78021afaf18SBorislav Petkov */ 78121afaf18SBorislav Petkov mce_wrmsrl(msr_ops.status(i), 0); 78221afaf18SBorislav Petkov } 78321afaf18SBorislav Petkov 78421afaf18SBorislav Petkov /* 78521afaf18SBorislav Petkov * Don't clear MCG_STATUS here because it's only defined for 78621afaf18SBorislav Petkov * exceptions. 78721afaf18SBorislav Petkov */ 78821afaf18SBorislav Petkov 78921afaf18SBorislav Petkov sync_core(); 79021afaf18SBorislav Petkov 79121afaf18SBorislav Petkov return error_seen; 79221afaf18SBorislav Petkov } 79321afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(machine_check_poll); 79421afaf18SBorislav Petkov 79521afaf18SBorislav Petkov /* 79621afaf18SBorislav Petkov * Do a quick check if any of the events requires a panic. 79721afaf18SBorislav Petkov * This decides if we keep the events around or clear them. 79821afaf18SBorislav Petkov */ 79921afaf18SBorislav Petkov static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, 80021afaf18SBorislav Petkov struct pt_regs *regs) 80121afaf18SBorislav Petkov { 8027a8bc2b0SJan H. Schönherr char *tmp = *msg; 80321afaf18SBorislav Petkov int i; 80421afaf18SBorislav Petkov 805c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 80621afaf18SBorislav Petkov m->status = mce_rdmsrl(msr_ops.status(i)); 80721afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 80821afaf18SBorislav Petkov continue; 80921afaf18SBorislav Petkov 81021afaf18SBorislav Petkov __set_bit(i, validp); 81121afaf18SBorislav Petkov if (quirk_no_way_out) 81221afaf18SBorislav Petkov quirk_no_way_out(i, m, regs); 81321afaf18SBorislav Petkov 814d28af26fSTony Luck m->bank = i; 815a3a57ddaSJan H. Schönherr if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) { 81621afaf18SBorislav Petkov mce_read_aux(m, i); 81721afaf18SBorislav Petkov *msg = tmp; 81821afaf18SBorislav Petkov return 1; 81921afaf18SBorislav Petkov } 82021afaf18SBorislav Petkov } 82121afaf18SBorislav Petkov return 0; 82221afaf18SBorislav Petkov } 82321afaf18SBorislav Petkov 82421afaf18SBorislav Petkov /* 82521afaf18SBorislav Petkov * Variable to establish order between CPUs while scanning. 82621afaf18SBorislav Petkov * Each CPU spins initially until executing is equal its number. 82721afaf18SBorislav Petkov */ 82821afaf18SBorislav Petkov static atomic_t mce_executing; 82921afaf18SBorislav Petkov 83021afaf18SBorislav Petkov /* 83121afaf18SBorislav Petkov * Defines order of CPUs on entry. First CPU becomes Monarch. 83221afaf18SBorislav Petkov */ 83321afaf18SBorislav Petkov static atomic_t mce_callin; 83421afaf18SBorislav Petkov 83521afaf18SBorislav Petkov /* 83621afaf18SBorislav Petkov * Check if a timeout waiting for other CPUs happened. 83721afaf18SBorislav Petkov */ 83821afaf18SBorislav Petkov static int mce_timed_out(u64 *t, const char *msg) 83921afaf18SBorislav Petkov { 84021afaf18SBorislav Petkov /* 84121afaf18SBorislav Petkov * The others already did panic for some reason. 84221afaf18SBorislav Petkov * Bail out like in a timeout. 84321afaf18SBorislav Petkov * rmb() to tell the compiler that system_state 84421afaf18SBorislav Petkov * might have been modified by someone else. 84521afaf18SBorislav Petkov */ 84621afaf18SBorislav Petkov rmb(); 84721afaf18SBorislav Petkov if (atomic_read(&mce_panicked)) 84821afaf18SBorislav Petkov wait_for_panic(); 84921afaf18SBorislav Petkov if (!mca_cfg.monarch_timeout) 85021afaf18SBorislav Petkov goto out; 85121afaf18SBorislav Petkov if ((s64)*t < SPINUNIT) { 85221afaf18SBorislav Petkov if (mca_cfg.tolerant <= 1) 85321afaf18SBorislav Petkov mce_panic(msg, NULL, NULL); 85421afaf18SBorislav Petkov cpu_missing = 1; 85521afaf18SBorislav Petkov return 1; 85621afaf18SBorislav Petkov } 85721afaf18SBorislav Petkov *t -= SPINUNIT; 85821afaf18SBorislav Petkov out: 85921afaf18SBorislav Petkov touch_nmi_watchdog(); 86021afaf18SBorislav Petkov return 0; 86121afaf18SBorislav Petkov } 86221afaf18SBorislav Petkov 86321afaf18SBorislav Petkov /* 86421afaf18SBorislav Petkov * The Monarch's reign. The Monarch is the CPU who entered 86521afaf18SBorislav Petkov * the machine check handler first. It waits for the others to 86621afaf18SBorislav Petkov * raise the exception too and then grades them. When any 86721afaf18SBorislav Petkov * error is fatal panic. Only then let the others continue. 86821afaf18SBorislav Petkov * 86921afaf18SBorislav Petkov * The other CPUs entering the MCE handler will be controlled by the 87021afaf18SBorislav Petkov * Monarch. They are called Subjects. 87121afaf18SBorislav Petkov * 87221afaf18SBorislav Petkov * This way we prevent any potential data corruption in a unrecoverable case 87321afaf18SBorislav Petkov * and also makes sure always all CPU's errors are examined. 87421afaf18SBorislav Petkov * 87521afaf18SBorislav Petkov * Also this detects the case of a machine check event coming from outer 87621afaf18SBorislav Petkov * space (not detected by any CPUs) In this case some external agent wants 87721afaf18SBorislav Petkov * us to shut down, so panic too. 87821afaf18SBorislav Petkov * 87921afaf18SBorislav Petkov * The other CPUs might still decide to panic if the handler happens 88021afaf18SBorislav Petkov * in a unrecoverable place, but in this case the system is in a semi-stable 88121afaf18SBorislav Petkov * state and won't corrupt anything by itself. It's ok to let the others 88221afaf18SBorislav Petkov * continue for a bit first. 88321afaf18SBorislav Petkov * 88421afaf18SBorislav Petkov * All the spin loops have timeouts; when a timeout happens a CPU 88521afaf18SBorislav Petkov * typically elects itself to be Monarch. 88621afaf18SBorislav Petkov */ 88721afaf18SBorislav Petkov static void mce_reign(void) 88821afaf18SBorislav Petkov { 88921afaf18SBorislav Petkov int cpu; 89021afaf18SBorislav Petkov struct mce *m = NULL; 89121afaf18SBorislav Petkov int global_worst = 0; 89221afaf18SBorislav Petkov char *msg = NULL; 89321afaf18SBorislav Petkov char *nmsg = NULL; 89421afaf18SBorislav Petkov 89521afaf18SBorislav Petkov /* 89621afaf18SBorislav Petkov * This CPU is the Monarch and the other CPUs have run 89721afaf18SBorislav Petkov * through their handlers. 89821afaf18SBorislav Petkov * Grade the severity of the errors of all the CPUs. 89921afaf18SBorislav Petkov */ 90021afaf18SBorislav Petkov for_each_possible_cpu(cpu) { 90121afaf18SBorislav Petkov int severity = mce_severity(&per_cpu(mces_seen, cpu), 90221afaf18SBorislav Petkov mca_cfg.tolerant, 90321afaf18SBorislav Petkov &nmsg, true); 90421afaf18SBorislav Petkov if (severity > global_worst) { 90521afaf18SBorislav Petkov msg = nmsg; 90621afaf18SBorislav Petkov global_worst = severity; 90721afaf18SBorislav Petkov m = &per_cpu(mces_seen, cpu); 90821afaf18SBorislav Petkov } 90921afaf18SBorislav Petkov } 91021afaf18SBorislav Petkov 91121afaf18SBorislav Petkov /* 91221afaf18SBorislav Petkov * Cannot recover? Panic here then. 91321afaf18SBorislav Petkov * This dumps all the mces in the log buffer and stops the 91421afaf18SBorislav Petkov * other CPUs. 91521afaf18SBorislav Petkov */ 91621afaf18SBorislav Petkov if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) 91721afaf18SBorislav Petkov mce_panic("Fatal machine check", m, msg); 91821afaf18SBorislav Petkov 91921afaf18SBorislav Petkov /* 92021afaf18SBorislav Petkov * For UC somewhere we let the CPU who detects it handle it. 92121afaf18SBorislav Petkov * Also must let continue the others, otherwise the handling 92221afaf18SBorislav Petkov * CPU could deadlock on a lock. 92321afaf18SBorislav Petkov */ 92421afaf18SBorislav Petkov 92521afaf18SBorislav Petkov /* 92621afaf18SBorislav Petkov * No machine check event found. Must be some external 92721afaf18SBorislav Petkov * source or one CPU is hung. Panic. 92821afaf18SBorislav Petkov */ 92921afaf18SBorislav Petkov if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) 93021afaf18SBorislav Petkov mce_panic("Fatal machine check from unknown source", NULL, NULL); 93121afaf18SBorislav Petkov 93221afaf18SBorislav Petkov /* 93321afaf18SBorislav Petkov * Now clear all the mces_seen so that they don't reappear on 93421afaf18SBorislav Petkov * the next mce. 93521afaf18SBorislav Petkov */ 93621afaf18SBorislav Petkov for_each_possible_cpu(cpu) 93721afaf18SBorislav Petkov memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); 93821afaf18SBorislav Petkov } 93921afaf18SBorislav Petkov 94021afaf18SBorislav Petkov static atomic_t global_nwo; 94121afaf18SBorislav Petkov 94221afaf18SBorislav Petkov /* 94321afaf18SBorislav Petkov * Start of Monarch synchronization. This waits until all CPUs have 94421afaf18SBorislav Petkov * entered the exception handler and then determines if any of them 94521afaf18SBorislav Petkov * saw a fatal event that requires panic. Then it executes them 94621afaf18SBorislav Petkov * in the entry order. 94721afaf18SBorislav Petkov * TBD double check parallel CPU hotunplug 94821afaf18SBorislav Petkov */ 94921afaf18SBorislav Petkov static int mce_start(int *no_way_out) 95021afaf18SBorislav Petkov { 95121afaf18SBorislav Petkov int order; 95221afaf18SBorislav Petkov int cpus = num_online_cpus(); 95321afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 95421afaf18SBorislav Petkov 95521afaf18SBorislav Petkov if (!timeout) 95621afaf18SBorislav Petkov return -1; 95721afaf18SBorislav Petkov 95821afaf18SBorislav Petkov atomic_add(*no_way_out, &global_nwo); 95921afaf18SBorislav Petkov /* 96021afaf18SBorislav Petkov * Rely on the implied barrier below, such that global_nwo 96121afaf18SBorislav Petkov * is updated before mce_callin. 96221afaf18SBorislav Petkov */ 96321afaf18SBorislav Petkov order = atomic_inc_return(&mce_callin); 96421afaf18SBorislav Petkov 96521afaf18SBorislav Petkov /* 96621afaf18SBorislav Petkov * Wait for everyone. 96721afaf18SBorislav Petkov */ 96821afaf18SBorislav Petkov while (atomic_read(&mce_callin) != cpus) { 96921afaf18SBorislav Petkov if (mce_timed_out(&timeout, 97021afaf18SBorislav Petkov "Timeout: Not all CPUs entered broadcast exception handler")) { 97121afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 97221afaf18SBorislav Petkov return -1; 97321afaf18SBorislav Petkov } 97421afaf18SBorislav Petkov ndelay(SPINUNIT); 97521afaf18SBorislav Petkov } 97621afaf18SBorislav Petkov 97721afaf18SBorislav Petkov /* 97821afaf18SBorislav Petkov * mce_callin should be read before global_nwo 97921afaf18SBorislav Petkov */ 98021afaf18SBorislav Petkov smp_rmb(); 98121afaf18SBorislav Petkov 98221afaf18SBorislav Petkov if (order == 1) { 98321afaf18SBorislav Petkov /* 98421afaf18SBorislav Petkov * Monarch: Starts executing now, the others wait. 98521afaf18SBorislav Petkov */ 98621afaf18SBorislav Petkov atomic_set(&mce_executing, 1); 98721afaf18SBorislav Petkov } else { 98821afaf18SBorislav Petkov /* 98921afaf18SBorislav Petkov * Subject: Now start the scanning loop one by one in 99021afaf18SBorislav Petkov * the original callin order. 99121afaf18SBorislav Petkov * This way when there are any shared banks it will be 99221afaf18SBorislav Petkov * only seen by one CPU before cleared, avoiding duplicates. 99321afaf18SBorislav Petkov */ 99421afaf18SBorislav Petkov while (atomic_read(&mce_executing) < order) { 99521afaf18SBorislav Petkov if (mce_timed_out(&timeout, 99621afaf18SBorislav Petkov "Timeout: Subject CPUs unable to finish machine check processing")) { 99721afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 99821afaf18SBorislav Petkov return -1; 99921afaf18SBorislav Petkov } 100021afaf18SBorislav Petkov ndelay(SPINUNIT); 100121afaf18SBorislav Petkov } 100221afaf18SBorislav Petkov } 100321afaf18SBorislav Petkov 100421afaf18SBorislav Petkov /* 100521afaf18SBorislav Petkov * Cache the global no_way_out state. 100621afaf18SBorislav Petkov */ 100721afaf18SBorislav Petkov *no_way_out = atomic_read(&global_nwo); 100821afaf18SBorislav Petkov 100921afaf18SBorislav Petkov return order; 101021afaf18SBorislav Petkov } 101121afaf18SBorislav Petkov 101221afaf18SBorislav Petkov /* 101321afaf18SBorislav Petkov * Synchronize between CPUs after main scanning loop. 101421afaf18SBorislav Petkov * This invokes the bulk of the Monarch processing. 101521afaf18SBorislav Petkov */ 101621afaf18SBorislav Petkov static int mce_end(int order) 101721afaf18SBorislav Petkov { 101821afaf18SBorislav Petkov int ret = -1; 101921afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 102021afaf18SBorislav Petkov 102121afaf18SBorislav Petkov if (!timeout) 102221afaf18SBorislav Petkov goto reset; 102321afaf18SBorislav Petkov if (order < 0) 102421afaf18SBorislav Petkov goto reset; 102521afaf18SBorislav Petkov 102621afaf18SBorislav Petkov /* 102721afaf18SBorislav Petkov * Allow others to run. 102821afaf18SBorislav Petkov */ 102921afaf18SBorislav Petkov atomic_inc(&mce_executing); 103021afaf18SBorislav Petkov 103121afaf18SBorislav Petkov if (order == 1) { 103221afaf18SBorislav Petkov /* CHECKME: Can this race with a parallel hotplug? */ 103321afaf18SBorislav Petkov int cpus = num_online_cpus(); 103421afaf18SBorislav Petkov 103521afaf18SBorislav Petkov /* 103621afaf18SBorislav Petkov * Monarch: Wait for everyone to go through their scanning 103721afaf18SBorislav Petkov * loops. 103821afaf18SBorislav Petkov */ 103921afaf18SBorislav Petkov while (atomic_read(&mce_executing) <= cpus) { 104021afaf18SBorislav Petkov if (mce_timed_out(&timeout, 104121afaf18SBorislav Petkov "Timeout: Monarch CPU unable to finish machine check processing")) 104221afaf18SBorislav Petkov goto reset; 104321afaf18SBorislav Petkov ndelay(SPINUNIT); 104421afaf18SBorislav Petkov } 104521afaf18SBorislav Petkov 104621afaf18SBorislav Petkov mce_reign(); 104721afaf18SBorislav Petkov barrier(); 104821afaf18SBorislav Petkov ret = 0; 104921afaf18SBorislav Petkov } else { 105021afaf18SBorislav Petkov /* 105121afaf18SBorislav Petkov * Subject: Wait for Monarch to finish. 105221afaf18SBorislav Petkov */ 105321afaf18SBorislav Petkov while (atomic_read(&mce_executing) != 0) { 105421afaf18SBorislav Petkov if (mce_timed_out(&timeout, 105521afaf18SBorislav Petkov "Timeout: Monarch CPU did not finish machine check processing")) 105621afaf18SBorislav Petkov goto reset; 105721afaf18SBorislav Petkov ndelay(SPINUNIT); 105821afaf18SBorislav Petkov } 105921afaf18SBorislav Petkov 106021afaf18SBorislav Petkov /* 106121afaf18SBorislav Petkov * Don't reset anything. That's done by the Monarch. 106221afaf18SBorislav Petkov */ 106321afaf18SBorislav Petkov return 0; 106421afaf18SBorislav Petkov } 106521afaf18SBorislav Petkov 106621afaf18SBorislav Petkov /* 106721afaf18SBorislav Petkov * Reset all global state. 106821afaf18SBorislav Petkov */ 106921afaf18SBorislav Petkov reset: 107021afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 107121afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 107221afaf18SBorislav Petkov barrier(); 107321afaf18SBorislav Petkov 107421afaf18SBorislav Petkov /* 107521afaf18SBorislav Petkov * Let others run again. 107621afaf18SBorislav Petkov */ 107721afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 107821afaf18SBorislav Petkov return ret; 107921afaf18SBorislav Petkov } 108021afaf18SBorislav Petkov 108121afaf18SBorislav Petkov static void mce_clear_state(unsigned long *toclear) 108221afaf18SBorislav Petkov { 108321afaf18SBorislav Petkov int i; 108421afaf18SBorislav Petkov 1085c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 108621afaf18SBorislav Petkov if (test_bit(i, toclear)) 108721afaf18SBorislav Petkov mce_wrmsrl(msr_ops.status(i), 0); 108821afaf18SBorislav Petkov } 108921afaf18SBorislav Petkov } 109021afaf18SBorislav Petkov 109121afaf18SBorislav Petkov /* 109221afaf18SBorislav Petkov * Cases where we avoid rendezvous handler timeout: 109321afaf18SBorislav Petkov * 1) If this CPU is offline. 109421afaf18SBorislav Petkov * 109521afaf18SBorislav Petkov * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to 109621afaf18SBorislav Petkov * skip those CPUs which remain looping in the 1st kernel - see 109721afaf18SBorislav Petkov * crash_nmi_callback(). 109821afaf18SBorislav Petkov * 109921afaf18SBorislav Petkov * Note: there still is a small window between kexec-ing and the new, 110021afaf18SBorislav Petkov * kdump kernel establishing a new #MC handler where a broadcasted MCE 110121afaf18SBorislav Petkov * might not get handled properly. 110221afaf18SBorislav Petkov */ 110394a46d31SThomas Gleixner static noinstr bool mce_check_crashing_cpu(void) 110421afaf18SBorislav Petkov { 110594a46d31SThomas Gleixner unsigned int cpu = smp_processor_id(); 110694a46d31SThomas Gleixner 110721afaf18SBorislav Petkov if (cpu_is_offline(cpu) || 110821afaf18SBorislav Petkov (crashing_cpu != -1 && crashing_cpu != cpu)) { 110921afaf18SBorislav Petkov u64 mcgstatus; 111021afaf18SBorislav Petkov 1111aedbdeabSThomas Gleixner mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS); 111270f0c230STony W Wang-oc 111370f0c230STony W Wang-oc if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { 111470f0c230STony W Wang-oc if (mcgstatus & MCG_STATUS_LMCES) 111570f0c230STony W Wang-oc return false; 111670f0c230STony W Wang-oc } 111770f0c230STony W Wang-oc 111821afaf18SBorislav Petkov if (mcgstatus & MCG_STATUS_RIPV) { 1119aedbdeabSThomas Gleixner __wrmsr(MSR_IA32_MCG_STATUS, 0, 0); 112021afaf18SBorislav Petkov return true; 112121afaf18SBorislav Petkov } 112221afaf18SBorislav Petkov } 112321afaf18SBorislav Petkov return false; 112421afaf18SBorislav Petkov } 112521afaf18SBorislav Petkov 112621afaf18SBorislav Petkov static void __mc_scan_banks(struct mce *m, struct mce *final, 112721afaf18SBorislav Petkov unsigned long *toclear, unsigned long *valid_banks, 112821afaf18SBorislav Petkov int no_way_out, int *worst) 112921afaf18SBorislav Petkov { 1130b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 113121afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 113221afaf18SBorislav Petkov int severity, i; 113321afaf18SBorislav Petkov 1134c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 113521afaf18SBorislav Petkov __clear_bit(i, toclear); 113621afaf18SBorislav Petkov if (!test_bit(i, valid_banks)) 113721afaf18SBorislav Petkov continue; 113821afaf18SBorislav Petkov 113921afaf18SBorislav Petkov if (!mce_banks[i].ctl) 114021afaf18SBorislav Petkov continue; 114121afaf18SBorislav Petkov 114221afaf18SBorislav Petkov m->misc = 0; 114321afaf18SBorislav Petkov m->addr = 0; 114421afaf18SBorislav Petkov m->bank = i; 114521afaf18SBorislav Petkov 114621afaf18SBorislav Petkov m->status = mce_rdmsrl(msr_ops.status(i)); 114721afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 114821afaf18SBorislav Petkov continue; 114921afaf18SBorislav Petkov 115021afaf18SBorislav Petkov /* 115121afaf18SBorislav Petkov * Corrected or non-signaled errors are handled by 115221afaf18SBorislav Petkov * machine_check_poll(). Leave them alone, unless this panics. 115321afaf18SBorislav Petkov */ 115421afaf18SBorislav Petkov if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && 115521afaf18SBorislav Petkov !no_way_out) 115621afaf18SBorislav Petkov continue; 115721afaf18SBorislav Petkov 115821afaf18SBorislav Petkov /* Set taint even when machine check was not enabled. */ 115921afaf18SBorislav Petkov add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 116021afaf18SBorislav Petkov 116121afaf18SBorislav Petkov severity = mce_severity(m, cfg->tolerant, NULL, true); 116221afaf18SBorislav Petkov 116321afaf18SBorislav Petkov /* 116421afaf18SBorislav Petkov * When machine check was for corrected/deferred handler don't 116521afaf18SBorislav Petkov * touch, unless we're panicking. 116621afaf18SBorislav Petkov */ 116721afaf18SBorislav Petkov if ((severity == MCE_KEEP_SEVERITY || 116821afaf18SBorislav Petkov severity == MCE_UCNA_SEVERITY) && !no_way_out) 116921afaf18SBorislav Petkov continue; 117021afaf18SBorislav Petkov 117121afaf18SBorislav Petkov __set_bit(i, toclear); 117221afaf18SBorislav Petkov 117321afaf18SBorislav Petkov /* Machine check event was not enabled. Clear, but ignore. */ 117421afaf18SBorislav Petkov if (severity == MCE_NO_SEVERITY) 117521afaf18SBorislav Petkov continue; 117621afaf18SBorislav Petkov 117721afaf18SBorislav Petkov mce_read_aux(m, i); 117821afaf18SBorislav Petkov 117921afaf18SBorislav Petkov /* assuming valid severity level != 0 */ 118021afaf18SBorislav Petkov m->severity = severity; 118121afaf18SBorislav Petkov 118221afaf18SBorislav Petkov mce_log(m); 118321afaf18SBorislav Petkov 118421afaf18SBorislav Petkov if (severity > *worst) { 118521afaf18SBorislav Petkov *final = *m; 118621afaf18SBorislav Petkov *worst = severity; 118721afaf18SBorislav Petkov } 118821afaf18SBorislav Petkov } 118921afaf18SBorislav Petkov 119021afaf18SBorislav Petkov /* mce_clear_state will clear *final, save locally for use later */ 119121afaf18SBorislav Petkov *m = *final; 119221afaf18SBorislav Petkov } 119321afaf18SBorislav Petkov 11945567d11cSPeter Zijlstra static void kill_me_now(struct callback_head *ch) 11955567d11cSPeter Zijlstra { 11965567d11cSPeter Zijlstra force_sig(SIGBUS); 11975567d11cSPeter Zijlstra } 11985567d11cSPeter Zijlstra 11995567d11cSPeter Zijlstra static void kill_me_maybe(struct callback_head *cb) 12005567d11cSPeter Zijlstra { 12015567d11cSPeter Zijlstra struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me); 12025567d11cSPeter Zijlstra int flags = MF_ACTION_REQUIRED; 12035567d11cSPeter Zijlstra 12045567d11cSPeter Zijlstra pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr); 12055567d11cSPeter Zijlstra if (!(p->mce_status & MCG_STATUS_RIPV)) 12065567d11cSPeter Zijlstra flags |= MF_MUST_KILL; 12075567d11cSPeter Zijlstra 12085567d11cSPeter Zijlstra if (!memory_failure(p->mce_addr >> PAGE_SHIFT, flags)) { 12095567d11cSPeter Zijlstra set_mce_nospec(p->mce_addr >> PAGE_SHIFT); 12105567d11cSPeter Zijlstra return; 12115567d11cSPeter Zijlstra } 12125567d11cSPeter Zijlstra 12135567d11cSPeter Zijlstra pr_err("Memory error not recovered"); 12145567d11cSPeter Zijlstra kill_me_now(cb); 12155567d11cSPeter Zijlstra } 12165567d11cSPeter Zijlstra 121721afaf18SBorislav Petkov /* 121821afaf18SBorislav Petkov * The actual machine check handler. This only handles real 121921afaf18SBorislav Petkov * exceptions when something got corrupted coming in through int 18. 122021afaf18SBorislav Petkov * 122121afaf18SBorislav Petkov * This is executed in NMI context not subject to normal locking rules. This 122221afaf18SBorislav Petkov * implies that most kernel services cannot be safely used. Don't even 122321afaf18SBorislav Petkov * think about putting a printk in there! 122421afaf18SBorislav Petkov * 122521afaf18SBorislav Petkov * On Intel systems this is entered on all CPUs in parallel through 122621afaf18SBorislav Petkov * MCE broadcast. However some CPUs might be broken beyond repair, 122721afaf18SBorislav Petkov * so be always careful when synchronizing with others. 122855ba18d6SAndy Lutomirski * 122955ba18d6SAndy Lutomirski * Tracing and kprobes are disabled: if we interrupted a kernel context 123055ba18d6SAndy Lutomirski * with IF=1, we need to minimize stack usage. There are also recursion 123155ba18d6SAndy Lutomirski * issues: if the machine check was due to a failure of the memory 123255ba18d6SAndy Lutomirski * backing the user stack, tracing that reads the user stack will cause 123355ba18d6SAndy Lutomirski * potentially infinite recursion. 123421afaf18SBorislav Petkov */ 12358cd501c1SThomas Gleixner void noinstr do_machine_check(struct pt_regs *regs) 123621afaf18SBorislav Petkov { 123721afaf18SBorislav Petkov DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); 123821afaf18SBorislav Petkov DECLARE_BITMAP(toclear, MAX_NR_BANKS); 123921afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 124021afaf18SBorislav Petkov struct mce m, *final; 12417a8bc2b0SJan H. Schönherr char *msg = NULL; 124221afaf18SBorislav Petkov int worst = 0; 124321afaf18SBorislav Petkov 124421afaf18SBorislav Petkov /* 124521afaf18SBorislav Petkov * Establish sequential order between the CPUs entering the machine 124621afaf18SBorislav Petkov * check handler. 124721afaf18SBorislav Petkov */ 124821afaf18SBorislav Petkov int order = -1; 124921afaf18SBorislav Petkov 125021afaf18SBorislav Petkov /* 125121afaf18SBorislav Petkov * If no_way_out gets set, there is no safe way to recover from this 125221afaf18SBorislav Petkov * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. 125321afaf18SBorislav Petkov */ 125421afaf18SBorislav Petkov int no_way_out = 0; 125521afaf18SBorislav Petkov 125621afaf18SBorislav Petkov /* 125721afaf18SBorislav Petkov * If kill_it gets set, there might be a way to recover from this 125821afaf18SBorislav Petkov * error. 125921afaf18SBorislav Petkov */ 126021afaf18SBorislav Petkov int kill_it = 0; 126121afaf18SBorislav Petkov 126221afaf18SBorislav Petkov /* 126321afaf18SBorislav Petkov * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES 126421afaf18SBorislav Petkov * on Intel. 126521afaf18SBorislav Petkov */ 126621afaf18SBorislav Petkov int lmce = 1; 126721afaf18SBorislav Petkov 126821afaf18SBorislav Petkov this_cpu_inc(mce_exception_count); 126921afaf18SBorislav Petkov 127021afaf18SBorislav Petkov mce_gather_info(&m, regs); 127121afaf18SBorislav Petkov m.tsc = rdtsc(); 127221afaf18SBorislav Petkov 127321afaf18SBorislav Petkov final = this_cpu_ptr(&mces_seen); 127421afaf18SBorislav Petkov *final = m; 127521afaf18SBorislav Petkov 127621afaf18SBorislav Petkov memset(valid_banks, 0, sizeof(valid_banks)); 127721afaf18SBorislav Petkov no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); 127821afaf18SBorislav Petkov 127921afaf18SBorislav Petkov barrier(); 128021afaf18SBorislav Petkov 128121afaf18SBorislav Petkov /* 128221afaf18SBorislav Petkov * When no restart IP might need to kill or panic. 128321afaf18SBorislav Petkov * Assume the worst for now, but if we find the 128421afaf18SBorislav Petkov * severity is MCE_AR_SEVERITY we have other options. 128521afaf18SBorislav Petkov */ 128621afaf18SBorislav Petkov if (!(m.mcgstatus & MCG_STATUS_RIPV)) 128721afaf18SBorislav Petkov kill_it = 1; 128821afaf18SBorislav Petkov 128921afaf18SBorislav Petkov /* 129021afaf18SBorislav Petkov * Check if this MCE is signaled to only this logical processor, 129170f0c230STony W Wang-oc * on Intel, Zhaoxin only. 129221afaf18SBorislav Petkov */ 129370f0c230STony W Wang-oc if (m.cpuvendor == X86_VENDOR_INTEL || 129470f0c230STony W Wang-oc m.cpuvendor == X86_VENDOR_ZHAOXIN) 129521afaf18SBorislav Petkov lmce = m.mcgstatus & MCG_STATUS_LMCES; 129621afaf18SBorislav Petkov 129721afaf18SBorislav Petkov /* 129821afaf18SBorislav Petkov * Local machine check may already know that we have to panic. 129921afaf18SBorislav Petkov * Broadcast machine check begins rendezvous in mce_start() 130021afaf18SBorislav Petkov * Go through all banks in exclusion of the other CPUs. This way we 130121afaf18SBorislav Petkov * don't report duplicated events on shared banks because the first one 130221afaf18SBorislav Petkov * to see it will clear it. 130321afaf18SBorislav Petkov */ 130421afaf18SBorislav Petkov if (lmce) { 130521afaf18SBorislav Petkov if (no_way_out) 130621afaf18SBorislav Petkov mce_panic("Fatal local machine check", &m, msg); 130721afaf18SBorislav Petkov } else { 130821afaf18SBorislav Petkov order = mce_start(&no_way_out); 130921afaf18SBorislav Petkov } 131021afaf18SBorislav Petkov 131121afaf18SBorislav Petkov __mc_scan_banks(&m, final, toclear, valid_banks, no_way_out, &worst); 131221afaf18SBorislav Petkov 131321afaf18SBorislav Petkov if (!no_way_out) 131421afaf18SBorislav Petkov mce_clear_state(toclear); 131521afaf18SBorislav Petkov 131621afaf18SBorislav Petkov /* 131721afaf18SBorislav Petkov * Do most of the synchronization with other CPUs. 131821afaf18SBorislav Petkov * When there's any problem use only local no_way_out state. 131921afaf18SBorislav Petkov */ 132021afaf18SBorislav Petkov if (!lmce) { 132121afaf18SBorislav Petkov if (mce_end(order) < 0) 132221afaf18SBorislav Petkov no_way_out = worst >= MCE_PANIC_SEVERITY; 132321afaf18SBorislav Petkov } else { 132421afaf18SBorislav Petkov /* 132521afaf18SBorislav Petkov * If there was a fatal machine check we should have 132621afaf18SBorislav Petkov * already called mce_panic earlier in this function. 132721afaf18SBorislav Petkov * Since we re-read the banks, we might have found 132821afaf18SBorislav Petkov * something new. Check again to see if we found a 132921afaf18SBorislav Petkov * fatal error. We call "mce_severity()" again to 133021afaf18SBorislav Petkov * make sure we have the right "msg". 133121afaf18SBorislav Petkov */ 133221afaf18SBorislav Petkov if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) { 133321afaf18SBorislav Petkov mce_severity(&m, cfg->tolerant, &msg, true); 133421afaf18SBorislav Petkov mce_panic("Local fatal machine check!", &m, msg); 133521afaf18SBorislav Petkov } 133621afaf18SBorislav Petkov } 133721afaf18SBorislav Petkov 133821afaf18SBorislav Petkov /* 133921afaf18SBorislav Petkov * If tolerant is at an insane level we drop requests to kill 134021afaf18SBorislav Petkov * processes and continue even when there is no way out. 134121afaf18SBorislav Petkov */ 134221afaf18SBorislav Petkov if (cfg->tolerant == 3) 134321afaf18SBorislav Petkov kill_it = 0; 134421afaf18SBorislav Petkov else if (no_way_out) 134521afaf18SBorislav Petkov mce_panic("Fatal machine check on current CPU", &m, msg); 134621afaf18SBorislav Petkov 134721afaf18SBorislav Petkov if (worst > 0) 134839f0584eSBorislav Petkov irq_work_queue(&mce_irq_work); 134939f0584eSBorislav Petkov 135021afaf18SBorislav Petkov mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); 135121afaf18SBorislav Petkov 135221afaf18SBorislav Petkov sync_core(); 135321afaf18SBorislav Petkov 135421afaf18SBorislav Petkov if (worst != MCE_AR_SEVERITY && !kill_it) 135594a46d31SThomas Gleixner return; 135621afaf18SBorislav Petkov 135721afaf18SBorislav Petkov /* Fault was in user mode and we need to take some action */ 135821afaf18SBorislav Petkov if ((m.cs & 3) == 3) { 1359b052df3dSThomas Gleixner /* If this triggers there is no way to recover. Die hard. */ 1360b052df3dSThomas Gleixner BUG_ON(!on_thread_stack() || !user_mode(regs)); 136121afaf18SBorislav Petkov 13625567d11cSPeter Zijlstra current->mce_addr = m.addr; 13635567d11cSPeter Zijlstra current->mce_status = m.mcgstatus; 13645567d11cSPeter Zijlstra current->mce_kill_me.func = kill_me_maybe; 13655567d11cSPeter Zijlstra if (kill_it) 13665567d11cSPeter Zijlstra current->mce_kill_me.func = kill_me_now; 13675567d11cSPeter Zijlstra task_work_add(current, ¤t->mce_kill_me, true); 136821afaf18SBorislav Petkov } else { 13698cd501c1SThomas Gleixner if (!fixup_exception(regs, X86_TRAP_MC, 0, 0)) 13702d806d07SJan H. Schönherr mce_panic("Failed kernel mode recovery", &m, msg); 137121afaf18SBorislav Petkov } 137221afaf18SBorislav Petkov } 137321afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(do_machine_check); 137421afaf18SBorislav Petkov 137521afaf18SBorislav Petkov #ifndef CONFIG_MEMORY_FAILURE 137621afaf18SBorislav Petkov int memory_failure(unsigned long pfn, int flags) 137721afaf18SBorislav Petkov { 137821afaf18SBorislav Petkov /* mce_severity() should not hand us an ACTION_REQUIRED error */ 137921afaf18SBorislav Petkov BUG_ON(flags & MF_ACTION_REQUIRED); 138021afaf18SBorislav Petkov pr_err("Uncorrected memory error in page 0x%lx ignored\n" 138121afaf18SBorislav Petkov "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", 138221afaf18SBorislav Petkov pfn); 138321afaf18SBorislav Petkov 138421afaf18SBorislav Petkov return 0; 138521afaf18SBorislav Petkov } 138621afaf18SBorislav Petkov #endif 138721afaf18SBorislav Petkov 138821afaf18SBorislav Petkov /* 138921afaf18SBorislav Petkov * Periodic polling timer for "silent" machine check errors. If the 139021afaf18SBorislav Petkov * poller finds an MCE, poll 2x faster. When the poller finds no more 139121afaf18SBorislav Petkov * errors, poll 2x slower (up to check_interval seconds). 139221afaf18SBorislav Petkov */ 139321afaf18SBorislav Petkov static unsigned long check_interval = INITIAL_CHECK_INTERVAL; 139421afaf18SBorislav Petkov 139521afaf18SBorislav Petkov static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ 139621afaf18SBorislav Petkov static DEFINE_PER_CPU(struct timer_list, mce_timer); 139721afaf18SBorislav Petkov 139821afaf18SBorislav Petkov static unsigned long mce_adjust_timer_default(unsigned long interval) 139921afaf18SBorislav Petkov { 140021afaf18SBorislav Petkov return interval; 140121afaf18SBorislav Petkov } 140221afaf18SBorislav Petkov 140321afaf18SBorislav Petkov static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; 140421afaf18SBorislav Petkov 140521afaf18SBorislav Petkov static void __start_timer(struct timer_list *t, unsigned long interval) 140621afaf18SBorislav Petkov { 140721afaf18SBorislav Petkov unsigned long when = jiffies + interval; 140821afaf18SBorislav Petkov unsigned long flags; 140921afaf18SBorislav Petkov 141021afaf18SBorislav Petkov local_irq_save(flags); 141121afaf18SBorislav Petkov 141221afaf18SBorislav Petkov if (!timer_pending(t) || time_before(when, t->expires)) 141321afaf18SBorislav Petkov mod_timer(t, round_jiffies(when)); 141421afaf18SBorislav Petkov 141521afaf18SBorislav Petkov local_irq_restore(flags); 141621afaf18SBorislav Petkov } 141721afaf18SBorislav Petkov 141821afaf18SBorislav Petkov static void mce_timer_fn(struct timer_list *t) 141921afaf18SBorislav Petkov { 142021afaf18SBorislav Petkov struct timer_list *cpu_t = this_cpu_ptr(&mce_timer); 142121afaf18SBorislav Petkov unsigned long iv; 142221afaf18SBorislav Petkov 142321afaf18SBorislav Petkov WARN_ON(cpu_t != t); 142421afaf18SBorislav Petkov 142521afaf18SBorislav Petkov iv = __this_cpu_read(mce_next_interval); 142621afaf18SBorislav Petkov 142721afaf18SBorislav Petkov if (mce_available(this_cpu_ptr(&cpu_info))) { 142821afaf18SBorislav Petkov machine_check_poll(0, this_cpu_ptr(&mce_poll_banks)); 142921afaf18SBorislav Petkov 143021afaf18SBorislav Petkov if (mce_intel_cmci_poll()) { 143121afaf18SBorislav Petkov iv = mce_adjust_timer(iv); 143221afaf18SBorislav Petkov goto done; 143321afaf18SBorislav Petkov } 143421afaf18SBorislav Petkov } 143521afaf18SBorislav Petkov 143621afaf18SBorislav Petkov /* 143721afaf18SBorislav Petkov * Alert userspace if needed. If we logged an MCE, reduce the polling 143821afaf18SBorislav Petkov * interval, otherwise increase the polling interval. 143921afaf18SBorislav Petkov */ 144021afaf18SBorislav Petkov if (mce_notify_irq()) 144121afaf18SBorislav Petkov iv = max(iv / 2, (unsigned long) HZ/100); 144221afaf18SBorislav Petkov else 144321afaf18SBorislav Petkov iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); 144421afaf18SBorislav Petkov 144521afaf18SBorislav Petkov done: 144621afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, iv); 144721afaf18SBorislav Petkov __start_timer(t, iv); 144821afaf18SBorislav Petkov } 144921afaf18SBorislav Petkov 145021afaf18SBorislav Petkov /* 145121afaf18SBorislav Petkov * Ensure that the timer is firing in @interval from now. 145221afaf18SBorislav Petkov */ 145321afaf18SBorislav Petkov void mce_timer_kick(unsigned long interval) 145421afaf18SBorislav Petkov { 145521afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 145621afaf18SBorislav Petkov unsigned long iv = __this_cpu_read(mce_next_interval); 145721afaf18SBorislav Petkov 145821afaf18SBorislav Petkov __start_timer(t, interval); 145921afaf18SBorislav Petkov 146021afaf18SBorislav Petkov if (interval < iv) 146121afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, interval); 146221afaf18SBorislav Petkov } 146321afaf18SBorislav Petkov 146421afaf18SBorislav Petkov /* Must not be called in IRQ context where del_timer_sync() can deadlock */ 146521afaf18SBorislav Petkov static void mce_timer_delete_all(void) 146621afaf18SBorislav Petkov { 146721afaf18SBorislav Petkov int cpu; 146821afaf18SBorislav Petkov 146921afaf18SBorislav Petkov for_each_online_cpu(cpu) 147021afaf18SBorislav Petkov del_timer_sync(&per_cpu(mce_timer, cpu)); 147121afaf18SBorislav Petkov } 147221afaf18SBorislav Petkov 147321afaf18SBorislav Petkov /* 147421afaf18SBorislav Petkov * Notify the user(s) about new machine check events. 147521afaf18SBorislav Petkov * Can be called from interrupt context, but not from machine check/NMI 147621afaf18SBorislav Petkov * context. 147721afaf18SBorislav Petkov */ 147821afaf18SBorislav Petkov int mce_notify_irq(void) 147921afaf18SBorislav Petkov { 148021afaf18SBorislav Petkov /* Not more than two messages every minute */ 148121afaf18SBorislav Petkov static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); 148221afaf18SBorislav Petkov 148321afaf18SBorislav Petkov if (test_and_clear_bit(0, &mce_need_notify)) { 148421afaf18SBorislav Petkov mce_work_trigger(); 148521afaf18SBorislav Petkov 148621afaf18SBorislav Petkov if (__ratelimit(&ratelimit)) 148721afaf18SBorislav Petkov pr_info(HW_ERR "Machine check events logged\n"); 148821afaf18SBorislav Petkov 148921afaf18SBorislav Petkov return 1; 149021afaf18SBorislav Petkov } 149121afaf18SBorislav Petkov return 0; 149221afaf18SBorislav Petkov } 149321afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_notify_irq); 149421afaf18SBorislav Petkov 1495b4914508SYazen Ghannam static void __mcheck_cpu_mce_banks_init(void) 149621afaf18SBorislav Petkov { 1497b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1498c7d314f3SYazen Ghannam u8 n_banks = this_cpu_read(mce_num_banks); 149921afaf18SBorislav Petkov int i; 150021afaf18SBorislav Petkov 1501c7d314f3SYazen Ghannam for (i = 0; i < n_banks; i++) { 150221afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 150321afaf18SBorislav Petkov 1504068b053dSYazen Ghannam /* 1505068b053dSYazen Ghannam * Init them all, __mcheck_cpu_apply_quirks() is going to apply 1506068b053dSYazen Ghannam * the required vendor quirks before 1507068b053dSYazen Ghannam * __mcheck_cpu_init_clear_banks() does the final bank setup. 1508068b053dSYazen Ghannam */ 150921afaf18SBorislav Petkov b->ctl = -1ULL; 151021afaf18SBorislav Petkov b->init = 1; 151121afaf18SBorislav Petkov } 151221afaf18SBorislav Petkov } 151321afaf18SBorislav Petkov 151421afaf18SBorislav Petkov /* 151521afaf18SBorislav Petkov * Initialize Machine Checks for a CPU. 151621afaf18SBorislav Petkov */ 1517b4914508SYazen Ghannam static void __mcheck_cpu_cap_init(void) 151821afaf18SBorislav Petkov { 151921afaf18SBorislav Petkov u64 cap; 1520006c0770SYazen Ghannam u8 b; 152121afaf18SBorislav Petkov 152221afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 152321afaf18SBorislav Petkov 152421afaf18SBorislav Petkov b = cap & MCG_BANKCNT_MASK; 152521afaf18SBorislav Petkov 1526c7d314f3SYazen Ghannam if (b > MAX_NR_BANKS) { 1527c7d314f3SYazen Ghannam pr_warn("CPU%d: Using only %u machine check banks out of %u\n", 1528c7d314f3SYazen Ghannam smp_processor_id(), MAX_NR_BANKS, b); 1529c7d314f3SYazen Ghannam b = MAX_NR_BANKS; 1530c7d314f3SYazen Ghannam } 1531c7d314f3SYazen Ghannam 1532c7d314f3SYazen Ghannam this_cpu_write(mce_num_banks, b); 153321afaf18SBorislav Petkov 1534b4914508SYazen Ghannam __mcheck_cpu_mce_banks_init(); 153521afaf18SBorislav Petkov 153621afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 153721afaf18SBorislav Petkov if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) 153821afaf18SBorislav Petkov mca_cfg.rip_msr = MSR_IA32_MCG_EIP; 153921afaf18SBorislav Petkov 154021afaf18SBorislav Petkov if (cap & MCG_SER_P) 154121afaf18SBorislav Petkov mca_cfg.ser = 1; 154221afaf18SBorislav Petkov } 154321afaf18SBorislav Petkov 154421afaf18SBorislav Petkov static void __mcheck_cpu_init_generic(void) 154521afaf18SBorislav Petkov { 154621afaf18SBorislav Petkov enum mcp_flags m_fl = 0; 154721afaf18SBorislav Petkov mce_banks_t all_banks; 154821afaf18SBorislav Petkov u64 cap; 154921afaf18SBorislav Petkov 155021afaf18SBorislav Petkov if (!mca_cfg.bootlog) 155121afaf18SBorislav Petkov m_fl = MCP_DONTLOG; 155221afaf18SBorislav Petkov 155321afaf18SBorislav Petkov /* 155421afaf18SBorislav Petkov * Log the machine checks left over from the previous reset. 155521afaf18SBorislav Petkov */ 155621afaf18SBorislav Petkov bitmap_fill(all_banks, MAX_NR_BANKS); 155721afaf18SBorislav Petkov machine_check_poll(MCP_UC | m_fl, &all_banks); 155821afaf18SBorislav Petkov 155921afaf18SBorislav Petkov cr4_set_bits(X86_CR4_MCE); 156021afaf18SBorislav Petkov 156121afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 156221afaf18SBorislav Petkov if (cap & MCG_CTL_P) 156321afaf18SBorislav Petkov wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); 156421afaf18SBorislav Petkov } 156521afaf18SBorislav Petkov 156621afaf18SBorislav Petkov static void __mcheck_cpu_init_clear_banks(void) 156721afaf18SBorislav Petkov { 1568b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 156921afaf18SBorislav Petkov int i; 157021afaf18SBorislav Petkov 1571c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 157221afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 157321afaf18SBorislav Petkov 157421afaf18SBorislav Petkov if (!b->init) 157521afaf18SBorislav Petkov continue; 157621afaf18SBorislav Petkov wrmsrl(msr_ops.ctl(i), b->ctl); 157721afaf18SBorislav Petkov wrmsrl(msr_ops.status(i), 0); 157821afaf18SBorislav Petkov } 157921afaf18SBorislav Petkov } 158021afaf18SBorislav Petkov 158121afaf18SBorislav Petkov /* 1582068b053dSYazen Ghannam * Do a final check to see if there are any unused/RAZ banks. 1583068b053dSYazen Ghannam * 1584068b053dSYazen Ghannam * This must be done after the banks have been initialized and any quirks have 1585068b053dSYazen Ghannam * been applied. 1586068b053dSYazen Ghannam * 1587068b053dSYazen Ghannam * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs. 1588068b053dSYazen Ghannam * Otherwise, a user who disables a bank will not be able to re-enable it 1589068b053dSYazen Ghannam * without a system reboot. 1590068b053dSYazen Ghannam */ 1591068b053dSYazen Ghannam static void __mcheck_cpu_check_banks(void) 1592068b053dSYazen Ghannam { 1593068b053dSYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1594068b053dSYazen Ghannam u64 msrval; 1595068b053dSYazen Ghannam int i; 1596068b053dSYazen Ghannam 1597068b053dSYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1598068b053dSYazen Ghannam struct mce_bank *b = &mce_banks[i]; 1599068b053dSYazen Ghannam 1600068b053dSYazen Ghannam if (!b->init) 1601068b053dSYazen Ghannam continue; 1602068b053dSYazen Ghannam 1603068b053dSYazen Ghannam rdmsrl(msr_ops.ctl(i), msrval); 1604068b053dSYazen Ghannam b->init = !!msrval; 1605068b053dSYazen Ghannam } 1606068b053dSYazen Ghannam } 1607068b053dSYazen Ghannam 1608068b053dSYazen Ghannam /* 160921afaf18SBorislav Petkov * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and 161021afaf18SBorislav Petkov * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM 161121afaf18SBorislav Petkov * Vol 3B Table 15-20). But this confuses both the code that determines 161221afaf18SBorislav Petkov * whether the machine check occurred in kernel or user mode, and also 161321afaf18SBorislav Petkov * the severity assessment code. Pretend that EIPV was set, and take the 161421afaf18SBorislav Petkov * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. 161521afaf18SBorislav Petkov */ 161621afaf18SBorislav Petkov static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) 161721afaf18SBorislav Petkov { 161821afaf18SBorislav Petkov if (bank != 0) 161921afaf18SBorislav Petkov return; 162021afaf18SBorislav Petkov if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) 162121afaf18SBorislav Petkov return; 162221afaf18SBorislav Petkov if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| 162321afaf18SBorislav Petkov MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| 162421afaf18SBorislav Petkov MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| 162521afaf18SBorislav Petkov MCACOD)) != 162621afaf18SBorislav Petkov (MCI_STATUS_UC|MCI_STATUS_EN| 162721afaf18SBorislav Petkov MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| 162821afaf18SBorislav Petkov MCI_STATUS_AR|MCACOD_INSTR)) 162921afaf18SBorislav Petkov return; 163021afaf18SBorislav Petkov 163121afaf18SBorislav Petkov m->mcgstatus |= MCG_STATUS_EIPV; 163221afaf18SBorislav Petkov m->ip = regs->ip; 163321afaf18SBorislav Petkov m->cs = regs->cs; 163421afaf18SBorislav Petkov } 163521afaf18SBorislav Petkov 163621afaf18SBorislav Petkov /* Add per CPU specific workarounds here */ 163721afaf18SBorislav Petkov static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) 163821afaf18SBorislav Petkov { 1639b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 164021afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 164121afaf18SBorislav Petkov 164221afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_UNKNOWN) { 164321afaf18SBorislav Petkov pr_info("unknown CPU type - not enabling MCE support\n"); 164421afaf18SBorislav Petkov return -EOPNOTSUPP; 164521afaf18SBorislav Petkov } 164621afaf18SBorislav Petkov 164721afaf18SBorislav Petkov /* This should be disabled by the BIOS, but isn't always */ 164821afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD) { 1649c7d314f3SYazen Ghannam if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { 165021afaf18SBorislav Petkov /* 165121afaf18SBorislav Petkov * disable GART TBL walk error reporting, which 165221afaf18SBorislav Petkov * trips off incorrectly with the IOMMU & 3ware 165321afaf18SBorislav Petkov * & Cerberus: 165421afaf18SBorislav Petkov */ 165521afaf18SBorislav Petkov clear_bit(10, (unsigned long *)&mce_banks[4].ctl); 165621afaf18SBorislav Petkov } 165721afaf18SBorislav Petkov if (c->x86 < 0x11 && cfg->bootlog < 0) { 165821afaf18SBorislav Petkov /* 165921afaf18SBorislav Petkov * Lots of broken BIOS around that don't clear them 166021afaf18SBorislav Petkov * by default and leave crap in there. Don't log: 166121afaf18SBorislav Petkov */ 166221afaf18SBorislav Petkov cfg->bootlog = 0; 166321afaf18SBorislav Petkov } 166421afaf18SBorislav Petkov /* 166521afaf18SBorislav Petkov * Various K7s with broken bank 0 around. Always disable 166621afaf18SBorislav Petkov * by default. 166721afaf18SBorislav Petkov */ 1668c7d314f3SYazen Ghannam if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0) 166921afaf18SBorislav Petkov mce_banks[0].ctl = 0; 167021afaf18SBorislav Petkov 167121afaf18SBorislav Petkov /* 167221afaf18SBorislav Petkov * overflow_recov is supported for F15h Models 00h-0fh 167321afaf18SBorislav Petkov * even though we don't have a CPUID bit for it. 167421afaf18SBorislav Petkov */ 167521afaf18SBorislav Petkov if (c->x86 == 0x15 && c->x86_model <= 0xf) 167621afaf18SBorislav Petkov mce_flags.overflow_recov = 1; 167721afaf18SBorislav Petkov 167821afaf18SBorislav Petkov } 167921afaf18SBorislav Petkov 168021afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_INTEL) { 168121afaf18SBorislav Petkov /* 168221afaf18SBorislav Petkov * SDM documents that on family 6 bank 0 should not be written 168321afaf18SBorislav Petkov * because it aliases to another special BIOS controlled 168421afaf18SBorislav Petkov * register. 168521afaf18SBorislav Petkov * But it's not aliased anymore on model 0x1a+ 168621afaf18SBorislav Petkov * Don't ignore bank 0 completely because there could be a 168721afaf18SBorislav Petkov * valid event later, merely don't write CTL0. 168821afaf18SBorislav Petkov */ 168921afaf18SBorislav Petkov 1690c7d314f3SYazen Ghannam if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) 169121afaf18SBorislav Petkov mce_banks[0].init = 0; 169221afaf18SBorislav Petkov 169321afaf18SBorislav Petkov /* 169421afaf18SBorislav Petkov * All newer Intel systems support MCE broadcasting. Enable 169521afaf18SBorislav Petkov * synchronization with a one second timeout. 169621afaf18SBorislav Petkov */ 169721afaf18SBorislav Petkov if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && 169821afaf18SBorislav Petkov cfg->monarch_timeout < 0) 169921afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 170021afaf18SBorislav Petkov 170121afaf18SBorislav Petkov /* 170221afaf18SBorislav Petkov * There are also broken BIOSes on some Pentium M and 170321afaf18SBorislav Petkov * earlier systems: 170421afaf18SBorislav Petkov */ 170521afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) 170621afaf18SBorislav Petkov cfg->bootlog = 0; 170721afaf18SBorislav Petkov 170821afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model == 45) 170921afaf18SBorislav Petkov quirk_no_way_out = quirk_sandybridge_ifu; 171021afaf18SBorislav Petkov } 17116e898d2bSTony W Wang-oc 17126e898d2bSTony W Wang-oc if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { 17136e898d2bSTony W Wang-oc /* 17146e898d2bSTony W Wang-oc * All newer Zhaoxin CPUs support MCE broadcasting. Enable 17156e898d2bSTony W Wang-oc * synchronization with a one second timeout. 17166e898d2bSTony W Wang-oc */ 17176e898d2bSTony W Wang-oc if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 17186e898d2bSTony W Wang-oc if (cfg->monarch_timeout < 0) 17196e898d2bSTony W Wang-oc cfg->monarch_timeout = USEC_PER_SEC; 17206e898d2bSTony W Wang-oc } 17216e898d2bSTony W Wang-oc } 17226e898d2bSTony W Wang-oc 172321afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 172421afaf18SBorislav Petkov cfg->monarch_timeout = 0; 172521afaf18SBorislav Petkov if (cfg->bootlog != 0) 172621afaf18SBorislav Petkov cfg->panic_timeout = 30; 172721afaf18SBorislav Petkov 172821afaf18SBorislav Petkov return 0; 172921afaf18SBorislav Petkov } 173021afaf18SBorislav Petkov 173121afaf18SBorislav Petkov static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) 173221afaf18SBorislav Petkov { 173321afaf18SBorislav Petkov if (c->x86 != 5) 173421afaf18SBorislav Petkov return 0; 173521afaf18SBorislav Petkov 173621afaf18SBorislav Petkov switch (c->x86_vendor) { 173721afaf18SBorislav Petkov case X86_VENDOR_INTEL: 173821afaf18SBorislav Petkov intel_p5_mcheck_init(c); 173921afaf18SBorislav Petkov return 1; 174021afaf18SBorislav Petkov break; 174121afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 174221afaf18SBorislav Petkov winchip_mcheck_init(c); 174321afaf18SBorislav Petkov return 1; 174421afaf18SBorislav Petkov break; 174521afaf18SBorislav Petkov default: 174621afaf18SBorislav Petkov return 0; 174721afaf18SBorislav Petkov } 174821afaf18SBorislav Petkov 174921afaf18SBorislav Petkov return 0; 175021afaf18SBorislav Petkov } 175121afaf18SBorislav Petkov 175221afaf18SBorislav Petkov /* 175321afaf18SBorislav Petkov * Init basic CPU features needed for early decoding of MCEs. 175421afaf18SBorislav Petkov */ 175521afaf18SBorislav Petkov static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) 175621afaf18SBorislav Petkov { 175721afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) { 175821afaf18SBorislav Petkov mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); 175921afaf18SBorislav Petkov mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); 176021afaf18SBorislav Petkov mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); 176121afaf18SBorislav Petkov 176221afaf18SBorislav Petkov if (mce_flags.smca) { 176321afaf18SBorislav Petkov msr_ops.ctl = smca_ctl_reg; 176421afaf18SBorislav Petkov msr_ops.status = smca_status_reg; 176521afaf18SBorislav Petkov msr_ops.addr = smca_addr_reg; 176621afaf18SBorislav Petkov msr_ops.misc = smca_misc_reg; 176721afaf18SBorislav Petkov } 176821afaf18SBorislav Petkov } 176921afaf18SBorislav Petkov } 177021afaf18SBorislav Petkov 177121afaf18SBorislav Petkov static void mce_centaur_feature_init(struct cpuinfo_x86 *c) 177221afaf18SBorislav Petkov { 177321afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 177421afaf18SBorislav Petkov 177521afaf18SBorislav Petkov /* 177621afaf18SBorislav Petkov * All newer Centaur CPUs support MCE broadcasting. Enable 177721afaf18SBorislav Petkov * synchronization with a one second timeout. 177821afaf18SBorislav Petkov */ 177921afaf18SBorislav Petkov if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) || 178021afaf18SBorislav Petkov c->x86 > 6) { 178121afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 178221afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 178321afaf18SBorislav Petkov } 178421afaf18SBorislav Petkov } 178521afaf18SBorislav Petkov 17865a3d56a0STony W Wang-oc static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) 17875a3d56a0STony W Wang-oc { 17885a3d56a0STony W Wang-oc struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 17895a3d56a0STony W Wang-oc 17905a3d56a0STony W Wang-oc /* 17915a3d56a0STony W Wang-oc * These CPUs have MCA bank 8 which reports only one error type called 17925a3d56a0STony W Wang-oc * SVAD (System View Address Decoder). The reporting of that error is 17935a3d56a0STony W Wang-oc * controlled by IA32_MC8.CTL.0. 17945a3d56a0STony W Wang-oc * 17955a3d56a0STony W Wang-oc * If enabled, prefetching on these CPUs will cause SVAD MCE when 17965a3d56a0STony W Wang-oc * virtual machines start and result in a system panic. Always disable 17975a3d56a0STony W Wang-oc * bank 8 SVAD error by default. 17985a3d56a0STony W Wang-oc */ 17995a3d56a0STony W Wang-oc if ((c->x86 == 7 && c->x86_model == 0x1b) || 18005a3d56a0STony W Wang-oc (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 18015a3d56a0STony W Wang-oc if (this_cpu_read(mce_num_banks) > 8) 18025a3d56a0STony W Wang-oc mce_banks[8].ctl = 0; 18035a3d56a0STony W Wang-oc } 18045a3d56a0STony W Wang-oc 18055a3d56a0STony W Wang-oc intel_init_cmci(); 180670f0c230STony W Wang-oc intel_init_lmce(); 18075a3d56a0STony W Wang-oc mce_adjust_timer = cmci_intel_adjust_timer; 18085a3d56a0STony W Wang-oc } 18095a3d56a0STony W Wang-oc 181070f0c230STony W Wang-oc static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) 181170f0c230STony W Wang-oc { 181270f0c230STony W Wang-oc intel_clear_lmce(); 181370f0c230STony W Wang-oc } 181470f0c230STony W Wang-oc 181521afaf18SBorislav Petkov static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) 181621afaf18SBorislav Petkov { 181721afaf18SBorislav Petkov switch (c->x86_vendor) { 181821afaf18SBorislav Petkov case X86_VENDOR_INTEL: 181921afaf18SBorislav Petkov mce_intel_feature_init(c); 182021afaf18SBorislav Petkov mce_adjust_timer = cmci_intel_adjust_timer; 182121afaf18SBorislav Petkov break; 182221afaf18SBorislav Petkov 182321afaf18SBorislav Petkov case X86_VENDOR_AMD: { 182421afaf18SBorislav Petkov mce_amd_feature_init(c); 182521afaf18SBorislav Petkov break; 182621afaf18SBorislav Petkov } 182721afaf18SBorislav Petkov 182821afaf18SBorislav Petkov case X86_VENDOR_HYGON: 182921afaf18SBorislav Petkov mce_hygon_feature_init(c); 183021afaf18SBorislav Petkov break; 183121afaf18SBorislav Petkov 183221afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 183321afaf18SBorislav Petkov mce_centaur_feature_init(c); 183421afaf18SBorislav Petkov break; 183521afaf18SBorislav Petkov 18365a3d56a0STony W Wang-oc case X86_VENDOR_ZHAOXIN: 18375a3d56a0STony W Wang-oc mce_zhaoxin_feature_init(c); 18385a3d56a0STony W Wang-oc break; 18395a3d56a0STony W Wang-oc 184021afaf18SBorislav Petkov default: 184121afaf18SBorislav Petkov break; 184221afaf18SBorislav Petkov } 184321afaf18SBorislav Petkov } 184421afaf18SBorislav Petkov 184521afaf18SBorislav Petkov static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) 184621afaf18SBorislav Petkov { 184721afaf18SBorislav Petkov switch (c->x86_vendor) { 184821afaf18SBorislav Petkov case X86_VENDOR_INTEL: 184921afaf18SBorislav Petkov mce_intel_feature_clear(c); 185021afaf18SBorislav Petkov break; 185170f0c230STony W Wang-oc 185270f0c230STony W Wang-oc case X86_VENDOR_ZHAOXIN: 185370f0c230STony W Wang-oc mce_zhaoxin_feature_clear(c); 185470f0c230STony W Wang-oc break; 185570f0c230STony W Wang-oc 185621afaf18SBorislav Petkov default: 185721afaf18SBorislav Petkov break; 185821afaf18SBorislav Petkov } 185921afaf18SBorislav Petkov } 186021afaf18SBorislav Petkov 186121afaf18SBorislav Petkov static void mce_start_timer(struct timer_list *t) 186221afaf18SBorislav Petkov { 186321afaf18SBorislav Petkov unsigned long iv = check_interval * HZ; 186421afaf18SBorislav Petkov 186521afaf18SBorislav Petkov if (mca_cfg.ignore_ce || !iv) 186621afaf18SBorislav Petkov return; 186721afaf18SBorislav Petkov 186821afaf18SBorislav Petkov this_cpu_write(mce_next_interval, iv); 186921afaf18SBorislav Petkov __start_timer(t, iv); 187021afaf18SBorislav Petkov } 187121afaf18SBorislav Petkov 187221afaf18SBorislav Petkov static void __mcheck_cpu_setup_timer(void) 187321afaf18SBorislav Petkov { 187421afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 187521afaf18SBorislav Petkov 187621afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 187721afaf18SBorislav Petkov } 187821afaf18SBorislav Petkov 187921afaf18SBorislav Petkov static void __mcheck_cpu_init_timer(void) 188021afaf18SBorislav Petkov { 188121afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 188221afaf18SBorislav Petkov 188321afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 188421afaf18SBorislav Petkov mce_start_timer(t); 188521afaf18SBorislav Petkov } 188621afaf18SBorislav Petkov 188745d4b7b9SYazen Ghannam bool filter_mce(struct mce *m) 188845d4b7b9SYazen Ghannam { 188971a84402SYazen Ghannam if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 189071a84402SYazen Ghannam return amd_filter_mce(m); 18912976908eSPrarit Bhargava if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 18922976908eSPrarit Bhargava return intel_filter_mce(m); 189371a84402SYazen Ghannam 189445d4b7b9SYazen Ghannam return false; 189545d4b7b9SYazen Ghannam } 189645d4b7b9SYazen Ghannam 189721afaf18SBorislav Petkov /* Handle unconfigured int18 (should never happen) */ 1898865d3a9aSThomas Gleixner static noinstr void unexpected_machine_check(struct pt_regs *regs) 189921afaf18SBorislav Petkov { 1900865d3a9aSThomas Gleixner instrumentation_begin(); 190121afaf18SBorislav Petkov pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", 190221afaf18SBorislav Petkov smp_processor_id()); 1903865d3a9aSThomas Gleixner instrumentation_end(); 190421afaf18SBorislav Petkov } 190521afaf18SBorislav Petkov 190621afaf18SBorislav Petkov /* Call the installed machine check handler for this CPU setup. */ 19078cd501c1SThomas Gleixner void (*machine_check_vector)(struct pt_regs *) = unexpected_machine_check; 190821afaf18SBorislav Petkov 19094c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_kernel(struct pt_regs *regs) 191021afaf18SBorislav Petkov { 19114c0dcd83SThomas Gleixner /* 19124c0dcd83SThomas Gleixner * Only required when from kernel mode. See 19134c0dcd83SThomas Gleixner * mce_check_crashing_cpu() for details. 19144c0dcd83SThomas Gleixner */ 191594a46d31SThomas Gleixner if (machine_check_vector == do_machine_check && 191694a46d31SThomas Gleixner mce_check_crashing_cpu()) 191794a46d31SThomas Gleixner return; 191894a46d31SThomas Gleixner 191994a46d31SThomas Gleixner nmi_enter(); 1920865d3a9aSThomas Gleixner /* 1921865d3a9aSThomas Gleixner * The call targets are marked noinstr, but objtool can't figure 1922865d3a9aSThomas Gleixner * that out because it's an indirect call. Annotate it. 1923865d3a9aSThomas Gleixner */ 1924865d3a9aSThomas Gleixner instrumentation_begin(); 1925bf2b3008SPeter Zijlstra trace_hardirqs_off_finish(); 19268cd501c1SThomas Gleixner machine_check_vector(regs); 19273ffdfdceSThomas Gleixner if (regs->flags & X86_EFLAGS_IF) 19283ffdfdceSThomas Gleixner trace_hardirqs_on_prepare(); 1929865d3a9aSThomas Gleixner instrumentation_end(); 193094a46d31SThomas Gleixner nmi_exit(); 193121afaf18SBorislav Petkov } 193221afaf18SBorislav Petkov 19334c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_user(struct pt_regs *regs) 19344c0dcd83SThomas Gleixner { 1935fa95d7dcSThomas Gleixner idtentry_enter_user(regs); 1936865d3a9aSThomas Gleixner instrumentation_begin(); 19374c0dcd83SThomas Gleixner machine_check_vector(regs); 1938865d3a9aSThomas Gleixner instrumentation_end(); 1939fa95d7dcSThomas Gleixner idtentry_exit_user(regs); 19404c0dcd83SThomas Gleixner } 19414c0dcd83SThomas Gleixner 19424c0dcd83SThomas Gleixner #ifdef CONFIG_X86_64 19434c0dcd83SThomas Gleixner /* MCE hit kernel mode */ 19444c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE(exc_machine_check) 19454c0dcd83SThomas Gleixner { 1946cd840e42SPeter Zijlstra unsigned long dr7; 1947cd840e42SPeter Zijlstra 1948cd840e42SPeter Zijlstra dr7 = local_db_save(); 19494c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 1950cd840e42SPeter Zijlstra local_db_restore(dr7); 19514c0dcd83SThomas Gleixner } 19524c0dcd83SThomas Gleixner 19534c0dcd83SThomas Gleixner /* The user mode variant. */ 19544c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE_USER(exc_machine_check) 19554c0dcd83SThomas Gleixner { 1956cd840e42SPeter Zijlstra unsigned long dr7; 1957cd840e42SPeter Zijlstra 1958cd840e42SPeter Zijlstra dr7 = local_db_save(); 19594c0dcd83SThomas Gleixner exc_machine_check_user(regs); 1960cd840e42SPeter Zijlstra local_db_restore(dr7); 19614c0dcd83SThomas Gleixner } 19624c0dcd83SThomas Gleixner #else 19634c0dcd83SThomas Gleixner /* 32bit unified entry point */ 19644c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE(exc_machine_check) 19654c0dcd83SThomas Gleixner { 1966cd840e42SPeter Zijlstra unsigned long dr7; 1967cd840e42SPeter Zijlstra 1968cd840e42SPeter Zijlstra dr7 = local_db_save(); 19694c0dcd83SThomas Gleixner if (user_mode(regs)) 19704c0dcd83SThomas Gleixner exc_machine_check_user(regs); 19714c0dcd83SThomas Gleixner else 19724c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 1973cd840e42SPeter Zijlstra local_db_restore(dr7); 19744c0dcd83SThomas Gleixner } 19754c0dcd83SThomas Gleixner #endif 19764c0dcd83SThomas Gleixner 197721afaf18SBorislav Petkov /* 197821afaf18SBorislav Petkov * Called for each booted CPU to set up machine checks. 197921afaf18SBorislav Petkov * Must be called with preempt off: 198021afaf18SBorislav Petkov */ 198121afaf18SBorislav Petkov void mcheck_cpu_init(struct cpuinfo_x86 *c) 198221afaf18SBorislav Petkov { 198321afaf18SBorislav Petkov if (mca_cfg.disabled) 198421afaf18SBorislav Petkov return; 198521afaf18SBorislav Petkov 198621afaf18SBorislav Petkov if (__mcheck_cpu_ancient_init(c)) 198721afaf18SBorislav Petkov return; 198821afaf18SBorislav Petkov 198921afaf18SBorislav Petkov if (!mce_available(c)) 199021afaf18SBorislav Petkov return; 199121afaf18SBorislav Petkov 1992b4914508SYazen Ghannam __mcheck_cpu_cap_init(); 1993b4914508SYazen Ghannam 1994b4914508SYazen Ghannam if (__mcheck_cpu_apply_quirks(c) < 0) { 199521afaf18SBorislav Petkov mca_cfg.disabled = 1; 199621afaf18SBorislav Petkov return; 199721afaf18SBorislav Petkov } 199821afaf18SBorislav Petkov 199921afaf18SBorislav Petkov if (mce_gen_pool_init()) { 200021afaf18SBorislav Petkov mca_cfg.disabled = 1; 200121afaf18SBorislav Petkov pr_emerg("Couldn't allocate MCE records pool!\n"); 200221afaf18SBorislav Petkov return; 200321afaf18SBorislav Petkov } 200421afaf18SBorislav Petkov 200521afaf18SBorislav Petkov machine_check_vector = do_machine_check; 200621afaf18SBorislav Petkov 200721afaf18SBorislav Petkov __mcheck_cpu_init_early(c); 200821afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 200921afaf18SBorislav Petkov __mcheck_cpu_init_vendor(c); 201021afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 2011068b053dSYazen Ghannam __mcheck_cpu_check_banks(); 201221afaf18SBorislav Petkov __mcheck_cpu_setup_timer(); 201321afaf18SBorislav Petkov } 201421afaf18SBorislav Petkov 201521afaf18SBorislav Petkov /* 201621afaf18SBorislav Petkov * Called for each booted CPU to clear some machine checks opt-ins 201721afaf18SBorislav Petkov */ 201821afaf18SBorislav Petkov void mcheck_cpu_clear(struct cpuinfo_x86 *c) 201921afaf18SBorislav Petkov { 202021afaf18SBorislav Petkov if (mca_cfg.disabled) 202121afaf18SBorislav Petkov return; 202221afaf18SBorislav Petkov 202321afaf18SBorislav Petkov if (!mce_available(c)) 202421afaf18SBorislav Petkov return; 202521afaf18SBorislav Petkov 202621afaf18SBorislav Petkov /* 202721afaf18SBorislav Petkov * Possibly to clear general settings generic to x86 202821afaf18SBorislav Petkov * __mcheck_cpu_clear_generic(c); 202921afaf18SBorislav Petkov */ 203021afaf18SBorislav Petkov __mcheck_cpu_clear_vendor(c); 203121afaf18SBorislav Petkov 203221afaf18SBorislav Petkov } 203321afaf18SBorislav Petkov 203421afaf18SBorislav Petkov static void __mce_disable_bank(void *arg) 203521afaf18SBorislav Petkov { 203621afaf18SBorislav Petkov int bank = *((int *)arg); 203721afaf18SBorislav Petkov __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); 203821afaf18SBorislav Petkov cmci_disable_bank(bank); 203921afaf18SBorislav Petkov } 204021afaf18SBorislav Petkov 204121afaf18SBorislav Petkov void mce_disable_bank(int bank) 204221afaf18SBorislav Petkov { 2043c7d314f3SYazen Ghannam if (bank >= this_cpu_read(mce_num_banks)) { 204421afaf18SBorislav Petkov pr_warn(FW_BUG 204521afaf18SBorislav Petkov "Ignoring request to disable invalid MCA bank %d.\n", 204621afaf18SBorislav Petkov bank); 204721afaf18SBorislav Petkov return; 204821afaf18SBorislav Petkov } 204921afaf18SBorislav Petkov set_bit(bank, mce_banks_ce_disabled); 205021afaf18SBorislav Petkov on_each_cpu(__mce_disable_bank, &bank, 1); 205121afaf18SBorislav Petkov } 205221afaf18SBorislav Petkov 205321afaf18SBorislav Petkov /* 205421afaf18SBorislav Petkov * mce=off Disables machine check 205521afaf18SBorislav Petkov * mce=no_cmci Disables CMCI 205621afaf18SBorislav Petkov * mce=no_lmce Disables LMCE 205721afaf18SBorislav Petkov * mce=dont_log_ce Clears corrected events silently, no log created for CEs. 205821afaf18SBorislav Petkov * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. 205921afaf18SBorislav Petkov * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) 206021afaf18SBorislav Petkov * monarchtimeout is how long to wait for other CPUs on machine 206121afaf18SBorislav Petkov * check, or 0 to not wait 206221afaf18SBorislav Petkov * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h 206321afaf18SBorislav Petkov and older. 206421afaf18SBorislav Petkov * mce=nobootlog Don't log MCEs from before booting. 206521afaf18SBorislav Petkov * mce=bios_cmci_threshold Don't program the CMCI threshold 206621afaf18SBorislav Petkov * mce=recovery force enable memcpy_mcsafe() 206721afaf18SBorislav Petkov */ 206821afaf18SBorislav Petkov static int __init mcheck_enable(char *str) 206921afaf18SBorislav Petkov { 207021afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 207121afaf18SBorislav Petkov 207221afaf18SBorislav Petkov if (*str == 0) { 207321afaf18SBorislav Petkov enable_p5_mce(); 207421afaf18SBorislav Petkov return 1; 207521afaf18SBorislav Petkov } 207621afaf18SBorislav Petkov if (*str == '=') 207721afaf18SBorislav Petkov str++; 207821afaf18SBorislav Petkov if (!strcmp(str, "off")) 207921afaf18SBorislav Petkov cfg->disabled = 1; 208021afaf18SBorislav Petkov else if (!strcmp(str, "no_cmci")) 208121afaf18SBorislav Petkov cfg->cmci_disabled = true; 208221afaf18SBorislav Petkov else if (!strcmp(str, "no_lmce")) 208321afaf18SBorislav Petkov cfg->lmce_disabled = 1; 208421afaf18SBorislav Petkov else if (!strcmp(str, "dont_log_ce")) 208521afaf18SBorislav Petkov cfg->dont_log_ce = true; 208621afaf18SBorislav Petkov else if (!strcmp(str, "ignore_ce")) 208721afaf18SBorislav Petkov cfg->ignore_ce = true; 208821afaf18SBorislav Petkov else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) 208921afaf18SBorislav Petkov cfg->bootlog = (str[0] == 'b'); 209021afaf18SBorislav Petkov else if (!strcmp(str, "bios_cmci_threshold")) 209121afaf18SBorislav Petkov cfg->bios_cmci_threshold = 1; 209221afaf18SBorislav Petkov else if (!strcmp(str, "recovery")) 209321afaf18SBorislav Petkov cfg->recovery = 1; 209421afaf18SBorislav Petkov else if (isdigit(str[0])) { 209521afaf18SBorislav Petkov if (get_option(&str, &cfg->tolerant) == 2) 209621afaf18SBorislav Petkov get_option(&str, &(cfg->monarch_timeout)); 209721afaf18SBorislav Petkov } else { 209821afaf18SBorislav Petkov pr_info("mce argument %s ignored. Please use /sys\n", str); 209921afaf18SBorislav Petkov return 0; 210021afaf18SBorislav Petkov } 210121afaf18SBorislav Petkov return 1; 210221afaf18SBorislav Petkov } 210321afaf18SBorislav Petkov __setup("mce", mcheck_enable); 210421afaf18SBorislav Petkov 210521afaf18SBorislav Petkov int __init mcheck_init(void) 210621afaf18SBorislav Petkov { 210721afaf18SBorislav Petkov mcheck_intel_therm_init(); 210821afaf18SBorislav Petkov mce_register_decode_chain(&first_nb); 21098438b84aSJan H. Schönherr mce_register_decode_chain(&mce_uc_nb); 211021afaf18SBorislav Petkov mce_register_decode_chain(&mce_default_nb); 211121afaf18SBorislav Petkov mcheck_vendor_init_severity(); 211221afaf18SBorislav Petkov 211321afaf18SBorislav Petkov INIT_WORK(&mce_work, mce_gen_pool_process); 211421afaf18SBorislav Petkov init_irq_work(&mce_irq_work, mce_irq_work_cb); 211521afaf18SBorislav Petkov 211621afaf18SBorislav Petkov return 0; 211721afaf18SBorislav Petkov } 211821afaf18SBorislav Petkov 211921afaf18SBorislav Petkov /* 212021afaf18SBorislav Petkov * mce_syscore: PM support 212121afaf18SBorislav Petkov */ 212221afaf18SBorislav Petkov 212321afaf18SBorislav Petkov /* 212421afaf18SBorislav Petkov * Disable machine checks on suspend and shutdown. We can't really handle 212521afaf18SBorislav Petkov * them later. 212621afaf18SBorislav Petkov */ 212721afaf18SBorislav Petkov static void mce_disable_error_reporting(void) 212821afaf18SBorislav Petkov { 2129b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 213021afaf18SBorislav Petkov int i; 213121afaf18SBorislav Petkov 2132c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 213321afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 213421afaf18SBorislav Petkov 213521afaf18SBorislav Petkov if (b->init) 213621afaf18SBorislav Petkov wrmsrl(msr_ops.ctl(i), 0); 213721afaf18SBorislav Petkov } 213821afaf18SBorislav Petkov return; 213921afaf18SBorislav Petkov } 214021afaf18SBorislav Petkov 214121afaf18SBorislav Petkov static void vendor_disable_error_reporting(void) 214221afaf18SBorislav Petkov { 214321afaf18SBorislav Petkov /* 21446e898d2bSTony W Wang-oc * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these 21456e898d2bSTony W Wang-oc * MSRs are socket-wide. Disabling them for just a single offlined CPU 21466e898d2bSTony W Wang-oc * is bad, since it will inhibit reporting for all shared resources on 21476e898d2bSTony W Wang-oc * the socket like the last level cache (LLC), the integrated memory 21486e898d2bSTony W Wang-oc * controller (iMC), etc. 214921afaf18SBorislav Petkov */ 215021afaf18SBorislav Petkov if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || 215121afaf18SBorislav Petkov boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || 21526e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 21536e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) 215421afaf18SBorislav Petkov return; 215521afaf18SBorislav Petkov 215621afaf18SBorislav Petkov mce_disable_error_reporting(); 215721afaf18SBorislav Petkov } 215821afaf18SBorislav Petkov 215921afaf18SBorislav Petkov static int mce_syscore_suspend(void) 216021afaf18SBorislav Petkov { 216121afaf18SBorislav Petkov vendor_disable_error_reporting(); 216221afaf18SBorislav Petkov return 0; 216321afaf18SBorislav Petkov } 216421afaf18SBorislav Petkov 216521afaf18SBorislav Petkov static void mce_syscore_shutdown(void) 216621afaf18SBorislav Petkov { 216721afaf18SBorislav Petkov vendor_disable_error_reporting(); 216821afaf18SBorislav Petkov } 216921afaf18SBorislav Petkov 217021afaf18SBorislav Petkov /* 217121afaf18SBorislav Petkov * On resume clear all MCE state. Don't want to see leftovers from the BIOS. 217221afaf18SBorislav Petkov * Only one CPU is active at this time, the others get re-added later using 217321afaf18SBorislav Petkov * CPU hotplug: 217421afaf18SBorislav Petkov */ 217521afaf18SBorislav Petkov static void mce_syscore_resume(void) 217621afaf18SBorislav Petkov { 217721afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 217821afaf18SBorislav Petkov __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); 217921afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 218021afaf18SBorislav Petkov } 218121afaf18SBorislav Petkov 218221afaf18SBorislav Petkov static struct syscore_ops mce_syscore_ops = { 218321afaf18SBorislav Petkov .suspend = mce_syscore_suspend, 218421afaf18SBorislav Petkov .shutdown = mce_syscore_shutdown, 218521afaf18SBorislav Petkov .resume = mce_syscore_resume, 218621afaf18SBorislav Petkov }; 218721afaf18SBorislav Petkov 218821afaf18SBorislav Petkov /* 218921afaf18SBorislav Petkov * mce_device: Sysfs support 219021afaf18SBorislav Petkov */ 219121afaf18SBorislav Petkov 219221afaf18SBorislav Petkov static void mce_cpu_restart(void *data) 219321afaf18SBorislav Petkov { 219421afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 219521afaf18SBorislav Petkov return; 219621afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 219721afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 219821afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 219921afaf18SBorislav Petkov } 220021afaf18SBorislav Petkov 220121afaf18SBorislav Petkov /* Reinit MCEs after user configuration changes */ 220221afaf18SBorislav Petkov static void mce_restart(void) 220321afaf18SBorislav Petkov { 220421afaf18SBorislav Petkov mce_timer_delete_all(); 220521afaf18SBorislav Petkov on_each_cpu(mce_cpu_restart, NULL, 1); 220621afaf18SBorislav Petkov } 220721afaf18SBorislav Petkov 220821afaf18SBorislav Petkov /* Toggle features for corrected errors */ 220921afaf18SBorislav Petkov static void mce_disable_cmci(void *data) 221021afaf18SBorislav Petkov { 221121afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 221221afaf18SBorislav Petkov return; 221321afaf18SBorislav Petkov cmci_clear(); 221421afaf18SBorislav Petkov } 221521afaf18SBorislav Petkov 221621afaf18SBorislav Petkov static void mce_enable_ce(void *all) 221721afaf18SBorislav Petkov { 221821afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 221921afaf18SBorislav Petkov return; 222021afaf18SBorislav Petkov cmci_reenable(); 222121afaf18SBorislav Petkov cmci_recheck(); 222221afaf18SBorislav Petkov if (all) 222321afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 222421afaf18SBorislav Petkov } 222521afaf18SBorislav Petkov 222621afaf18SBorislav Petkov static struct bus_type mce_subsys = { 222721afaf18SBorislav Petkov .name = "machinecheck", 222821afaf18SBorislav Petkov .dev_name = "machinecheck", 222921afaf18SBorislav Petkov }; 223021afaf18SBorislav Petkov 223121afaf18SBorislav Petkov DEFINE_PER_CPU(struct device *, mce_device); 223221afaf18SBorislav Petkov 2233b4914508SYazen Ghannam static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr) 223421afaf18SBorislav Petkov { 2235b4914508SYazen Ghannam return container_of(attr, struct mce_bank_dev, attr); 223621afaf18SBorislav Petkov } 223721afaf18SBorislav Petkov 223821afaf18SBorislav Petkov static ssize_t show_bank(struct device *s, struct device_attribute *attr, 223921afaf18SBorislav Petkov char *buf) 224021afaf18SBorislav Petkov { 2241b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2242b4914508SYazen Ghannam struct mce_bank *b; 2243b4914508SYazen Ghannam 2244c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2245b4914508SYazen Ghannam return -EINVAL; 2246b4914508SYazen Ghannam 2247b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2248b4914508SYazen Ghannam 2249068b053dSYazen Ghannam if (!b->init) 2250068b053dSYazen Ghannam return -ENODEV; 2251068b053dSYazen Ghannam 2252b4914508SYazen Ghannam return sprintf(buf, "%llx\n", b->ctl); 225321afaf18SBorislav Petkov } 225421afaf18SBorislav Petkov 225521afaf18SBorislav Petkov static ssize_t set_bank(struct device *s, struct device_attribute *attr, 225621afaf18SBorislav Petkov const char *buf, size_t size) 225721afaf18SBorislav Petkov { 2258b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2259b4914508SYazen Ghannam struct mce_bank *b; 226021afaf18SBorislav Petkov u64 new; 226121afaf18SBorislav Petkov 226221afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 226321afaf18SBorislav Petkov return -EINVAL; 226421afaf18SBorislav Petkov 2265c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2266b4914508SYazen Ghannam return -EINVAL; 2267b4914508SYazen Ghannam 2268b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2269b4914508SYazen Ghannam 2270068b053dSYazen Ghannam if (!b->init) 2271068b053dSYazen Ghannam return -ENODEV; 2272068b053dSYazen Ghannam 2273b4914508SYazen Ghannam b->ctl = new; 227421afaf18SBorislav Petkov mce_restart(); 227521afaf18SBorislav Petkov 227621afaf18SBorislav Petkov return size; 227721afaf18SBorislav Petkov } 227821afaf18SBorislav Petkov 227921afaf18SBorislav Petkov static ssize_t set_ignore_ce(struct device *s, 228021afaf18SBorislav Petkov struct device_attribute *attr, 228121afaf18SBorislav Petkov const char *buf, size_t size) 228221afaf18SBorislav Petkov { 228321afaf18SBorislav Petkov u64 new; 228421afaf18SBorislav Petkov 228521afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 228621afaf18SBorislav Petkov return -EINVAL; 228721afaf18SBorislav Petkov 228821afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 228921afaf18SBorislav Petkov if (mca_cfg.ignore_ce ^ !!new) { 229021afaf18SBorislav Petkov if (new) { 229121afaf18SBorislav Petkov /* disable ce features */ 229221afaf18SBorislav Petkov mce_timer_delete_all(); 229321afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 229421afaf18SBorislav Petkov mca_cfg.ignore_ce = true; 229521afaf18SBorislav Petkov } else { 229621afaf18SBorislav Petkov /* enable ce features */ 229721afaf18SBorislav Petkov mca_cfg.ignore_ce = false; 229821afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, (void *)1, 1); 229921afaf18SBorislav Petkov } 230021afaf18SBorislav Petkov } 230121afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 230221afaf18SBorislav Petkov 230321afaf18SBorislav Petkov return size; 230421afaf18SBorislav Petkov } 230521afaf18SBorislav Petkov 230621afaf18SBorislav Petkov static ssize_t set_cmci_disabled(struct device *s, 230721afaf18SBorislav Petkov struct device_attribute *attr, 230821afaf18SBorislav Petkov const char *buf, size_t size) 230921afaf18SBorislav Petkov { 231021afaf18SBorislav Petkov u64 new; 231121afaf18SBorislav Petkov 231221afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 231321afaf18SBorislav Petkov return -EINVAL; 231421afaf18SBorislav Petkov 231521afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 231621afaf18SBorislav Petkov if (mca_cfg.cmci_disabled ^ !!new) { 231721afaf18SBorislav Petkov if (new) { 231821afaf18SBorislav Petkov /* disable cmci */ 231921afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 232021afaf18SBorislav Petkov mca_cfg.cmci_disabled = true; 232121afaf18SBorislav Petkov } else { 232221afaf18SBorislav Petkov /* enable cmci */ 232321afaf18SBorislav Petkov mca_cfg.cmci_disabled = false; 232421afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, NULL, 1); 232521afaf18SBorislav Petkov } 232621afaf18SBorislav Petkov } 232721afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 232821afaf18SBorislav Petkov 232921afaf18SBorislav Petkov return size; 233021afaf18SBorislav Petkov } 233121afaf18SBorislav Petkov 233221afaf18SBorislav Petkov static ssize_t store_int_with_restart(struct device *s, 233321afaf18SBorislav Petkov struct device_attribute *attr, 233421afaf18SBorislav Petkov const char *buf, size_t size) 233521afaf18SBorislav Petkov { 233621afaf18SBorislav Petkov unsigned long old_check_interval = check_interval; 233721afaf18SBorislav Petkov ssize_t ret = device_store_ulong(s, attr, buf, size); 233821afaf18SBorislav Petkov 233921afaf18SBorislav Petkov if (check_interval == old_check_interval) 234021afaf18SBorislav Petkov return ret; 234121afaf18SBorislav Petkov 234221afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 234321afaf18SBorislav Petkov mce_restart(); 234421afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 234521afaf18SBorislav Petkov 234621afaf18SBorislav Petkov return ret; 234721afaf18SBorislav Petkov } 234821afaf18SBorislav Petkov 234921afaf18SBorislav Petkov static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); 235021afaf18SBorislav Petkov static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); 235121afaf18SBorislav Petkov static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); 235221afaf18SBorislav Petkov 235321afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_check_interval = { 235421afaf18SBorislav Petkov __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), 235521afaf18SBorislav Petkov &check_interval 235621afaf18SBorislav Petkov }; 235721afaf18SBorislav Petkov 235821afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_ignore_ce = { 235921afaf18SBorislav Petkov __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), 236021afaf18SBorislav Petkov &mca_cfg.ignore_ce 236121afaf18SBorislav Petkov }; 236221afaf18SBorislav Petkov 236321afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_cmci_disabled = { 236421afaf18SBorislav Petkov __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), 236521afaf18SBorislav Petkov &mca_cfg.cmci_disabled 236621afaf18SBorislav Petkov }; 236721afaf18SBorislav Petkov 236821afaf18SBorislav Petkov static struct device_attribute *mce_device_attrs[] = { 236921afaf18SBorislav Petkov &dev_attr_tolerant.attr, 237021afaf18SBorislav Petkov &dev_attr_check_interval.attr, 237121afaf18SBorislav Petkov #ifdef CONFIG_X86_MCELOG_LEGACY 237221afaf18SBorislav Petkov &dev_attr_trigger, 237321afaf18SBorislav Petkov #endif 237421afaf18SBorislav Petkov &dev_attr_monarch_timeout.attr, 237521afaf18SBorislav Petkov &dev_attr_dont_log_ce.attr, 237621afaf18SBorislav Petkov &dev_attr_ignore_ce.attr, 237721afaf18SBorislav Petkov &dev_attr_cmci_disabled.attr, 237821afaf18SBorislav Petkov NULL 237921afaf18SBorislav Petkov }; 238021afaf18SBorislav Petkov 238121afaf18SBorislav Petkov static cpumask_var_t mce_device_initialized; 238221afaf18SBorislav Petkov 238321afaf18SBorislav Petkov static void mce_device_release(struct device *dev) 238421afaf18SBorislav Petkov { 238521afaf18SBorislav Petkov kfree(dev); 238621afaf18SBorislav Petkov } 238721afaf18SBorislav Petkov 2388b4914508SYazen Ghannam /* Per CPU device init. All of the CPUs still share the same bank device: */ 238921afaf18SBorislav Petkov static int mce_device_create(unsigned int cpu) 239021afaf18SBorislav Petkov { 239121afaf18SBorislav Petkov struct device *dev; 239221afaf18SBorislav Petkov int err; 239321afaf18SBorislav Petkov int i, j; 239421afaf18SBorislav Petkov 239521afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) 239621afaf18SBorislav Petkov return -EIO; 239721afaf18SBorislav Petkov 239821afaf18SBorislav Petkov dev = per_cpu(mce_device, cpu); 239921afaf18SBorislav Petkov if (dev) 240021afaf18SBorislav Petkov return 0; 240121afaf18SBorislav Petkov 240221afaf18SBorislav Petkov dev = kzalloc(sizeof(*dev), GFP_KERNEL); 240321afaf18SBorislav Petkov if (!dev) 240421afaf18SBorislav Petkov return -ENOMEM; 240521afaf18SBorislav Petkov dev->id = cpu; 240621afaf18SBorislav Petkov dev->bus = &mce_subsys; 240721afaf18SBorislav Petkov dev->release = &mce_device_release; 240821afaf18SBorislav Petkov 240921afaf18SBorislav Petkov err = device_register(dev); 241021afaf18SBorislav Petkov if (err) { 241121afaf18SBorislav Petkov put_device(dev); 241221afaf18SBorislav Petkov return err; 241321afaf18SBorislav Petkov } 241421afaf18SBorislav Petkov 241521afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) { 241621afaf18SBorislav Petkov err = device_create_file(dev, mce_device_attrs[i]); 241721afaf18SBorislav Petkov if (err) 241821afaf18SBorislav Petkov goto error; 241921afaf18SBorislav Petkov } 2420c7d314f3SYazen Ghannam for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) { 2421b4914508SYazen Ghannam err = device_create_file(dev, &mce_bank_devs[j].attr); 242221afaf18SBorislav Petkov if (err) 242321afaf18SBorislav Petkov goto error2; 242421afaf18SBorislav Petkov } 242521afaf18SBorislav Petkov cpumask_set_cpu(cpu, mce_device_initialized); 242621afaf18SBorislav Petkov per_cpu(mce_device, cpu) = dev; 242721afaf18SBorislav Petkov 242821afaf18SBorislav Petkov return 0; 242921afaf18SBorislav Petkov error2: 243021afaf18SBorislav Petkov while (--j >= 0) 2431b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[j].attr); 243221afaf18SBorislav Petkov error: 243321afaf18SBorislav Petkov while (--i >= 0) 243421afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 243521afaf18SBorislav Petkov 243621afaf18SBorislav Petkov device_unregister(dev); 243721afaf18SBorislav Petkov 243821afaf18SBorislav Petkov return err; 243921afaf18SBorislav Petkov } 244021afaf18SBorislav Petkov 244121afaf18SBorislav Petkov static void mce_device_remove(unsigned int cpu) 244221afaf18SBorislav Petkov { 244321afaf18SBorislav Petkov struct device *dev = per_cpu(mce_device, cpu); 244421afaf18SBorislav Petkov int i; 244521afaf18SBorislav Petkov 244621afaf18SBorislav Petkov if (!cpumask_test_cpu(cpu, mce_device_initialized)) 244721afaf18SBorislav Petkov return; 244821afaf18SBorislav Petkov 244921afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) 245021afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 245121afaf18SBorislav Petkov 2452c7d314f3SYazen Ghannam for (i = 0; i < per_cpu(mce_num_banks, cpu); i++) 2453b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[i].attr); 245421afaf18SBorislav Petkov 245521afaf18SBorislav Petkov device_unregister(dev); 245621afaf18SBorislav Petkov cpumask_clear_cpu(cpu, mce_device_initialized); 245721afaf18SBorislav Petkov per_cpu(mce_device, cpu) = NULL; 245821afaf18SBorislav Petkov } 245921afaf18SBorislav Petkov 246021afaf18SBorislav Petkov /* Make sure there are no machine checks on offlined CPUs. */ 246121afaf18SBorislav Petkov static void mce_disable_cpu(void) 246221afaf18SBorislav Petkov { 246321afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 246421afaf18SBorislav Petkov return; 246521afaf18SBorislav Petkov 246621afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 246721afaf18SBorislav Petkov cmci_clear(); 246821afaf18SBorislav Petkov 246921afaf18SBorislav Petkov vendor_disable_error_reporting(); 247021afaf18SBorislav Petkov } 247121afaf18SBorislav Petkov 247221afaf18SBorislav Petkov static void mce_reenable_cpu(void) 247321afaf18SBorislav Petkov { 2474b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 247521afaf18SBorislav Petkov int i; 247621afaf18SBorislav Petkov 247721afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 247821afaf18SBorislav Petkov return; 247921afaf18SBorislav Petkov 248021afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 248121afaf18SBorislav Petkov cmci_reenable(); 2482c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 248321afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 248421afaf18SBorislav Petkov 248521afaf18SBorislav Petkov if (b->init) 248621afaf18SBorislav Petkov wrmsrl(msr_ops.ctl(i), b->ctl); 248721afaf18SBorislav Petkov } 248821afaf18SBorislav Petkov } 248921afaf18SBorislav Petkov 249021afaf18SBorislav Petkov static int mce_cpu_dead(unsigned int cpu) 249121afaf18SBorislav Petkov { 249221afaf18SBorislav Petkov mce_intel_hcpu_update(cpu); 249321afaf18SBorislav Petkov 249421afaf18SBorislav Petkov /* intentionally ignoring frozen here */ 249521afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 249621afaf18SBorislav Petkov cmci_rediscover(); 249721afaf18SBorislav Petkov return 0; 249821afaf18SBorislav Petkov } 249921afaf18SBorislav Petkov 250021afaf18SBorislav Petkov static int mce_cpu_online(unsigned int cpu) 250121afaf18SBorislav Petkov { 250221afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 250321afaf18SBorislav Petkov int ret; 250421afaf18SBorislav Petkov 250521afaf18SBorislav Petkov mce_device_create(cpu); 250621afaf18SBorislav Petkov 250721afaf18SBorislav Petkov ret = mce_threshold_create_device(cpu); 250821afaf18SBorislav Petkov if (ret) { 250921afaf18SBorislav Petkov mce_device_remove(cpu); 251021afaf18SBorislav Petkov return ret; 251121afaf18SBorislav Petkov } 251221afaf18SBorislav Petkov mce_reenable_cpu(); 251321afaf18SBorislav Petkov mce_start_timer(t); 251421afaf18SBorislav Petkov return 0; 251521afaf18SBorislav Petkov } 251621afaf18SBorislav Petkov 251721afaf18SBorislav Petkov static int mce_cpu_pre_down(unsigned int cpu) 251821afaf18SBorislav Petkov { 251921afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 252021afaf18SBorislav Petkov 252121afaf18SBorislav Petkov mce_disable_cpu(); 252221afaf18SBorislav Petkov del_timer_sync(t); 252321afaf18SBorislav Petkov mce_threshold_remove_device(cpu); 252421afaf18SBorislav Petkov mce_device_remove(cpu); 252521afaf18SBorislav Petkov return 0; 252621afaf18SBorislav Petkov } 252721afaf18SBorislav Petkov 252821afaf18SBorislav Petkov static __init void mce_init_banks(void) 252921afaf18SBorislav Petkov { 253021afaf18SBorislav Petkov int i; 253121afaf18SBorislav Petkov 2532b4914508SYazen Ghannam for (i = 0; i < MAX_NR_BANKS; i++) { 2533b4914508SYazen Ghannam struct mce_bank_dev *b = &mce_bank_devs[i]; 253421afaf18SBorislav Petkov struct device_attribute *a = &b->attr; 253521afaf18SBorislav Petkov 2536b4914508SYazen Ghannam b->bank = i; 2537b4914508SYazen Ghannam 253821afaf18SBorislav Petkov sysfs_attr_init(&a->attr); 253921afaf18SBorislav Petkov a->attr.name = b->attrname; 254021afaf18SBorislav Petkov snprintf(b->attrname, ATTR_LEN, "bank%d", i); 254121afaf18SBorislav Petkov 254221afaf18SBorislav Petkov a->attr.mode = 0644; 254321afaf18SBorislav Petkov a->show = show_bank; 254421afaf18SBorislav Petkov a->store = set_bank; 254521afaf18SBorislav Petkov } 254621afaf18SBorislav Petkov } 254721afaf18SBorislav Petkov 254821afaf18SBorislav Petkov static __init int mcheck_init_device(void) 254921afaf18SBorislav Petkov { 255021afaf18SBorislav Petkov int err; 255121afaf18SBorislav Petkov 255221afaf18SBorislav Petkov /* 255321afaf18SBorislav Petkov * Check if we have a spare virtual bit. This will only become 255421afaf18SBorislav Petkov * a problem if/when we move beyond 5-level page tables. 255521afaf18SBorislav Petkov */ 255621afaf18SBorislav Petkov MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63); 255721afaf18SBorislav Petkov 255821afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) { 255921afaf18SBorislav Petkov err = -EIO; 256021afaf18SBorislav Petkov goto err_out; 256121afaf18SBorislav Petkov } 256221afaf18SBorislav Petkov 256321afaf18SBorislav Petkov if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { 256421afaf18SBorislav Petkov err = -ENOMEM; 256521afaf18SBorislav Petkov goto err_out; 256621afaf18SBorislav Petkov } 256721afaf18SBorislav Petkov 256821afaf18SBorislav Petkov mce_init_banks(); 256921afaf18SBorislav Petkov 257021afaf18SBorislav Petkov err = subsys_system_register(&mce_subsys, NULL); 257121afaf18SBorislav Petkov if (err) 257221afaf18SBorislav Petkov goto err_out_mem; 257321afaf18SBorislav Petkov 257421afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL, 257521afaf18SBorislav Petkov mce_cpu_dead); 257621afaf18SBorislav Petkov if (err) 257721afaf18SBorislav Petkov goto err_out_mem; 257821afaf18SBorislav Petkov 257921afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online", 258021afaf18SBorislav Petkov mce_cpu_online, mce_cpu_pre_down); 258121afaf18SBorislav Petkov if (err < 0) 258221afaf18SBorislav Petkov goto err_out_online; 258321afaf18SBorislav Petkov 258421afaf18SBorislav Petkov register_syscore_ops(&mce_syscore_ops); 258521afaf18SBorislav Petkov 258621afaf18SBorislav Petkov return 0; 258721afaf18SBorislav Petkov 258821afaf18SBorislav Petkov err_out_online: 258921afaf18SBorislav Petkov cpuhp_remove_state(CPUHP_X86_MCE_DEAD); 259021afaf18SBorislav Petkov 259121afaf18SBorislav Petkov err_out_mem: 259221afaf18SBorislav Petkov free_cpumask_var(mce_device_initialized); 259321afaf18SBorislav Petkov 259421afaf18SBorislav Petkov err_out: 259521afaf18SBorislav Petkov pr_err("Unable to init MCE device (rc: %d)\n", err); 259621afaf18SBorislav Petkov 259721afaf18SBorislav Petkov return err; 259821afaf18SBorislav Petkov } 259921afaf18SBorislav Petkov device_initcall_sync(mcheck_init_device); 260021afaf18SBorislav Petkov 260121afaf18SBorislav Petkov /* 260221afaf18SBorislav Petkov * Old style boot options parsing. Only for compatibility. 260321afaf18SBorislav Petkov */ 260421afaf18SBorislav Petkov static int __init mcheck_disable(char *str) 260521afaf18SBorislav Petkov { 260621afaf18SBorislav Petkov mca_cfg.disabled = 1; 260721afaf18SBorislav Petkov return 1; 260821afaf18SBorislav Petkov } 260921afaf18SBorislav Petkov __setup("nomce", mcheck_disable); 261021afaf18SBorislav Petkov 261121afaf18SBorislav Petkov #ifdef CONFIG_DEBUG_FS 261221afaf18SBorislav Petkov struct dentry *mce_get_debugfs_dir(void) 261321afaf18SBorislav Petkov { 261421afaf18SBorislav Petkov static struct dentry *dmce; 261521afaf18SBorislav Petkov 261621afaf18SBorislav Petkov if (!dmce) 261721afaf18SBorislav Petkov dmce = debugfs_create_dir("mce", NULL); 261821afaf18SBorislav Petkov 261921afaf18SBorislav Petkov return dmce; 262021afaf18SBorislav Petkov } 262121afaf18SBorislav Petkov 262221afaf18SBorislav Petkov static void mce_reset(void) 262321afaf18SBorislav Petkov { 262421afaf18SBorislav Petkov cpu_missing = 0; 262521afaf18SBorislav Petkov atomic_set(&mce_fake_panicked, 0); 262621afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 262721afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 262821afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 262921afaf18SBorislav Petkov } 263021afaf18SBorislav Petkov 263121afaf18SBorislav Petkov static int fake_panic_get(void *data, u64 *val) 263221afaf18SBorislav Petkov { 263321afaf18SBorislav Petkov *val = fake_panic; 263421afaf18SBorislav Petkov return 0; 263521afaf18SBorislav Petkov } 263621afaf18SBorislav Petkov 263721afaf18SBorislav Petkov static int fake_panic_set(void *data, u64 val) 263821afaf18SBorislav Petkov { 263921afaf18SBorislav Petkov mce_reset(); 264021afaf18SBorislav Petkov fake_panic = val; 264121afaf18SBorislav Petkov return 0; 264221afaf18SBorislav Petkov } 264321afaf18SBorislav Petkov 264428156d76SYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set, 264528156d76SYueHaibing "%llu\n"); 264621afaf18SBorislav Petkov 26476e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) 264821afaf18SBorislav Petkov { 26496e4f929eSGreg Kroah-Hartman struct dentry *dmce; 265021afaf18SBorislav Petkov 265121afaf18SBorislav Petkov dmce = mce_get_debugfs_dir(); 26526e4f929eSGreg Kroah-Hartman debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL, 26536e4f929eSGreg Kroah-Hartman &fake_panic_fops); 265421afaf18SBorislav Petkov } 265521afaf18SBorislav Petkov #else 26566e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) { } 265721afaf18SBorislav Petkov #endif 265821afaf18SBorislav Petkov 265921afaf18SBorislav Petkov DEFINE_STATIC_KEY_FALSE(mcsafe_key); 266021afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mcsafe_key); 266121afaf18SBorislav Petkov 266221afaf18SBorislav Petkov static int __init mcheck_late_init(void) 266321afaf18SBorislav Petkov { 266421afaf18SBorislav Petkov if (mca_cfg.recovery) 266521afaf18SBorislav Petkov static_branch_inc(&mcsafe_key); 266621afaf18SBorislav Petkov 266721afaf18SBorislav Petkov mcheck_debugfs_init(); 266821afaf18SBorislav Petkov cec_init(); 266921afaf18SBorislav Petkov 267021afaf18SBorislav Petkov /* 267121afaf18SBorislav Petkov * Flush out everything that has been logged during early boot, now that 267221afaf18SBorislav Petkov * everything has been initialized (workqueues, decoders, ...). 267321afaf18SBorislav Petkov */ 267421afaf18SBorislav Petkov mce_schedule_work(); 267521afaf18SBorislav Petkov 267621afaf18SBorislav Petkov return 0; 267721afaf18SBorislav Petkov } 267821afaf18SBorislav Petkov late_initcall(mcheck_late_init); 2679