1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 221afaf18SBorislav Petkov /* 321afaf18SBorislav Petkov * Machine check handler. 421afaf18SBorislav Petkov * 521afaf18SBorislav Petkov * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. 621afaf18SBorislav Petkov * Rest from unknown author(s). 721afaf18SBorislav Petkov * 2004 Andi Kleen. Rewrote most of it. 821afaf18SBorislav Petkov * Copyright 2008 Intel Corporation 921afaf18SBorislav Petkov * Author: Andi Kleen 1021afaf18SBorislav Petkov */ 1121afaf18SBorislav Petkov 1221afaf18SBorislav Petkov #include <linux/thread_info.h> 1321afaf18SBorislav Petkov #include <linux/capability.h> 1421afaf18SBorislav Petkov #include <linux/miscdevice.h> 1521afaf18SBorislav Petkov #include <linux/ratelimit.h> 1621afaf18SBorislav Petkov #include <linux/rcupdate.h> 1721afaf18SBorislav Petkov #include <linux/kobject.h> 1821afaf18SBorislav Petkov #include <linux/uaccess.h> 1921afaf18SBorislav Petkov #include <linux/kdebug.h> 2021afaf18SBorislav Petkov #include <linux/kernel.h> 2121afaf18SBorislav Petkov #include <linux/percpu.h> 2221afaf18SBorislav Petkov #include <linux/string.h> 2321afaf18SBorislav Petkov #include <linux/device.h> 2421afaf18SBorislav Petkov #include <linux/syscore_ops.h> 2521afaf18SBorislav Petkov #include <linux/delay.h> 2621afaf18SBorislav Petkov #include <linux/ctype.h> 2721afaf18SBorislav Petkov #include <linux/sched.h> 2821afaf18SBorislav Petkov #include <linux/sysfs.h> 2921afaf18SBorislav Petkov #include <linux/types.h> 3021afaf18SBorislav Petkov #include <linux/slab.h> 3121afaf18SBorislav Petkov #include <linux/init.h> 3221afaf18SBorislav Petkov #include <linux/kmod.h> 3321afaf18SBorislav Petkov #include <linux/poll.h> 3421afaf18SBorislav Petkov #include <linux/nmi.h> 3521afaf18SBorislav Petkov #include <linux/cpu.h> 3621afaf18SBorislav Petkov #include <linux/ras.h> 3721afaf18SBorislav Petkov #include <linux/smp.h> 3821afaf18SBorislav Petkov #include <linux/fs.h> 3921afaf18SBorislav Petkov #include <linux/mm.h> 4021afaf18SBorislav Petkov #include <linux/debugfs.h> 4121afaf18SBorislav Petkov #include <linux/irq_work.h> 4221afaf18SBorislav Petkov #include <linux/export.h> 4321afaf18SBorislav Petkov #include <linux/jump_label.h> 4421afaf18SBorislav Petkov #include <linux/set_memory.h> 4521afaf18SBorislav Petkov 4621afaf18SBorislav Petkov #include <asm/intel-family.h> 4721afaf18SBorislav Petkov #include <asm/processor.h> 4821afaf18SBorislav Petkov #include <asm/traps.h> 4921afaf18SBorislav Petkov #include <asm/tlbflush.h> 5021afaf18SBorislav Petkov #include <asm/mce.h> 5121afaf18SBorislav Petkov #include <asm/msr.h> 5221afaf18SBorislav Petkov #include <asm/reboot.h> 5321afaf18SBorislav Petkov 5421afaf18SBorislav Petkov #include "internal.h" 5521afaf18SBorislav Petkov 5621afaf18SBorislav Petkov /* sysfs synchronization */ 5721afaf18SBorislav Petkov static DEFINE_MUTEX(mce_sysfs_mutex); 5821afaf18SBorislav Petkov 5921afaf18SBorislav Petkov #define CREATE_TRACE_POINTS 6021afaf18SBorislav Petkov #include <trace/events/mce.h> 6121afaf18SBorislav Petkov 6221afaf18SBorislav Petkov #define SPINUNIT 100 /* 100ns */ 6321afaf18SBorislav Petkov 6421afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_exception_count); 6521afaf18SBorislav Petkov 66c7d314f3SYazen Ghannam DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks); 67c7d314f3SYazen Ghannam 6895fdce6bSYazen Ghannam struct mce_bank { 6995fdce6bSYazen Ghannam u64 ctl; /* subevents to enable */ 7095fdce6bSYazen Ghannam bool init; /* initialise bank? */ 71b4914508SYazen Ghannam }; 72b4914508SYazen Ghannam static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); 73b4914508SYazen Ghannam 74b4914508SYazen Ghannam #define ATTR_LEN 16 75b4914508SYazen Ghannam /* One object for each MCE bank, shared by all CPUs */ 76b4914508SYazen Ghannam struct mce_bank_dev { 7795fdce6bSYazen Ghannam struct device_attribute attr; /* device attribute */ 7895fdce6bSYazen Ghannam char attrname[ATTR_LEN]; /* attribute name */ 79b4914508SYazen Ghannam u8 bank; /* bank number */ 8095fdce6bSYazen Ghannam }; 81b4914508SYazen Ghannam static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS]; 8295fdce6bSYazen Ghannam 8321afaf18SBorislav Petkov struct mce_vendor_flags mce_flags __read_mostly; 8421afaf18SBorislav Petkov 8521afaf18SBorislav Petkov struct mca_config mca_cfg __read_mostly = { 8621afaf18SBorislav Petkov .bootlog = -1, 8721afaf18SBorislav Petkov /* 8821afaf18SBorislav Petkov * Tolerant levels: 8921afaf18SBorislav Petkov * 0: always panic on uncorrected errors, log corrected errors 9021afaf18SBorislav Petkov * 1: panic or SIGBUS on uncorrected errors, log corrected errors 9121afaf18SBorislav Petkov * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors 9221afaf18SBorislav Petkov * 3: never panic or SIGBUS, log all errors (for testing only) 9321afaf18SBorislav Petkov */ 9421afaf18SBorislav Petkov .tolerant = 1, 9521afaf18SBorislav Petkov .monarch_timeout = -1 9621afaf18SBorislav Petkov }; 9721afaf18SBorislav Petkov 9821afaf18SBorislav Petkov static DEFINE_PER_CPU(struct mce, mces_seen); 9921afaf18SBorislav Petkov static unsigned long mce_need_notify; 10021afaf18SBorislav Petkov static int cpu_missing; 10121afaf18SBorislav Petkov 10221afaf18SBorislav Petkov /* 10321afaf18SBorislav Petkov * MCA banks polled by the period polling timer for corrected events. 10421afaf18SBorislav Petkov * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). 10521afaf18SBorislav Petkov */ 10621afaf18SBorislav Petkov DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { 10721afaf18SBorislav Petkov [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL 10821afaf18SBorislav Petkov }; 10921afaf18SBorislav Petkov 11021afaf18SBorislav Petkov /* 11121afaf18SBorislav Petkov * MCA banks controlled through firmware first for corrected errors. 11221afaf18SBorislav Petkov * This is a global list of banks for which we won't enable CMCI and we 11321afaf18SBorislav Petkov * won't poll. Firmware controls these banks and is responsible for 11421afaf18SBorislav Petkov * reporting corrected errors through GHES. Uncorrected/recoverable 11521afaf18SBorislav Petkov * errors are still notified through a machine check. 11621afaf18SBorislav Petkov */ 11721afaf18SBorislav Petkov mce_banks_t mce_banks_ce_disabled; 11821afaf18SBorislav Petkov 11921afaf18SBorislav Petkov static struct work_struct mce_work; 12021afaf18SBorislav Petkov static struct irq_work mce_irq_work; 12121afaf18SBorislav Petkov 12221afaf18SBorislav Petkov static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); 12321afaf18SBorislav Petkov 12421afaf18SBorislav Petkov /* 12521afaf18SBorislav Petkov * CPU/chipset specific EDAC code can register a notifier call here to print 12621afaf18SBorislav Petkov * MCE errors in a human-readable form. 12721afaf18SBorislav Petkov */ 12821afaf18SBorislav Petkov BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); 12921afaf18SBorislav Petkov 13021afaf18SBorislav Petkov /* Do initial initialization of a struct mce */ 13121afaf18SBorislav Petkov void mce_setup(struct mce *m) 13221afaf18SBorislav Petkov { 13321afaf18SBorislav Petkov memset(m, 0, sizeof(struct mce)); 13421afaf18SBorislav Petkov m->cpu = m->extcpu = smp_processor_id(); 13521afaf18SBorislav Petkov /* need the internal __ version to avoid deadlocks */ 13621afaf18SBorislav Petkov m->time = __ktime_get_real_seconds(); 13721afaf18SBorislav Petkov m->cpuvendor = boot_cpu_data.x86_vendor; 13821afaf18SBorislav Petkov m->cpuid = cpuid_eax(1); 13921afaf18SBorislav Petkov m->socketid = cpu_data(m->extcpu).phys_proc_id; 14021afaf18SBorislav Petkov m->apicid = cpu_data(m->extcpu).initial_apicid; 14121afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); 14221afaf18SBorislav Petkov 14321afaf18SBorislav Petkov if (this_cpu_has(X86_FEATURE_INTEL_PPIN)) 14421afaf18SBorislav Petkov rdmsrl(MSR_PPIN, m->ppin); 145077168e2SWei Huang else if (this_cpu_has(X86_FEATURE_AMD_PPIN)) 146077168e2SWei Huang rdmsrl(MSR_AMD_PPIN, m->ppin); 14721afaf18SBorislav Petkov 14821afaf18SBorislav Petkov m->microcode = boot_cpu_data.microcode; 14921afaf18SBorislav Petkov } 15021afaf18SBorislav Petkov 15121afaf18SBorislav Petkov DEFINE_PER_CPU(struct mce, injectm); 15221afaf18SBorislav Petkov EXPORT_PER_CPU_SYMBOL_GPL(injectm); 15321afaf18SBorislav Petkov 15421afaf18SBorislav Petkov void mce_log(struct mce *m) 15521afaf18SBorislav Petkov { 15621afaf18SBorislav Petkov if (!mce_gen_pool_add(m)) 15721afaf18SBorislav Petkov irq_work_queue(&mce_irq_work); 15821afaf18SBorislav Petkov } 15981736abdSJan H. Schönherr EXPORT_SYMBOL_GPL(mce_log); 16021afaf18SBorislav Petkov 16121afaf18SBorislav Petkov void mce_register_decode_chain(struct notifier_block *nb) 16221afaf18SBorislav Petkov { 16321afaf18SBorislav Petkov if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC)) 16421afaf18SBorislav Petkov return; 16521afaf18SBorislav Petkov 16621afaf18SBorislav Petkov blocking_notifier_chain_register(&x86_mce_decoder_chain, nb); 16721afaf18SBorislav Petkov } 16821afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_register_decode_chain); 16921afaf18SBorislav Petkov 17021afaf18SBorislav Petkov void mce_unregister_decode_chain(struct notifier_block *nb) 17121afaf18SBorislav Petkov { 17221afaf18SBorislav Petkov blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb); 17321afaf18SBorislav Petkov } 17421afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); 17521afaf18SBorislav Petkov 17621afaf18SBorislav Petkov static inline u32 ctl_reg(int bank) 17721afaf18SBorislav Petkov { 17821afaf18SBorislav Petkov return MSR_IA32_MCx_CTL(bank); 17921afaf18SBorislav Petkov } 18021afaf18SBorislav Petkov 18121afaf18SBorislav Petkov static inline u32 status_reg(int bank) 18221afaf18SBorislav Petkov { 18321afaf18SBorislav Petkov return MSR_IA32_MCx_STATUS(bank); 18421afaf18SBorislav Petkov } 18521afaf18SBorislav Petkov 18621afaf18SBorislav Petkov static inline u32 addr_reg(int bank) 18721afaf18SBorislav Petkov { 18821afaf18SBorislav Petkov return MSR_IA32_MCx_ADDR(bank); 18921afaf18SBorislav Petkov } 19021afaf18SBorislav Petkov 19121afaf18SBorislav Petkov static inline u32 misc_reg(int bank) 19221afaf18SBorislav Petkov { 19321afaf18SBorislav Petkov return MSR_IA32_MCx_MISC(bank); 19421afaf18SBorislav Petkov } 19521afaf18SBorislav Petkov 19621afaf18SBorislav Petkov static inline u32 smca_ctl_reg(int bank) 19721afaf18SBorislav Petkov { 19821afaf18SBorislav Petkov return MSR_AMD64_SMCA_MCx_CTL(bank); 19921afaf18SBorislav Petkov } 20021afaf18SBorislav Petkov 20121afaf18SBorislav Petkov static inline u32 smca_status_reg(int bank) 20221afaf18SBorislav Petkov { 20321afaf18SBorislav Petkov return MSR_AMD64_SMCA_MCx_STATUS(bank); 20421afaf18SBorislav Petkov } 20521afaf18SBorislav Petkov 20621afaf18SBorislav Petkov static inline u32 smca_addr_reg(int bank) 20721afaf18SBorislav Petkov { 20821afaf18SBorislav Petkov return MSR_AMD64_SMCA_MCx_ADDR(bank); 20921afaf18SBorislav Petkov } 21021afaf18SBorislav Petkov 21121afaf18SBorislav Petkov static inline u32 smca_misc_reg(int bank) 21221afaf18SBorislav Petkov { 21321afaf18SBorislav Petkov return MSR_AMD64_SMCA_MCx_MISC(bank); 21421afaf18SBorislav Petkov } 21521afaf18SBorislav Petkov 21621afaf18SBorislav Petkov struct mca_msr_regs msr_ops = { 21721afaf18SBorislav Petkov .ctl = ctl_reg, 21821afaf18SBorislav Petkov .status = status_reg, 21921afaf18SBorislav Petkov .addr = addr_reg, 22021afaf18SBorislav Petkov .misc = misc_reg 22121afaf18SBorislav Petkov }; 22221afaf18SBorislav Petkov 22321afaf18SBorislav Petkov static void __print_mce(struct mce *m) 22421afaf18SBorislav Petkov { 22521afaf18SBorislav Petkov pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", 22621afaf18SBorislav Petkov m->extcpu, 22721afaf18SBorislav Petkov (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""), 22821afaf18SBorislav Petkov m->mcgstatus, m->bank, m->status); 22921afaf18SBorislav Petkov 23021afaf18SBorislav Petkov if (m->ip) { 23121afaf18SBorislav Petkov pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", 23221afaf18SBorislav Petkov !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", 23321afaf18SBorislav Petkov m->cs, m->ip); 23421afaf18SBorislav Petkov 23521afaf18SBorislav Petkov if (m->cs == __KERNEL_CS) 23621afaf18SBorislav Petkov pr_cont("{%pS}", (void *)(unsigned long)m->ip); 23721afaf18SBorislav Petkov pr_cont("\n"); 23821afaf18SBorislav Petkov } 23921afaf18SBorislav Petkov 24021afaf18SBorislav Petkov pr_emerg(HW_ERR "TSC %llx ", m->tsc); 24121afaf18SBorislav Petkov if (m->addr) 24221afaf18SBorislav Petkov pr_cont("ADDR %llx ", m->addr); 24321afaf18SBorislav Petkov if (m->misc) 24421afaf18SBorislav Petkov pr_cont("MISC %llx ", m->misc); 24521afaf18SBorislav Petkov 24621afaf18SBorislav Petkov if (mce_flags.smca) { 24721afaf18SBorislav Petkov if (m->synd) 24821afaf18SBorislav Petkov pr_cont("SYND %llx ", m->synd); 24921afaf18SBorislav Petkov if (m->ipid) 25021afaf18SBorislav Petkov pr_cont("IPID %llx ", m->ipid); 25121afaf18SBorislav Petkov } 25221afaf18SBorislav Petkov 25321afaf18SBorislav Petkov pr_cont("\n"); 254925946cfSTony Luck 25521afaf18SBorislav Petkov /* 25621afaf18SBorislav Petkov * Note this output is parsed by external tools and old fields 25721afaf18SBorislav Petkov * should not be changed. 25821afaf18SBorislav Petkov */ 25921afaf18SBorislav Petkov pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", 26021afaf18SBorislav Petkov m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, 26121afaf18SBorislav Petkov m->microcode); 26221afaf18SBorislav Petkov } 26321afaf18SBorislav Petkov 26421afaf18SBorislav Petkov static void print_mce(struct mce *m) 26521afaf18SBorislav Petkov { 26621afaf18SBorislav Petkov __print_mce(m); 26721afaf18SBorislav Petkov 26821afaf18SBorislav Petkov if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON) 26921afaf18SBorislav Petkov pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); 27021afaf18SBorislav Petkov } 27121afaf18SBorislav Petkov 27221afaf18SBorislav Petkov #define PANIC_TIMEOUT 5 /* 5 seconds */ 27321afaf18SBorislav Petkov 27421afaf18SBorislav Petkov static atomic_t mce_panicked; 27521afaf18SBorislav Petkov 27621afaf18SBorislav Petkov static int fake_panic; 27721afaf18SBorislav Petkov static atomic_t mce_fake_panicked; 27821afaf18SBorislav Petkov 27921afaf18SBorislav Petkov /* Panic in progress. Enable interrupts and wait for final IPI */ 28021afaf18SBorislav Petkov static void wait_for_panic(void) 28121afaf18SBorislav Petkov { 28221afaf18SBorislav Petkov long timeout = PANIC_TIMEOUT*USEC_PER_SEC; 28321afaf18SBorislav Petkov 28421afaf18SBorislav Petkov preempt_disable(); 28521afaf18SBorislav Petkov local_irq_enable(); 28621afaf18SBorislav Petkov while (timeout-- > 0) 28721afaf18SBorislav Petkov udelay(1); 28821afaf18SBorislav Petkov if (panic_timeout == 0) 28921afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 29021afaf18SBorislav Petkov panic("Panicing machine check CPU died"); 29121afaf18SBorislav Petkov } 29221afaf18SBorislav Petkov 29321afaf18SBorislav Petkov static void mce_panic(const char *msg, struct mce *final, char *exp) 29421afaf18SBorislav Petkov { 29521afaf18SBorislav Petkov int apei_err = 0; 29621afaf18SBorislav Petkov struct llist_node *pending; 29721afaf18SBorislav Petkov struct mce_evt_llist *l; 29821afaf18SBorislav Petkov 29921afaf18SBorislav Petkov if (!fake_panic) { 30021afaf18SBorislav Petkov /* 30121afaf18SBorislav Petkov * Make sure only one CPU runs in machine check panic 30221afaf18SBorislav Petkov */ 30321afaf18SBorislav Petkov if (atomic_inc_return(&mce_panicked) > 1) 30421afaf18SBorislav Petkov wait_for_panic(); 30521afaf18SBorislav Petkov barrier(); 30621afaf18SBorislav Petkov 30721afaf18SBorislav Petkov bust_spinlocks(1); 30821afaf18SBorislav Petkov console_verbose(); 30921afaf18SBorislav Petkov } else { 31021afaf18SBorislav Petkov /* Don't log too much for fake panic */ 31121afaf18SBorislav Petkov if (atomic_inc_return(&mce_fake_panicked) > 1) 31221afaf18SBorislav Petkov return; 31321afaf18SBorislav Petkov } 31421afaf18SBorislav Petkov pending = mce_gen_pool_prepare_records(); 31521afaf18SBorislav Petkov /* First print corrected ones that are still unlogged */ 31621afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 31721afaf18SBorislav Petkov struct mce *m = &l->mce; 31821afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) { 31921afaf18SBorislav Petkov print_mce(m); 32021afaf18SBorislav Petkov if (!apei_err) 32121afaf18SBorislav Petkov apei_err = apei_write_mce(m); 32221afaf18SBorislav Petkov } 32321afaf18SBorislav Petkov } 32421afaf18SBorislav Petkov /* Now print uncorrected but with the final one last */ 32521afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 32621afaf18SBorislav Petkov struct mce *m = &l->mce; 32721afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) 32821afaf18SBorislav Petkov continue; 32921afaf18SBorislav Petkov if (!final || mce_cmp(m, final)) { 33021afaf18SBorislav Petkov print_mce(m); 33121afaf18SBorislav Petkov if (!apei_err) 33221afaf18SBorislav Petkov apei_err = apei_write_mce(m); 33321afaf18SBorislav Petkov } 33421afaf18SBorislav Petkov } 33521afaf18SBorislav Petkov if (final) { 33621afaf18SBorislav Petkov print_mce(final); 33721afaf18SBorislav Petkov if (!apei_err) 33821afaf18SBorislav Petkov apei_err = apei_write_mce(final); 33921afaf18SBorislav Petkov } 34021afaf18SBorislav Petkov if (cpu_missing) 34121afaf18SBorislav Petkov pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); 34221afaf18SBorislav Petkov if (exp) 34321afaf18SBorislav Petkov pr_emerg(HW_ERR "Machine check: %s\n", exp); 34421afaf18SBorislav Petkov if (!fake_panic) { 34521afaf18SBorislav Petkov if (panic_timeout == 0) 34621afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 34721afaf18SBorislav Petkov panic(msg); 34821afaf18SBorislav Petkov } else 34921afaf18SBorislav Petkov pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); 35021afaf18SBorislav Petkov } 35121afaf18SBorislav Petkov 35221afaf18SBorislav Petkov /* Support code for software error injection */ 35321afaf18SBorislav Petkov 35421afaf18SBorislav Petkov static int msr_to_offset(u32 msr) 35521afaf18SBorislav Petkov { 35621afaf18SBorislav Petkov unsigned bank = __this_cpu_read(injectm.bank); 35721afaf18SBorislav Petkov 35821afaf18SBorislav Petkov if (msr == mca_cfg.rip_msr) 35921afaf18SBorislav Petkov return offsetof(struct mce, ip); 36021afaf18SBorislav Petkov if (msr == msr_ops.status(bank)) 36121afaf18SBorislav Petkov return offsetof(struct mce, status); 36221afaf18SBorislav Petkov if (msr == msr_ops.addr(bank)) 36321afaf18SBorislav Petkov return offsetof(struct mce, addr); 36421afaf18SBorislav Petkov if (msr == msr_ops.misc(bank)) 36521afaf18SBorislav Petkov return offsetof(struct mce, misc); 36621afaf18SBorislav Petkov if (msr == MSR_IA32_MCG_STATUS) 36721afaf18SBorislav Petkov return offsetof(struct mce, mcgstatus); 36821afaf18SBorislav Petkov return -1; 36921afaf18SBorislav Petkov } 37021afaf18SBorislav Petkov 37121afaf18SBorislav Petkov /* MSR access wrappers used for error injection */ 37221afaf18SBorislav Petkov static u64 mce_rdmsrl(u32 msr) 37321afaf18SBorislav Petkov { 37421afaf18SBorislav Petkov u64 v; 37521afaf18SBorislav Petkov 37621afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 37721afaf18SBorislav Petkov int offset = msr_to_offset(msr); 37821afaf18SBorislav Petkov 37921afaf18SBorislav Petkov if (offset < 0) 38021afaf18SBorislav Petkov return 0; 38121afaf18SBorislav Petkov return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); 38221afaf18SBorislav Petkov } 38321afaf18SBorislav Petkov 38421afaf18SBorislav Petkov if (rdmsrl_safe(msr, &v)) { 38521afaf18SBorislav Petkov WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr); 38621afaf18SBorislav Petkov /* 38721afaf18SBorislav Petkov * Return zero in case the access faulted. This should 38821afaf18SBorislav Petkov * not happen normally but can happen if the CPU does 38921afaf18SBorislav Petkov * something weird, or if the code is buggy. 39021afaf18SBorislav Petkov */ 39121afaf18SBorislav Petkov v = 0; 39221afaf18SBorislav Petkov } 39321afaf18SBorislav Petkov 39421afaf18SBorislav Petkov return v; 39521afaf18SBorislav Petkov } 39621afaf18SBorislav Petkov 39721afaf18SBorislav Petkov static void mce_wrmsrl(u32 msr, u64 v) 39821afaf18SBorislav Petkov { 39921afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 40021afaf18SBorislav Petkov int offset = msr_to_offset(msr); 40121afaf18SBorislav Petkov 40221afaf18SBorislav Petkov if (offset >= 0) 40321afaf18SBorislav Petkov *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; 40421afaf18SBorislav Petkov return; 40521afaf18SBorislav Petkov } 40621afaf18SBorislav Petkov wrmsrl(msr, v); 40721afaf18SBorislav Petkov } 40821afaf18SBorislav Petkov 40921afaf18SBorislav Petkov /* 41021afaf18SBorislav Petkov * Collect all global (w.r.t. this processor) status about this machine 41121afaf18SBorislav Petkov * check into our "mce" struct so that we can use it later to assess 41221afaf18SBorislav Petkov * the severity of the problem as we read per-bank specific details. 41321afaf18SBorislav Petkov */ 41421afaf18SBorislav Petkov static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) 41521afaf18SBorislav Petkov { 41621afaf18SBorislav Petkov mce_setup(m); 41721afaf18SBorislav Petkov 41821afaf18SBorislav Petkov m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 41921afaf18SBorislav Petkov if (regs) { 42021afaf18SBorislav Petkov /* 42121afaf18SBorislav Petkov * Get the address of the instruction at the time of 42221afaf18SBorislav Petkov * the machine check error. 42321afaf18SBorislav Petkov */ 42421afaf18SBorislav Petkov if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { 42521afaf18SBorislav Petkov m->ip = regs->ip; 42621afaf18SBorislav Petkov m->cs = regs->cs; 42721afaf18SBorislav Petkov 42821afaf18SBorislav Petkov /* 42921afaf18SBorislav Petkov * When in VM86 mode make the cs look like ring 3 43021afaf18SBorislav Petkov * always. This is a lie, but it's better than passing 43121afaf18SBorislav Petkov * the additional vm86 bit around everywhere. 43221afaf18SBorislav Petkov */ 43321afaf18SBorislav Petkov if (v8086_mode(regs)) 43421afaf18SBorislav Petkov m->cs |= 3; 43521afaf18SBorislav Petkov } 43621afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 43721afaf18SBorislav Petkov if (mca_cfg.rip_msr) 43821afaf18SBorislav Petkov m->ip = mce_rdmsrl(mca_cfg.rip_msr); 43921afaf18SBorislav Petkov } 44021afaf18SBorislav Petkov } 44121afaf18SBorislav Petkov 44221afaf18SBorislav Petkov int mce_available(struct cpuinfo_x86 *c) 44321afaf18SBorislav Petkov { 44421afaf18SBorislav Petkov if (mca_cfg.disabled) 44521afaf18SBorislav Petkov return 0; 44621afaf18SBorislav Petkov return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); 44721afaf18SBorislav Petkov } 44821afaf18SBorislav Petkov 44921afaf18SBorislav Petkov static void mce_schedule_work(void) 45021afaf18SBorislav Petkov { 45121afaf18SBorislav Petkov if (!mce_gen_pool_empty()) 45221afaf18SBorislav Petkov schedule_work(&mce_work); 45321afaf18SBorislav Petkov } 45421afaf18SBorislav Petkov 45521afaf18SBorislav Petkov static void mce_irq_work_cb(struct irq_work *entry) 45621afaf18SBorislav Petkov { 45721afaf18SBorislav Petkov mce_schedule_work(); 45821afaf18SBorislav Petkov } 45921afaf18SBorislav Petkov 46021afaf18SBorislav Petkov /* 46121afaf18SBorislav Petkov * Check if the address reported by the CPU is in a format we can parse. 46221afaf18SBorislav Petkov * It would be possible to add code for most other cases, but all would 46321afaf18SBorislav Petkov * be somewhat complicated (e.g. segment offset would require an instruction 46421afaf18SBorislav Petkov * parser). So only support physical addresses up to page granuality for now. 46521afaf18SBorislav Petkov */ 46621afaf18SBorislav Petkov int mce_usable_address(struct mce *m) 46721afaf18SBorislav Petkov { 46821afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_ADDRV)) 46921afaf18SBorislav Petkov return 0; 47021afaf18SBorislav Petkov 4716e898d2bSTony W Wang-oc /* Checks after this one are Intel/Zhaoxin-specific: */ 4726e898d2bSTony W Wang-oc if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && 4736e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) 47421afaf18SBorislav Petkov return 1; 47521afaf18SBorislav Petkov 47621afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_MISCV)) 47721afaf18SBorislav Petkov return 0; 47821afaf18SBorislav Petkov 47921afaf18SBorislav Petkov if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) 48021afaf18SBorislav Petkov return 0; 48121afaf18SBorislav Petkov 48221afaf18SBorislav Petkov if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) 48321afaf18SBorislav Petkov return 0; 48421afaf18SBorislav Petkov 48521afaf18SBorislav Petkov return 1; 48621afaf18SBorislav Petkov } 48721afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_usable_address); 48821afaf18SBorislav Petkov 48921afaf18SBorislav Petkov bool mce_is_memory_error(struct mce *m) 49021afaf18SBorislav Petkov { 4916e898d2bSTony W Wang-oc switch (m->cpuvendor) { 4926e898d2bSTony W Wang-oc case X86_VENDOR_AMD: 4936e898d2bSTony W Wang-oc case X86_VENDOR_HYGON: 49421afaf18SBorislav Petkov return amd_mce_is_memory_error(m); 4956e898d2bSTony W Wang-oc 4966e898d2bSTony W Wang-oc case X86_VENDOR_INTEL: 4976e898d2bSTony W Wang-oc case X86_VENDOR_ZHAOXIN: 49821afaf18SBorislav Petkov /* 49921afaf18SBorislav Petkov * Intel SDM Volume 3B - 15.9.2 Compound Error Codes 50021afaf18SBorislav Petkov * 50121afaf18SBorislav Petkov * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for 50221afaf18SBorislav Petkov * indicating a memory error. Bit 8 is used for indicating a 50321afaf18SBorislav Petkov * cache hierarchy error. The combination of bit 2 and bit 3 50421afaf18SBorislav Petkov * is used for indicating a `generic' cache hierarchy error 50521afaf18SBorislav Petkov * But we can't just blindly check the above bits, because if 50621afaf18SBorislav Petkov * bit 11 is set, then it is a bus/interconnect error - and 50721afaf18SBorislav Petkov * either way the above bits just gives more detail on what 50821afaf18SBorislav Petkov * bus/interconnect error happened. Note that bit 12 can be 50921afaf18SBorislav Petkov * ignored, as it's the "filter" bit. 51021afaf18SBorislav Petkov */ 51121afaf18SBorislav Petkov return (m->status & 0xef80) == BIT(7) || 51221afaf18SBorislav Petkov (m->status & 0xef00) == BIT(8) || 51321afaf18SBorislav Petkov (m->status & 0xeffc) == 0xc; 51421afaf18SBorislav Petkov 5156e898d2bSTony W Wang-oc default: 51621afaf18SBorislav Petkov return false; 51721afaf18SBorislav Petkov } 5186e898d2bSTony W Wang-oc } 51921afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_memory_error); 52021afaf18SBorislav Petkov 52121afaf18SBorislav Petkov bool mce_is_correctable(struct mce *m) 52221afaf18SBorislav Petkov { 52321afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED) 52421afaf18SBorislav Petkov return false; 52521afaf18SBorislav Petkov 52621afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED) 52721afaf18SBorislav Petkov return false; 52821afaf18SBorislav Petkov 52921afaf18SBorislav Petkov if (m->status & MCI_STATUS_UC) 53021afaf18SBorislav Petkov return false; 53121afaf18SBorislav Petkov 53221afaf18SBorislav Petkov return true; 53321afaf18SBorislav Petkov } 53421afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_correctable); 53521afaf18SBorislav Petkov 536c9c6d216STony Luck static int mce_early_notifier(struct notifier_block *nb, unsigned long val, 53721afaf18SBorislav Petkov void *data) 53821afaf18SBorislav Petkov { 53921afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 54021afaf18SBorislav Petkov 54121afaf18SBorislav Petkov if (!m) 54221afaf18SBorislav Petkov return NOTIFY_DONE; 54321afaf18SBorislav Petkov 54421afaf18SBorislav Petkov /* Emit the trace record: */ 54521afaf18SBorislav Petkov trace_mce_record(m); 54621afaf18SBorislav Petkov 54721afaf18SBorislav Petkov set_bit(0, &mce_need_notify); 54821afaf18SBorislav Petkov 54921afaf18SBorislav Petkov mce_notify_irq(); 55021afaf18SBorislav Petkov 55121afaf18SBorislav Petkov return NOTIFY_DONE; 55221afaf18SBorislav Petkov } 55321afaf18SBorislav Petkov 554c9c6d216STony Luck static struct notifier_block early_nb = { 555c9c6d216STony Luck .notifier_call = mce_early_notifier, 556c9c6d216STony Luck .priority = MCE_PRIO_EARLY, 55721afaf18SBorislav Petkov }; 55821afaf18SBorislav Petkov 5598438b84aSJan H. Schönherr static int uc_decode_notifier(struct notifier_block *nb, unsigned long val, 56021afaf18SBorislav Petkov void *data) 56121afaf18SBorislav Petkov { 56221afaf18SBorislav Petkov struct mce *mce = (struct mce *)data; 56321afaf18SBorislav Petkov unsigned long pfn; 56421afaf18SBorislav Petkov 5658438b84aSJan H. Schönherr if (!mce || !mce_usable_address(mce)) 56621afaf18SBorislav Petkov return NOTIFY_DONE; 56721afaf18SBorislav Petkov 5688438b84aSJan H. Schönherr if (mce->severity != MCE_AO_SEVERITY && 5698438b84aSJan H. Schönherr mce->severity != MCE_DEFERRED_SEVERITY) 5708438b84aSJan H. Schönherr return NOTIFY_DONE; 5718438b84aSJan H. Schönherr 57221afaf18SBorislav Petkov pfn = mce->addr >> PAGE_SHIFT; 57323ba710aSTony Luck if (!memory_failure(pfn, 0)) { 57421afaf18SBorislav Petkov set_mce_nospec(pfn); 57523ba710aSTony Luck mce->kflags |= MCE_HANDLED_UC; 57623ba710aSTony Luck } 57721afaf18SBorislav Petkov 57821afaf18SBorislav Petkov return NOTIFY_OK; 57921afaf18SBorislav Petkov } 5808438b84aSJan H. Schönherr 5818438b84aSJan H. Schönherr static struct notifier_block mce_uc_nb = { 5828438b84aSJan H. Schönherr .notifier_call = uc_decode_notifier, 5838438b84aSJan H. Schönherr .priority = MCE_PRIO_UC, 58421afaf18SBorislav Petkov }; 58521afaf18SBorislav Petkov 58621afaf18SBorislav Petkov static int mce_default_notifier(struct notifier_block *nb, unsigned long val, 58721afaf18SBorislav Petkov void *data) 58821afaf18SBorislav Petkov { 58921afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 59021afaf18SBorislav Petkov 59121afaf18SBorislav Petkov if (!m) 59221afaf18SBorislav Petkov return NOTIFY_DONE; 59321afaf18SBorislav Petkov 594925946cfSTony Luck if (!m->kflags) 59521afaf18SBorislav Petkov __print_mce(m); 59621afaf18SBorislav Petkov 59721afaf18SBorislav Petkov return NOTIFY_DONE; 59821afaf18SBorislav Petkov } 59921afaf18SBorislav Petkov 60021afaf18SBorislav Petkov static struct notifier_block mce_default_nb = { 60121afaf18SBorislav Petkov .notifier_call = mce_default_notifier, 60221afaf18SBorislav Petkov /* lowest prio, we want it to run last. */ 60321afaf18SBorislav Petkov .priority = MCE_PRIO_LOWEST, 60421afaf18SBorislav Petkov }; 60521afaf18SBorislav Petkov 60621afaf18SBorislav Petkov /* 60721afaf18SBorislav Petkov * Read ADDR and MISC registers. 60821afaf18SBorislav Petkov */ 60921afaf18SBorislav Petkov static void mce_read_aux(struct mce *m, int i) 61021afaf18SBorislav Petkov { 61121afaf18SBorislav Petkov if (m->status & MCI_STATUS_MISCV) 61221afaf18SBorislav Petkov m->misc = mce_rdmsrl(msr_ops.misc(i)); 61321afaf18SBorislav Petkov 61421afaf18SBorislav Petkov if (m->status & MCI_STATUS_ADDRV) { 61521afaf18SBorislav Petkov m->addr = mce_rdmsrl(msr_ops.addr(i)); 61621afaf18SBorislav Petkov 61721afaf18SBorislav Petkov /* 61821afaf18SBorislav Petkov * Mask the reported address by the reported granularity. 61921afaf18SBorislav Petkov */ 62021afaf18SBorislav Petkov if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { 62121afaf18SBorislav Petkov u8 shift = MCI_MISC_ADDR_LSB(m->misc); 62221afaf18SBorislav Petkov m->addr >>= shift; 62321afaf18SBorislav Petkov m->addr <<= shift; 62421afaf18SBorislav Petkov } 62521afaf18SBorislav Petkov 62621afaf18SBorislav Petkov /* 62721afaf18SBorislav Petkov * Extract [55:<lsb>] where lsb is the least significant 62821afaf18SBorislav Petkov * *valid* bit of the address bits. 62921afaf18SBorislav Petkov */ 63021afaf18SBorislav Petkov if (mce_flags.smca) { 63121afaf18SBorislav Petkov u8 lsb = (m->addr >> 56) & 0x3f; 63221afaf18SBorislav Petkov 63321afaf18SBorislav Petkov m->addr &= GENMASK_ULL(55, lsb); 63421afaf18SBorislav Petkov } 63521afaf18SBorislav Petkov } 63621afaf18SBorislav Petkov 63721afaf18SBorislav Petkov if (mce_flags.smca) { 63821afaf18SBorislav Petkov m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); 63921afaf18SBorislav Petkov 64021afaf18SBorislav Petkov if (m->status & MCI_STATUS_SYNDV) 64121afaf18SBorislav Petkov m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); 64221afaf18SBorislav Petkov } 64321afaf18SBorislav Petkov } 64421afaf18SBorislav Petkov 64521afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_poll_count); 64621afaf18SBorislav Petkov 64721afaf18SBorislav Petkov /* 64821afaf18SBorislav Petkov * Poll for corrected events or events that happened before reset. 64921afaf18SBorislav Petkov * Those are just logged through /dev/mcelog. 65021afaf18SBorislav Petkov * 65121afaf18SBorislav Petkov * This is executed in standard interrupt context. 65221afaf18SBorislav Petkov * 65321afaf18SBorislav Petkov * Note: spec recommends to panic for fatal unsignalled 65421afaf18SBorislav Petkov * errors here. However this would be quite problematic -- 65521afaf18SBorislav Petkov * we would need to reimplement the Monarch handling and 65621afaf18SBorislav Petkov * it would mess up the exclusion between exception handler 657312a4661SLinus Torvalds * and poll handler -- * so we skip this for now. 65821afaf18SBorislav Petkov * These cases should not happen anyways, or only when the CPU 65921afaf18SBorislav Petkov * is already totally * confused. In this case it's likely it will 66021afaf18SBorislav Petkov * not fully execute the machine check handler either. 66121afaf18SBorislav Petkov */ 66221afaf18SBorislav Petkov bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) 66321afaf18SBorislav Petkov { 664b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 66521afaf18SBorislav Petkov bool error_seen = false; 66621afaf18SBorislav Petkov struct mce m; 66721afaf18SBorislav Petkov int i; 66821afaf18SBorislav Petkov 66921afaf18SBorislav Petkov this_cpu_inc(mce_poll_count); 67021afaf18SBorislav Petkov 67121afaf18SBorislav Petkov mce_gather_info(&m, NULL); 67221afaf18SBorislav Petkov 67321afaf18SBorislav Petkov if (flags & MCP_TIMESTAMP) 67421afaf18SBorislav Petkov m.tsc = rdtsc(); 67521afaf18SBorislav Petkov 676c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 67721afaf18SBorislav Petkov if (!mce_banks[i].ctl || !test_bit(i, *b)) 67821afaf18SBorislav Petkov continue; 67921afaf18SBorislav Petkov 68021afaf18SBorislav Petkov m.misc = 0; 68121afaf18SBorislav Petkov m.addr = 0; 68221afaf18SBorislav Petkov m.bank = i; 68321afaf18SBorislav Petkov 68421afaf18SBorislav Petkov barrier(); 68521afaf18SBorislav Petkov m.status = mce_rdmsrl(msr_ops.status(i)); 686f19501aaSTony Luck 687f19501aaSTony Luck /* If this entry is not valid, ignore it */ 68821afaf18SBorislav Petkov if (!(m.status & MCI_STATUS_VAL)) 68921afaf18SBorislav Petkov continue; 69021afaf18SBorislav Petkov 69121afaf18SBorislav Petkov /* 692f19501aaSTony Luck * If we are logging everything (at CPU online) or this 693f19501aaSTony Luck * is a corrected error, then we must log it. 69421afaf18SBorislav Petkov */ 695f19501aaSTony Luck if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC)) 696f19501aaSTony Luck goto log_it; 697f19501aaSTony Luck 698f19501aaSTony Luck /* 699f19501aaSTony Luck * Newer Intel systems that support software error 700f19501aaSTony Luck * recovery need to make additional checks. Other 701f19501aaSTony Luck * CPUs should skip over uncorrected errors, but log 702f19501aaSTony Luck * everything else. 703f19501aaSTony Luck */ 704f19501aaSTony Luck if (!mca_cfg.ser) { 705f19501aaSTony Luck if (m.status & MCI_STATUS_UC) 706f19501aaSTony Luck continue; 707f19501aaSTony Luck goto log_it; 708f19501aaSTony Luck } 709f19501aaSTony Luck 710f19501aaSTony Luck /* Log "not enabled" (speculative) errors */ 711f19501aaSTony Luck if (!(m.status & MCI_STATUS_EN)) 712f19501aaSTony Luck goto log_it; 713f19501aaSTony Luck 714f19501aaSTony Luck /* 715f19501aaSTony Luck * Log UCNA (SDM: 15.6.3 "UCR Error Classification") 716f19501aaSTony Luck * UC == 1 && PCC == 0 && S == 0 717f19501aaSTony Luck */ 718f19501aaSTony Luck if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S)) 719f19501aaSTony Luck goto log_it; 720f19501aaSTony Luck 721f19501aaSTony Luck /* 722f19501aaSTony Luck * Skip anything else. Presumption is that our read of this 723f19501aaSTony Luck * bank is racing with a machine check. Leave the log alone 724f19501aaSTony Luck * for do_machine_check() to deal with it. 725f19501aaSTony Luck */ 72621afaf18SBorislav Petkov continue; 72721afaf18SBorislav Petkov 728f19501aaSTony Luck log_it: 72921afaf18SBorislav Petkov error_seen = true; 73021afaf18SBorislav Petkov 73190454e49SJan H. Schönherr if (flags & MCP_DONTLOG) 73290454e49SJan H. Schönherr goto clear_it; 73390454e49SJan H. Schönherr 73421afaf18SBorislav Petkov mce_read_aux(&m, i); 73521afaf18SBorislav Petkov m.severity = mce_severity(&m, mca_cfg.tolerant, NULL, false); 73621afaf18SBorislav Petkov /* 73721afaf18SBorislav Petkov * Don't get the IP here because it's unlikely to 73821afaf18SBorislav Petkov * have anything to do with the actual error location. 73921afaf18SBorislav Petkov */ 74021afaf18SBorislav Petkov 74190454e49SJan H. Schönherr if (mca_cfg.dont_log_ce && !mce_usable_address(&m)) 74290454e49SJan H. Schönherr goto clear_it; 74390454e49SJan H. Schönherr 74490454e49SJan H. Schönherr mce_log(&m); 74590454e49SJan H. Schönherr 74690454e49SJan H. Schönherr clear_it: 74721afaf18SBorislav Petkov /* 74821afaf18SBorislav Petkov * Clear state for this bank. 74921afaf18SBorislav Petkov */ 75021afaf18SBorislav Petkov mce_wrmsrl(msr_ops.status(i), 0); 75121afaf18SBorislav Petkov } 75221afaf18SBorislav Petkov 75321afaf18SBorislav Petkov /* 75421afaf18SBorislav Petkov * Don't clear MCG_STATUS here because it's only defined for 75521afaf18SBorislav Petkov * exceptions. 75621afaf18SBorislav Petkov */ 75721afaf18SBorislav Petkov 75821afaf18SBorislav Petkov sync_core(); 75921afaf18SBorislav Petkov 76021afaf18SBorislav Petkov return error_seen; 76121afaf18SBorislav Petkov } 76221afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(machine_check_poll); 76321afaf18SBorislav Petkov 76421afaf18SBorislav Petkov /* 76521afaf18SBorislav Petkov * Do a quick check if any of the events requires a panic. 76621afaf18SBorislav Petkov * This decides if we keep the events around or clear them. 76721afaf18SBorislav Petkov */ 76821afaf18SBorislav Petkov static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, 76921afaf18SBorislav Petkov struct pt_regs *regs) 77021afaf18SBorislav Petkov { 7717a8bc2b0SJan H. Schönherr char *tmp = *msg; 77221afaf18SBorislav Petkov int i; 77321afaf18SBorislav Petkov 774c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 77521afaf18SBorislav Petkov m->status = mce_rdmsrl(msr_ops.status(i)); 77621afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 77721afaf18SBorislav Petkov continue; 77821afaf18SBorislav Petkov 77921afaf18SBorislav Petkov __set_bit(i, validp); 78021afaf18SBorislav Petkov if (quirk_no_way_out) 78121afaf18SBorislav Petkov quirk_no_way_out(i, m, regs); 78221afaf18SBorislav Petkov 783d28af26fSTony Luck m->bank = i; 784a3a57ddaSJan H. Schönherr if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) { 78521afaf18SBorislav Petkov mce_read_aux(m, i); 78621afaf18SBorislav Petkov *msg = tmp; 78721afaf18SBorislav Petkov return 1; 78821afaf18SBorislav Petkov } 78921afaf18SBorislav Petkov } 79021afaf18SBorislav Petkov return 0; 79121afaf18SBorislav Petkov } 79221afaf18SBorislav Petkov 79321afaf18SBorislav Petkov /* 79421afaf18SBorislav Petkov * Variable to establish order between CPUs while scanning. 79521afaf18SBorislav Petkov * Each CPU spins initially until executing is equal its number. 79621afaf18SBorislav Petkov */ 79721afaf18SBorislav Petkov static atomic_t mce_executing; 79821afaf18SBorislav Petkov 79921afaf18SBorislav Petkov /* 80021afaf18SBorislav Petkov * Defines order of CPUs on entry. First CPU becomes Monarch. 80121afaf18SBorislav Petkov */ 80221afaf18SBorislav Petkov static atomic_t mce_callin; 80321afaf18SBorislav Petkov 80421afaf18SBorislav Petkov /* 80521afaf18SBorislav Petkov * Check if a timeout waiting for other CPUs happened. 80621afaf18SBorislav Petkov */ 80721afaf18SBorislav Petkov static int mce_timed_out(u64 *t, const char *msg) 80821afaf18SBorislav Petkov { 80921afaf18SBorislav Petkov /* 81021afaf18SBorislav Petkov * The others already did panic for some reason. 81121afaf18SBorislav Petkov * Bail out like in a timeout. 81221afaf18SBorislav Petkov * rmb() to tell the compiler that system_state 81321afaf18SBorislav Petkov * might have been modified by someone else. 81421afaf18SBorislav Petkov */ 81521afaf18SBorislav Petkov rmb(); 81621afaf18SBorislav Petkov if (atomic_read(&mce_panicked)) 81721afaf18SBorislav Petkov wait_for_panic(); 81821afaf18SBorislav Petkov if (!mca_cfg.monarch_timeout) 81921afaf18SBorislav Petkov goto out; 82021afaf18SBorislav Petkov if ((s64)*t < SPINUNIT) { 82121afaf18SBorislav Petkov if (mca_cfg.tolerant <= 1) 82221afaf18SBorislav Petkov mce_panic(msg, NULL, NULL); 82321afaf18SBorislav Petkov cpu_missing = 1; 82421afaf18SBorislav Petkov return 1; 82521afaf18SBorislav Petkov } 82621afaf18SBorislav Petkov *t -= SPINUNIT; 82721afaf18SBorislav Petkov out: 82821afaf18SBorislav Petkov touch_nmi_watchdog(); 82921afaf18SBorislav Petkov return 0; 83021afaf18SBorislav Petkov } 83121afaf18SBorislav Petkov 83221afaf18SBorislav Petkov /* 83321afaf18SBorislav Petkov * The Monarch's reign. The Monarch is the CPU who entered 83421afaf18SBorislav Petkov * the machine check handler first. It waits for the others to 83521afaf18SBorislav Petkov * raise the exception too and then grades them. When any 83621afaf18SBorislav Petkov * error is fatal panic. Only then let the others continue. 83721afaf18SBorislav Petkov * 83821afaf18SBorislav Petkov * The other CPUs entering the MCE handler will be controlled by the 83921afaf18SBorislav Petkov * Monarch. They are called Subjects. 84021afaf18SBorislav Petkov * 84121afaf18SBorislav Petkov * This way we prevent any potential data corruption in a unrecoverable case 84221afaf18SBorislav Petkov * and also makes sure always all CPU's errors are examined. 84321afaf18SBorislav Petkov * 84421afaf18SBorislav Petkov * Also this detects the case of a machine check event coming from outer 84521afaf18SBorislav Petkov * space (not detected by any CPUs) In this case some external agent wants 84621afaf18SBorislav Petkov * us to shut down, so panic too. 84721afaf18SBorislav Petkov * 84821afaf18SBorislav Petkov * The other CPUs might still decide to panic if the handler happens 84921afaf18SBorislav Petkov * in a unrecoverable place, but in this case the system is in a semi-stable 85021afaf18SBorislav Petkov * state and won't corrupt anything by itself. It's ok to let the others 85121afaf18SBorislav Petkov * continue for a bit first. 85221afaf18SBorislav Petkov * 85321afaf18SBorislav Petkov * All the spin loops have timeouts; when a timeout happens a CPU 85421afaf18SBorislav Petkov * typically elects itself to be Monarch. 85521afaf18SBorislav Petkov */ 85621afaf18SBorislav Petkov static void mce_reign(void) 85721afaf18SBorislav Petkov { 85821afaf18SBorislav Petkov int cpu; 85921afaf18SBorislav Petkov struct mce *m = NULL; 86021afaf18SBorislav Petkov int global_worst = 0; 86121afaf18SBorislav Petkov char *msg = NULL; 86221afaf18SBorislav Petkov char *nmsg = NULL; 86321afaf18SBorislav Petkov 86421afaf18SBorislav Petkov /* 86521afaf18SBorislav Petkov * This CPU is the Monarch and the other CPUs have run 86621afaf18SBorislav Petkov * through their handlers. 86721afaf18SBorislav Petkov * Grade the severity of the errors of all the CPUs. 86821afaf18SBorislav Petkov */ 86921afaf18SBorislav Petkov for_each_possible_cpu(cpu) { 87021afaf18SBorislav Petkov int severity = mce_severity(&per_cpu(mces_seen, cpu), 87121afaf18SBorislav Petkov mca_cfg.tolerant, 87221afaf18SBorislav Petkov &nmsg, true); 87321afaf18SBorislav Petkov if (severity > global_worst) { 87421afaf18SBorislav Petkov msg = nmsg; 87521afaf18SBorislav Petkov global_worst = severity; 87621afaf18SBorislav Petkov m = &per_cpu(mces_seen, cpu); 87721afaf18SBorislav Petkov } 87821afaf18SBorislav Petkov } 87921afaf18SBorislav Petkov 88021afaf18SBorislav Petkov /* 88121afaf18SBorislav Petkov * Cannot recover? Panic here then. 88221afaf18SBorislav Petkov * This dumps all the mces in the log buffer and stops the 88321afaf18SBorislav Petkov * other CPUs. 88421afaf18SBorislav Petkov */ 88521afaf18SBorislav Petkov if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) 88621afaf18SBorislav Petkov mce_panic("Fatal machine check", m, msg); 88721afaf18SBorislav Petkov 88821afaf18SBorislav Petkov /* 88921afaf18SBorislav Petkov * For UC somewhere we let the CPU who detects it handle it. 89021afaf18SBorislav Petkov * Also must let continue the others, otherwise the handling 89121afaf18SBorislav Petkov * CPU could deadlock on a lock. 89221afaf18SBorislav Petkov */ 89321afaf18SBorislav Petkov 89421afaf18SBorislav Petkov /* 89521afaf18SBorislav Petkov * No machine check event found. Must be some external 89621afaf18SBorislav Petkov * source or one CPU is hung. Panic. 89721afaf18SBorislav Petkov */ 89821afaf18SBorislav Petkov if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) 89921afaf18SBorislav Petkov mce_panic("Fatal machine check from unknown source", NULL, NULL); 90021afaf18SBorislav Petkov 90121afaf18SBorislav Petkov /* 90221afaf18SBorislav Petkov * Now clear all the mces_seen so that they don't reappear on 90321afaf18SBorislav Petkov * the next mce. 90421afaf18SBorislav Petkov */ 90521afaf18SBorislav Petkov for_each_possible_cpu(cpu) 90621afaf18SBorislav Petkov memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); 90721afaf18SBorislav Petkov } 90821afaf18SBorislav Petkov 90921afaf18SBorislav Petkov static atomic_t global_nwo; 91021afaf18SBorislav Petkov 91121afaf18SBorislav Petkov /* 91221afaf18SBorislav Petkov * Start of Monarch synchronization. This waits until all CPUs have 91321afaf18SBorislav Petkov * entered the exception handler and then determines if any of them 91421afaf18SBorislav Petkov * saw a fatal event that requires panic. Then it executes them 91521afaf18SBorislav Petkov * in the entry order. 91621afaf18SBorislav Petkov * TBD double check parallel CPU hotunplug 91721afaf18SBorislav Petkov */ 91821afaf18SBorislav Petkov static int mce_start(int *no_way_out) 91921afaf18SBorislav Petkov { 92021afaf18SBorislav Petkov int order; 92121afaf18SBorislav Petkov int cpus = num_online_cpus(); 92221afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 92321afaf18SBorislav Petkov 92421afaf18SBorislav Petkov if (!timeout) 92521afaf18SBorislav Petkov return -1; 92621afaf18SBorislav Petkov 92721afaf18SBorislav Petkov atomic_add(*no_way_out, &global_nwo); 92821afaf18SBorislav Petkov /* 92921afaf18SBorislav Petkov * Rely on the implied barrier below, such that global_nwo 93021afaf18SBorislav Petkov * is updated before mce_callin. 93121afaf18SBorislav Petkov */ 93221afaf18SBorislav Petkov order = atomic_inc_return(&mce_callin); 93321afaf18SBorislav Petkov 93421afaf18SBorislav Petkov /* 93521afaf18SBorislav Petkov * Wait for everyone. 93621afaf18SBorislav Petkov */ 93721afaf18SBorislav Petkov while (atomic_read(&mce_callin) != cpus) { 93821afaf18SBorislav Petkov if (mce_timed_out(&timeout, 93921afaf18SBorislav Petkov "Timeout: Not all CPUs entered broadcast exception handler")) { 94021afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 94121afaf18SBorislav Petkov return -1; 94221afaf18SBorislav Petkov } 94321afaf18SBorislav Petkov ndelay(SPINUNIT); 94421afaf18SBorislav Petkov } 94521afaf18SBorislav Petkov 94621afaf18SBorislav Petkov /* 94721afaf18SBorislav Petkov * mce_callin should be read before global_nwo 94821afaf18SBorislav Petkov */ 94921afaf18SBorislav Petkov smp_rmb(); 95021afaf18SBorislav Petkov 95121afaf18SBorislav Petkov if (order == 1) { 95221afaf18SBorislav Petkov /* 95321afaf18SBorislav Petkov * Monarch: Starts executing now, the others wait. 95421afaf18SBorislav Petkov */ 95521afaf18SBorislav Petkov atomic_set(&mce_executing, 1); 95621afaf18SBorislav Petkov } else { 95721afaf18SBorislav Petkov /* 95821afaf18SBorislav Petkov * Subject: Now start the scanning loop one by one in 95921afaf18SBorislav Petkov * the original callin order. 96021afaf18SBorislav Petkov * This way when there are any shared banks it will be 96121afaf18SBorislav Petkov * only seen by one CPU before cleared, avoiding duplicates. 96221afaf18SBorislav Petkov */ 96321afaf18SBorislav Petkov while (atomic_read(&mce_executing) < order) { 96421afaf18SBorislav Petkov if (mce_timed_out(&timeout, 96521afaf18SBorislav Petkov "Timeout: Subject CPUs unable to finish machine check processing")) { 96621afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 96721afaf18SBorislav Petkov return -1; 96821afaf18SBorislav Petkov } 96921afaf18SBorislav Petkov ndelay(SPINUNIT); 97021afaf18SBorislav Petkov } 97121afaf18SBorislav Petkov } 97221afaf18SBorislav Petkov 97321afaf18SBorislav Petkov /* 97421afaf18SBorislav Petkov * Cache the global no_way_out state. 97521afaf18SBorislav Petkov */ 97621afaf18SBorislav Petkov *no_way_out = atomic_read(&global_nwo); 97721afaf18SBorislav Petkov 97821afaf18SBorislav Petkov return order; 97921afaf18SBorislav Petkov } 98021afaf18SBorislav Petkov 98121afaf18SBorislav Petkov /* 98221afaf18SBorislav Petkov * Synchronize between CPUs after main scanning loop. 98321afaf18SBorislav Petkov * This invokes the bulk of the Monarch processing. 98421afaf18SBorislav Petkov */ 98521afaf18SBorislav Petkov static int mce_end(int order) 98621afaf18SBorislav Petkov { 98721afaf18SBorislav Petkov int ret = -1; 98821afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 98921afaf18SBorislav Petkov 99021afaf18SBorislav Petkov if (!timeout) 99121afaf18SBorislav Petkov goto reset; 99221afaf18SBorislav Petkov if (order < 0) 99321afaf18SBorislav Petkov goto reset; 99421afaf18SBorislav Petkov 99521afaf18SBorislav Petkov /* 99621afaf18SBorislav Petkov * Allow others to run. 99721afaf18SBorislav Petkov */ 99821afaf18SBorislav Petkov atomic_inc(&mce_executing); 99921afaf18SBorislav Petkov 100021afaf18SBorislav Petkov if (order == 1) { 100121afaf18SBorislav Petkov /* CHECKME: Can this race with a parallel hotplug? */ 100221afaf18SBorislav Petkov int cpus = num_online_cpus(); 100321afaf18SBorislav Petkov 100421afaf18SBorislav Petkov /* 100521afaf18SBorislav Petkov * Monarch: Wait for everyone to go through their scanning 100621afaf18SBorislav Petkov * loops. 100721afaf18SBorislav Petkov */ 100821afaf18SBorislav Petkov while (atomic_read(&mce_executing) <= cpus) { 100921afaf18SBorislav Petkov if (mce_timed_out(&timeout, 101021afaf18SBorislav Petkov "Timeout: Monarch CPU unable to finish machine check processing")) 101121afaf18SBorislav Petkov goto reset; 101221afaf18SBorislav Petkov ndelay(SPINUNIT); 101321afaf18SBorislav Petkov } 101421afaf18SBorislav Petkov 101521afaf18SBorislav Petkov mce_reign(); 101621afaf18SBorislav Petkov barrier(); 101721afaf18SBorislav Petkov ret = 0; 101821afaf18SBorislav Petkov } else { 101921afaf18SBorislav Petkov /* 102021afaf18SBorislav Petkov * Subject: Wait for Monarch to finish. 102121afaf18SBorislav Petkov */ 102221afaf18SBorislav Petkov while (atomic_read(&mce_executing) != 0) { 102321afaf18SBorislav Petkov if (mce_timed_out(&timeout, 102421afaf18SBorislav Petkov "Timeout: Monarch CPU did not finish machine check processing")) 102521afaf18SBorislav Petkov goto reset; 102621afaf18SBorislav Petkov ndelay(SPINUNIT); 102721afaf18SBorislav Petkov } 102821afaf18SBorislav Petkov 102921afaf18SBorislav Petkov /* 103021afaf18SBorislav Petkov * Don't reset anything. That's done by the Monarch. 103121afaf18SBorislav Petkov */ 103221afaf18SBorislav Petkov return 0; 103321afaf18SBorislav Petkov } 103421afaf18SBorislav Petkov 103521afaf18SBorislav Petkov /* 103621afaf18SBorislav Petkov * Reset all global state. 103721afaf18SBorislav Petkov */ 103821afaf18SBorislav Petkov reset: 103921afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 104021afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 104121afaf18SBorislav Petkov barrier(); 104221afaf18SBorislav Petkov 104321afaf18SBorislav Petkov /* 104421afaf18SBorislav Petkov * Let others run again. 104521afaf18SBorislav Petkov */ 104621afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 104721afaf18SBorislav Petkov return ret; 104821afaf18SBorislav Petkov } 104921afaf18SBorislav Petkov 105021afaf18SBorislav Petkov static void mce_clear_state(unsigned long *toclear) 105121afaf18SBorislav Petkov { 105221afaf18SBorislav Petkov int i; 105321afaf18SBorislav Petkov 1054c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 105521afaf18SBorislav Petkov if (test_bit(i, toclear)) 105621afaf18SBorislav Petkov mce_wrmsrl(msr_ops.status(i), 0); 105721afaf18SBorislav Petkov } 105821afaf18SBorislav Petkov } 105921afaf18SBorislav Petkov 106021afaf18SBorislav Petkov static int do_memory_failure(struct mce *m) 106121afaf18SBorislav Petkov { 106221afaf18SBorislav Petkov int flags = MF_ACTION_REQUIRED; 106321afaf18SBorislav Petkov int ret; 106421afaf18SBorislav Petkov 106521afaf18SBorislav Petkov pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr); 106621afaf18SBorislav Petkov if (!(m->mcgstatus & MCG_STATUS_RIPV)) 106721afaf18SBorislav Petkov flags |= MF_MUST_KILL; 106821afaf18SBorislav Petkov ret = memory_failure(m->addr >> PAGE_SHIFT, flags); 106921afaf18SBorislav Petkov if (ret) 107021afaf18SBorislav Petkov pr_err("Memory error not recovered"); 107121afaf18SBorislav Petkov else 107221afaf18SBorislav Petkov set_mce_nospec(m->addr >> PAGE_SHIFT); 107321afaf18SBorislav Petkov return ret; 107421afaf18SBorislav Petkov } 107521afaf18SBorislav Petkov 107621afaf18SBorislav Petkov 107721afaf18SBorislav Petkov /* 107821afaf18SBorislav Petkov * Cases where we avoid rendezvous handler timeout: 107921afaf18SBorislav Petkov * 1) If this CPU is offline. 108021afaf18SBorislav Petkov * 108121afaf18SBorislav Petkov * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to 108221afaf18SBorislav Petkov * skip those CPUs which remain looping in the 1st kernel - see 108321afaf18SBorislav Petkov * crash_nmi_callback(). 108421afaf18SBorislav Petkov * 108521afaf18SBorislav Petkov * Note: there still is a small window between kexec-ing and the new, 108621afaf18SBorislav Petkov * kdump kernel establishing a new #MC handler where a broadcasted MCE 108721afaf18SBorislav Petkov * might not get handled properly. 108821afaf18SBorislav Petkov */ 108921afaf18SBorislav Petkov static bool __mc_check_crashing_cpu(int cpu) 109021afaf18SBorislav Petkov { 109121afaf18SBorislav Petkov if (cpu_is_offline(cpu) || 109221afaf18SBorislav Petkov (crashing_cpu != -1 && crashing_cpu != cpu)) { 109321afaf18SBorislav Petkov u64 mcgstatus; 109421afaf18SBorislav Petkov 109521afaf18SBorislav Petkov mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 109670f0c230STony W Wang-oc 109770f0c230STony W Wang-oc if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { 109870f0c230STony W Wang-oc if (mcgstatus & MCG_STATUS_LMCES) 109970f0c230STony W Wang-oc return false; 110070f0c230STony W Wang-oc } 110170f0c230STony W Wang-oc 110221afaf18SBorislav Petkov if (mcgstatus & MCG_STATUS_RIPV) { 110321afaf18SBorislav Petkov mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); 110421afaf18SBorislav Petkov return true; 110521afaf18SBorislav Petkov } 110621afaf18SBorislav Petkov } 110721afaf18SBorislav Petkov return false; 110821afaf18SBorislav Petkov } 110921afaf18SBorislav Petkov 111021afaf18SBorislav Petkov static void __mc_scan_banks(struct mce *m, struct mce *final, 111121afaf18SBorislav Petkov unsigned long *toclear, unsigned long *valid_banks, 111221afaf18SBorislav Petkov int no_way_out, int *worst) 111321afaf18SBorislav Petkov { 1114b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 111521afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 111621afaf18SBorislav Petkov int severity, i; 111721afaf18SBorislav Petkov 1118c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 111921afaf18SBorislav Petkov __clear_bit(i, toclear); 112021afaf18SBorislav Petkov if (!test_bit(i, valid_banks)) 112121afaf18SBorislav Petkov continue; 112221afaf18SBorislav Petkov 112321afaf18SBorislav Petkov if (!mce_banks[i].ctl) 112421afaf18SBorislav Petkov continue; 112521afaf18SBorislav Petkov 112621afaf18SBorislav Petkov m->misc = 0; 112721afaf18SBorislav Petkov m->addr = 0; 112821afaf18SBorislav Petkov m->bank = i; 112921afaf18SBorislav Petkov 113021afaf18SBorislav Petkov m->status = mce_rdmsrl(msr_ops.status(i)); 113121afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 113221afaf18SBorislav Petkov continue; 113321afaf18SBorislav Petkov 113421afaf18SBorislav Petkov /* 113521afaf18SBorislav Petkov * Corrected or non-signaled errors are handled by 113621afaf18SBorislav Petkov * machine_check_poll(). Leave them alone, unless this panics. 113721afaf18SBorislav Petkov */ 113821afaf18SBorislav Petkov if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && 113921afaf18SBorislav Petkov !no_way_out) 114021afaf18SBorislav Petkov continue; 114121afaf18SBorislav Petkov 114221afaf18SBorislav Petkov /* Set taint even when machine check was not enabled. */ 114321afaf18SBorislav Petkov add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 114421afaf18SBorislav Petkov 114521afaf18SBorislav Petkov severity = mce_severity(m, cfg->tolerant, NULL, true); 114621afaf18SBorislav Petkov 114721afaf18SBorislav Petkov /* 114821afaf18SBorislav Petkov * When machine check was for corrected/deferred handler don't 114921afaf18SBorislav Petkov * touch, unless we're panicking. 115021afaf18SBorislav Petkov */ 115121afaf18SBorislav Petkov if ((severity == MCE_KEEP_SEVERITY || 115221afaf18SBorislav Petkov severity == MCE_UCNA_SEVERITY) && !no_way_out) 115321afaf18SBorislav Petkov continue; 115421afaf18SBorislav Petkov 115521afaf18SBorislav Petkov __set_bit(i, toclear); 115621afaf18SBorislav Petkov 115721afaf18SBorislav Petkov /* Machine check event was not enabled. Clear, but ignore. */ 115821afaf18SBorislav Petkov if (severity == MCE_NO_SEVERITY) 115921afaf18SBorislav Petkov continue; 116021afaf18SBorislav Petkov 116121afaf18SBorislav Petkov mce_read_aux(m, i); 116221afaf18SBorislav Petkov 116321afaf18SBorislav Petkov /* assuming valid severity level != 0 */ 116421afaf18SBorislav Petkov m->severity = severity; 116521afaf18SBorislav Petkov 116621afaf18SBorislav Petkov mce_log(m); 116721afaf18SBorislav Petkov 116821afaf18SBorislav Petkov if (severity > *worst) { 116921afaf18SBorislav Petkov *final = *m; 117021afaf18SBorislav Petkov *worst = severity; 117121afaf18SBorislav Petkov } 117221afaf18SBorislav Petkov } 117321afaf18SBorislav Petkov 117421afaf18SBorislav Petkov /* mce_clear_state will clear *final, save locally for use later */ 117521afaf18SBorislav Petkov *m = *final; 117621afaf18SBorislav Petkov } 117721afaf18SBorislav Petkov 117821afaf18SBorislav Petkov /* 117921afaf18SBorislav Petkov * The actual machine check handler. This only handles real 118021afaf18SBorislav Petkov * exceptions when something got corrupted coming in through int 18. 118121afaf18SBorislav Petkov * 118221afaf18SBorislav Petkov * This is executed in NMI context not subject to normal locking rules. This 118321afaf18SBorislav Petkov * implies that most kernel services cannot be safely used. Don't even 118421afaf18SBorislav Petkov * think about putting a printk in there! 118521afaf18SBorislav Petkov * 118621afaf18SBorislav Petkov * On Intel systems this is entered on all CPUs in parallel through 118721afaf18SBorislav Petkov * MCE broadcast. However some CPUs might be broken beyond repair, 118821afaf18SBorislav Petkov * so be always careful when synchronizing with others. 118955ba18d6SAndy Lutomirski * 119055ba18d6SAndy Lutomirski * Tracing and kprobes are disabled: if we interrupted a kernel context 119155ba18d6SAndy Lutomirski * with IF=1, we need to minimize stack usage. There are also recursion 119255ba18d6SAndy Lutomirski * issues: if the machine check was due to a failure of the memory 119355ba18d6SAndy Lutomirski * backing the user stack, tracing that reads the user stack will cause 119455ba18d6SAndy Lutomirski * potentially infinite recursion. 119521afaf18SBorislav Petkov */ 119655ba18d6SAndy Lutomirski void notrace do_machine_check(struct pt_regs *regs, long error_code) 119721afaf18SBorislav Petkov { 119821afaf18SBorislav Petkov DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); 119921afaf18SBorislav Petkov DECLARE_BITMAP(toclear, MAX_NR_BANKS); 120021afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 120121afaf18SBorislav Petkov int cpu = smp_processor_id(); 120221afaf18SBorislav Petkov struct mce m, *final; 12037a8bc2b0SJan H. Schönherr char *msg = NULL; 120421afaf18SBorislav Petkov int worst = 0; 120521afaf18SBorislav Petkov 120621afaf18SBorislav Petkov /* 120721afaf18SBorislav Petkov * Establish sequential order between the CPUs entering the machine 120821afaf18SBorislav Petkov * check handler. 120921afaf18SBorislav Petkov */ 121021afaf18SBorislav Petkov int order = -1; 121121afaf18SBorislav Petkov 121221afaf18SBorislav Petkov /* 121321afaf18SBorislav Petkov * If no_way_out gets set, there is no safe way to recover from this 121421afaf18SBorislav Petkov * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. 121521afaf18SBorislav Petkov */ 121621afaf18SBorislav Petkov int no_way_out = 0; 121721afaf18SBorislav Petkov 121821afaf18SBorislav Petkov /* 121921afaf18SBorislav Petkov * If kill_it gets set, there might be a way to recover from this 122021afaf18SBorislav Petkov * error. 122121afaf18SBorislav Petkov */ 122221afaf18SBorislav Petkov int kill_it = 0; 122321afaf18SBorislav Petkov 122421afaf18SBorislav Petkov /* 122521afaf18SBorislav Petkov * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES 122621afaf18SBorislav Petkov * on Intel. 122721afaf18SBorislav Petkov */ 122821afaf18SBorislav Petkov int lmce = 1; 122921afaf18SBorislav Petkov 123021afaf18SBorislav Petkov if (__mc_check_crashing_cpu(cpu)) 123121afaf18SBorislav Petkov return; 123221afaf18SBorislav Petkov 123321afaf18SBorislav Petkov ist_enter(regs); 123421afaf18SBorislav Petkov 123521afaf18SBorislav Petkov this_cpu_inc(mce_exception_count); 123621afaf18SBorislav Petkov 123721afaf18SBorislav Petkov mce_gather_info(&m, regs); 123821afaf18SBorislav Petkov m.tsc = rdtsc(); 123921afaf18SBorislav Petkov 124021afaf18SBorislav Petkov final = this_cpu_ptr(&mces_seen); 124121afaf18SBorislav Petkov *final = m; 124221afaf18SBorislav Petkov 124321afaf18SBorislav Petkov memset(valid_banks, 0, sizeof(valid_banks)); 124421afaf18SBorislav Petkov no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); 124521afaf18SBorislav Petkov 124621afaf18SBorislav Petkov barrier(); 124721afaf18SBorislav Petkov 124821afaf18SBorislav Petkov /* 124921afaf18SBorislav Petkov * When no restart IP might need to kill or panic. 125021afaf18SBorislav Petkov * Assume the worst for now, but if we find the 125121afaf18SBorislav Petkov * severity is MCE_AR_SEVERITY we have other options. 125221afaf18SBorislav Petkov */ 125321afaf18SBorislav Petkov if (!(m.mcgstatus & MCG_STATUS_RIPV)) 125421afaf18SBorislav Petkov kill_it = 1; 125521afaf18SBorislav Petkov 125621afaf18SBorislav Petkov /* 125721afaf18SBorislav Petkov * Check if this MCE is signaled to only this logical processor, 125870f0c230STony W Wang-oc * on Intel, Zhaoxin only. 125921afaf18SBorislav Petkov */ 126070f0c230STony W Wang-oc if (m.cpuvendor == X86_VENDOR_INTEL || 126170f0c230STony W Wang-oc m.cpuvendor == X86_VENDOR_ZHAOXIN) 126221afaf18SBorislav Petkov lmce = m.mcgstatus & MCG_STATUS_LMCES; 126321afaf18SBorislav Petkov 126421afaf18SBorislav Petkov /* 126521afaf18SBorislav Petkov * Local machine check may already know that we have to panic. 126621afaf18SBorislav Petkov * Broadcast machine check begins rendezvous in mce_start() 126721afaf18SBorislav Petkov * Go through all banks in exclusion of the other CPUs. This way we 126821afaf18SBorislav Petkov * don't report duplicated events on shared banks because the first one 126921afaf18SBorislav Petkov * to see it will clear it. 127021afaf18SBorislav Petkov */ 127121afaf18SBorislav Petkov if (lmce) { 127221afaf18SBorislav Petkov if (no_way_out) 127321afaf18SBorislav Petkov mce_panic("Fatal local machine check", &m, msg); 127421afaf18SBorislav Petkov } else { 127521afaf18SBorislav Petkov order = mce_start(&no_way_out); 127621afaf18SBorislav Petkov } 127721afaf18SBorislav Petkov 127821afaf18SBorislav Petkov __mc_scan_banks(&m, final, toclear, valid_banks, no_way_out, &worst); 127921afaf18SBorislav Petkov 128021afaf18SBorislav Petkov if (!no_way_out) 128121afaf18SBorislav Petkov mce_clear_state(toclear); 128221afaf18SBorislav Petkov 128321afaf18SBorislav Petkov /* 128421afaf18SBorislav Petkov * Do most of the synchronization with other CPUs. 128521afaf18SBorislav Petkov * When there's any problem use only local no_way_out state. 128621afaf18SBorislav Petkov */ 128721afaf18SBorislav Petkov if (!lmce) { 128821afaf18SBorislav Petkov if (mce_end(order) < 0) 128921afaf18SBorislav Petkov no_way_out = worst >= MCE_PANIC_SEVERITY; 129021afaf18SBorislav Petkov } else { 129121afaf18SBorislav Petkov /* 129221afaf18SBorislav Petkov * If there was a fatal machine check we should have 129321afaf18SBorislav Petkov * already called mce_panic earlier in this function. 129421afaf18SBorislav Petkov * Since we re-read the banks, we might have found 129521afaf18SBorislav Petkov * something new. Check again to see if we found a 129621afaf18SBorislav Petkov * fatal error. We call "mce_severity()" again to 129721afaf18SBorislav Petkov * make sure we have the right "msg". 129821afaf18SBorislav Petkov */ 129921afaf18SBorislav Petkov if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) { 130021afaf18SBorislav Petkov mce_severity(&m, cfg->tolerant, &msg, true); 130121afaf18SBorislav Petkov mce_panic("Local fatal machine check!", &m, msg); 130221afaf18SBorislav Petkov } 130321afaf18SBorislav Petkov } 130421afaf18SBorislav Petkov 130521afaf18SBorislav Petkov /* 130621afaf18SBorislav Petkov * If tolerant is at an insane level we drop requests to kill 130721afaf18SBorislav Petkov * processes and continue even when there is no way out. 130821afaf18SBorislav Petkov */ 130921afaf18SBorislav Petkov if (cfg->tolerant == 3) 131021afaf18SBorislav Petkov kill_it = 0; 131121afaf18SBorislav Petkov else if (no_way_out) 131221afaf18SBorislav Petkov mce_panic("Fatal machine check on current CPU", &m, msg); 131321afaf18SBorislav Petkov 131421afaf18SBorislav Petkov if (worst > 0) 131539f0584eSBorislav Petkov irq_work_queue(&mce_irq_work); 131639f0584eSBorislav Petkov 131721afaf18SBorislav Petkov mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); 131821afaf18SBorislav Petkov 131921afaf18SBorislav Petkov sync_core(); 132021afaf18SBorislav Petkov 132121afaf18SBorislav Petkov if (worst != MCE_AR_SEVERITY && !kill_it) 132221afaf18SBorislav Petkov goto out_ist; 132321afaf18SBorislav Petkov 132421afaf18SBorislav Petkov /* Fault was in user mode and we need to take some action */ 132521afaf18SBorislav Petkov if ((m.cs & 3) == 3) { 132621afaf18SBorislav Petkov ist_begin_non_atomic(regs); 132721afaf18SBorislav Petkov local_irq_enable(); 132821afaf18SBorislav Petkov 132921afaf18SBorislav Petkov if (kill_it || do_memory_failure(&m)) 13303cf5d076SEric W. Biederman force_sig(SIGBUS); 133121afaf18SBorislav Petkov local_irq_disable(); 133221afaf18SBorislav Petkov ist_end_non_atomic(); 133321afaf18SBorislav Petkov } else { 133421afaf18SBorislav Petkov if (!fixup_exception(regs, X86_TRAP_MC, error_code, 0)) 13352d806d07SJan H. Schönherr mce_panic("Failed kernel mode recovery", &m, msg); 133621afaf18SBorislav Petkov } 133721afaf18SBorislav Petkov 133821afaf18SBorislav Petkov out_ist: 133921afaf18SBorislav Petkov ist_exit(regs); 134021afaf18SBorislav Petkov } 134121afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(do_machine_check); 134255ba18d6SAndy Lutomirski NOKPROBE_SYMBOL(do_machine_check); 134321afaf18SBorislav Petkov 134421afaf18SBorislav Petkov #ifndef CONFIG_MEMORY_FAILURE 134521afaf18SBorislav Petkov int memory_failure(unsigned long pfn, int flags) 134621afaf18SBorislav Petkov { 134721afaf18SBorislav Petkov /* mce_severity() should not hand us an ACTION_REQUIRED error */ 134821afaf18SBorislav Petkov BUG_ON(flags & MF_ACTION_REQUIRED); 134921afaf18SBorislav Petkov pr_err("Uncorrected memory error in page 0x%lx ignored\n" 135021afaf18SBorislav Petkov "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", 135121afaf18SBorislav Petkov pfn); 135221afaf18SBorislav Petkov 135321afaf18SBorislav Petkov return 0; 135421afaf18SBorislav Petkov } 135521afaf18SBorislav Petkov #endif 135621afaf18SBorislav Petkov 135721afaf18SBorislav Petkov /* 135821afaf18SBorislav Petkov * Periodic polling timer for "silent" machine check errors. If the 135921afaf18SBorislav Petkov * poller finds an MCE, poll 2x faster. When the poller finds no more 136021afaf18SBorislav Petkov * errors, poll 2x slower (up to check_interval seconds). 136121afaf18SBorislav Petkov */ 136221afaf18SBorislav Petkov static unsigned long check_interval = INITIAL_CHECK_INTERVAL; 136321afaf18SBorislav Petkov 136421afaf18SBorislav Petkov static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ 136521afaf18SBorislav Petkov static DEFINE_PER_CPU(struct timer_list, mce_timer); 136621afaf18SBorislav Petkov 136721afaf18SBorislav Petkov static unsigned long mce_adjust_timer_default(unsigned long interval) 136821afaf18SBorislav Petkov { 136921afaf18SBorislav Petkov return interval; 137021afaf18SBorislav Petkov } 137121afaf18SBorislav Petkov 137221afaf18SBorislav Petkov static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; 137321afaf18SBorislav Petkov 137421afaf18SBorislav Petkov static void __start_timer(struct timer_list *t, unsigned long interval) 137521afaf18SBorislav Petkov { 137621afaf18SBorislav Petkov unsigned long when = jiffies + interval; 137721afaf18SBorislav Petkov unsigned long flags; 137821afaf18SBorislav Petkov 137921afaf18SBorislav Petkov local_irq_save(flags); 138021afaf18SBorislav Petkov 138121afaf18SBorislav Petkov if (!timer_pending(t) || time_before(when, t->expires)) 138221afaf18SBorislav Petkov mod_timer(t, round_jiffies(when)); 138321afaf18SBorislav Petkov 138421afaf18SBorislav Petkov local_irq_restore(flags); 138521afaf18SBorislav Petkov } 138621afaf18SBorislav Petkov 138721afaf18SBorislav Petkov static void mce_timer_fn(struct timer_list *t) 138821afaf18SBorislav Petkov { 138921afaf18SBorislav Petkov struct timer_list *cpu_t = this_cpu_ptr(&mce_timer); 139021afaf18SBorislav Petkov unsigned long iv; 139121afaf18SBorislav Petkov 139221afaf18SBorislav Petkov WARN_ON(cpu_t != t); 139321afaf18SBorislav Petkov 139421afaf18SBorislav Petkov iv = __this_cpu_read(mce_next_interval); 139521afaf18SBorislav Petkov 139621afaf18SBorislav Petkov if (mce_available(this_cpu_ptr(&cpu_info))) { 139721afaf18SBorislav Petkov machine_check_poll(0, this_cpu_ptr(&mce_poll_banks)); 139821afaf18SBorislav Petkov 139921afaf18SBorislav Petkov if (mce_intel_cmci_poll()) { 140021afaf18SBorislav Petkov iv = mce_adjust_timer(iv); 140121afaf18SBorislav Petkov goto done; 140221afaf18SBorislav Petkov } 140321afaf18SBorislav Petkov } 140421afaf18SBorislav Petkov 140521afaf18SBorislav Petkov /* 140621afaf18SBorislav Petkov * Alert userspace if needed. If we logged an MCE, reduce the polling 140721afaf18SBorislav Petkov * interval, otherwise increase the polling interval. 140821afaf18SBorislav Petkov */ 140921afaf18SBorislav Petkov if (mce_notify_irq()) 141021afaf18SBorislav Petkov iv = max(iv / 2, (unsigned long) HZ/100); 141121afaf18SBorislav Petkov else 141221afaf18SBorislav Petkov iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); 141321afaf18SBorislav Petkov 141421afaf18SBorislav Petkov done: 141521afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, iv); 141621afaf18SBorislav Petkov __start_timer(t, iv); 141721afaf18SBorislav Petkov } 141821afaf18SBorislav Petkov 141921afaf18SBorislav Petkov /* 142021afaf18SBorislav Petkov * Ensure that the timer is firing in @interval from now. 142121afaf18SBorislav Petkov */ 142221afaf18SBorislav Petkov void mce_timer_kick(unsigned long interval) 142321afaf18SBorislav Petkov { 142421afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 142521afaf18SBorislav Petkov unsigned long iv = __this_cpu_read(mce_next_interval); 142621afaf18SBorislav Petkov 142721afaf18SBorislav Petkov __start_timer(t, interval); 142821afaf18SBorislav Petkov 142921afaf18SBorislav Petkov if (interval < iv) 143021afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, interval); 143121afaf18SBorislav Petkov } 143221afaf18SBorislav Petkov 143321afaf18SBorislav Petkov /* Must not be called in IRQ context where del_timer_sync() can deadlock */ 143421afaf18SBorislav Petkov static void mce_timer_delete_all(void) 143521afaf18SBorislav Petkov { 143621afaf18SBorislav Petkov int cpu; 143721afaf18SBorislav Petkov 143821afaf18SBorislav Petkov for_each_online_cpu(cpu) 143921afaf18SBorislav Petkov del_timer_sync(&per_cpu(mce_timer, cpu)); 144021afaf18SBorislav Petkov } 144121afaf18SBorislav Petkov 144221afaf18SBorislav Petkov /* 144321afaf18SBorislav Petkov * Notify the user(s) about new machine check events. 144421afaf18SBorislav Petkov * Can be called from interrupt context, but not from machine check/NMI 144521afaf18SBorislav Petkov * context. 144621afaf18SBorislav Petkov */ 144721afaf18SBorislav Petkov int mce_notify_irq(void) 144821afaf18SBorislav Petkov { 144921afaf18SBorislav Petkov /* Not more than two messages every minute */ 145021afaf18SBorislav Petkov static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); 145121afaf18SBorislav Petkov 145221afaf18SBorislav Petkov if (test_and_clear_bit(0, &mce_need_notify)) { 145321afaf18SBorislav Petkov mce_work_trigger(); 145421afaf18SBorislav Petkov 145521afaf18SBorislav Petkov if (__ratelimit(&ratelimit)) 145621afaf18SBorislav Petkov pr_info(HW_ERR "Machine check events logged\n"); 145721afaf18SBorislav Petkov 145821afaf18SBorislav Petkov return 1; 145921afaf18SBorislav Petkov } 146021afaf18SBorislav Petkov return 0; 146121afaf18SBorislav Petkov } 146221afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_notify_irq); 146321afaf18SBorislav Petkov 1464b4914508SYazen Ghannam static void __mcheck_cpu_mce_banks_init(void) 146521afaf18SBorislav Petkov { 1466b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1467c7d314f3SYazen Ghannam u8 n_banks = this_cpu_read(mce_num_banks); 146821afaf18SBorislav Petkov int i; 146921afaf18SBorislav Petkov 1470c7d314f3SYazen Ghannam for (i = 0; i < n_banks; i++) { 147121afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 147221afaf18SBorislav Petkov 1473068b053dSYazen Ghannam /* 1474068b053dSYazen Ghannam * Init them all, __mcheck_cpu_apply_quirks() is going to apply 1475068b053dSYazen Ghannam * the required vendor quirks before 1476068b053dSYazen Ghannam * __mcheck_cpu_init_clear_banks() does the final bank setup. 1477068b053dSYazen Ghannam */ 147821afaf18SBorislav Petkov b->ctl = -1ULL; 147921afaf18SBorislav Petkov b->init = 1; 148021afaf18SBorislav Petkov } 148121afaf18SBorislav Petkov } 148221afaf18SBorislav Petkov 148321afaf18SBorislav Petkov /* 148421afaf18SBorislav Petkov * Initialize Machine Checks for a CPU. 148521afaf18SBorislav Petkov */ 1486b4914508SYazen Ghannam static void __mcheck_cpu_cap_init(void) 148721afaf18SBorislav Petkov { 148821afaf18SBorislav Petkov u64 cap; 1489006c0770SYazen Ghannam u8 b; 149021afaf18SBorislav Petkov 149121afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 149221afaf18SBorislav Petkov 149321afaf18SBorislav Petkov b = cap & MCG_BANKCNT_MASK; 149421afaf18SBorislav Petkov 1495c7d314f3SYazen Ghannam if (b > MAX_NR_BANKS) { 1496c7d314f3SYazen Ghannam pr_warn("CPU%d: Using only %u machine check banks out of %u\n", 1497c7d314f3SYazen Ghannam smp_processor_id(), MAX_NR_BANKS, b); 1498c7d314f3SYazen Ghannam b = MAX_NR_BANKS; 1499c7d314f3SYazen Ghannam } 1500c7d314f3SYazen Ghannam 1501c7d314f3SYazen Ghannam this_cpu_write(mce_num_banks, b); 150221afaf18SBorislav Petkov 1503b4914508SYazen Ghannam __mcheck_cpu_mce_banks_init(); 150421afaf18SBorislav Petkov 150521afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 150621afaf18SBorislav Petkov if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) 150721afaf18SBorislav Petkov mca_cfg.rip_msr = MSR_IA32_MCG_EIP; 150821afaf18SBorislav Petkov 150921afaf18SBorislav Petkov if (cap & MCG_SER_P) 151021afaf18SBorislav Petkov mca_cfg.ser = 1; 151121afaf18SBorislav Petkov } 151221afaf18SBorislav Petkov 151321afaf18SBorislav Petkov static void __mcheck_cpu_init_generic(void) 151421afaf18SBorislav Petkov { 151521afaf18SBorislav Petkov enum mcp_flags m_fl = 0; 151621afaf18SBorislav Petkov mce_banks_t all_banks; 151721afaf18SBorislav Petkov u64 cap; 151821afaf18SBorislav Petkov 151921afaf18SBorislav Petkov if (!mca_cfg.bootlog) 152021afaf18SBorislav Petkov m_fl = MCP_DONTLOG; 152121afaf18SBorislav Petkov 152221afaf18SBorislav Petkov /* 152321afaf18SBorislav Petkov * Log the machine checks left over from the previous reset. 152421afaf18SBorislav Petkov */ 152521afaf18SBorislav Petkov bitmap_fill(all_banks, MAX_NR_BANKS); 152621afaf18SBorislav Petkov machine_check_poll(MCP_UC | m_fl, &all_banks); 152721afaf18SBorislav Petkov 152821afaf18SBorislav Petkov cr4_set_bits(X86_CR4_MCE); 152921afaf18SBorislav Petkov 153021afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 153121afaf18SBorislav Petkov if (cap & MCG_CTL_P) 153221afaf18SBorislav Petkov wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); 153321afaf18SBorislav Petkov } 153421afaf18SBorislav Petkov 153521afaf18SBorislav Petkov static void __mcheck_cpu_init_clear_banks(void) 153621afaf18SBorislav Petkov { 1537b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 153821afaf18SBorislav Petkov int i; 153921afaf18SBorislav Petkov 1540c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 154121afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 154221afaf18SBorislav Petkov 154321afaf18SBorislav Petkov if (!b->init) 154421afaf18SBorislav Petkov continue; 154521afaf18SBorislav Petkov wrmsrl(msr_ops.ctl(i), b->ctl); 154621afaf18SBorislav Petkov wrmsrl(msr_ops.status(i), 0); 154721afaf18SBorislav Petkov } 154821afaf18SBorislav Petkov } 154921afaf18SBorislav Petkov 155021afaf18SBorislav Petkov /* 1551068b053dSYazen Ghannam * Do a final check to see if there are any unused/RAZ banks. 1552068b053dSYazen Ghannam * 1553068b053dSYazen Ghannam * This must be done after the banks have been initialized and any quirks have 1554068b053dSYazen Ghannam * been applied. 1555068b053dSYazen Ghannam * 1556068b053dSYazen Ghannam * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs. 1557068b053dSYazen Ghannam * Otherwise, a user who disables a bank will not be able to re-enable it 1558068b053dSYazen Ghannam * without a system reboot. 1559068b053dSYazen Ghannam */ 1560068b053dSYazen Ghannam static void __mcheck_cpu_check_banks(void) 1561068b053dSYazen Ghannam { 1562068b053dSYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1563068b053dSYazen Ghannam u64 msrval; 1564068b053dSYazen Ghannam int i; 1565068b053dSYazen Ghannam 1566068b053dSYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1567068b053dSYazen Ghannam struct mce_bank *b = &mce_banks[i]; 1568068b053dSYazen Ghannam 1569068b053dSYazen Ghannam if (!b->init) 1570068b053dSYazen Ghannam continue; 1571068b053dSYazen Ghannam 1572068b053dSYazen Ghannam rdmsrl(msr_ops.ctl(i), msrval); 1573068b053dSYazen Ghannam b->init = !!msrval; 1574068b053dSYazen Ghannam } 1575068b053dSYazen Ghannam } 1576068b053dSYazen Ghannam 1577068b053dSYazen Ghannam /* 157821afaf18SBorislav Petkov * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and 157921afaf18SBorislav Petkov * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM 158021afaf18SBorislav Petkov * Vol 3B Table 15-20). But this confuses both the code that determines 158121afaf18SBorislav Petkov * whether the machine check occurred in kernel or user mode, and also 158221afaf18SBorislav Petkov * the severity assessment code. Pretend that EIPV was set, and take the 158321afaf18SBorislav Petkov * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. 158421afaf18SBorislav Petkov */ 158521afaf18SBorislav Petkov static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) 158621afaf18SBorislav Petkov { 158721afaf18SBorislav Petkov if (bank != 0) 158821afaf18SBorislav Petkov return; 158921afaf18SBorislav Petkov if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) 159021afaf18SBorislav Petkov return; 159121afaf18SBorislav Petkov if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| 159221afaf18SBorislav Petkov MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| 159321afaf18SBorislav Petkov MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| 159421afaf18SBorislav Petkov MCACOD)) != 159521afaf18SBorislav Petkov (MCI_STATUS_UC|MCI_STATUS_EN| 159621afaf18SBorislav Petkov MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| 159721afaf18SBorislav Petkov MCI_STATUS_AR|MCACOD_INSTR)) 159821afaf18SBorislav Petkov return; 159921afaf18SBorislav Petkov 160021afaf18SBorislav Petkov m->mcgstatus |= MCG_STATUS_EIPV; 160121afaf18SBorislav Petkov m->ip = regs->ip; 160221afaf18SBorislav Petkov m->cs = regs->cs; 160321afaf18SBorislav Petkov } 160421afaf18SBorislav Petkov 160521afaf18SBorislav Petkov /* Add per CPU specific workarounds here */ 160621afaf18SBorislav Petkov static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) 160721afaf18SBorislav Petkov { 1608b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 160921afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 161021afaf18SBorislav Petkov 161121afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_UNKNOWN) { 161221afaf18SBorislav Petkov pr_info("unknown CPU type - not enabling MCE support\n"); 161321afaf18SBorislav Petkov return -EOPNOTSUPP; 161421afaf18SBorislav Petkov } 161521afaf18SBorislav Petkov 161621afaf18SBorislav Petkov /* This should be disabled by the BIOS, but isn't always */ 161721afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD) { 1618c7d314f3SYazen Ghannam if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { 161921afaf18SBorislav Petkov /* 162021afaf18SBorislav Petkov * disable GART TBL walk error reporting, which 162121afaf18SBorislav Petkov * trips off incorrectly with the IOMMU & 3ware 162221afaf18SBorislav Petkov * & Cerberus: 162321afaf18SBorislav Petkov */ 162421afaf18SBorislav Petkov clear_bit(10, (unsigned long *)&mce_banks[4].ctl); 162521afaf18SBorislav Petkov } 162621afaf18SBorislav Petkov if (c->x86 < 0x11 && cfg->bootlog < 0) { 162721afaf18SBorislav Petkov /* 162821afaf18SBorislav Petkov * Lots of broken BIOS around that don't clear them 162921afaf18SBorislav Petkov * by default and leave crap in there. Don't log: 163021afaf18SBorislav Petkov */ 163121afaf18SBorislav Petkov cfg->bootlog = 0; 163221afaf18SBorislav Petkov } 163321afaf18SBorislav Petkov /* 163421afaf18SBorislav Petkov * Various K7s with broken bank 0 around. Always disable 163521afaf18SBorislav Petkov * by default. 163621afaf18SBorislav Petkov */ 1637c7d314f3SYazen Ghannam if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0) 163821afaf18SBorislav Petkov mce_banks[0].ctl = 0; 163921afaf18SBorislav Petkov 164021afaf18SBorislav Petkov /* 164121afaf18SBorislav Petkov * overflow_recov is supported for F15h Models 00h-0fh 164221afaf18SBorislav Petkov * even though we don't have a CPUID bit for it. 164321afaf18SBorislav Petkov */ 164421afaf18SBorislav Petkov if (c->x86 == 0x15 && c->x86_model <= 0xf) 164521afaf18SBorislav Petkov mce_flags.overflow_recov = 1; 164621afaf18SBorislav Petkov 164721afaf18SBorislav Petkov } 164821afaf18SBorislav Petkov 164921afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_INTEL) { 165021afaf18SBorislav Petkov /* 165121afaf18SBorislav Petkov * SDM documents that on family 6 bank 0 should not be written 165221afaf18SBorislav Petkov * because it aliases to another special BIOS controlled 165321afaf18SBorislav Petkov * register. 165421afaf18SBorislav Petkov * But it's not aliased anymore on model 0x1a+ 165521afaf18SBorislav Petkov * Don't ignore bank 0 completely because there could be a 165621afaf18SBorislav Petkov * valid event later, merely don't write CTL0. 165721afaf18SBorislav Petkov */ 165821afaf18SBorislav Petkov 1659c7d314f3SYazen Ghannam if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) 166021afaf18SBorislav Petkov mce_banks[0].init = 0; 166121afaf18SBorislav Petkov 166221afaf18SBorislav Petkov /* 166321afaf18SBorislav Petkov * All newer Intel systems support MCE broadcasting. Enable 166421afaf18SBorislav Petkov * synchronization with a one second timeout. 166521afaf18SBorislav Petkov */ 166621afaf18SBorislav Petkov if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && 166721afaf18SBorislav Petkov cfg->monarch_timeout < 0) 166821afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 166921afaf18SBorislav Petkov 167021afaf18SBorislav Petkov /* 167121afaf18SBorislav Petkov * There are also broken BIOSes on some Pentium M and 167221afaf18SBorislav Petkov * earlier systems: 167321afaf18SBorislav Petkov */ 167421afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) 167521afaf18SBorislav Petkov cfg->bootlog = 0; 167621afaf18SBorislav Petkov 167721afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model == 45) 167821afaf18SBorislav Petkov quirk_no_way_out = quirk_sandybridge_ifu; 167921afaf18SBorislav Petkov } 16806e898d2bSTony W Wang-oc 16816e898d2bSTony W Wang-oc if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { 16826e898d2bSTony W Wang-oc /* 16836e898d2bSTony W Wang-oc * All newer Zhaoxin CPUs support MCE broadcasting. Enable 16846e898d2bSTony W Wang-oc * synchronization with a one second timeout. 16856e898d2bSTony W Wang-oc */ 16866e898d2bSTony W Wang-oc if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 16876e898d2bSTony W Wang-oc if (cfg->monarch_timeout < 0) 16886e898d2bSTony W Wang-oc cfg->monarch_timeout = USEC_PER_SEC; 16896e898d2bSTony W Wang-oc } 16906e898d2bSTony W Wang-oc } 16916e898d2bSTony W Wang-oc 169221afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 169321afaf18SBorislav Petkov cfg->monarch_timeout = 0; 169421afaf18SBorislav Petkov if (cfg->bootlog != 0) 169521afaf18SBorislav Petkov cfg->panic_timeout = 30; 169621afaf18SBorislav Petkov 169721afaf18SBorislav Petkov return 0; 169821afaf18SBorislav Petkov } 169921afaf18SBorislav Petkov 170021afaf18SBorislav Petkov static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) 170121afaf18SBorislav Petkov { 170221afaf18SBorislav Petkov if (c->x86 != 5) 170321afaf18SBorislav Petkov return 0; 170421afaf18SBorislav Petkov 170521afaf18SBorislav Petkov switch (c->x86_vendor) { 170621afaf18SBorislav Petkov case X86_VENDOR_INTEL: 170721afaf18SBorislav Petkov intel_p5_mcheck_init(c); 170821afaf18SBorislav Petkov return 1; 170921afaf18SBorislav Petkov break; 171021afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 171121afaf18SBorislav Petkov winchip_mcheck_init(c); 171221afaf18SBorislav Petkov return 1; 171321afaf18SBorislav Petkov break; 171421afaf18SBorislav Petkov default: 171521afaf18SBorislav Petkov return 0; 171621afaf18SBorislav Petkov } 171721afaf18SBorislav Petkov 171821afaf18SBorislav Petkov return 0; 171921afaf18SBorislav Petkov } 172021afaf18SBorislav Petkov 172121afaf18SBorislav Petkov /* 172221afaf18SBorislav Petkov * Init basic CPU features needed for early decoding of MCEs. 172321afaf18SBorislav Petkov */ 172421afaf18SBorislav Petkov static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) 172521afaf18SBorislav Petkov { 172621afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) { 172721afaf18SBorislav Petkov mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); 172821afaf18SBorislav Petkov mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); 172921afaf18SBorislav Petkov mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); 1730c9bf318fSThomas Gleixner mce_flags.amd_threshold = 1; 173121afaf18SBorislav Petkov 173221afaf18SBorislav Petkov if (mce_flags.smca) { 173321afaf18SBorislav Petkov msr_ops.ctl = smca_ctl_reg; 173421afaf18SBorislav Petkov msr_ops.status = smca_status_reg; 173521afaf18SBorislav Petkov msr_ops.addr = smca_addr_reg; 173621afaf18SBorislav Petkov msr_ops.misc = smca_misc_reg; 173721afaf18SBorislav Petkov } 173821afaf18SBorislav Petkov } 173921afaf18SBorislav Petkov } 174021afaf18SBorislav Petkov 174121afaf18SBorislav Petkov static void mce_centaur_feature_init(struct cpuinfo_x86 *c) 174221afaf18SBorislav Petkov { 174321afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 174421afaf18SBorislav Petkov 174521afaf18SBorislav Petkov /* 174621afaf18SBorislav Petkov * All newer Centaur CPUs support MCE broadcasting. Enable 174721afaf18SBorislav Petkov * synchronization with a one second timeout. 174821afaf18SBorislav Petkov */ 174921afaf18SBorislav Petkov if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) || 175021afaf18SBorislav Petkov c->x86 > 6) { 175121afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 175221afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 175321afaf18SBorislav Petkov } 175421afaf18SBorislav Petkov } 175521afaf18SBorislav Petkov 17565a3d56a0STony W Wang-oc static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) 17575a3d56a0STony W Wang-oc { 17585a3d56a0STony W Wang-oc struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 17595a3d56a0STony W Wang-oc 17605a3d56a0STony W Wang-oc /* 17615a3d56a0STony W Wang-oc * These CPUs have MCA bank 8 which reports only one error type called 17625a3d56a0STony W Wang-oc * SVAD (System View Address Decoder). The reporting of that error is 17635a3d56a0STony W Wang-oc * controlled by IA32_MC8.CTL.0. 17645a3d56a0STony W Wang-oc * 17655a3d56a0STony W Wang-oc * If enabled, prefetching on these CPUs will cause SVAD MCE when 17665a3d56a0STony W Wang-oc * virtual machines start and result in a system panic. Always disable 17675a3d56a0STony W Wang-oc * bank 8 SVAD error by default. 17685a3d56a0STony W Wang-oc */ 17695a3d56a0STony W Wang-oc if ((c->x86 == 7 && c->x86_model == 0x1b) || 17705a3d56a0STony W Wang-oc (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 17715a3d56a0STony W Wang-oc if (this_cpu_read(mce_num_banks) > 8) 17725a3d56a0STony W Wang-oc mce_banks[8].ctl = 0; 17735a3d56a0STony W Wang-oc } 17745a3d56a0STony W Wang-oc 17755a3d56a0STony W Wang-oc intel_init_cmci(); 177670f0c230STony W Wang-oc intel_init_lmce(); 17775a3d56a0STony W Wang-oc mce_adjust_timer = cmci_intel_adjust_timer; 17785a3d56a0STony W Wang-oc } 17795a3d56a0STony W Wang-oc 178070f0c230STony W Wang-oc static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) 178170f0c230STony W Wang-oc { 178270f0c230STony W Wang-oc intel_clear_lmce(); 178370f0c230STony W Wang-oc } 178470f0c230STony W Wang-oc 178521afaf18SBorislav Petkov static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) 178621afaf18SBorislav Petkov { 178721afaf18SBorislav Petkov switch (c->x86_vendor) { 178821afaf18SBorislav Petkov case X86_VENDOR_INTEL: 178921afaf18SBorislav Petkov mce_intel_feature_init(c); 179021afaf18SBorislav Petkov mce_adjust_timer = cmci_intel_adjust_timer; 179121afaf18SBorislav Petkov break; 179221afaf18SBorislav Petkov 179321afaf18SBorislav Petkov case X86_VENDOR_AMD: { 179421afaf18SBorislav Petkov mce_amd_feature_init(c); 179521afaf18SBorislav Petkov break; 179621afaf18SBorislav Petkov } 179721afaf18SBorislav Petkov 179821afaf18SBorislav Petkov case X86_VENDOR_HYGON: 179921afaf18SBorislav Petkov mce_hygon_feature_init(c); 180021afaf18SBorislav Petkov break; 180121afaf18SBorislav Petkov 180221afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 180321afaf18SBorislav Petkov mce_centaur_feature_init(c); 180421afaf18SBorislav Petkov break; 180521afaf18SBorislav Petkov 18065a3d56a0STony W Wang-oc case X86_VENDOR_ZHAOXIN: 18075a3d56a0STony W Wang-oc mce_zhaoxin_feature_init(c); 18085a3d56a0STony W Wang-oc break; 18095a3d56a0STony W Wang-oc 181021afaf18SBorislav Petkov default: 181121afaf18SBorislav Petkov break; 181221afaf18SBorislav Petkov } 181321afaf18SBorislav Petkov } 181421afaf18SBorislav Petkov 181521afaf18SBorislav Petkov static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) 181621afaf18SBorislav Petkov { 181721afaf18SBorislav Petkov switch (c->x86_vendor) { 181821afaf18SBorislav Petkov case X86_VENDOR_INTEL: 181921afaf18SBorislav Petkov mce_intel_feature_clear(c); 182021afaf18SBorislav Petkov break; 182170f0c230STony W Wang-oc 182270f0c230STony W Wang-oc case X86_VENDOR_ZHAOXIN: 182370f0c230STony W Wang-oc mce_zhaoxin_feature_clear(c); 182470f0c230STony W Wang-oc break; 182570f0c230STony W Wang-oc 182621afaf18SBorislav Petkov default: 182721afaf18SBorislav Petkov break; 182821afaf18SBorislav Petkov } 182921afaf18SBorislav Petkov } 183021afaf18SBorislav Petkov 183121afaf18SBorislav Petkov static void mce_start_timer(struct timer_list *t) 183221afaf18SBorislav Petkov { 183321afaf18SBorislav Petkov unsigned long iv = check_interval * HZ; 183421afaf18SBorislav Petkov 183521afaf18SBorislav Petkov if (mca_cfg.ignore_ce || !iv) 183621afaf18SBorislav Petkov return; 183721afaf18SBorislav Petkov 183821afaf18SBorislav Petkov this_cpu_write(mce_next_interval, iv); 183921afaf18SBorislav Petkov __start_timer(t, iv); 184021afaf18SBorislav Petkov } 184121afaf18SBorislav Petkov 184221afaf18SBorislav Petkov static void __mcheck_cpu_setup_timer(void) 184321afaf18SBorislav Petkov { 184421afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 184521afaf18SBorislav Petkov 184621afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 184721afaf18SBorislav Petkov } 184821afaf18SBorislav Petkov 184921afaf18SBorislav Petkov static void __mcheck_cpu_init_timer(void) 185021afaf18SBorislav Petkov { 185121afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 185221afaf18SBorislav Petkov 185321afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 185421afaf18SBorislav Petkov mce_start_timer(t); 185521afaf18SBorislav Petkov } 185621afaf18SBorislav Petkov 185745d4b7b9SYazen Ghannam bool filter_mce(struct mce *m) 185845d4b7b9SYazen Ghannam { 185971a84402SYazen Ghannam if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 186071a84402SYazen Ghannam return amd_filter_mce(m); 18612976908eSPrarit Bhargava if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 18622976908eSPrarit Bhargava return intel_filter_mce(m); 186371a84402SYazen Ghannam 186445d4b7b9SYazen Ghannam return false; 186545d4b7b9SYazen Ghannam } 186645d4b7b9SYazen Ghannam 186721afaf18SBorislav Petkov /* Handle unconfigured int18 (should never happen) */ 186821afaf18SBorislav Petkov static void unexpected_machine_check(struct pt_regs *regs, long error_code) 186921afaf18SBorislav Petkov { 187021afaf18SBorislav Petkov pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", 187121afaf18SBorislav Petkov smp_processor_id()); 187221afaf18SBorislav Petkov } 187321afaf18SBorislav Petkov 187421afaf18SBorislav Petkov /* Call the installed machine check handler for this CPU setup. */ 187521afaf18SBorislav Petkov void (*machine_check_vector)(struct pt_regs *, long error_code) = 187621afaf18SBorislav Petkov unexpected_machine_check; 187721afaf18SBorislav Petkov 187855ba18d6SAndy Lutomirski dotraplinkage notrace void do_mce(struct pt_regs *regs, long error_code) 187921afaf18SBorislav Petkov { 188021afaf18SBorislav Petkov machine_check_vector(regs, error_code); 188121afaf18SBorislav Petkov } 188255ba18d6SAndy Lutomirski NOKPROBE_SYMBOL(do_mce); 188321afaf18SBorislav Petkov 188421afaf18SBorislav Petkov /* 188521afaf18SBorislav Petkov * Called for each booted CPU to set up machine checks. 188621afaf18SBorislav Petkov * Must be called with preempt off: 188721afaf18SBorislav Petkov */ 188821afaf18SBorislav Petkov void mcheck_cpu_init(struct cpuinfo_x86 *c) 188921afaf18SBorislav Petkov { 189021afaf18SBorislav Petkov if (mca_cfg.disabled) 189121afaf18SBorislav Petkov return; 189221afaf18SBorislav Petkov 189321afaf18SBorislav Petkov if (__mcheck_cpu_ancient_init(c)) 189421afaf18SBorislav Petkov return; 189521afaf18SBorislav Petkov 189621afaf18SBorislav Petkov if (!mce_available(c)) 189721afaf18SBorislav Petkov return; 189821afaf18SBorislav Petkov 1899b4914508SYazen Ghannam __mcheck_cpu_cap_init(); 1900b4914508SYazen Ghannam 1901b4914508SYazen Ghannam if (__mcheck_cpu_apply_quirks(c) < 0) { 190221afaf18SBorislav Petkov mca_cfg.disabled = 1; 190321afaf18SBorislav Petkov return; 190421afaf18SBorislav Petkov } 190521afaf18SBorislav Petkov 190621afaf18SBorislav Petkov if (mce_gen_pool_init()) { 190721afaf18SBorislav Petkov mca_cfg.disabled = 1; 190821afaf18SBorislav Petkov pr_emerg("Couldn't allocate MCE records pool!\n"); 190921afaf18SBorislav Petkov return; 191021afaf18SBorislav Petkov } 191121afaf18SBorislav Petkov 191221afaf18SBorislav Petkov machine_check_vector = do_machine_check; 191321afaf18SBorislav Petkov 191421afaf18SBorislav Petkov __mcheck_cpu_init_early(c); 191521afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 191621afaf18SBorislav Petkov __mcheck_cpu_init_vendor(c); 191721afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 1918068b053dSYazen Ghannam __mcheck_cpu_check_banks(); 191921afaf18SBorislav Petkov __mcheck_cpu_setup_timer(); 192021afaf18SBorislav Petkov } 192121afaf18SBorislav Petkov 192221afaf18SBorislav Petkov /* 192321afaf18SBorislav Petkov * Called for each booted CPU to clear some machine checks opt-ins 192421afaf18SBorislav Petkov */ 192521afaf18SBorislav Petkov void mcheck_cpu_clear(struct cpuinfo_x86 *c) 192621afaf18SBorislav Petkov { 192721afaf18SBorislav Petkov if (mca_cfg.disabled) 192821afaf18SBorislav Petkov return; 192921afaf18SBorislav Petkov 193021afaf18SBorislav Petkov if (!mce_available(c)) 193121afaf18SBorislav Petkov return; 193221afaf18SBorislav Petkov 193321afaf18SBorislav Petkov /* 193421afaf18SBorislav Petkov * Possibly to clear general settings generic to x86 193521afaf18SBorislav Petkov * __mcheck_cpu_clear_generic(c); 193621afaf18SBorislav Petkov */ 193721afaf18SBorislav Petkov __mcheck_cpu_clear_vendor(c); 193821afaf18SBorislav Petkov 193921afaf18SBorislav Petkov } 194021afaf18SBorislav Petkov 194121afaf18SBorislav Petkov static void __mce_disable_bank(void *arg) 194221afaf18SBorislav Petkov { 194321afaf18SBorislav Petkov int bank = *((int *)arg); 194421afaf18SBorislav Petkov __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); 194521afaf18SBorislav Petkov cmci_disable_bank(bank); 194621afaf18SBorislav Petkov } 194721afaf18SBorislav Petkov 194821afaf18SBorislav Petkov void mce_disable_bank(int bank) 194921afaf18SBorislav Petkov { 1950c7d314f3SYazen Ghannam if (bank >= this_cpu_read(mce_num_banks)) { 195121afaf18SBorislav Petkov pr_warn(FW_BUG 195221afaf18SBorislav Petkov "Ignoring request to disable invalid MCA bank %d.\n", 195321afaf18SBorislav Petkov bank); 195421afaf18SBorislav Petkov return; 195521afaf18SBorislav Petkov } 195621afaf18SBorislav Petkov set_bit(bank, mce_banks_ce_disabled); 195721afaf18SBorislav Petkov on_each_cpu(__mce_disable_bank, &bank, 1); 195821afaf18SBorislav Petkov } 195921afaf18SBorislav Petkov 196021afaf18SBorislav Petkov /* 196121afaf18SBorislav Petkov * mce=off Disables machine check 196221afaf18SBorislav Petkov * mce=no_cmci Disables CMCI 196321afaf18SBorislav Petkov * mce=no_lmce Disables LMCE 196421afaf18SBorislav Petkov * mce=dont_log_ce Clears corrected events silently, no log created for CEs. 196521afaf18SBorislav Petkov * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. 196621afaf18SBorislav Petkov * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) 196721afaf18SBorislav Petkov * monarchtimeout is how long to wait for other CPUs on machine 196821afaf18SBorislav Petkov * check, or 0 to not wait 196921afaf18SBorislav Petkov * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h 197021afaf18SBorislav Petkov and older. 197121afaf18SBorislav Petkov * mce=nobootlog Don't log MCEs from before booting. 197221afaf18SBorislav Petkov * mce=bios_cmci_threshold Don't program the CMCI threshold 197321afaf18SBorislav Petkov * mce=recovery force enable memcpy_mcsafe() 197421afaf18SBorislav Petkov */ 197521afaf18SBorislav Petkov static int __init mcheck_enable(char *str) 197621afaf18SBorislav Petkov { 197721afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 197821afaf18SBorislav Petkov 197921afaf18SBorislav Petkov if (*str == 0) { 198021afaf18SBorislav Petkov enable_p5_mce(); 198121afaf18SBorislav Petkov return 1; 198221afaf18SBorislav Petkov } 198321afaf18SBorislav Petkov if (*str == '=') 198421afaf18SBorislav Petkov str++; 198521afaf18SBorislav Petkov if (!strcmp(str, "off")) 198621afaf18SBorislav Petkov cfg->disabled = 1; 198721afaf18SBorislav Petkov else if (!strcmp(str, "no_cmci")) 198821afaf18SBorislav Petkov cfg->cmci_disabled = true; 198921afaf18SBorislav Petkov else if (!strcmp(str, "no_lmce")) 199021afaf18SBorislav Petkov cfg->lmce_disabled = 1; 199121afaf18SBorislav Petkov else if (!strcmp(str, "dont_log_ce")) 199221afaf18SBorislav Petkov cfg->dont_log_ce = true; 199321afaf18SBorislav Petkov else if (!strcmp(str, "ignore_ce")) 199421afaf18SBorislav Petkov cfg->ignore_ce = true; 199521afaf18SBorislav Petkov else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) 199621afaf18SBorislav Petkov cfg->bootlog = (str[0] == 'b'); 199721afaf18SBorislav Petkov else if (!strcmp(str, "bios_cmci_threshold")) 199821afaf18SBorislav Petkov cfg->bios_cmci_threshold = 1; 199921afaf18SBorislav Petkov else if (!strcmp(str, "recovery")) 200021afaf18SBorislav Petkov cfg->recovery = 1; 200121afaf18SBorislav Petkov else if (isdigit(str[0])) { 200221afaf18SBorislav Petkov if (get_option(&str, &cfg->tolerant) == 2) 200321afaf18SBorislav Petkov get_option(&str, &(cfg->monarch_timeout)); 200421afaf18SBorislav Petkov } else { 200521afaf18SBorislav Petkov pr_info("mce argument %s ignored. Please use /sys\n", str); 200621afaf18SBorislav Petkov return 0; 200721afaf18SBorislav Petkov } 200821afaf18SBorislav Petkov return 1; 200921afaf18SBorislav Petkov } 201021afaf18SBorislav Petkov __setup("mce", mcheck_enable); 201121afaf18SBorislav Petkov 201221afaf18SBorislav Petkov int __init mcheck_init(void) 201321afaf18SBorislav Petkov { 201421afaf18SBorislav Petkov mcheck_intel_therm_init(); 2015c9c6d216STony Luck mce_register_decode_chain(&early_nb); 20168438b84aSJan H. Schönherr mce_register_decode_chain(&mce_uc_nb); 201721afaf18SBorislav Petkov mce_register_decode_chain(&mce_default_nb); 201821afaf18SBorislav Petkov mcheck_vendor_init_severity(); 201921afaf18SBorislav Petkov 202021afaf18SBorislav Petkov INIT_WORK(&mce_work, mce_gen_pool_process); 202121afaf18SBorislav Petkov init_irq_work(&mce_irq_work, mce_irq_work_cb); 202221afaf18SBorislav Petkov 202321afaf18SBorislav Petkov return 0; 202421afaf18SBorislav Petkov } 202521afaf18SBorislav Petkov 202621afaf18SBorislav Petkov /* 202721afaf18SBorislav Petkov * mce_syscore: PM support 202821afaf18SBorislav Petkov */ 202921afaf18SBorislav Petkov 203021afaf18SBorislav Petkov /* 203121afaf18SBorislav Petkov * Disable machine checks on suspend and shutdown. We can't really handle 203221afaf18SBorislav Petkov * them later. 203321afaf18SBorislav Petkov */ 203421afaf18SBorislav Petkov static void mce_disable_error_reporting(void) 203521afaf18SBorislav Petkov { 2036b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 203721afaf18SBorislav Petkov int i; 203821afaf18SBorislav Petkov 2039c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 204021afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 204121afaf18SBorislav Petkov 204221afaf18SBorislav Petkov if (b->init) 204321afaf18SBorislav Petkov wrmsrl(msr_ops.ctl(i), 0); 204421afaf18SBorislav Petkov } 204521afaf18SBorislav Petkov return; 204621afaf18SBorislav Petkov } 204721afaf18SBorislav Petkov 204821afaf18SBorislav Petkov static void vendor_disable_error_reporting(void) 204921afaf18SBorislav Petkov { 205021afaf18SBorislav Petkov /* 20516e898d2bSTony W Wang-oc * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these 20526e898d2bSTony W Wang-oc * MSRs are socket-wide. Disabling them for just a single offlined CPU 20536e898d2bSTony W Wang-oc * is bad, since it will inhibit reporting for all shared resources on 20546e898d2bSTony W Wang-oc * the socket like the last level cache (LLC), the integrated memory 20556e898d2bSTony W Wang-oc * controller (iMC), etc. 205621afaf18SBorislav Petkov */ 205721afaf18SBorislav Petkov if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || 205821afaf18SBorislav Petkov boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || 20596e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 20606e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) 206121afaf18SBorislav Petkov return; 206221afaf18SBorislav Petkov 206321afaf18SBorislav Petkov mce_disable_error_reporting(); 206421afaf18SBorislav Petkov } 206521afaf18SBorislav Petkov 206621afaf18SBorislav Petkov static int mce_syscore_suspend(void) 206721afaf18SBorislav Petkov { 206821afaf18SBorislav Petkov vendor_disable_error_reporting(); 206921afaf18SBorislav Petkov return 0; 207021afaf18SBorislav Petkov } 207121afaf18SBorislav Petkov 207221afaf18SBorislav Petkov static void mce_syscore_shutdown(void) 207321afaf18SBorislav Petkov { 207421afaf18SBorislav Petkov vendor_disable_error_reporting(); 207521afaf18SBorislav Petkov } 207621afaf18SBorislav Petkov 207721afaf18SBorislav Petkov /* 207821afaf18SBorislav Petkov * On resume clear all MCE state. Don't want to see leftovers from the BIOS. 207921afaf18SBorislav Petkov * Only one CPU is active at this time, the others get re-added later using 208021afaf18SBorislav Petkov * CPU hotplug: 208121afaf18SBorislav Petkov */ 208221afaf18SBorislav Petkov static void mce_syscore_resume(void) 208321afaf18SBorislav Petkov { 208421afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 208521afaf18SBorislav Petkov __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); 208621afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 208721afaf18SBorislav Petkov } 208821afaf18SBorislav Petkov 208921afaf18SBorislav Petkov static struct syscore_ops mce_syscore_ops = { 209021afaf18SBorislav Petkov .suspend = mce_syscore_suspend, 209121afaf18SBorislav Petkov .shutdown = mce_syscore_shutdown, 209221afaf18SBorislav Petkov .resume = mce_syscore_resume, 209321afaf18SBorislav Petkov }; 209421afaf18SBorislav Petkov 209521afaf18SBorislav Petkov /* 209621afaf18SBorislav Petkov * mce_device: Sysfs support 209721afaf18SBorislav Petkov */ 209821afaf18SBorislav Petkov 209921afaf18SBorislav Petkov static void mce_cpu_restart(void *data) 210021afaf18SBorislav Petkov { 210121afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 210221afaf18SBorislav Petkov return; 210321afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 210421afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 210521afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 210621afaf18SBorislav Petkov } 210721afaf18SBorislav Petkov 210821afaf18SBorislav Petkov /* Reinit MCEs after user configuration changes */ 210921afaf18SBorislav Petkov static void mce_restart(void) 211021afaf18SBorislav Petkov { 211121afaf18SBorislav Petkov mce_timer_delete_all(); 211221afaf18SBorislav Petkov on_each_cpu(mce_cpu_restart, NULL, 1); 211321afaf18SBorislav Petkov } 211421afaf18SBorislav Petkov 211521afaf18SBorislav Petkov /* Toggle features for corrected errors */ 211621afaf18SBorislav Petkov static void mce_disable_cmci(void *data) 211721afaf18SBorislav Petkov { 211821afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 211921afaf18SBorislav Petkov return; 212021afaf18SBorislav Petkov cmci_clear(); 212121afaf18SBorislav Petkov } 212221afaf18SBorislav Petkov 212321afaf18SBorislav Petkov static void mce_enable_ce(void *all) 212421afaf18SBorislav Petkov { 212521afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 212621afaf18SBorislav Petkov return; 212721afaf18SBorislav Petkov cmci_reenable(); 212821afaf18SBorislav Petkov cmci_recheck(); 212921afaf18SBorislav Petkov if (all) 213021afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 213121afaf18SBorislav Petkov } 213221afaf18SBorislav Petkov 213321afaf18SBorislav Petkov static struct bus_type mce_subsys = { 213421afaf18SBorislav Petkov .name = "machinecheck", 213521afaf18SBorislav Petkov .dev_name = "machinecheck", 213621afaf18SBorislav Petkov }; 213721afaf18SBorislav Petkov 213821afaf18SBorislav Petkov DEFINE_PER_CPU(struct device *, mce_device); 213921afaf18SBorislav Petkov 2140b4914508SYazen Ghannam static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr) 214121afaf18SBorislav Petkov { 2142b4914508SYazen Ghannam return container_of(attr, struct mce_bank_dev, attr); 214321afaf18SBorislav Petkov } 214421afaf18SBorislav Petkov 214521afaf18SBorislav Petkov static ssize_t show_bank(struct device *s, struct device_attribute *attr, 214621afaf18SBorislav Petkov char *buf) 214721afaf18SBorislav Petkov { 2148b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2149b4914508SYazen Ghannam struct mce_bank *b; 2150b4914508SYazen Ghannam 2151c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2152b4914508SYazen Ghannam return -EINVAL; 2153b4914508SYazen Ghannam 2154b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2155b4914508SYazen Ghannam 2156068b053dSYazen Ghannam if (!b->init) 2157068b053dSYazen Ghannam return -ENODEV; 2158068b053dSYazen Ghannam 2159b4914508SYazen Ghannam return sprintf(buf, "%llx\n", b->ctl); 216021afaf18SBorislav Petkov } 216121afaf18SBorislav Petkov 216221afaf18SBorislav Petkov static ssize_t set_bank(struct device *s, struct device_attribute *attr, 216321afaf18SBorislav Petkov const char *buf, size_t size) 216421afaf18SBorislav Petkov { 2165b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2166b4914508SYazen Ghannam struct mce_bank *b; 216721afaf18SBorislav Petkov u64 new; 216821afaf18SBorislav Petkov 216921afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 217021afaf18SBorislav Petkov return -EINVAL; 217121afaf18SBorislav Petkov 2172c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2173b4914508SYazen Ghannam return -EINVAL; 2174b4914508SYazen Ghannam 2175b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2176b4914508SYazen Ghannam 2177068b053dSYazen Ghannam if (!b->init) 2178068b053dSYazen Ghannam return -ENODEV; 2179068b053dSYazen Ghannam 2180b4914508SYazen Ghannam b->ctl = new; 218121afaf18SBorislav Petkov mce_restart(); 218221afaf18SBorislav Petkov 218321afaf18SBorislav Petkov return size; 218421afaf18SBorislav Petkov } 218521afaf18SBorislav Petkov 218621afaf18SBorislav Petkov static ssize_t set_ignore_ce(struct device *s, 218721afaf18SBorislav Petkov struct device_attribute *attr, 218821afaf18SBorislav Petkov const char *buf, size_t size) 218921afaf18SBorislav Petkov { 219021afaf18SBorislav Petkov u64 new; 219121afaf18SBorislav Petkov 219221afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 219321afaf18SBorislav Petkov return -EINVAL; 219421afaf18SBorislav Petkov 219521afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 219621afaf18SBorislav Petkov if (mca_cfg.ignore_ce ^ !!new) { 219721afaf18SBorislav Petkov if (new) { 219821afaf18SBorislav Petkov /* disable ce features */ 219921afaf18SBorislav Petkov mce_timer_delete_all(); 220021afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 220121afaf18SBorislav Petkov mca_cfg.ignore_ce = true; 220221afaf18SBorislav Petkov } else { 220321afaf18SBorislav Petkov /* enable ce features */ 220421afaf18SBorislav Petkov mca_cfg.ignore_ce = false; 220521afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, (void *)1, 1); 220621afaf18SBorislav Petkov } 220721afaf18SBorislav Petkov } 220821afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 220921afaf18SBorislav Petkov 221021afaf18SBorislav Petkov return size; 221121afaf18SBorislav Petkov } 221221afaf18SBorislav Petkov 221321afaf18SBorislav Petkov static ssize_t set_cmci_disabled(struct device *s, 221421afaf18SBorislav Petkov struct device_attribute *attr, 221521afaf18SBorislav Petkov const char *buf, size_t size) 221621afaf18SBorislav Petkov { 221721afaf18SBorislav Petkov u64 new; 221821afaf18SBorislav Petkov 221921afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 222021afaf18SBorislav Petkov return -EINVAL; 222121afaf18SBorislav Petkov 222221afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 222321afaf18SBorislav Petkov if (mca_cfg.cmci_disabled ^ !!new) { 222421afaf18SBorislav Petkov if (new) { 222521afaf18SBorislav Petkov /* disable cmci */ 222621afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 222721afaf18SBorislav Petkov mca_cfg.cmci_disabled = true; 222821afaf18SBorislav Petkov } else { 222921afaf18SBorislav Petkov /* enable cmci */ 223021afaf18SBorislav Petkov mca_cfg.cmci_disabled = false; 223121afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, NULL, 1); 223221afaf18SBorislav Petkov } 223321afaf18SBorislav Petkov } 223421afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 223521afaf18SBorislav Petkov 223621afaf18SBorislav Petkov return size; 223721afaf18SBorislav Petkov } 223821afaf18SBorislav Petkov 223921afaf18SBorislav Petkov static ssize_t store_int_with_restart(struct device *s, 224021afaf18SBorislav Petkov struct device_attribute *attr, 224121afaf18SBorislav Petkov const char *buf, size_t size) 224221afaf18SBorislav Petkov { 224321afaf18SBorislav Petkov unsigned long old_check_interval = check_interval; 224421afaf18SBorislav Petkov ssize_t ret = device_store_ulong(s, attr, buf, size); 224521afaf18SBorislav Petkov 224621afaf18SBorislav Petkov if (check_interval == old_check_interval) 224721afaf18SBorislav Petkov return ret; 224821afaf18SBorislav Petkov 224921afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 225021afaf18SBorislav Petkov mce_restart(); 225121afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 225221afaf18SBorislav Petkov 225321afaf18SBorislav Petkov return ret; 225421afaf18SBorislav Petkov } 225521afaf18SBorislav Petkov 225621afaf18SBorislav Petkov static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); 225721afaf18SBorislav Petkov static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); 225821afaf18SBorislav Petkov static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); 225921afaf18SBorislav Petkov 226021afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_check_interval = { 226121afaf18SBorislav Petkov __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), 226221afaf18SBorislav Petkov &check_interval 226321afaf18SBorislav Petkov }; 226421afaf18SBorislav Petkov 226521afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_ignore_ce = { 226621afaf18SBorislav Petkov __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), 226721afaf18SBorislav Petkov &mca_cfg.ignore_ce 226821afaf18SBorislav Petkov }; 226921afaf18SBorislav Petkov 227021afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_cmci_disabled = { 227121afaf18SBorislav Petkov __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), 227221afaf18SBorislav Petkov &mca_cfg.cmci_disabled 227321afaf18SBorislav Petkov }; 227421afaf18SBorislav Petkov 227521afaf18SBorislav Petkov static struct device_attribute *mce_device_attrs[] = { 227621afaf18SBorislav Petkov &dev_attr_tolerant.attr, 227721afaf18SBorislav Petkov &dev_attr_check_interval.attr, 227821afaf18SBorislav Petkov #ifdef CONFIG_X86_MCELOG_LEGACY 227921afaf18SBorislav Petkov &dev_attr_trigger, 228021afaf18SBorislav Petkov #endif 228121afaf18SBorislav Petkov &dev_attr_monarch_timeout.attr, 228221afaf18SBorislav Petkov &dev_attr_dont_log_ce.attr, 228321afaf18SBorislav Petkov &dev_attr_ignore_ce.attr, 228421afaf18SBorislav Petkov &dev_attr_cmci_disabled.attr, 228521afaf18SBorislav Petkov NULL 228621afaf18SBorislav Petkov }; 228721afaf18SBorislav Petkov 228821afaf18SBorislav Petkov static cpumask_var_t mce_device_initialized; 228921afaf18SBorislav Petkov 229021afaf18SBorislav Petkov static void mce_device_release(struct device *dev) 229121afaf18SBorislav Petkov { 229221afaf18SBorislav Petkov kfree(dev); 229321afaf18SBorislav Petkov } 229421afaf18SBorislav Petkov 2295b4914508SYazen Ghannam /* Per CPU device init. All of the CPUs still share the same bank device: */ 229621afaf18SBorislav Petkov static int mce_device_create(unsigned int cpu) 229721afaf18SBorislav Petkov { 229821afaf18SBorislav Petkov struct device *dev; 229921afaf18SBorislav Petkov int err; 230021afaf18SBorislav Petkov int i, j; 230121afaf18SBorislav Petkov 230221afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) 230321afaf18SBorislav Petkov return -EIO; 230421afaf18SBorislav Petkov 230521afaf18SBorislav Petkov dev = per_cpu(mce_device, cpu); 230621afaf18SBorislav Petkov if (dev) 230721afaf18SBorislav Petkov return 0; 230821afaf18SBorislav Petkov 230921afaf18SBorislav Petkov dev = kzalloc(sizeof(*dev), GFP_KERNEL); 231021afaf18SBorislav Petkov if (!dev) 231121afaf18SBorislav Petkov return -ENOMEM; 231221afaf18SBorislav Petkov dev->id = cpu; 231321afaf18SBorislav Petkov dev->bus = &mce_subsys; 231421afaf18SBorislav Petkov dev->release = &mce_device_release; 231521afaf18SBorislav Petkov 231621afaf18SBorislav Petkov err = device_register(dev); 231721afaf18SBorislav Petkov if (err) { 231821afaf18SBorislav Petkov put_device(dev); 231921afaf18SBorislav Petkov return err; 232021afaf18SBorislav Petkov } 232121afaf18SBorislav Petkov 232221afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) { 232321afaf18SBorislav Petkov err = device_create_file(dev, mce_device_attrs[i]); 232421afaf18SBorislav Petkov if (err) 232521afaf18SBorislav Petkov goto error; 232621afaf18SBorislav Petkov } 2327c7d314f3SYazen Ghannam for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) { 2328b4914508SYazen Ghannam err = device_create_file(dev, &mce_bank_devs[j].attr); 232921afaf18SBorislav Petkov if (err) 233021afaf18SBorislav Petkov goto error2; 233121afaf18SBorislav Petkov } 233221afaf18SBorislav Petkov cpumask_set_cpu(cpu, mce_device_initialized); 233321afaf18SBorislav Petkov per_cpu(mce_device, cpu) = dev; 233421afaf18SBorislav Petkov 233521afaf18SBorislav Petkov return 0; 233621afaf18SBorislav Petkov error2: 233721afaf18SBorislav Petkov while (--j >= 0) 2338b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[j].attr); 233921afaf18SBorislav Petkov error: 234021afaf18SBorislav Petkov while (--i >= 0) 234121afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 234221afaf18SBorislav Petkov 234321afaf18SBorislav Petkov device_unregister(dev); 234421afaf18SBorislav Petkov 234521afaf18SBorislav Petkov return err; 234621afaf18SBorislav Petkov } 234721afaf18SBorislav Petkov 234821afaf18SBorislav Petkov static void mce_device_remove(unsigned int cpu) 234921afaf18SBorislav Petkov { 235021afaf18SBorislav Petkov struct device *dev = per_cpu(mce_device, cpu); 235121afaf18SBorislav Petkov int i; 235221afaf18SBorislav Petkov 235321afaf18SBorislav Petkov if (!cpumask_test_cpu(cpu, mce_device_initialized)) 235421afaf18SBorislav Petkov return; 235521afaf18SBorislav Petkov 235621afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) 235721afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 235821afaf18SBorislav Petkov 2359c7d314f3SYazen Ghannam for (i = 0; i < per_cpu(mce_num_banks, cpu); i++) 2360b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[i].attr); 236121afaf18SBorislav Petkov 236221afaf18SBorislav Petkov device_unregister(dev); 236321afaf18SBorislav Petkov cpumask_clear_cpu(cpu, mce_device_initialized); 236421afaf18SBorislav Petkov per_cpu(mce_device, cpu) = NULL; 236521afaf18SBorislav Petkov } 236621afaf18SBorislav Petkov 236721afaf18SBorislav Petkov /* Make sure there are no machine checks on offlined CPUs. */ 236821afaf18SBorislav Petkov static void mce_disable_cpu(void) 236921afaf18SBorislav Petkov { 237021afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 237121afaf18SBorislav Petkov return; 237221afaf18SBorislav Petkov 237321afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 237421afaf18SBorislav Petkov cmci_clear(); 237521afaf18SBorislav Petkov 237621afaf18SBorislav Petkov vendor_disable_error_reporting(); 237721afaf18SBorislav Petkov } 237821afaf18SBorislav Petkov 237921afaf18SBorislav Petkov static void mce_reenable_cpu(void) 238021afaf18SBorislav Petkov { 2381b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 238221afaf18SBorislav Petkov int i; 238321afaf18SBorislav Petkov 238421afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 238521afaf18SBorislav Petkov return; 238621afaf18SBorislav Petkov 238721afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 238821afaf18SBorislav Petkov cmci_reenable(); 2389c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 239021afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 239121afaf18SBorislav Petkov 239221afaf18SBorislav Petkov if (b->init) 239321afaf18SBorislav Petkov wrmsrl(msr_ops.ctl(i), b->ctl); 239421afaf18SBorislav Petkov } 239521afaf18SBorislav Petkov } 239621afaf18SBorislav Petkov 239721afaf18SBorislav Petkov static int mce_cpu_dead(unsigned int cpu) 239821afaf18SBorislav Petkov { 239921afaf18SBorislav Petkov mce_intel_hcpu_update(cpu); 240021afaf18SBorislav Petkov 240121afaf18SBorislav Petkov /* intentionally ignoring frozen here */ 240221afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 240321afaf18SBorislav Petkov cmci_rediscover(); 240421afaf18SBorislav Petkov return 0; 240521afaf18SBorislav Petkov } 240621afaf18SBorislav Petkov 240721afaf18SBorislav Petkov static int mce_cpu_online(unsigned int cpu) 240821afaf18SBorislav Petkov { 240921afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 241021afaf18SBorislav Petkov int ret; 241121afaf18SBorislav Petkov 241221afaf18SBorislav Petkov mce_device_create(cpu); 241321afaf18SBorislav Petkov 241421afaf18SBorislav Petkov ret = mce_threshold_create_device(cpu); 241521afaf18SBorislav Petkov if (ret) { 241621afaf18SBorislav Petkov mce_device_remove(cpu); 241721afaf18SBorislav Petkov return ret; 241821afaf18SBorislav Petkov } 241921afaf18SBorislav Petkov mce_reenable_cpu(); 242021afaf18SBorislav Petkov mce_start_timer(t); 242121afaf18SBorislav Petkov return 0; 242221afaf18SBorislav Petkov } 242321afaf18SBorislav Petkov 242421afaf18SBorislav Petkov static int mce_cpu_pre_down(unsigned int cpu) 242521afaf18SBorislav Petkov { 242621afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 242721afaf18SBorislav Petkov 242821afaf18SBorislav Petkov mce_disable_cpu(); 242921afaf18SBorislav Petkov del_timer_sync(t); 243021afaf18SBorislav Petkov mce_threshold_remove_device(cpu); 243121afaf18SBorislav Petkov mce_device_remove(cpu); 243221afaf18SBorislav Petkov return 0; 243321afaf18SBorislav Petkov } 243421afaf18SBorislav Petkov 243521afaf18SBorislav Petkov static __init void mce_init_banks(void) 243621afaf18SBorislav Petkov { 243721afaf18SBorislav Petkov int i; 243821afaf18SBorislav Petkov 2439b4914508SYazen Ghannam for (i = 0; i < MAX_NR_BANKS; i++) { 2440b4914508SYazen Ghannam struct mce_bank_dev *b = &mce_bank_devs[i]; 244121afaf18SBorislav Petkov struct device_attribute *a = &b->attr; 244221afaf18SBorislav Petkov 2443b4914508SYazen Ghannam b->bank = i; 2444b4914508SYazen Ghannam 244521afaf18SBorislav Petkov sysfs_attr_init(&a->attr); 244621afaf18SBorislav Petkov a->attr.name = b->attrname; 244721afaf18SBorislav Petkov snprintf(b->attrname, ATTR_LEN, "bank%d", i); 244821afaf18SBorislav Petkov 244921afaf18SBorislav Petkov a->attr.mode = 0644; 245021afaf18SBorislav Petkov a->show = show_bank; 245121afaf18SBorislav Petkov a->store = set_bank; 245221afaf18SBorislav Petkov } 245321afaf18SBorislav Petkov } 245421afaf18SBorislav Petkov 24556e7a41c6SThomas Gleixner /* 24566e7a41c6SThomas Gleixner * When running on XEN, this initcall is ordered against the XEN mcelog 24576e7a41c6SThomas Gleixner * initcall: 24586e7a41c6SThomas Gleixner * 24596e7a41c6SThomas Gleixner * device_initcall(xen_late_init_mcelog); 24606e7a41c6SThomas Gleixner * device_initcall_sync(mcheck_init_device); 24616e7a41c6SThomas Gleixner */ 246221afaf18SBorislav Petkov static __init int mcheck_init_device(void) 246321afaf18SBorislav Petkov { 246421afaf18SBorislav Petkov int err; 246521afaf18SBorislav Petkov 246621afaf18SBorislav Petkov /* 246721afaf18SBorislav Petkov * Check if we have a spare virtual bit. This will only become 246821afaf18SBorislav Petkov * a problem if/when we move beyond 5-level page tables. 246921afaf18SBorislav Petkov */ 247021afaf18SBorislav Petkov MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63); 247121afaf18SBorislav Petkov 247221afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) { 247321afaf18SBorislav Petkov err = -EIO; 247421afaf18SBorislav Petkov goto err_out; 247521afaf18SBorislav Petkov } 247621afaf18SBorislav Petkov 247721afaf18SBorislav Petkov if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { 247821afaf18SBorislav Petkov err = -ENOMEM; 247921afaf18SBorislav Petkov goto err_out; 248021afaf18SBorislav Petkov } 248121afaf18SBorislav Petkov 248221afaf18SBorislav Petkov mce_init_banks(); 248321afaf18SBorislav Petkov 248421afaf18SBorislav Petkov err = subsys_system_register(&mce_subsys, NULL); 248521afaf18SBorislav Petkov if (err) 248621afaf18SBorislav Petkov goto err_out_mem; 248721afaf18SBorislav Petkov 248821afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL, 248921afaf18SBorislav Petkov mce_cpu_dead); 249021afaf18SBorislav Petkov if (err) 249121afaf18SBorislav Petkov goto err_out_mem; 249221afaf18SBorislav Petkov 24936e7a41c6SThomas Gleixner /* 24946e7a41c6SThomas Gleixner * Invokes mce_cpu_online() on all CPUs which are online when 24956e7a41c6SThomas Gleixner * the state is installed. 24966e7a41c6SThomas Gleixner */ 249721afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online", 249821afaf18SBorislav Petkov mce_cpu_online, mce_cpu_pre_down); 249921afaf18SBorislav Petkov if (err < 0) 250021afaf18SBorislav Petkov goto err_out_online; 250121afaf18SBorislav Petkov 250221afaf18SBorislav Petkov register_syscore_ops(&mce_syscore_ops); 250321afaf18SBorislav Petkov 250421afaf18SBorislav Petkov return 0; 250521afaf18SBorislav Petkov 250621afaf18SBorislav Petkov err_out_online: 250721afaf18SBorislav Petkov cpuhp_remove_state(CPUHP_X86_MCE_DEAD); 250821afaf18SBorislav Petkov 250921afaf18SBorislav Petkov err_out_mem: 251021afaf18SBorislav Petkov free_cpumask_var(mce_device_initialized); 251121afaf18SBorislav Petkov 251221afaf18SBorislav Petkov err_out: 251321afaf18SBorislav Petkov pr_err("Unable to init MCE device (rc: %d)\n", err); 251421afaf18SBorislav Petkov 251521afaf18SBorislav Petkov return err; 251621afaf18SBorislav Petkov } 251721afaf18SBorislav Petkov device_initcall_sync(mcheck_init_device); 251821afaf18SBorislav Petkov 251921afaf18SBorislav Petkov /* 252021afaf18SBorislav Petkov * Old style boot options parsing. Only for compatibility. 252121afaf18SBorislav Petkov */ 252221afaf18SBorislav Petkov static int __init mcheck_disable(char *str) 252321afaf18SBorislav Petkov { 252421afaf18SBorislav Petkov mca_cfg.disabled = 1; 252521afaf18SBorislav Petkov return 1; 252621afaf18SBorislav Petkov } 252721afaf18SBorislav Petkov __setup("nomce", mcheck_disable); 252821afaf18SBorislav Petkov 252921afaf18SBorislav Petkov #ifdef CONFIG_DEBUG_FS 253021afaf18SBorislav Petkov struct dentry *mce_get_debugfs_dir(void) 253121afaf18SBorislav Petkov { 253221afaf18SBorislav Petkov static struct dentry *dmce; 253321afaf18SBorislav Petkov 253421afaf18SBorislav Petkov if (!dmce) 253521afaf18SBorislav Petkov dmce = debugfs_create_dir("mce", NULL); 253621afaf18SBorislav Petkov 253721afaf18SBorislav Petkov return dmce; 253821afaf18SBorislav Petkov } 253921afaf18SBorislav Petkov 254021afaf18SBorislav Petkov static void mce_reset(void) 254121afaf18SBorislav Petkov { 254221afaf18SBorislav Petkov cpu_missing = 0; 254321afaf18SBorislav Petkov atomic_set(&mce_fake_panicked, 0); 254421afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 254521afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 254621afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 254721afaf18SBorislav Petkov } 254821afaf18SBorislav Petkov 254921afaf18SBorislav Petkov static int fake_panic_get(void *data, u64 *val) 255021afaf18SBorislav Petkov { 255121afaf18SBorislav Petkov *val = fake_panic; 255221afaf18SBorislav Petkov return 0; 255321afaf18SBorislav Petkov } 255421afaf18SBorislav Petkov 255521afaf18SBorislav Petkov static int fake_panic_set(void *data, u64 val) 255621afaf18SBorislav Petkov { 255721afaf18SBorislav Petkov mce_reset(); 255821afaf18SBorislav Petkov fake_panic = val; 255921afaf18SBorislav Petkov return 0; 256021afaf18SBorislav Petkov } 256121afaf18SBorislav Petkov 256228156d76SYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set, 256328156d76SYueHaibing "%llu\n"); 256421afaf18SBorislav Petkov 25656e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) 256621afaf18SBorislav Petkov { 25676e4f929eSGreg Kroah-Hartman struct dentry *dmce; 256821afaf18SBorislav Petkov 256921afaf18SBorislav Petkov dmce = mce_get_debugfs_dir(); 25706e4f929eSGreg Kroah-Hartman debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL, 25716e4f929eSGreg Kroah-Hartman &fake_panic_fops); 257221afaf18SBorislav Petkov } 257321afaf18SBorislav Petkov #else 25746e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) { } 257521afaf18SBorislav Petkov #endif 257621afaf18SBorislav Petkov 257721afaf18SBorislav Petkov DEFINE_STATIC_KEY_FALSE(mcsafe_key); 257821afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mcsafe_key); 257921afaf18SBorislav Petkov 258021afaf18SBorislav Petkov static int __init mcheck_late_init(void) 258121afaf18SBorislav Petkov { 258221afaf18SBorislav Petkov if (mca_cfg.recovery) 258321afaf18SBorislav Petkov static_branch_inc(&mcsafe_key); 258421afaf18SBorislav Petkov 258521afaf18SBorislav Petkov mcheck_debugfs_init(); 258621afaf18SBorislav Petkov 258721afaf18SBorislav Petkov /* 258821afaf18SBorislav Petkov * Flush out everything that has been logged during early boot, now that 258921afaf18SBorislav Petkov * everything has been initialized (workqueues, decoders, ...). 259021afaf18SBorislav Petkov */ 259121afaf18SBorislav Petkov mce_schedule_work(); 259221afaf18SBorislav Petkov 259321afaf18SBorislav Petkov return 0; 259421afaf18SBorislav Petkov } 259521afaf18SBorislav Petkov late_initcall(mcheck_late_init); 2596