1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 221afaf18SBorislav Petkov /* 321afaf18SBorislav Petkov * Machine check handler. 421afaf18SBorislav Petkov * 521afaf18SBorislav Petkov * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. 621afaf18SBorislav Petkov * Rest from unknown author(s). 721afaf18SBorislav Petkov * 2004 Andi Kleen. Rewrote most of it. 821afaf18SBorislav Petkov * Copyright 2008 Intel Corporation 921afaf18SBorislav Petkov * Author: Andi Kleen 1021afaf18SBorislav Petkov */ 1121afaf18SBorislav Petkov 1221afaf18SBorislav Petkov #include <linux/thread_info.h> 1321afaf18SBorislav Petkov #include <linux/capability.h> 1421afaf18SBorislav Petkov #include <linux/miscdevice.h> 1521afaf18SBorislav Petkov #include <linux/ratelimit.h> 1621afaf18SBorislav Petkov #include <linux/rcupdate.h> 1721afaf18SBorislav Petkov #include <linux/kobject.h> 1821afaf18SBorislav Petkov #include <linux/uaccess.h> 1921afaf18SBorislav Petkov #include <linux/kdebug.h> 2021afaf18SBorislav Petkov #include <linux/kernel.h> 2121afaf18SBorislav Petkov #include <linux/percpu.h> 2221afaf18SBorislav Petkov #include <linux/string.h> 2321afaf18SBorislav Petkov #include <linux/device.h> 2421afaf18SBorislav Petkov #include <linux/syscore_ops.h> 2521afaf18SBorislav Petkov #include <linux/delay.h> 2621afaf18SBorislav Petkov #include <linux/ctype.h> 2721afaf18SBorislav Petkov #include <linux/sched.h> 2821afaf18SBorislav Petkov #include <linux/sysfs.h> 2921afaf18SBorislav Petkov #include <linux/types.h> 3021afaf18SBorislav Petkov #include <linux/slab.h> 3121afaf18SBorislav Petkov #include <linux/init.h> 3221afaf18SBorislav Petkov #include <linux/kmod.h> 3321afaf18SBorislav Petkov #include <linux/poll.h> 3421afaf18SBorislav Petkov #include <linux/nmi.h> 3521afaf18SBorislav Petkov #include <linux/cpu.h> 3621afaf18SBorislav Petkov #include <linux/ras.h> 3721afaf18SBorislav Petkov #include <linux/smp.h> 3821afaf18SBorislav Petkov #include <linux/fs.h> 3921afaf18SBorislav Petkov #include <linux/mm.h> 4021afaf18SBorislav Petkov #include <linux/debugfs.h> 4121afaf18SBorislav Petkov #include <linux/irq_work.h> 4221afaf18SBorislav Petkov #include <linux/export.h> 4321afaf18SBorislav Petkov #include <linux/set_memory.h> 449998a983SRicardo Neri #include <linux/sync_core.h> 455567d11cSPeter Zijlstra #include <linux/task_work.h> 460d00449cSPeter Zijlstra #include <linux/hardirq.h> 4721afaf18SBorislav Petkov 4821afaf18SBorislav Petkov #include <asm/intel-family.h> 4921afaf18SBorislav Petkov #include <asm/processor.h> 5021afaf18SBorislav Petkov #include <asm/traps.h> 5121afaf18SBorislav Petkov #include <asm/tlbflush.h> 5221afaf18SBorislav Petkov #include <asm/mce.h> 5321afaf18SBorislav Petkov #include <asm/msr.h> 5421afaf18SBorislav Petkov #include <asm/reboot.h> 5521afaf18SBorislav Petkov 5621afaf18SBorislav Petkov #include "internal.h" 5721afaf18SBorislav Petkov 5821afaf18SBorislav Petkov /* sysfs synchronization */ 5921afaf18SBorislav Petkov static DEFINE_MUTEX(mce_sysfs_mutex); 6021afaf18SBorislav Petkov 6121afaf18SBorislav Petkov #define CREATE_TRACE_POINTS 6221afaf18SBorislav Petkov #include <trace/events/mce.h> 6321afaf18SBorislav Petkov 6421afaf18SBorislav Petkov #define SPINUNIT 100 /* 100ns */ 6521afaf18SBorislav Petkov 6621afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_exception_count); 6721afaf18SBorislav Petkov 68c7d314f3SYazen Ghannam DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks); 69c7d314f3SYazen Ghannam 7095fdce6bSYazen Ghannam struct mce_bank { 7195fdce6bSYazen Ghannam u64 ctl; /* subevents to enable */ 7295fdce6bSYazen Ghannam bool init; /* initialise bank? */ 73b4914508SYazen Ghannam }; 74b4914508SYazen Ghannam static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); 75b4914508SYazen Ghannam 76b4914508SYazen Ghannam #define ATTR_LEN 16 77b4914508SYazen Ghannam /* One object for each MCE bank, shared by all CPUs */ 78b4914508SYazen Ghannam struct mce_bank_dev { 7995fdce6bSYazen Ghannam struct device_attribute attr; /* device attribute */ 8095fdce6bSYazen Ghannam char attrname[ATTR_LEN]; /* attribute name */ 81b4914508SYazen Ghannam u8 bank; /* bank number */ 8295fdce6bSYazen Ghannam }; 83b4914508SYazen Ghannam static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS]; 8495fdce6bSYazen Ghannam 8521afaf18SBorislav Petkov struct mce_vendor_flags mce_flags __read_mostly; 8621afaf18SBorislav Petkov 8721afaf18SBorislav Petkov struct mca_config mca_cfg __read_mostly = { 8821afaf18SBorislav Petkov .bootlog = -1, 8921afaf18SBorislav Petkov /* 9021afaf18SBorislav Petkov * Tolerant levels: 9121afaf18SBorislav Petkov * 0: always panic on uncorrected errors, log corrected errors 9221afaf18SBorislav Petkov * 1: panic or SIGBUS on uncorrected errors, log corrected errors 9321afaf18SBorislav Petkov * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors 9421afaf18SBorislav Petkov * 3: never panic or SIGBUS, log all errors (for testing only) 9521afaf18SBorislav Petkov */ 9621afaf18SBorislav Petkov .tolerant = 1, 9721afaf18SBorislav Petkov .monarch_timeout = -1 9821afaf18SBorislav Petkov }; 9921afaf18SBorislav Petkov 10021afaf18SBorislav Petkov static DEFINE_PER_CPU(struct mce, mces_seen); 10121afaf18SBorislav Petkov static unsigned long mce_need_notify; 10221afaf18SBorislav Petkov 10321afaf18SBorislav Petkov /* 10421afaf18SBorislav Petkov * MCA banks polled by the period polling timer for corrected events. 10521afaf18SBorislav Petkov * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). 10621afaf18SBorislav Petkov */ 10721afaf18SBorislav Petkov DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { 10821afaf18SBorislav Petkov [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL 10921afaf18SBorislav Petkov }; 11021afaf18SBorislav Petkov 11121afaf18SBorislav Petkov /* 11221afaf18SBorislav Petkov * MCA banks controlled through firmware first for corrected errors. 11321afaf18SBorislav Petkov * This is a global list of banks for which we won't enable CMCI and we 11421afaf18SBorislav Petkov * won't poll. Firmware controls these banks and is responsible for 11521afaf18SBorislav Petkov * reporting corrected errors through GHES. Uncorrected/recoverable 11621afaf18SBorislav Petkov * errors are still notified through a machine check. 11721afaf18SBorislav Petkov */ 11821afaf18SBorislav Petkov mce_banks_t mce_banks_ce_disabled; 11921afaf18SBorislav Petkov 12021afaf18SBorislav Petkov static struct work_struct mce_work; 12121afaf18SBorislav Petkov static struct irq_work mce_irq_work; 12221afaf18SBorislav Petkov 12321afaf18SBorislav Petkov /* 12421afaf18SBorislav Petkov * CPU/chipset specific EDAC code can register a notifier call here to print 12521afaf18SBorislav Petkov * MCE errors in a human-readable form. 12621afaf18SBorislav Petkov */ 12721afaf18SBorislav Petkov BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); 12821afaf18SBorislav Petkov 12921afaf18SBorislav Petkov /* Do initial initialization of a struct mce */ 130487d654dSBorislav Petkov void mce_setup(struct mce *m) 13121afaf18SBorislav Petkov { 13221afaf18SBorislav Petkov memset(m, 0, sizeof(struct mce)); 13321afaf18SBorislav Petkov m->cpu = m->extcpu = smp_processor_id(); 13421afaf18SBorislav Petkov /* need the internal __ version to avoid deadlocks */ 13521afaf18SBorislav Petkov m->time = __ktime_get_real_seconds(); 13621afaf18SBorislav Petkov m->cpuvendor = boot_cpu_data.x86_vendor; 13721afaf18SBorislav Petkov m->cpuid = cpuid_eax(1); 13821afaf18SBorislav Petkov m->socketid = cpu_data(m->extcpu).phys_proc_id; 13921afaf18SBorislav Petkov m->apicid = cpu_data(m->extcpu).initial_apicid; 140865d3a9aSThomas Gleixner m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); 14121afaf18SBorislav Petkov 14221afaf18SBorislav Petkov if (this_cpu_has(X86_FEATURE_INTEL_PPIN)) 143865d3a9aSThomas Gleixner m->ppin = __rdmsr(MSR_PPIN); 144077168e2SWei Huang else if (this_cpu_has(X86_FEATURE_AMD_PPIN)) 145865d3a9aSThomas Gleixner m->ppin = __rdmsr(MSR_AMD_PPIN); 14621afaf18SBorislav Petkov 14721afaf18SBorislav Petkov m->microcode = boot_cpu_data.microcode; 14821afaf18SBorislav Petkov } 14921afaf18SBorislav Petkov 15021afaf18SBorislav Petkov DEFINE_PER_CPU(struct mce, injectm); 15121afaf18SBorislav Petkov EXPORT_PER_CPU_SYMBOL_GPL(injectm); 15221afaf18SBorislav Petkov 15321afaf18SBorislav Petkov void mce_log(struct mce *m) 15421afaf18SBorislav Petkov { 15521afaf18SBorislav Petkov if (!mce_gen_pool_add(m)) 15621afaf18SBorislav Petkov irq_work_queue(&mce_irq_work); 15721afaf18SBorislav Petkov } 15881736abdSJan H. Schönherr EXPORT_SYMBOL_GPL(mce_log); 15921afaf18SBorislav Petkov 16021afaf18SBorislav Petkov void mce_register_decode_chain(struct notifier_block *nb) 16121afaf18SBorislav Petkov { 16215af3659SZhen Lei if (WARN_ON(nb->priority < MCE_PRIO_LOWEST || 16315af3659SZhen Lei nb->priority > MCE_PRIO_HIGHEST)) 16421afaf18SBorislav Petkov return; 16521afaf18SBorislav Petkov 16621afaf18SBorislav Petkov blocking_notifier_chain_register(&x86_mce_decoder_chain, nb); 16721afaf18SBorislav Petkov } 16821afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_register_decode_chain); 16921afaf18SBorislav Petkov 17021afaf18SBorislav Petkov void mce_unregister_decode_chain(struct notifier_block *nb) 17121afaf18SBorislav Petkov { 17221afaf18SBorislav Petkov blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb); 17321afaf18SBorislav Petkov } 17421afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); 17521afaf18SBorislav Petkov 17621afaf18SBorislav Petkov static void __print_mce(struct mce *m) 17721afaf18SBorislav Petkov { 17821afaf18SBorislav Petkov pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", 17921afaf18SBorislav Petkov m->extcpu, 18021afaf18SBorislav Petkov (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""), 18121afaf18SBorislav Petkov m->mcgstatus, m->bank, m->status); 18221afaf18SBorislav Petkov 18321afaf18SBorislav Petkov if (m->ip) { 18421afaf18SBorislav Petkov pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", 18521afaf18SBorislav Petkov !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", 18621afaf18SBorislav Petkov m->cs, m->ip); 18721afaf18SBorislav Petkov 18821afaf18SBorislav Petkov if (m->cs == __KERNEL_CS) 18921afaf18SBorislav Petkov pr_cont("{%pS}", (void *)(unsigned long)m->ip); 19021afaf18SBorislav Petkov pr_cont("\n"); 19121afaf18SBorislav Petkov } 19221afaf18SBorislav Petkov 19321afaf18SBorislav Petkov pr_emerg(HW_ERR "TSC %llx ", m->tsc); 19421afaf18SBorislav Petkov if (m->addr) 19521afaf18SBorislav Petkov pr_cont("ADDR %llx ", m->addr); 19621afaf18SBorislav Petkov if (m->misc) 19721afaf18SBorislav Petkov pr_cont("MISC %llx ", m->misc); 198bb2de0adSSmita Koralahalli if (m->ppin) 199bb2de0adSSmita Koralahalli pr_cont("PPIN %llx ", m->ppin); 20021afaf18SBorislav Petkov 20121afaf18SBorislav Petkov if (mce_flags.smca) { 20221afaf18SBorislav Petkov if (m->synd) 20321afaf18SBorislav Petkov pr_cont("SYND %llx ", m->synd); 20421afaf18SBorislav Petkov if (m->ipid) 20521afaf18SBorislav Petkov pr_cont("IPID %llx ", m->ipid); 20621afaf18SBorislav Petkov } 20721afaf18SBorislav Petkov 20821afaf18SBorislav Petkov pr_cont("\n"); 209925946cfSTony Luck 21021afaf18SBorislav Petkov /* 21121afaf18SBorislav Petkov * Note this output is parsed by external tools and old fields 21221afaf18SBorislav Petkov * should not be changed. 21321afaf18SBorislav Petkov */ 21421afaf18SBorislav Petkov pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", 21521afaf18SBorislav Petkov m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, 21621afaf18SBorislav Petkov m->microcode); 21721afaf18SBorislav Petkov } 21821afaf18SBorislav Petkov 21921afaf18SBorislav Petkov static void print_mce(struct mce *m) 22021afaf18SBorislav Petkov { 22121afaf18SBorislav Petkov __print_mce(m); 22221afaf18SBorislav Petkov 22321afaf18SBorislav Petkov if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON) 22421afaf18SBorislav Petkov pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); 22521afaf18SBorislav Petkov } 22621afaf18SBorislav Petkov 22721afaf18SBorislav Petkov #define PANIC_TIMEOUT 5 /* 5 seconds */ 22821afaf18SBorislav Petkov 22921afaf18SBorislav Petkov static atomic_t mce_panicked; 23021afaf18SBorislav Petkov 23121afaf18SBorislav Petkov static int fake_panic; 23221afaf18SBorislav Petkov static atomic_t mce_fake_panicked; 23321afaf18SBorislav Petkov 23421afaf18SBorislav Petkov /* Panic in progress. Enable interrupts and wait for final IPI */ 23521afaf18SBorislav Petkov static void wait_for_panic(void) 23621afaf18SBorislav Petkov { 23721afaf18SBorislav Petkov long timeout = PANIC_TIMEOUT*USEC_PER_SEC; 23821afaf18SBorislav Petkov 23921afaf18SBorislav Petkov preempt_disable(); 24021afaf18SBorislav Petkov local_irq_enable(); 24121afaf18SBorislav Petkov while (timeout-- > 0) 24221afaf18SBorislav Petkov udelay(1); 24321afaf18SBorislav Petkov if (panic_timeout == 0) 24421afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 24521afaf18SBorislav Petkov panic("Panicing machine check CPU died"); 24621afaf18SBorislav Petkov } 24721afaf18SBorislav Petkov 2483c7ce80aSBorislav Petkov static noinstr void mce_panic(const char *msg, struct mce *final, char *exp) 24921afaf18SBorislav Petkov { 25021afaf18SBorislav Petkov struct llist_node *pending; 25121afaf18SBorislav Petkov struct mce_evt_llist *l; 2523c7ce80aSBorislav Petkov int apei_err = 0; 2533c7ce80aSBorislav Petkov 2543c7ce80aSBorislav Petkov /* 2553c7ce80aSBorislav Petkov * Allow instrumentation around external facilities usage. Not that it 2563c7ce80aSBorislav Petkov * matters a whole lot since the machine is going to panic anyway. 2573c7ce80aSBorislav Petkov */ 2583c7ce80aSBorislav Petkov instrumentation_begin(); 25921afaf18SBorislav Petkov 26021afaf18SBorislav Petkov if (!fake_panic) { 26121afaf18SBorislav Petkov /* 26221afaf18SBorislav Petkov * Make sure only one CPU runs in machine check panic 26321afaf18SBorislav Petkov */ 26421afaf18SBorislav Petkov if (atomic_inc_return(&mce_panicked) > 1) 26521afaf18SBorislav Petkov wait_for_panic(); 26621afaf18SBorislav Petkov barrier(); 26721afaf18SBorislav Petkov 26821afaf18SBorislav Petkov bust_spinlocks(1); 26921afaf18SBorislav Petkov console_verbose(); 27021afaf18SBorislav Petkov } else { 27121afaf18SBorislav Petkov /* Don't log too much for fake panic */ 27221afaf18SBorislav Petkov if (atomic_inc_return(&mce_fake_panicked) > 1) 2733c7ce80aSBorislav Petkov goto out; 27421afaf18SBorislav Petkov } 27521afaf18SBorislav Petkov pending = mce_gen_pool_prepare_records(); 27621afaf18SBorislav Petkov /* First print corrected ones that are still unlogged */ 27721afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 27821afaf18SBorislav Petkov struct mce *m = &l->mce; 27921afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) { 28021afaf18SBorislav Petkov print_mce(m); 28121afaf18SBorislav Petkov if (!apei_err) 28221afaf18SBorislav Petkov apei_err = apei_write_mce(m); 28321afaf18SBorislav Petkov } 28421afaf18SBorislav Petkov } 28521afaf18SBorislav Petkov /* Now print uncorrected but with the final one last */ 28621afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 28721afaf18SBorislav Petkov struct mce *m = &l->mce; 28821afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) 28921afaf18SBorislav Petkov continue; 29021afaf18SBorislav Petkov if (!final || mce_cmp(m, final)) { 29121afaf18SBorislav Petkov print_mce(m); 29221afaf18SBorislav Petkov if (!apei_err) 29321afaf18SBorislav Petkov apei_err = apei_write_mce(m); 29421afaf18SBorislav Petkov } 29521afaf18SBorislav Petkov } 29621afaf18SBorislav Petkov if (final) { 29721afaf18SBorislav Petkov print_mce(final); 29821afaf18SBorislav Petkov if (!apei_err) 29921afaf18SBorislav Petkov apei_err = apei_write_mce(final); 30021afaf18SBorislav Petkov } 30121afaf18SBorislav Petkov if (exp) 30221afaf18SBorislav Petkov pr_emerg(HW_ERR "Machine check: %s\n", exp); 30321afaf18SBorislav Petkov if (!fake_panic) { 30421afaf18SBorislav Petkov if (panic_timeout == 0) 30521afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 30621afaf18SBorislav Petkov panic(msg); 30721afaf18SBorislav Petkov } else 30821afaf18SBorislav Petkov pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); 3093c7ce80aSBorislav Petkov 3103c7ce80aSBorislav Petkov out: 3113c7ce80aSBorislav Petkov instrumentation_end(); 31221afaf18SBorislav Petkov } 31321afaf18SBorislav Petkov 31421afaf18SBorislav Petkov /* Support code for software error injection */ 31521afaf18SBorislav Petkov 31621afaf18SBorislav Petkov static int msr_to_offset(u32 msr) 31721afaf18SBorislav Petkov { 31821afaf18SBorislav Petkov unsigned bank = __this_cpu_read(injectm.bank); 31921afaf18SBorislav Petkov 32021afaf18SBorislav Petkov if (msr == mca_cfg.rip_msr) 32121afaf18SBorislav Petkov return offsetof(struct mce, ip); 3228121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_STATUS)) 32321afaf18SBorislav Petkov return offsetof(struct mce, status); 3248121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_ADDR)) 32521afaf18SBorislav Petkov return offsetof(struct mce, addr); 3268121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_MISC)) 32721afaf18SBorislav Petkov return offsetof(struct mce, misc); 32821afaf18SBorislav Petkov if (msr == MSR_IA32_MCG_STATUS) 32921afaf18SBorislav Petkov return offsetof(struct mce, mcgstatus); 33021afaf18SBorislav Petkov return -1; 33121afaf18SBorislav Petkov } 33221afaf18SBorislav Petkov 33346d28947SThomas Gleixner void ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr) 334e2def7d4SBorislav Petkov { 335e42404afSThomas Gleixner if (wrmsr) { 336e42404afSThomas Gleixner pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n", 337e42404afSThomas Gleixner (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax, 338e42404afSThomas Gleixner regs->ip, (void *)regs->ip); 339e42404afSThomas Gleixner } else { 340e2def7d4SBorislav Petkov pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n", 341e2def7d4SBorislav Petkov (unsigned int)regs->cx, regs->ip, (void *)regs->ip); 342e42404afSThomas Gleixner } 343e2def7d4SBorislav Petkov 344e2def7d4SBorislav Petkov show_stack_regs(regs); 345e2def7d4SBorislav Petkov 346e2def7d4SBorislav Petkov panic("MCA architectural violation!\n"); 347e2def7d4SBorislav Petkov 348e2def7d4SBorislav Petkov while (true) 349e2def7d4SBorislav Petkov cpu_relax(); 350e42404afSThomas Gleixner } 351e2def7d4SBorislav Petkov 35221afaf18SBorislav Petkov /* MSR access wrappers used for error injection */ 35388f66a42SBorislav Petkov noinstr u64 mce_rdmsrl(u32 msr) 35421afaf18SBorislav Petkov { 355e2def7d4SBorislav Petkov DECLARE_ARGS(val, low, high); 35621afaf18SBorislav Petkov 35721afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 358e1007770SBorislav Petkov int offset; 359e1007770SBorislav Petkov u64 ret; 36021afaf18SBorislav Petkov 361e1007770SBorislav Petkov instrumentation_begin(); 362e1007770SBorislav Petkov 363e1007770SBorislav Petkov offset = msr_to_offset(msr); 36421afaf18SBorislav Petkov if (offset < 0) 365e1007770SBorislav Petkov ret = 0; 366e1007770SBorislav Petkov else 367e1007770SBorislav Petkov ret = *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); 368e1007770SBorislav Petkov 369e1007770SBorislav Petkov instrumentation_end(); 370e1007770SBorislav Petkov 371e1007770SBorislav Petkov return ret; 37221afaf18SBorislav Petkov } 37321afaf18SBorislav Petkov 37421afaf18SBorislav Petkov /* 375e2def7d4SBorislav Petkov * RDMSR on MCA MSRs should not fault. If they do, this is very much an 376e2def7d4SBorislav Petkov * architectural violation and needs to be reported to hw vendor. Panic 377e2def7d4SBorislav Petkov * the box to not allow any further progress. 37821afaf18SBorislav Petkov */ 379e2def7d4SBorislav Petkov asm volatile("1: rdmsr\n" 380e2def7d4SBorislav Petkov "2:\n" 38146d28947SThomas Gleixner _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR_IN_MCE) 382e2def7d4SBorislav Petkov : EAX_EDX_RET(val, low, high) : "c" (msr)); 383e2def7d4SBorislav Petkov 384e2def7d4SBorislav Petkov 385e2def7d4SBorislav Petkov return EAX_EDX_VAL(val, low, high); 38621afaf18SBorislav Petkov } 38721afaf18SBorislav Petkov 388e1007770SBorislav Petkov static noinstr void mce_wrmsrl(u32 msr, u64 v) 38921afaf18SBorislav Petkov { 390e2def7d4SBorislav Petkov u32 low, high; 391e2def7d4SBorislav Petkov 39221afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 393e1007770SBorislav Petkov int offset; 39421afaf18SBorislav Petkov 395e1007770SBorislav Petkov instrumentation_begin(); 396e1007770SBorislav Petkov 397e1007770SBorislav Petkov offset = msr_to_offset(msr); 39821afaf18SBorislav Petkov if (offset >= 0) 39921afaf18SBorislav Petkov *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; 400e1007770SBorislav Petkov 401e1007770SBorislav Petkov instrumentation_end(); 402e1007770SBorislav Petkov 40321afaf18SBorislav Petkov return; 40421afaf18SBorislav Petkov } 405e2def7d4SBorislav Petkov 406e2def7d4SBorislav Petkov low = (u32)v; 407e2def7d4SBorislav Petkov high = (u32)(v >> 32); 408e2def7d4SBorislav Petkov 409e2def7d4SBorislav Petkov /* See comment in mce_rdmsrl() */ 410e2def7d4SBorislav Petkov asm volatile("1: wrmsr\n" 411e2def7d4SBorislav Petkov "2:\n" 41246d28947SThomas Gleixner _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR_IN_MCE) 413e2def7d4SBorislav Petkov : : "c" (msr), "a"(low), "d" (high) : "memory"); 41421afaf18SBorislav Petkov } 41521afaf18SBorislav Petkov 41621afaf18SBorislav Petkov /* 41721afaf18SBorislav Petkov * Collect all global (w.r.t. this processor) status about this machine 41821afaf18SBorislav Petkov * check into our "mce" struct so that we can use it later to assess 41921afaf18SBorislav Petkov * the severity of the problem as we read per-bank specific details. 42021afaf18SBorislav Petkov */ 421487d654dSBorislav Petkov static noinstr void mce_gather_info(struct mce *m, struct pt_regs *regs) 42221afaf18SBorislav Petkov { 423487d654dSBorislav Petkov /* 424487d654dSBorislav Petkov * Enable instrumentation around mce_setup() which calls external 425487d654dSBorislav Petkov * facilities. 426487d654dSBorislav Petkov */ 427487d654dSBorislav Petkov instrumentation_begin(); 42821afaf18SBorislav Petkov mce_setup(m); 429487d654dSBorislav Petkov instrumentation_end(); 43021afaf18SBorislav Petkov 43121afaf18SBorislav Petkov m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 43221afaf18SBorislav Petkov if (regs) { 43321afaf18SBorislav Petkov /* 43421afaf18SBorislav Petkov * Get the address of the instruction at the time of 43521afaf18SBorislav Petkov * the machine check error. 43621afaf18SBorislav Petkov */ 43721afaf18SBorislav Petkov if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { 43821afaf18SBorislav Petkov m->ip = regs->ip; 43921afaf18SBorislav Petkov m->cs = regs->cs; 44021afaf18SBorislav Petkov 44121afaf18SBorislav Petkov /* 44221afaf18SBorislav Petkov * When in VM86 mode make the cs look like ring 3 44321afaf18SBorislav Petkov * always. This is a lie, but it's better than passing 44421afaf18SBorislav Petkov * the additional vm86 bit around everywhere. 44521afaf18SBorislav Petkov */ 44621afaf18SBorislav Petkov if (v8086_mode(regs)) 44721afaf18SBorislav Petkov m->cs |= 3; 44821afaf18SBorislav Petkov } 44921afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 45021afaf18SBorislav Petkov if (mca_cfg.rip_msr) 45121afaf18SBorislav Petkov m->ip = mce_rdmsrl(mca_cfg.rip_msr); 45221afaf18SBorislav Petkov } 45321afaf18SBorislav Petkov } 45421afaf18SBorislav Petkov 45521afaf18SBorislav Petkov int mce_available(struct cpuinfo_x86 *c) 45621afaf18SBorislav Petkov { 45721afaf18SBorislav Petkov if (mca_cfg.disabled) 45821afaf18SBorislav Petkov return 0; 45921afaf18SBorislav Petkov return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); 46021afaf18SBorislav Petkov } 46121afaf18SBorislav Petkov 46221afaf18SBorislav Petkov static void mce_schedule_work(void) 46321afaf18SBorislav Petkov { 46421afaf18SBorislav Petkov if (!mce_gen_pool_empty()) 46521afaf18SBorislav Petkov schedule_work(&mce_work); 46621afaf18SBorislav Petkov } 46721afaf18SBorislav Petkov 46821afaf18SBorislav Petkov static void mce_irq_work_cb(struct irq_work *entry) 46921afaf18SBorislav Petkov { 47021afaf18SBorislav Petkov mce_schedule_work(); 47121afaf18SBorislav Petkov } 47221afaf18SBorislav Petkov 47321afaf18SBorislav Petkov /* 47421afaf18SBorislav Petkov * Check if the address reported by the CPU is in a format we can parse. 47521afaf18SBorislav Petkov * It would be possible to add code for most other cases, but all would 47621afaf18SBorislav Petkov * be somewhat complicated (e.g. segment offset would require an instruction 477d9f6e12fSIngo Molnar * parser). So only support physical addresses up to page granularity for now. 47821afaf18SBorislav Petkov */ 47921afaf18SBorislav Petkov int mce_usable_address(struct mce *m) 48021afaf18SBorislav Petkov { 48121afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_ADDRV)) 48221afaf18SBorislav Petkov return 0; 48321afaf18SBorislav Petkov 4846e898d2bSTony W Wang-oc /* Checks after this one are Intel/Zhaoxin-specific: */ 4856e898d2bSTony W Wang-oc if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && 4866e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) 48721afaf18SBorislav Petkov return 1; 48821afaf18SBorislav Petkov 48921afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_MISCV)) 49021afaf18SBorislav Petkov return 0; 49121afaf18SBorislav Petkov 49221afaf18SBorislav Petkov if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) 49321afaf18SBorislav Petkov return 0; 49421afaf18SBorislav Petkov 49521afaf18SBorislav Petkov if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) 49621afaf18SBorislav Petkov return 0; 49721afaf18SBorislav Petkov 49821afaf18SBorislav Petkov return 1; 49921afaf18SBorislav Petkov } 50021afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_usable_address); 50121afaf18SBorislav Petkov 50221afaf18SBorislav Petkov bool mce_is_memory_error(struct mce *m) 50321afaf18SBorislav Petkov { 5046e898d2bSTony W Wang-oc switch (m->cpuvendor) { 5056e898d2bSTony W Wang-oc case X86_VENDOR_AMD: 5066e898d2bSTony W Wang-oc case X86_VENDOR_HYGON: 50721afaf18SBorislav Petkov return amd_mce_is_memory_error(m); 5086e898d2bSTony W Wang-oc 5096e898d2bSTony W Wang-oc case X86_VENDOR_INTEL: 5106e898d2bSTony W Wang-oc case X86_VENDOR_ZHAOXIN: 51121afaf18SBorislav Petkov /* 51221afaf18SBorislav Petkov * Intel SDM Volume 3B - 15.9.2 Compound Error Codes 51321afaf18SBorislav Petkov * 51421afaf18SBorislav Petkov * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for 51521afaf18SBorislav Petkov * indicating a memory error. Bit 8 is used for indicating a 51621afaf18SBorislav Petkov * cache hierarchy error. The combination of bit 2 and bit 3 51721afaf18SBorislav Petkov * is used for indicating a `generic' cache hierarchy error 51821afaf18SBorislav Petkov * But we can't just blindly check the above bits, because if 51921afaf18SBorislav Petkov * bit 11 is set, then it is a bus/interconnect error - and 52021afaf18SBorislav Petkov * either way the above bits just gives more detail on what 52121afaf18SBorislav Petkov * bus/interconnect error happened. Note that bit 12 can be 52221afaf18SBorislav Petkov * ignored, as it's the "filter" bit. 52321afaf18SBorislav Petkov */ 52421afaf18SBorislav Petkov return (m->status & 0xef80) == BIT(7) || 52521afaf18SBorislav Petkov (m->status & 0xef00) == BIT(8) || 52621afaf18SBorislav Petkov (m->status & 0xeffc) == 0xc; 52721afaf18SBorislav Petkov 5286e898d2bSTony W Wang-oc default: 52921afaf18SBorislav Petkov return false; 53021afaf18SBorislav Petkov } 5316e898d2bSTony W Wang-oc } 53221afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_memory_error); 53321afaf18SBorislav Petkov 53417fae129STony Luck static bool whole_page(struct mce *m) 53517fae129STony Luck { 53617fae129STony Luck if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV)) 53717fae129STony Luck return true; 53817fae129STony Luck 53917fae129STony Luck return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT; 54017fae129STony Luck } 54117fae129STony Luck 54221afaf18SBorislav Petkov bool mce_is_correctable(struct mce *m) 54321afaf18SBorislav Petkov { 54421afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED) 54521afaf18SBorislav Petkov return false; 54621afaf18SBorislav Petkov 54721afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED) 54821afaf18SBorislav Petkov return false; 54921afaf18SBorislav Petkov 55021afaf18SBorislav Petkov if (m->status & MCI_STATUS_UC) 55121afaf18SBorislav Petkov return false; 55221afaf18SBorislav Petkov 55321afaf18SBorislav Petkov return true; 55421afaf18SBorislav Petkov } 55521afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_correctable); 55621afaf18SBorislav Petkov 557c9c6d216STony Luck static int mce_early_notifier(struct notifier_block *nb, unsigned long val, 55821afaf18SBorislav Petkov void *data) 55921afaf18SBorislav Petkov { 56021afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 56121afaf18SBorislav Petkov 56221afaf18SBorislav Petkov if (!m) 56321afaf18SBorislav Petkov return NOTIFY_DONE; 56421afaf18SBorislav Petkov 56521afaf18SBorislav Petkov /* Emit the trace record: */ 56621afaf18SBorislav Petkov trace_mce_record(m); 56721afaf18SBorislav Petkov 56821afaf18SBorislav Petkov set_bit(0, &mce_need_notify); 56921afaf18SBorislav Petkov 57021afaf18SBorislav Petkov mce_notify_irq(); 57121afaf18SBorislav Petkov 57221afaf18SBorislav Petkov return NOTIFY_DONE; 57321afaf18SBorislav Petkov } 57421afaf18SBorislav Petkov 575c9c6d216STony Luck static struct notifier_block early_nb = { 576c9c6d216STony Luck .notifier_call = mce_early_notifier, 577c9c6d216STony Luck .priority = MCE_PRIO_EARLY, 57821afaf18SBorislav Petkov }; 57921afaf18SBorislav Petkov 5808438b84aSJan H. Schönherr static int uc_decode_notifier(struct notifier_block *nb, unsigned long val, 58121afaf18SBorislav Petkov void *data) 58221afaf18SBorislav Petkov { 58321afaf18SBorislav Petkov struct mce *mce = (struct mce *)data; 58421afaf18SBorislav Petkov unsigned long pfn; 58521afaf18SBorislav Petkov 5868438b84aSJan H. Schönherr if (!mce || !mce_usable_address(mce)) 58721afaf18SBorislav Petkov return NOTIFY_DONE; 58821afaf18SBorislav Petkov 5898438b84aSJan H. Schönherr if (mce->severity != MCE_AO_SEVERITY && 5908438b84aSJan H. Schönherr mce->severity != MCE_DEFERRED_SEVERITY) 5918438b84aSJan H. Schönherr return NOTIFY_DONE; 5928438b84aSJan H. Schönherr 59321afaf18SBorislav Petkov pfn = mce->addr >> PAGE_SHIFT; 59423ba710aSTony Luck if (!memory_failure(pfn, 0)) { 59517fae129STony Luck set_mce_nospec(pfn, whole_page(mce)); 59623ba710aSTony Luck mce->kflags |= MCE_HANDLED_UC; 59723ba710aSTony Luck } 59821afaf18SBorislav Petkov 59921afaf18SBorislav Petkov return NOTIFY_OK; 60021afaf18SBorislav Petkov } 6018438b84aSJan H. Schönherr 6028438b84aSJan H. Schönherr static struct notifier_block mce_uc_nb = { 6038438b84aSJan H. Schönherr .notifier_call = uc_decode_notifier, 6048438b84aSJan H. Schönherr .priority = MCE_PRIO_UC, 60521afaf18SBorislav Petkov }; 60621afaf18SBorislav Petkov 60721afaf18SBorislav Petkov static int mce_default_notifier(struct notifier_block *nb, unsigned long val, 60821afaf18SBorislav Petkov void *data) 60921afaf18SBorislav Petkov { 61021afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 61121afaf18SBorislav Petkov 61221afaf18SBorislav Petkov if (!m) 61321afaf18SBorislav Petkov return NOTIFY_DONE; 61421afaf18SBorislav Petkov 61543505646STony Luck if (mca_cfg.print_all || !m->kflags) 61621afaf18SBorislav Petkov __print_mce(m); 61721afaf18SBorislav Petkov 61821afaf18SBorislav Petkov return NOTIFY_DONE; 61921afaf18SBorislav Petkov } 62021afaf18SBorislav Petkov 62121afaf18SBorislav Petkov static struct notifier_block mce_default_nb = { 62221afaf18SBorislav Petkov .notifier_call = mce_default_notifier, 62321afaf18SBorislav Petkov /* lowest prio, we want it to run last. */ 62421afaf18SBorislav Petkov .priority = MCE_PRIO_LOWEST, 62521afaf18SBorislav Petkov }; 62621afaf18SBorislav Petkov 62721afaf18SBorislav Petkov /* 62821afaf18SBorislav Petkov * Read ADDR and MISC registers. 62921afaf18SBorislav Petkov */ 630db6c996dSBorislav Petkov static noinstr void mce_read_aux(struct mce *m, int i) 63121afaf18SBorislav Petkov { 63221afaf18SBorislav Petkov if (m->status & MCI_STATUS_MISCV) 6338121b8f9SBorislav Petkov m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC)); 63421afaf18SBorislav Petkov 63521afaf18SBorislav Petkov if (m->status & MCI_STATUS_ADDRV) { 6368121b8f9SBorislav Petkov m->addr = mce_rdmsrl(mca_msr_reg(i, MCA_ADDR)); 63721afaf18SBorislav Petkov 63821afaf18SBorislav Petkov /* 63921afaf18SBorislav Petkov * Mask the reported address by the reported granularity. 64021afaf18SBorislav Petkov */ 64121afaf18SBorislav Petkov if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { 64221afaf18SBorislav Petkov u8 shift = MCI_MISC_ADDR_LSB(m->misc); 64321afaf18SBorislav Petkov m->addr >>= shift; 64421afaf18SBorislav Petkov m->addr <<= shift; 64521afaf18SBorislav Petkov } 64621afaf18SBorislav Petkov 64721afaf18SBorislav Petkov /* 64821afaf18SBorislav Petkov * Extract [55:<lsb>] where lsb is the least significant 64921afaf18SBorislav Petkov * *valid* bit of the address bits. 65021afaf18SBorislav Petkov */ 65121afaf18SBorislav Petkov if (mce_flags.smca) { 65221afaf18SBorislav Petkov u8 lsb = (m->addr >> 56) & 0x3f; 65321afaf18SBorislav Petkov 65421afaf18SBorislav Petkov m->addr &= GENMASK_ULL(55, lsb); 65521afaf18SBorislav Petkov } 65621afaf18SBorislav Petkov } 65721afaf18SBorislav Petkov 65821afaf18SBorislav Petkov if (mce_flags.smca) { 65921afaf18SBorislav Petkov m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); 66021afaf18SBorislav Petkov 66121afaf18SBorislav Petkov if (m->status & MCI_STATUS_SYNDV) 66221afaf18SBorislav Petkov m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); 66321afaf18SBorislav Petkov } 66421afaf18SBorislav Petkov } 66521afaf18SBorislav Petkov 66621afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_poll_count); 66721afaf18SBorislav Petkov 66821afaf18SBorislav Petkov /* 66921afaf18SBorislav Petkov * Poll for corrected events or events that happened before reset. 67021afaf18SBorislav Petkov * Those are just logged through /dev/mcelog. 67121afaf18SBorislav Petkov * 67221afaf18SBorislav Petkov * This is executed in standard interrupt context. 67321afaf18SBorislav Petkov * 67421afaf18SBorislav Petkov * Note: spec recommends to panic for fatal unsignalled 67521afaf18SBorislav Petkov * errors here. However this would be quite problematic -- 67621afaf18SBorislav Petkov * we would need to reimplement the Monarch handling and 67721afaf18SBorislav Petkov * it would mess up the exclusion between exception handler 678312a4661SLinus Torvalds * and poll handler -- * so we skip this for now. 67921afaf18SBorislav Petkov * These cases should not happen anyways, or only when the CPU 68021afaf18SBorislav Petkov * is already totally * confused. In this case it's likely it will 68121afaf18SBorislav Petkov * not fully execute the machine check handler either. 68221afaf18SBorislav Petkov */ 68321afaf18SBorislav Petkov bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) 68421afaf18SBorislav Petkov { 685b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 68621afaf18SBorislav Petkov bool error_seen = false; 68721afaf18SBorislav Petkov struct mce m; 68821afaf18SBorislav Petkov int i; 68921afaf18SBorislav Petkov 69021afaf18SBorislav Petkov this_cpu_inc(mce_poll_count); 69121afaf18SBorislav Petkov 69221afaf18SBorislav Petkov mce_gather_info(&m, NULL); 69321afaf18SBorislav Petkov 69421afaf18SBorislav Petkov if (flags & MCP_TIMESTAMP) 69521afaf18SBorislav Petkov m.tsc = rdtsc(); 69621afaf18SBorislav Petkov 697c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 69821afaf18SBorislav Petkov if (!mce_banks[i].ctl || !test_bit(i, *b)) 69921afaf18SBorislav Petkov continue; 70021afaf18SBorislav Petkov 70121afaf18SBorislav Petkov m.misc = 0; 70221afaf18SBorislav Petkov m.addr = 0; 70321afaf18SBorislav Petkov m.bank = i; 70421afaf18SBorislav Petkov 70521afaf18SBorislav Petkov barrier(); 7068121b8f9SBorislav Petkov m.status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 707f19501aaSTony Luck 708f19501aaSTony Luck /* If this entry is not valid, ignore it */ 70921afaf18SBorislav Petkov if (!(m.status & MCI_STATUS_VAL)) 71021afaf18SBorislav Petkov continue; 71121afaf18SBorislav Petkov 71221afaf18SBorislav Petkov /* 713f19501aaSTony Luck * If we are logging everything (at CPU online) or this 714f19501aaSTony Luck * is a corrected error, then we must log it. 71521afaf18SBorislav Petkov */ 716f19501aaSTony Luck if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC)) 717f19501aaSTony Luck goto log_it; 718f19501aaSTony Luck 719f19501aaSTony Luck /* 720f19501aaSTony Luck * Newer Intel systems that support software error 721f19501aaSTony Luck * recovery need to make additional checks. Other 722f19501aaSTony Luck * CPUs should skip over uncorrected errors, but log 723f19501aaSTony Luck * everything else. 724f19501aaSTony Luck */ 725f19501aaSTony Luck if (!mca_cfg.ser) { 726f19501aaSTony Luck if (m.status & MCI_STATUS_UC) 727f19501aaSTony Luck continue; 728f19501aaSTony Luck goto log_it; 729f19501aaSTony Luck } 730f19501aaSTony Luck 731f19501aaSTony Luck /* Log "not enabled" (speculative) errors */ 732f19501aaSTony Luck if (!(m.status & MCI_STATUS_EN)) 733f19501aaSTony Luck goto log_it; 734f19501aaSTony Luck 735f19501aaSTony Luck /* 736f19501aaSTony Luck * Log UCNA (SDM: 15.6.3 "UCR Error Classification") 737f19501aaSTony Luck * UC == 1 && PCC == 0 && S == 0 738f19501aaSTony Luck */ 739f19501aaSTony Luck if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S)) 740f19501aaSTony Luck goto log_it; 741f19501aaSTony Luck 742f19501aaSTony Luck /* 743f19501aaSTony Luck * Skip anything else. Presumption is that our read of this 744f19501aaSTony Luck * bank is racing with a machine check. Leave the log alone 745f19501aaSTony Luck * for do_machine_check() to deal with it. 746f19501aaSTony Luck */ 74721afaf18SBorislav Petkov continue; 74821afaf18SBorislav Petkov 749f19501aaSTony Luck log_it: 75021afaf18SBorislav Petkov error_seen = true; 75121afaf18SBorislav Petkov 75290454e49SJan H. Schönherr if (flags & MCP_DONTLOG) 75390454e49SJan H. Schönherr goto clear_it; 75490454e49SJan H. Schönherr 75521afaf18SBorislav Petkov mce_read_aux(&m, i); 75641ce0564SYouquan Song m.severity = mce_severity(&m, NULL, mca_cfg.tolerant, NULL, false); 75721afaf18SBorislav Petkov /* 75821afaf18SBorislav Petkov * Don't get the IP here because it's unlikely to 75921afaf18SBorislav Petkov * have anything to do with the actual error location. 76021afaf18SBorislav Petkov */ 76121afaf18SBorislav Petkov 76290454e49SJan H. Schönherr if (mca_cfg.dont_log_ce && !mce_usable_address(&m)) 76390454e49SJan H. Schönherr goto clear_it; 76490454e49SJan H. Schönherr 7653bff147bSBorislav Petkov if (flags & MCP_QUEUE_LOG) 7663bff147bSBorislav Petkov mce_gen_pool_add(&m); 7673bff147bSBorislav Petkov else 76890454e49SJan H. Schönherr mce_log(&m); 76990454e49SJan H. Schönherr 77090454e49SJan H. Schönherr clear_it: 77121afaf18SBorislav Petkov /* 77221afaf18SBorislav Petkov * Clear state for this bank. 77321afaf18SBorislav Petkov */ 7748121b8f9SBorislav Petkov mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 77521afaf18SBorislav Petkov } 77621afaf18SBorislav Petkov 77721afaf18SBorislav Petkov /* 77821afaf18SBorislav Petkov * Don't clear MCG_STATUS here because it's only defined for 77921afaf18SBorislav Petkov * exceptions. 78021afaf18SBorislav Petkov */ 78121afaf18SBorislav Petkov 78221afaf18SBorislav Petkov sync_core(); 78321afaf18SBorislav Petkov 78421afaf18SBorislav Petkov return error_seen; 78521afaf18SBorislav Petkov } 78621afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(machine_check_poll); 78721afaf18SBorislav Petkov 78821afaf18SBorislav Petkov /* 789cc466666SBorislav Petkov * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and 790cc466666SBorislav Petkov * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM 791cc466666SBorislav Petkov * Vol 3B Table 15-20). But this confuses both the code that determines 792cc466666SBorislav Petkov * whether the machine check occurred in kernel or user mode, and also 793cc466666SBorislav Petkov * the severity assessment code. Pretend that EIPV was set, and take the 794cc466666SBorislav Petkov * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. 795cc466666SBorislav Petkov */ 796f11445baSBorislav Petkov static __always_inline void 797f11445baSBorislav Petkov quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) 798cc466666SBorislav Petkov { 799cc466666SBorislav Petkov if (bank != 0) 800cc466666SBorislav Petkov return; 801cc466666SBorislav Petkov if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) 802cc466666SBorislav Petkov return; 803cc466666SBorislav Petkov if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| 804cc466666SBorislav Petkov MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| 805cc466666SBorislav Petkov MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| 806cc466666SBorislav Petkov MCACOD)) != 807cc466666SBorislav Petkov (MCI_STATUS_UC|MCI_STATUS_EN| 808cc466666SBorislav Petkov MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| 809cc466666SBorislav Petkov MCI_STATUS_AR|MCACOD_INSTR)) 810cc466666SBorislav Petkov return; 811cc466666SBorislav Petkov 812cc466666SBorislav Petkov m->mcgstatus |= MCG_STATUS_EIPV; 813cc466666SBorislav Petkov m->ip = regs->ip; 814cc466666SBorislav Petkov m->cs = regs->cs; 815cc466666SBorislav Petkov } 816cc466666SBorislav Petkov 817cc466666SBorislav Petkov /* 818*8ca97812SJue Wang * Disable fast string copy and return from the MCE handler upon the first SRAR 819*8ca97812SJue Wang * MCE on bank 1 due to a CPU erratum on Intel Skylake/Cascade Lake/Cooper Lake 820*8ca97812SJue Wang * CPUs. 821*8ca97812SJue Wang * The fast string copy instructions ("REP; MOVS*") could consume an 822*8ca97812SJue Wang * uncorrectable memory error in the cache line _right after_ the desired region 823*8ca97812SJue Wang * to copy and raise an MCE with RIP pointing to the instruction _after_ the 824*8ca97812SJue Wang * "REP; MOVS*". 825*8ca97812SJue Wang * This mitigation addresses the issue completely with the caveat of performance 826*8ca97812SJue Wang * degradation on the CPU affected. This is still better than the OS crashing on 827*8ca97812SJue Wang * MCEs raised on an irrelevant process due to "REP; MOVS*" accesses from a 828*8ca97812SJue Wang * kernel context (e.g., copy_page). 829*8ca97812SJue Wang * 830*8ca97812SJue Wang * Returns true when fast string copy on CPU has been disabled. 831*8ca97812SJue Wang */ 832*8ca97812SJue Wang static noinstr bool quirk_skylake_repmov(void) 833*8ca97812SJue Wang { 834*8ca97812SJue Wang u64 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 835*8ca97812SJue Wang u64 misc_enable = mce_rdmsrl(MSR_IA32_MISC_ENABLE); 836*8ca97812SJue Wang u64 mc1_status; 837*8ca97812SJue Wang 838*8ca97812SJue Wang /* 839*8ca97812SJue Wang * Apply the quirk only to local machine checks, i.e., no broadcast 840*8ca97812SJue Wang * sync is needed. 841*8ca97812SJue Wang */ 842*8ca97812SJue Wang if (!(mcgstatus & MCG_STATUS_LMCES) || 843*8ca97812SJue Wang !(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) 844*8ca97812SJue Wang return false; 845*8ca97812SJue Wang 846*8ca97812SJue Wang mc1_status = mce_rdmsrl(MSR_IA32_MCx_STATUS(1)); 847*8ca97812SJue Wang 848*8ca97812SJue Wang /* Check for a software-recoverable data fetch error. */ 849*8ca97812SJue Wang if ((mc1_status & 850*8ca97812SJue Wang (MCI_STATUS_VAL | MCI_STATUS_OVER | MCI_STATUS_UC | MCI_STATUS_EN | 851*8ca97812SJue Wang MCI_STATUS_ADDRV | MCI_STATUS_MISCV | MCI_STATUS_PCC | 852*8ca97812SJue Wang MCI_STATUS_AR | MCI_STATUS_S)) == 853*8ca97812SJue Wang (MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | 854*8ca97812SJue Wang MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 855*8ca97812SJue Wang MCI_STATUS_AR | MCI_STATUS_S)) { 856*8ca97812SJue Wang misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING; 857*8ca97812SJue Wang mce_wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 858*8ca97812SJue Wang mce_wrmsrl(MSR_IA32_MCx_STATUS(1), 0); 859*8ca97812SJue Wang 860*8ca97812SJue Wang instrumentation_begin(); 861*8ca97812SJue Wang pr_err_once("Erratum detected, disable fast string copy instructions.\n"); 862*8ca97812SJue Wang instrumentation_end(); 863*8ca97812SJue Wang 864*8ca97812SJue Wang return true; 865*8ca97812SJue Wang } 866*8ca97812SJue Wang 867*8ca97812SJue Wang return false; 868*8ca97812SJue Wang } 869*8ca97812SJue Wang 870*8ca97812SJue Wang /* 87121afaf18SBorislav Petkov * Do a quick check if any of the events requires a panic. 87221afaf18SBorislav Petkov * This decides if we keep the events around or clear them. 87321afaf18SBorislav Petkov */ 874f11445baSBorislav Petkov static __always_inline int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, 87521afaf18SBorislav Petkov struct pt_regs *regs) 87621afaf18SBorislav Petkov { 8777a8bc2b0SJan H. Schönherr char *tmp = *msg; 87821afaf18SBorislav Petkov int i; 87921afaf18SBorislav Petkov 880c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 8818121b8f9SBorislav Petkov m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 88221afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 88321afaf18SBorislav Petkov continue; 88421afaf18SBorislav Petkov 885f11445baSBorislav Petkov arch___set_bit(i, validp); 886cc466666SBorislav Petkov if (mce_flags.snb_ifu_quirk) 887cc466666SBorislav Petkov quirk_sandybridge_ifu(i, m, regs); 88821afaf18SBorislav Petkov 889d28af26fSTony Luck m->bank = i; 89041ce0564SYouquan Song if (mce_severity(m, regs, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) { 89121afaf18SBorislav Petkov mce_read_aux(m, i); 89221afaf18SBorislav Petkov *msg = tmp; 89321afaf18SBorislav Petkov return 1; 89421afaf18SBorislav Petkov } 89521afaf18SBorislav Petkov } 89621afaf18SBorislav Petkov return 0; 89721afaf18SBorislav Petkov } 89821afaf18SBorislav Petkov 89921afaf18SBorislav Petkov /* 90021afaf18SBorislav Petkov * Variable to establish order between CPUs while scanning. 90121afaf18SBorislav Petkov * Each CPU spins initially until executing is equal its number. 90221afaf18SBorislav Petkov */ 90321afaf18SBorislav Petkov static atomic_t mce_executing; 90421afaf18SBorislav Petkov 90521afaf18SBorislav Petkov /* 90621afaf18SBorislav Petkov * Defines order of CPUs on entry. First CPU becomes Monarch. 90721afaf18SBorislav Petkov */ 90821afaf18SBorislav Petkov static atomic_t mce_callin; 90921afaf18SBorislav Petkov 91021afaf18SBorislav Petkov /* 9117bb39313SPaul E. McKenney * Track which CPUs entered the MCA broadcast synchronization and which not in 9127bb39313SPaul E. McKenney * order to print holdouts. 9137bb39313SPaul E. McKenney */ 9147bb39313SPaul E. McKenney static cpumask_t mce_missing_cpus = CPU_MASK_ALL; 9157bb39313SPaul E. McKenney 9167bb39313SPaul E. McKenney /* 91721afaf18SBorislav Petkov * Check if a timeout waiting for other CPUs happened. 91821afaf18SBorislav Petkov */ 919edb3d07eSBorislav Petkov static noinstr int mce_timed_out(u64 *t, const char *msg) 92021afaf18SBorislav Petkov { 921edb3d07eSBorislav Petkov int ret = 0; 922edb3d07eSBorislav Petkov 923edb3d07eSBorislav Petkov /* Enable instrumentation around calls to external facilities */ 924edb3d07eSBorislav Petkov instrumentation_begin(); 925edb3d07eSBorislav Petkov 92621afaf18SBorislav Petkov /* 92721afaf18SBorislav Petkov * The others already did panic for some reason. 92821afaf18SBorislav Petkov * Bail out like in a timeout. 92921afaf18SBorislav Petkov * rmb() to tell the compiler that system_state 93021afaf18SBorislav Petkov * might have been modified by someone else. 93121afaf18SBorislav Petkov */ 93221afaf18SBorislav Petkov rmb(); 93321afaf18SBorislav Petkov if (atomic_read(&mce_panicked)) 93421afaf18SBorislav Petkov wait_for_panic(); 93521afaf18SBorislav Petkov if (!mca_cfg.monarch_timeout) 93621afaf18SBorislav Petkov goto out; 93721afaf18SBorislav Petkov if ((s64)*t < SPINUNIT) { 9387bb39313SPaul E. McKenney if (mca_cfg.tolerant <= 1) { 9397bb39313SPaul E. McKenney if (cpumask_and(&mce_missing_cpus, cpu_online_mask, &mce_missing_cpus)) 9407bb39313SPaul E. McKenney pr_emerg("CPUs not responding to MCE broadcast (may include false positives): %*pbl\n", 9417bb39313SPaul E. McKenney cpumask_pr_args(&mce_missing_cpus)); 94221afaf18SBorislav Petkov mce_panic(msg, NULL, NULL); 9437bb39313SPaul E. McKenney } 944edb3d07eSBorislav Petkov ret = 1; 945edb3d07eSBorislav Petkov goto out; 94621afaf18SBorislav Petkov } 94721afaf18SBorislav Petkov *t -= SPINUNIT; 948edb3d07eSBorislav Petkov 94921afaf18SBorislav Petkov out: 95021afaf18SBorislav Petkov touch_nmi_watchdog(); 951edb3d07eSBorislav Petkov 952edb3d07eSBorislav Petkov instrumentation_end(); 953edb3d07eSBorislav Petkov 954edb3d07eSBorislav Petkov return ret; 95521afaf18SBorislav Petkov } 95621afaf18SBorislav Petkov 95721afaf18SBorislav Petkov /* 95821afaf18SBorislav Petkov * The Monarch's reign. The Monarch is the CPU who entered 95921afaf18SBorislav Petkov * the machine check handler first. It waits for the others to 96021afaf18SBorislav Petkov * raise the exception too and then grades them. When any 96121afaf18SBorislav Petkov * error is fatal panic. Only then let the others continue. 96221afaf18SBorislav Petkov * 96321afaf18SBorislav Petkov * The other CPUs entering the MCE handler will be controlled by the 96421afaf18SBorislav Petkov * Monarch. They are called Subjects. 96521afaf18SBorislav Petkov * 96621afaf18SBorislav Petkov * This way we prevent any potential data corruption in a unrecoverable case 96721afaf18SBorislav Petkov * and also makes sure always all CPU's errors are examined. 96821afaf18SBorislav Petkov * 96921afaf18SBorislav Petkov * Also this detects the case of a machine check event coming from outer 97021afaf18SBorislav Petkov * space (not detected by any CPUs) In this case some external agent wants 97121afaf18SBorislav Petkov * us to shut down, so panic too. 97221afaf18SBorislav Petkov * 97321afaf18SBorislav Petkov * The other CPUs might still decide to panic if the handler happens 97421afaf18SBorislav Petkov * in a unrecoverable place, but in this case the system is in a semi-stable 97521afaf18SBorislav Petkov * state and won't corrupt anything by itself. It's ok to let the others 97621afaf18SBorislav Petkov * continue for a bit first. 97721afaf18SBorislav Petkov * 97821afaf18SBorislav Petkov * All the spin loops have timeouts; when a timeout happens a CPU 97921afaf18SBorislav Petkov * typically elects itself to be Monarch. 98021afaf18SBorislav Petkov */ 98121afaf18SBorislav Petkov static void mce_reign(void) 98221afaf18SBorislav Petkov { 98321afaf18SBorislav Petkov int cpu; 98421afaf18SBorislav Petkov struct mce *m = NULL; 98521afaf18SBorislav Petkov int global_worst = 0; 98621afaf18SBorislav Petkov char *msg = NULL; 98721afaf18SBorislav Petkov 98821afaf18SBorislav Petkov /* 98921afaf18SBorislav Petkov * This CPU is the Monarch and the other CPUs have run 99021afaf18SBorislav Petkov * through their handlers. 99121afaf18SBorislav Petkov * Grade the severity of the errors of all the CPUs. 99221afaf18SBorislav Petkov */ 99321afaf18SBorislav Petkov for_each_possible_cpu(cpu) { 99413c877f4STony Luck struct mce *mtmp = &per_cpu(mces_seen, cpu); 99513c877f4STony Luck 99613c877f4STony Luck if (mtmp->severity > global_worst) { 99713c877f4STony Luck global_worst = mtmp->severity; 99821afaf18SBorislav Petkov m = &per_cpu(mces_seen, cpu); 99921afaf18SBorislav Petkov } 100021afaf18SBorislav Petkov } 100121afaf18SBorislav Petkov 100221afaf18SBorislav Petkov /* 100321afaf18SBorislav Petkov * Cannot recover? Panic here then. 100421afaf18SBorislav Petkov * This dumps all the mces in the log buffer and stops the 100521afaf18SBorislav Petkov * other CPUs. 100621afaf18SBorislav Petkov */ 100713c877f4STony Luck if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) { 100813c877f4STony Luck /* call mce_severity() to get "msg" for panic */ 100941ce0564SYouquan Song mce_severity(m, NULL, mca_cfg.tolerant, &msg, true); 101021afaf18SBorislav Petkov mce_panic("Fatal machine check", m, msg); 101113c877f4STony Luck } 101221afaf18SBorislav Petkov 101321afaf18SBorislav Petkov /* 101421afaf18SBorislav Petkov * For UC somewhere we let the CPU who detects it handle it. 101521afaf18SBorislav Petkov * Also must let continue the others, otherwise the handling 101621afaf18SBorislav Petkov * CPU could deadlock on a lock. 101721afaf18SBorislav Petkov */ 101821afaf18SBorislav Petkov 101921afaf18SBorislav Petkov /* 102021afaf18SBorislav Petkov * No machine check event found. Must be some external 102121afaf18SBorislav Petkov * source or one CPU is hung. Panic. 102221afaf18SBorislav Petkov */ 102321afaf18SBorislav Petkov if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) 102421afaf18SBorislav Petkov mce_panic("Fatal machine check from unknown source", NULL, NULL); 102521afaf18SBorislav Petkov 102621afaf18SBorislav Petkov /* 102721afaf18SBorislav Petkov * Now clear all the mces_seen so that they don't reappear on 102821afaf18SBorislav Petkov * the next mce. 102921afaf18SBorislav Petkov */ 103021afaf18SBorislav Petkov for_each_possible_cpu(cpu) 103121afaf18SBorislav Petkov memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); 103221afaf18SBorislav Petkov } 103321afaf18SBorislav Petkov 103421afaf18SBorislav Petkov static atomic_t global_nwo; 103521afaf18SBorislav Petkov 103621afaf18SBorislav Petkov /* 103721afaf18SBorislav Petkov * Start of Monarch synchronization. This waits until all CPUs have 103821afaf18SBorislav Petkov * entered the exception handler and then determines if any of them 103921afaf18SBorislav Petkov * saw a fatal event that requires panic. Then it executes them 104021afaf18SBorislav Petkov * in the entry order. 104121afaf18SBorislav Petkov * TBD double check parallel CPU hotunplug 104221afaf18SBorislav Petkov */ 1043e3d72e8eSBorislav Petkov static noinstr int mce_start(int *no_way_out) 104421afaf18SBorislav Petkov { 104521afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 1046e3d72e8eSBorislav Petkov int order, ret = -1; 104721afaf18SBorislav Petkov 104821afaf18SBorislav Petkov if (!timeout) 1049e3d72e8eSBorislav Petkov return ret; 105021afaf18SBorislav Petkov 1051f11445baSBorislav Petkov arch_atomic_add(*no_way_out, &global_nwo); 105221afaf18SBorislav Petkov /* 105321afaf18SBorislav Petkov * Rely on the implied barrier below, such that global_nwo 105421afaf18SBorislav Petkov * is updated before mce_callin. 105521afaf18SBorislav Petkov */ 1056f11445baSBorislav Petkov order = arch_atomic_inc_return(&mce_callin); 1057f11445baSBorislav Petkov arch_cpumask_clear_cpu(smp_processor_id(), &mce_missing_cpus); 105821afaf18SBorislav Petkov 1059e3d72e8eSBorislav Petkov /* Enable instrumentation around calls to external facilities */ 1060e3d72e8eSBorislav Petkov instrumentation_begin(); 1061e3d72e8eSBorislav Petkov 106221afaf18SBorislav Petkov /* 106321afaf18SBorislav Petkov * Wait for everyone. 106421afaf18SBorislav Petkov */ 1065f11445baSBorislav Petkov while (arch_atomic_read(&mce_callin) != num_online_cpus()) { 106621afaf18SBorislav Petkov if (mce_timed_out(&timeout, 106721afaf18SBorislav Petkov "Timeout: Not all CPUs entered broadcast exception handler")) { 1068f11445baSBorislav Petkov arch_atomic_set(&global_nwo, 0); 1069e3d72e8eSBorislav Petkov goto out; 107021afaf18SBorislav Petkov } 107121afaf18SBorislav Petkov ndelay(SPINUNIT); 107221afaf18SBorislav Petkov } 107321afaf18SBorislav Petkov 107421afaf18SBorislav Petkov /* 107521afaf18SBorislav Petkov * mce_callin should be read before global_nwo 107621afaf18SBorislav Petkov */ 107721afaf18SBorislav Petkov smp_rmb(); 107821afaf18SBorislav Petkov 107921afaf18SBorislav Petkov if (order == 1) { 108021afaf18SBorislav Petkov /* 108121afaf18SBorislav Petkov * Monarch: Starts executing now, the others wait. 108221afaf18SBorislav Petkov */ 1083f11445baSBorislav Petkov arch_atomic_set(&mce_executing, 1); 108421afaf18SBorislav Petkov } else { 108521afaf18SBorislav Petkov /* 108621afaf18SBorislav Petkov * Subject: Now start the scanning loop one by one in 108721afaf18SBorislav Petkov * the original callin order. 108821afaf18SBorislav Petkov * This way when there are any shared banks it will be 108921afaf18SBorislav Petkov * only seen by one CPU before cleared, avoiding duplicates. 109021afaf18SBorislav Petkov */ 1091f11445baSBorislav Petkov while (arch_atomic_read(&mce_executing) < order) { 109221afaf18SBorislav Petkov if (mce_timed_out(&timeout, 109321afaf18SBorislav Petkov "Timeout: Subject CPUs unable to finish machine check processing")) { 1094f11445baSBorislav Petkov arch_atomic_set(&global_nwo, 0); 1095e3d72e8eSBorislav Petkov goto out; 109621afaf18SBorislav Petkov } 109721afaf18SBorislav Petkov ndelay(SPINUNIT); 109821afaf18SBorislav Petkov } 109921afaf18SBorislav Petkov } 110021afaf18SBorislav Petkov 110121afaf18SBorislav Petkov /* 110221afaf18SBorislav Petkov * Cache the global no_way_out state. 110321afaf18SBorislav Petkov */ 1104f11445baSBorislav Petkov *no_way_out = arch_atomic_read(&global_nwo); 110521afaf18SBorislav Petkov 1106e3d72e8eSBorislav Petkov ret = order; 1107e3d72e8eSBorislav Petkov 1108e3d72e8eSBorislav Petkov out: 1109e3d72e8eSBorislav Petkov instrumentation_end(); 1110e3d72e8eSBorislav Petkov 1111e3d72e8eSBorislav Petkov return ret; 111221afaf18SBorislav Petkov } 111321afaf18SBorislav Petkov 111421afaf18SBorislav Petkov /* 111521afaf18SBorislav Petkov * Synchronize between CPUs after main scanning loop. 111621afaf18SBorislav Petkov * This invokes the bulk of the Monarch processing. 111721afaf18SBorislav Petkov */ 1118b4813539SBorislav Petkov static noinstr int mce_end(int order) 111921afaf18SBorislav Petkov { 112021afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 1121b4813539SBorislav Petkov int ret = -1; 1122b4813539SBorislav Petkov 1123b4813539SBorislav Petkov /* Allow instrumentation around external facilities. */ 1124b4813539SBorislav Petkov instrumentation_begin(); 112521afaf18SBorislav Petkov 112621afaf18SBorislav Petkov if (!timeout) 112721afaf18SBorislav Petkov goto reset; 112821afaf18SBorislav Petkov if (order < 0) 112921afaf18SBorislav Petkov goto reset; 113021afaf18SBorislav Petkov 113121afaf18SBorislav Petkov /* 113221afaf18SBorislav Petkov * Allow others to run. 113321afaf18SBorislav Petkov */ 113421afaf18SBorislav Petkov atomic_inc(&mce_executing); 113521afaf18SBorislav Petkov 113621afaf18SBorislav Petkov if (order == 1) { 113721afaf18SBorislav Petkov /* 113821afaf18SBorislav Petkov * Monarch: Wait for everyone to go through their scanning 113921afaf18SBorislav Petkov * loops. 114021afaf18SBorislav Petkov */ 1141ad669ec1SBorislav Petkov while (atomic_read(&mce_executing) <= num_online_cpus()) { 114221afaf18SBorislav Petkov if (mce_timed_out(&timeout, 114321afaf18SBorislav Petkov "Timeout: Monarch CPU unable to finish machine check processing")) 114421afaf18SBorislav Petkov goto reset; 114521afaf18SBorislav Petkov ndelay(SPINUNIT); 114621afaf18SBorislav Petkov } 114721afaf18SBorislav Petkov 114821afaf18SBorislav Petkov mce_reign(); 114921afaf18SBorislav Petkov barrier(); 115021afaf18SBorislav Petkov ret = 0; 115121afaf18SBorislav Petkov } else { 115221afaf18SBorislav Petkov /* 115321afaf18SBorislav Petkov * Subject: Wait for Monarch to finish. 115421afaf18SBorislav Petkov */ 115521afaf18SBorislav Petkov while (atomic_read(&mce_executing) != 0) { 115621afaf18SBorislav Petkov if (mce_timed_out(&timeout, 115721afaf18SBorislav Petkov "Timeout: Monarch CPU did not finish machine check processing")) 115821afaf18SBorislav Petkov goto reset; 115921afaf18SBorislav Petkov ndelay(SPINUNIT); 116021afaf18SBorislav Petkov } 116121afaf18SBorislav Petkov 116221afaf18SBorislav Petkov /* 116321afaf18SBorislav Petkov * Don't reset anything. That's done by the Monarch. 116421afaf18SBorislav Petkov */ 1165b4813539SBorislav Petkov ret = 0; 1166b4813539SBorislav Petkov goto out; 116721afaf18SBorislav Petkov } 116821afaf18SBorislav Petkov 116921afaf18SBorislav Petkov /* 117021afaf18SBorislav Petkov * Reset all global state. 117121afaf18SBorislav Petkov */ 117221afaf18SBorislav Petkov reset: 117321afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 117421afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 11757bb39313SPaul E. McKenney cpumask_setall(&mce_missing_cpus); 117621afaf18SBorislav Petkov barrier(); 117721afaf18SBorislav Petkov 117821afaf18SBorislav Petkov /* 117921afaf18SBorislav Petkov * Let others run again. 118021afaf18SBorislav Petkov */ 118121afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 1182b4813539SBorislav Petkov 1183b4813539SBorislav Petkov out: 1184b4813539SBorislav Petkov instrumentation_end(); 1185b4813539SBorislav Petkov 118621afaf18SBorislav Petkov return ret; 118721afaf18SBorislav Petkov } 118821afaf18SBorislav Petkov 1189f11445baSBorislav Petkov static __always_inline void mce_clear_state(unsigned long *toclear) 119021afaf18SBorislav Petkov { 119121afaf18SBorislav Petkov int i; 119221afaf18SBorislav Petkov 1193c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1194f11445baSBorislav Petkov if (arch_test_bit(i, toclear)) 11958121b8f9SBorislav Petkov mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 119621afaf18SBorislav Petkov } 119721afaf18SBorislav Petkov } 119821afaf18SBorislav Petkov 119921afaf18SBorislav Petkov /* 120021afaf18SBorislav Petkov * Cases where we avoid rendezvous handler timeout: 120121afaf18SBorislav Petkov * 1) If this CPU is offline. 120221afaf18SBorislav Petkov * 120321afaf18SBorislav Petkov * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to 120421afaf18SBorislav Petkov * skip those CPUs which remain looping in the 1st kernel - see 120521afaf18SBorislav Petkov * crash_nmi_callback(). 120621afaf18SBorislav Petkov * 120721afaf18SBorislav Petkov * Note: there still is a small window between kexec-ing and the new, 120821afaf18SBorislav Petkov * kdump kernel establishing a new #MC handler where a broadcasted MCE 120921afaf18SBorislav Petkov * might not get handled properly. 121021afaf18SBorislav Petkov */ 121194a46d31SThomas Gleixner static noinstr bool mce_check_crashing_cpu(void) 121221afaf18SBorislav Petkov { 121394a46d31SThomas Gleixner unsigned int cpu = smp_processor_id(); 121494a46d31SThomas Gleixner 121514d3b376SPeter Zijlstra if (arch_cpu_is_offline(cpu) || 121621afaf18SBorislav Petkov (crashing_cpu != -1 && crashing_cpu != cpu)) { 121721afaf18SBorislav Petkov u64 mcgstatus; 121821afaf18SBorislav Petkov 1219aedbdeabSThomas Gleixner mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS); 122070f0c230STony W Wang-oc 122170f0c230STony W Wang-oc if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { 122270f0c230STony W Wang-oc if (mcgstatus & MCG_STATUS_LMCES) 122370f0c230STony W Wang-oc return false; 122470f0c230STony W Wang-oc } 122570f0c230STony W Wang-oc 122621afaf18SBorislav Petkov if (mcgstatus & MCG_STATUS_RIPV) { 1227aedbdeabSThomas Gleixner __wrmsr(MSR_IA32_MCG_STATUS, 0, 0); 122821afaf18SBorislav Petkov return true; 122921afaf18SBorislav Petkov } 123021afaf18SBorislav Petkov } 123121afaf18SBorislav Petkov return false; 123221afaf18SBorislav Petkov } 123321afaf18SBorislav Petkov 123475581a20SBorislav Petkov static __always_inline int 123575581a20SBorislav Petkov __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final, 123675581a20SBorislav Petkov unsigned long *toclear, unsigned long *valid_banks, int no_way_out, 123775581a20SBorislav Petkov int *worst) 123821afaf18SBorislav Petkov { 1239b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 124021afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 124175581a20SBorislav Petkov int severity, i, taint = 0; 124221afaf18SBorislav Petkov 1243c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1244f11445baSBorislav Petkov arch___clear_bit(i, toclear); 1245f11445baSBorislav Petkov if (!arch_test_bit(i, valid_banks)) 124621afaf18SBorislav Petkov continue; 124721afaf18SBorislav Petkov 124821afaf18SBorislav Petkov if (!mce_banks[i].ctl) 124921afaf18SBorislav Petkov continue; 125021afaf18SBorislav Petkov 125121afaf18SBorislav Petkov m->misc = 0; 125221afaf18SBorislav Petkov m->addr = 0; 125321afaf18SBorislav Petkov m->bank = i; 125421afaf18SBorislav Petkov 12558121b8f9SBorislav Petkov m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 125621afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 125721afaf18SBorislav Petkov continue; 125821afaf18SBorislav Petkov 125921afaf18SBorislav Petkov /* 126021afaf18SBorislav Petkov * Corrected or non-signaled errors are handled by 126121afaf18SBorislav Petkov * machine_check_poll(). Leave them alone, unless this panics. 126221afaf18SBorislav Petkov */ 126321afaf18SBorislav Petkov if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && 126421afaf18SBorislav Petkov !no_way_out) 126521afaf18SBorislav Petkov continue; 126621afaf18SBorislav Petkov 126721afaf18SBorislav Petkov /* Set taint even when machine check was not enabled. */ 126875581a20SBorislav Petkov taint++; 126921afaf18SBorislav Petkov 127041ce0564SYouquan Song severity = mce_severity(m, regs, cfg->tolerant, NULL, true); 127121afaf18SBorislav Petkov 127221afaf18SBorislav Petkov /* 127321afaf18SBorislav Petkov * When machine check was for corrected/deferred handler don't 127421afaf18SBorislav Petkov * touch, unless we're panicking. 127521afaf18SBorislav Petkov */ 127621afaf18SBorislav Petkov if ((severity == MCE_KEEP_SEVERITY || 127721afaf18SBorislav Petkov severity == MCE_UCNA_SEVERITY) && !no_way_out) 127821afaf18SBorislav Petkov continue; 127921afaf18SBorislav Petkov 1280f11445baSBorislav Petkov arch___set_bit(i, toclear); 128121afaf18SBorislav Petkov 128221afaf18SBorislav Petkov /* Machine check event was not enabled. Clear, but ignore. */ 128321afaf18SBorislav Petkov if (severity == MCE_NO_SEVERITY) 128421afaf18SBorislav Petkov continue; 128521afaf18SBorislav Petkov 128621afaf18SBorislav Petkov mce_read_aux(m, i); 128721afaf18SBorislav Petkov 128821afaf18SBorislav Petkov /* assuming valid severity level != 0 */ 128921afaf18SBorislav Petkov m->severity = severity; 129021afaf18SBorislav Petkov 129175581a20SBorislav Petkov /* 129275581a20SBorislav Petkov * Enable instrumentation around the mce_log() call which is 129375581a20SBorislav Petkov * done in #MC context, where instrumentation is disabled. 129475581a20SBorislav Petkov */ 129575581a20SBorislav Petkov instrumentation_begin(); 129621afaf18SBorislav Petkov mce_log(m); 129775581a20SBorislav Petkov instrumentation_end(); 129821afaf18SBorislav Petkov 129921afaf18SBorislav Petkov if (severity > *worst) { 130021afaf18SBorislav Petkov *final = *m; 130121afaf18SBorislav Petkov *worst = severity; 130221afaf18SBorislav Petkov } 130321afaf18SBorislav Petkov } 130421afaf18SBorislav Petkov 130521afaf18SBorislav Petkov /* mce_clear_state will clear *final, save locally for use later */ 130621afaf18SBorislav Petkov *m = *final; 130775581a20SBorislav Petkov 130875581a20SBorislav Petkov return taint; 130921afaf18SBorislav Petkov } 131021afaf18SBorislav Petkov 13115567d11cSPeter Zijlstra static void kill_me_now(struct callback_head *ch) 13125567d11cSPeter Zijlstra { 131381065b35STony Luck struct task_struct *p = container_of(ch, struct task_struct, mce_kill_me); 131481065b35STony Luck 131581065b35STony Luck p->mce_count = 0; 13165567d11cSPeter Zijlstra force_sig(SIGBUS); 13175567d11cSPeter Zijlstra } 13185567d11cSPeter Zijlstra 13195567d11cSPeter Zijlstra static void kill_me_maybe(struct callback_head *cb) 13205567d11cSPeter Zijlstra { 13215567d11cSPeter Zijlstra struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me); 13225567d11cSPeter Zijlstra int flags = MF_ACTION_REQUIRED; 1323a3f5d80eSNaoya Horiguchi int ret; 13245567d11cSPeter Zijlstra 132581065b35STony Luck p->mce_count = 0; 13265567d11cSPeter Zijlstra pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr); 132717fae129STony Luck 132817fae129STony Luck if (!p->mce_ripv) 13295567d11cSPeter Zijlstra flags |= MF_MUST_KILL; 13305567d11cSPeter Zijlstra 1331a3f5d80eSNaoya Horiguchi ret = memory_failure(p->mce_addr >> PAGE_SHIFT, flags); 1332a6e3cf70STony Luck if (!ret) { 133317fae129STony Luck set_mce_nospec(p->mce_addr >> PAGE_SHIFT, p->mce_whole_page); 13341e36d9c6STony Luck sync_core(); 13355567d11cSPeter Zijlstra return; 13365567d11cSPeter Zijlstra } 13375567d11cSPeter Zijlstra 1338a3f5d80eSNaoya Horiguchi /* 1339a3f5d80eSNaoya Horiguchi * -EHWPOISON from memory_failure() means that it already sent SIGBUS 1340a3f5d80eSNaoya Horiguchi * to the current process with the proper error info, so no need to 1341a3f5d80eSNaoya Horiguchi * send SIGBUS here again. 1342a3f5d80eSNaoya Horiguchi */ 1343a3f5d80eSNaoya Horiguchi if (ret == -EHWPOISON) 1344a3f5d80eSNaoya Horiguchi return; 1345a3f5d80eSNaoya Horiguchi 13465567d11cSPeter Zijlstra pr_err("Memory error not recovered"); 13475567d11cSPeter Zijlstra kill_me_now(cb); 13485567d11cSPeter Zijlstra } 1349a6e3cf70STony Luck 1350a6e3cf70STony Luck static void kill_me_never(struct callback_head *cb) 1351a6e3cf70STony Luck { 1352a6e3cf70STony Luck struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me); 1353a6e3cf70STony Luck 1354a6e3cf70STony Luck p->mce_count = 0; 1355a6e3cf70STony Luck pr_err("Kernel accessed poison in user space at %llx\n", p->mce_addr); 1356a6e3cf70STony Luck if (!memory_failure(p->mce_addr >> PAGE_SHIFT, 0)) 1357a6e3cf70STony Luck set_mce_nospec(p->mce_addr >> PAGE_SHIFT, p->mce_whole_page); 135830063810STony Luck } 13595567d11cSPeter Zijlstra 1360a6e3cf70STony Luck static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callback_head *)) 1361c0ab7ffcSTony Luck { 136281065b35STony Luck int count = ++current->mce_count; 136381065b35STony Luck 136481065b35STony Luck /* First call, save all the details */ 136581065b35STony Luck if (count == 1) { 1366c0ab7ffcSTony Luck current->mce_addr = m->addr; 1367c0ab7ffcSTony Luck current->mce_kflags = m->kflags; 1368c0ab7ffcSTony Luck current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV); 1369c0ab7ffcSTony Luck current->mce_whole_page = whole_page(m); 1370a6e3cf70STony Luck current->mce_kill_me.func = func; 137181065b35STony Luck } 137281065b35STony Luck 137381065b35STony Luck /* Ten is likely overkill. Don't expect more than two faults before task_work() */ 137481065b35STony Luck if (count > 10) 137581065b35STony Luck mce_panic("Too many consecutive machine checks while accessing user data", m, msg); 137681065b35STony Luck 137781065b35STony Luck /* Second or later call, make sure page address matches the one from first call */ 137881065b35STony Luck if (count > 1 && (current->mce_addr >> PAGE_SHIFT) != (m->addr >> PAGE_SHIFT)) 137981065b35STony Luck mce_panic("Consecutive machine checks to different user pages", m, msg); 138081065b35STony Luck 138181065b35STony Luck /* Do not call task_work_add() more than once */ 138281065b35STony Luck if (count > 1) 138381065b35STony Luck return; 1384c0ab7ffcSTony Luck 138591989c70SJens Axboe task_work_add(current, ¤t->mce_kill_me, TWA_RESUME); 1386c0ab7ffcSTony Luck } 138721afaf18SBorislav Petkov 1388cbe1de16SBorislav Petkov /* Handle unconfigured int18 (should never happen) */ 1389cbe1de16SBorislav Petkov static noinstr void unexpected_machine_check(struct pt_regs *regs) 1390cbe1de16SBorislav Petkov { 1391cbe1de16SBorislav Petkov instrumentation_begin(); 1392cbe1de16SBorislav Petkov pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", 1393cbe1de16SBorislav Petkov smp_processor_id()); 1394cbe1de16SBorislav Petkov instrumentation_end(); 1395cbe1de16SBorislav Petkov } 1396cbe1de16SBorislav Petkov 139721afaf18SBorislav Petkov /* 1398487d654dSBorislav Petkov * The actual machine check handler. This only handles real exceptions when 1399487d654dSBorislav Petkov * something got corrupted coming in through int 18. 140021afaf18SBorislav Petkov * 1401487d654dSBorislav Petkov * This is executed in #MC context not subject to normal locking rules. 1402487d654dSBorislav Petkov * This implies that most kernel services cannot be safely used. Don't even 140321afaf18SBorislav Petkov * think about putting a printk in there! 140421afaf18SBorislav Petkov * 140521afaf18SBorislav Petkov * On Intel systems this is entered on all CPUs in parallel through 140621afaf18SBorislav Petkov * MCE broadcast. However some CPUs might be broken beyond repair, 140721afaf18SBorislav Petkov * so be always careful when synchronizing with others. 140855ba18d6SAndy Lutomirski * 140955ba18d6SAndy Lutomirski * Tracing and kprobes are disabled: if we interrupted a kernel context 141055ba18d6SAndy Lutomirski * with IF=1, we need to minimize stack usage. There are also recursion 141155ba18d6SAndy Lutomirski * issues: if the machine check was due to a failure of the memory 141255ba18d6SAndy Lutomirski * backing the user stack, tracing that reads the user stack will cause 141355ba18d6SAndy Lutomirski * potentially infinite recursion. 1414487d654dSBorislav Petkov * 1415487d654dSBorislav Petkov * Currently, the #MC handler calls out to a number of external facilities 1416487d654dSBorislav Petkov * and, therefore, allows instrumentation around them. The optimal thing to 1417487d654dSBorislav Petkov * have would be to do the absolutely minimal work required in #MC context 1418487d654dSBorislav Petkov * and have instrumentation disabled only around that. Further processing can 1419487d654dSBorislav Petkov * then happen in process context where instrumentation is allowed. Achieving 1420487d654dSBorislav Petkov * that requires careful auditing and modifications. Until then, the code 1421487d654dSBorislav Petkov * allows instrumentation temporarily, where required. * 142221afaf18SBorislav Petkov */ 14237f6fa101SIra Weiny noinstr void do_machine_check(struct pt_regs *regs) 142421afaf18SBorislav Petkov { 142575581a20SBorislav Petkov int worst = 0, order, no_way_out, kill_current_task, lmce, taint = 0; 1426cd5e0d1fSBorislav Petkov DECLARE_BITMAP(valid_banks, MAX_NR_BANKS) = { 0 }; 1427cd5e0d1fSBorislav Petkov DECLARE_BITMAP(toclear, MAX_NR_BANKS) = { 0 }; 142821afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 142921afaf18SBorislav Petkov struct mce m, *final; 14307a8bc2b0SJan H. Schönherr char *msg = NULL; 1431cbe1de16SBorislav Petkov 1432cbe1de16SBorislav Petkov if (unlikely(mce_flags.p5)) 1433cbe1de16SBorislav Petkov return pentium_machine_check(regs); 1434cbe1de16SBorislav Petkov else if (unlikely(mce_flags.winchip)) 1435cbe1de16SBorislav Petkov return winchip_machine_check(regs); 1436cbe1de16SBorislav Petkov else if (unlikely(!mca_cfg.initialized)) 1437cbe1de16SBorislav Petkov return unexpected_machine_check(regs); 143821afaf18SBorislav Petkov 1439*8ca97812SJue Wang if (mce_flags.skx_repmov_quirk && quirk_skylake_repmov()) 1440*8ca97812SJue Wang goto clear; 1441*8ca97812SJue Wang 144221afaf18SBorislav Petkov /* 144321afaf18SBorislav Petkov * Establish sequential order between the CPUs entering the machine 144421afaf18SBorislav Petkov * check handler. 144521afaf18SBorislav Petkov */ 1446cbe1de16SBorislav Petkov order = -1; 144721afaf18SBorislav Petkov 144821afaf18SBorislav Petkov /* 144921afaf18SBorislav Petkov * If no_way_out gets set, there is no safe way to recover from this 145021afaf18SBorislav Petkov * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. 145121afaf18SBorislav Petkov */ 1452cbe1de16SBorislav Petkov no_way_out = 0; 145321afaf18SBorislav Petkov 145421afaf18SBorislav Petkov /* 1455e1c06d23SGabriele Paoloni * If kill_current_task is not set, there might be a way to recover from this 145621afaf18SBorislav Petkov * error. 145721afaf18SBorislav Petkov */ 1458cbe1de16SBorislav Petkov kill_current_task = 0; 145921afaf18SBorislav Petkov 146021afaf18SBorislav Petkov /* 146121afaf18SBorislav Petkov * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES 146221afaf18SBorislav Petkov * on Intel. 146321afaf18SBorislav Petkov */ 1464cbe1de16SBorislav Petkov lmce = 1; 146521afaf18SBorislav Petkov 146621afaf18SBorislav Petkov this_cpu_inc(mce_exception_count); 146721afaf18SBorislav Petkov 146821afaf18SBorislav Petkov mce_gather_info(&m, regs); 146921afaf18SBorislav Petkov m.tsc = rdtsc(); 147021afaf18SBorislav Petkov 147121afaf18SBorislav Petkov final = this_cpu_ptr(&mces_seen); 147221afaf18SBorislav Petkov *final = m; 147321afaf18SBorislav Petkov 147421afaf18SBorislav Petkov no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); 147521afaf18SBorislav Petkov 147621afaf18SBorislav Petkov barrier(); 147721afaf18SBorislav Petkov 147821afaf18SBorislav Petkov /* 147921afaf18SBorislav Petkov * When no restart IP might need to kill or panic. 148021afaf18SBorislav Petkov * Assume the worst for now, but if we find the 148121afaf18SBorislav Petkov * severity is MCE_AR_SEVERITY we have other options. 148221afaf18SBorislav Petkov */ 148321afaf18SBorislav Petkov if (!(m.mcgstatus & MCG_STATUS_RIPV)) 1484e1c06d23SGabriele Paoloni kill_current_task = (cfg->tolerant == 3) ? 0 : 1; 148521afaf18SBorislav Petkov /* 148621afaf18SBorislav Petkov * Check if this MCE is signaled to only this logical processor, 148770f0c230STony W Wang-oc * on Intel, Zhaoxin only. 148821afaf18SBorislav Petkov */ 148970f0c230STony W Wang-oc if (m.cpuvendor == X86_VENDOR_INTEL || 149070f0c230STony W Wang-oc m.cpuvendor == X86_VENDOR_ZHAOXIN) 149121afaf18SBorislav Petkov lmce = m.mcgstatus & MCG_STATUS_LMCES; 149221afaf18SBorislav Petkov 149321afaf18SBorislav Petkov /* 149421afaf18SBorislav Petkov * Local machine check may already know that we have to panic. 149521afaf18SBorislav Petkov * Broadcast machine check begins rendezvous in mce_start() 149621afaf18SBorislav Petkov * Go through all banks in exclusion of the other CPUs. This way we 149721afaf18SBorislav Petkov * don't report duplicated events on shared banks because the first one 149821afaf18SBorislav Petkov * to see it will clear it. 149921afaf18SBorislav Petkov */ 150021afaf18SBorislav Petkov if (lmce) { 15013a866b16SGabriele Paoloni if (no_way_out && cfg->tolerant < 3) 150221afaf18SBorislav Petkov mce_panic("Fatal local machine check", &m, msg); 150321afaf18SBorislav Petkov } else { 150421afaf18SBorislav Petkov order = mce_start(&no_way_out); 150521afaf18SBorislav Petkov } 150621afaf18SBorislav Petkov 150775581a20SBorislav Petkov taint = __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst); 150821afaf18SBorislav Petkov 150921afaf18SBorislav Petkov if (!no_way_out) 151021afaf18SBorislav Petkov mce_clear_state(toclear); 151121afaf18SBorislav Petkov 151221afaf18SBorislav Petkov /* 151321afaf18SBorislav Petkov * Do most of the synchronization with other CPUs. 151421afaf18SBorislav Petkov * When there's any problem use only local no_way_out state. 151521afaf18SBorislav Petkov */ 151621afaf18SBorislav Petkov if (!lmce) { 151725bc65d8SGabriele Paoloni if (mce_end(order) < 0) { 151825bc65d8SGabriele Paoloni if (!no_way_out) 151921afaf18SBorislav Petkov no_way_out = worst >= MCE_PANIC_SEVERITY; 1520e273e6e1SGabriele Paoloni 1521e273e6e1SGabriele Paoloni if (no_way_out && cfg->tolerant < 3) 1522e273e6e1SGabriele Paoloni mce_panic("Fatal machine check on current CPU", &m, msg); 152325bc65d8SGabriele Paoloni } 152421afaf18SBorislav Petkov } else { 152521afaf18SBorislav Petkov /* 152621afaf18SBorislav Petkov * If there was a fatal machine check we should have 152721afaf18SBorislav Petkov * already called mce_panic earlier in this function. 152821afaf18SBorislav Petkov * Since we re-read the banks, we might have found 152921afaf18SBorislav Petkov * something new. Check again to see if we found a 153021afaf18SBorislav Petkov * fatal error. We call "mce_severity()" again to 153121afaf18SBorislav Petkov * make sure we have the right "msg". 153221afaf18SBorislav Petkov */ 153321afaf18SBorislav Petkov if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) { 153441ce0564SYouquan Song mce_severity(&m, regs, cfg->tolerant, &msg, true); 153521afaf18SBorislav Petkov mce_panic("Local fatal machine check!", &m, msg); 153621afaf18SBorislav Petkov } 153721afaf18SBorislav Petkov } 153821afaf18SBorislav Petkov 15394fbce464SBorislav Petkov /* 154075581a20SBorislav Petkov * Enable instrumentation around the external facilities like task_work_add() 154175581a20SBorislav Petkov * (via queue_task_work()), fixup_exception() etc. For now, that is. Fixing this 154275581a20SBorislav Petkov * properly would need a lot more involved reorganization. 15434fbce464SBorislav Petkov */ 15444fbce464SBorislav Petkov instrumentation_begin(); 15454fbce464SBorislav Petkov 154675581a20SBorislav Petkov if (taint) 154775581a20SBorislav Petkov add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 154875581a20SBorislav Petkov 154975581a20SBorislav Petkov if (worst != MCE_AR_SEVERITY && !kill_current_task) 155075581a20SBorislav Petkov goto out; 155175581a20SBorislav Petkov 155221afaf18SBorislav Petkov /* Fault was in user mode and we need to take some action */ 155321afaf18SBorislav Petkov if ((m.cs & 3) == 3) { 1554b052df3dSThomas Gleixner /* If this triggers there is no way to recover. Die hard. */ 1555b052df3dSThomas Gleixner BUG_ON(!on_thread_stack() || !user_mode(regs)); 155621afaf18SBorislav Petkov 1557a6e3cf70STony Luck if (kill_current_task) 1558a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_now); 1559a6e3cf70STony Luck else 1560a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_maybe); 1561c0ab7ffcSTony Luck 156221afaf18SBorislav Petkov } else { 15631df73b21SBorislav Petkov /* 15641df73b21SBorislav Petkov * Handle an MCE which has happened in kernel space but from 15651df73b21SBorislav Petkov * which the kernel can recover: ex_has_fault_handler() has 15661df73b21SBorislav Petkov * already verified that the rIP at which the error happened is 15671df73b21SBorislav Petkov * a rIP from which the kernel can recover (by jumping to 15681df73b21SBorislav Petkov * recovery code specified in _ASM_EXTABLE_FAULT()) and the 15691df73b21SBorislav Petkov * corresponding exception handler which would do that is the 15701df73b21SBorislav Petkov * proper one. 15711df73b21SBorislav Petkov */ 15721df73b21SBorislav Petkov if (m.kflags & MCE_IN_KERNEL_RECOV) { 15738cd501c1SThomas Gleixner if (!fixup_exception(regs, X86_TRAP_MC, 0, 0)) 15742d806d07SJan H. Schönherr mce_panic("Failed kernel mode recovery", &m, msg); 157521afaf18SBorislav Petkov } 1576c0ab7ffcSTony Luck 1577c0ab7ffcSTony Luck if (m.kflags & MCE_IN_KERNEL_COPYIN) 1578a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_never); 15791df73b21SBorislav Petkov } 15804fbce464SBorislav Petkov 158175581a20SBorislav Petkov out: 15824fbce464SBorislav Petkov instrumentation_end(); 15834fbce464SBorislav Petkov 1584*8ca97812SJue Wang clear: 15851e36d9c6STony Luck mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); 158621afaf18SBorislav Petkov } 158721afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(do_machine_check); 158821afaf18SBorislav Petkov 158921afaf18SBorislav Petkov #ifndef CONFIG_MEMORY_FAILURE 159021afaf18SBorislav Petkov int memory_failure(unsigned long pfn, int flags) 159121afaf18SBorislav Petkov { 159221afaf18SBorislav Petkov /* mce_severity() should not hand us an ACTION_REQUIRED error */ 159321afaf18SBorislav Petkov BUG_ON(flags & MF_ACTION_REQUIRED); 159421afaf18SBorislav Petkov pr_err("Uncorrected memory error in page 0x%lx ignored\n" 159521afaf18SBorislav Petkov "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", 159621afaf18SBorislav Petkov pfn); 159721afaf18SBorislav Petkov 159821afaf18SBorislav Petkov return 0; 159921afaf18SBorislav Petkov } 160021afaf18SBorislav Petkov #endif 160121afaf18SBorislav Petkov 160221afaf18SBorislav Petkov /* 160321afaf18SBorislav Petkov * Periodic polling timer for "silent" machine check errors. If the 160421afaf18SBorislav Petkov * poller finds an MCE, poll 2x faster. When the poller finds no more 160521afaf18SBorislav Petkov * errors, poll 2x slower (up to check_interval seconds). 160621afaf18SBorislav Petkov */ 160721afaf18SBorislav Petkov static unsigned long check_interval = INITIAL_CHECK_INTERVAL; 160821afaf18SBorislav Petkov 160921afaf18SBorislav Petkov static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ 161021afaf18SBorislav Petkov static DEFINE_PER_CPU(struct timer_list, mce_timer); 161121afaf18SBorislav Petkov 161221afaf18SBorislav Petkov static unsigned long mce_adjust_timer_default(unsigned long interval) 161321afaf18SBorislav Petkov { 161421afaf18SBorislav Petkov return interval; 161521afaf18SBorislav Petkov } 161621afaf18SBorislav Petkov 161721afaf18SBorislav Petkov static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; 161821afaf18SBorislav Petkov 161921afaf18SBorislav Petkov static void __start_timer(struct timer_list *t, unsigned long interval) 162021afaf18SBorislav Petkov { 162121afaf18SBorislav Petkov unsigned long when = jiffies + interval; 162221afaf18SBorislav Petkov unsigned long flags; 162321afaf18SBorislav Petkov 162421afaf18SBorislav Petkov local_irq_save(flags); 162521afaf18SBorislav Petkov 162621afaf18SBorislav Petkov if (!timer_pending(t) || time_before(when, t->expires)) 162721afaf18SBorislav Petkov mod_timer(t, round_jiffies(when)); 162821afaf18SBorislav Petkov 162921afaf18SBorislav Petkov local_irq_restore(flags); 163021afaf18SBorislav Petkov } 163121afaf18SBorislav Petkov 163221afaf18SBorislav Petkov static void mce_timer_fn(struct timer_list *t) 163321afaf18SBorislav Petkov { 163421afaf18SBorislav Petkov struct timer_list *cpu_t = this_cpu_ptr(&mce_timer); 163521afaf18SBorislav Petkov unsigned long iv; 163621afaf18SBorislav Petkov 163721afaf18SBorislav Petkov WARN_ON(cpu_t != t); 163821afaf18SBorislav Petkov 163921afaf18SBorislav Petkov iv = __this_cpu_read(mce_next_interval); 164021afaf18SBorislav Petkov 164121afaf18SBorislav Petkov if (mce_available(this_cpu_ptr(&cpu_info))) { 164221afaf18SBorislav Petkov machine_check_poll(0, this_cpu_ptr(&mce_poll_banks)); 164321afaf18SBorislav Petkov 164421afaf18SBorislav Petkov if (mce_intel_cmci_poll()) { 164521afaf18SBorislav Petkov iv = mce_adjust_timer(iv); 164621afaf18SBorislav Petkov goto done; 164721afaf18SBorislav Petkov } 164821afaf18SBorislav Petkov } 164921afaf18SBorislav Petkov 165021afaf18SBorislav Petkov /* 165121afaf18SBorislav Petkov * Alert userspace if needed. If we logged an MCE, reduce the polling 165221afaf18SBorislav Petkov * interval, otherwise increase the polling interval. 165321afaf18SBorislav Petkov */ 165421afaf18SBorislav Petkov if (mce_notify_irq()) 165521afaf18SBorislav Petkov iv = max(iv / 2, (unsigned long) HZ/100); 165621afaf18SBorislav Petkov else 165721afaf18SBorislav Petkov iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); 165821afaf18SBorislav Petkov 165921afaf18SBorislav Petkov done: 166021afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, iv); 166121afaf18SBorislav Petkov __start_timer(t, iv); 166221afaf18SBorislav Petkov } 166321afaf18SBorislav Petkov 166421afaf18SBorislav Petkov /* 166521afaf18SBorislav Petkov * Ensure that the timer is firing in @interval from now. 166621afaf18SBorislav Petkov */ 166721afaf18SBorislav Petkov void mce_timer_kick(unsigned long interval) 166821afaf18SBorislav Petkov { 166921afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 167021afaf18SBorislav Petkov unsigned long iv = __this_cpu_read(mce_next_interval); 167121afaf18SBorislav Petkov 167221afaf18SBorislav Petkov __start_timer(t, interval); 167321afaf18SBorislav Petkov 167421afaf18SBorislav Petkov if (interval < iv) 167521afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, interval); 167621afaf18SBorislav Petkov } 167721afaf18SBorislav Petkov 167821afaf18SBorislav Petkov /* Must not be called in IRQ context where del_timer_sync() can deadlock */ 167921afaf18SBorislav Petkov static void mce_timer_delete_all(void) 168021afaf18SBorislav Petkov { 168121afaf18SBorislav Petkov int cpu; 168221afaf18SBorislav Petkov 168321afaf18SBorislav Petkov for_each_online_cpu(cpu) 168421afaf18SBorislav Petkov del_timer_sync(&per_cpu(mce_timer, cpu)); 168521afaf18SBorislav Petkov } 168621afaf18SBorislav Petkov 168721afaf18SBorislav Petkov /* 168821afaf18SBorislav Petkov * Notify the user(s) about new machine check events. 168921afaf18SBorislav Petkov * Can be called from interrupt context, but not from machine check/NMI 169021afaf18SBorislav Petkov * context. 169121afaf18SBorislav Petkov */ 169221afaf18SBorislav Petkov int mce_notify_irq(void) 169321afaf18SBorislav Petkov { 169421afaf18SBorislav Petkov /* Not more than two messages every minute */ 169521afaf18SBorislav Petkov static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); 169621afaf18SBorislav Petkov 169721afaf18SBorislav Petkov if (test_and_clear_bit(0, &mce_need_notify)) { 169821afaf18SBorislav Petkov mce_work_trigger(); 169921afaf18SBorislav Petkov 170021afaf18SBorislav Petkov if (__ratelimit(&ratelimit)) 170121afaf18SBorislav Petkov pr_info(HW_ERR "Machine check events logged\n"); 170221afaf18SBorislav Petkov 170321afaf18SBorislav Petkov return 1; 170421afaf18SBorislav Petkov } 170521afaf18SBorislav Petkov return 0; 170621afaf18SBorislav Petkov } 170721afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_notify_irq); 170821afaf18SBorislav Petkov 1709b4914508SYazen Ghannam static void __mcheck_cpu_mce_banks_init(void) 171021afaf18SBorislav Petkov { 1711b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1712c7d314f3SYazen Ghannam u8 n_banks = this_cpu_read(mce_num_banks); 171321afaf18SBorislav Petkov int i; 171421afaf18SBorislav Petkov 1715c7d314f3SYazen Ghannam for (i = 0; i < n_banks; i++) { 171621afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 171721afaf18SBorislav Petkov 1718068b053dSYazen Ghannam /* 1719068b053dSYazen Ghannam * Init them all, __mcheck_cpu_apply_quirks() is going to apply 1720068b053dSYazen Ghannam * the required vendor quirks before 1721068b053dSYazen Ghannam * __mcheck_cpu_init_clear_banks() does the final bank setup. 1722068b053dSYazen Ghannam */ 172321afaf18SBorislav Petkov b->ctl = -1ULL; 172477080929SKaixu Xia b->init = true; 172521afaf18SBorislav Petkov } 172621afaf18SBorislav Petkov } 172721afaf18SBorislav Petkov 172821afaf18SBorislav Petkov /* 172921afaf18SBorislav Petkov * Initialize Machine Checks for a CPU. 173021afaf18SBorislav Petkov */ 1731b4914508SYazen Ghannam static void __mcheck_cpu_cap_init(void) 173221afaf18SBorislav Petkov { 173321afaf18SBorislav Petkov u64 cap; 1734006c0770SYazen Ghannam u8 b; 173521afaf18SBorislav Petkov 173621afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 173721afaf18SBorislav Petkov 173821afaf18SBorislav Petkov b = cap & MCG_BANKCNT_MASK; 173921afaf18SBorislav Petkov 1740c7d314f3SYazen Ghannam if (b > MAX_NR_BANKS) { 1741c7d314f3SYazen Ghannam pr_warn("CPU%d: Using only %u machine check banks out of %u\n", 1742c7d314f3SYazen Ghannam smp_processor_id(), MAX_NR_BANKS, b); 1743c7d314f3SYazen Ghannam b = MAX_NR_BANKS; 1744c7d314f3SYazen Ghannam } 1745c7d314f3SYazen Ghannam 1746c7d314f3SYazen Ghannam this_cpu_write(mce_num_banks, b); 174721afaf18SBorislav Petkov 1748b4914508SYazen Ghannam __mcheck_cpu_mce_banks_init(); 174921afaf18SBorislav Petkov 175021afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 175121afaf18SBorislav Petkov if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) 175221afaf18SBorislav Petkov mca_cfg.rip_msr = MSR_IA32_MCG_EIP; 175321afaf18SBorislav Petkov 175421afaf18SBorislav Petkov if (cap & MCG_SER_P) 175521afaf18SBorislav Petkov mca_cfg.ser = 1; 175621afaf18SBorislav Petkov } 175721afaf18SBorislav Petkov 175821afaf18SBorislav Petkov static void __mcheck_cpu_init_generic(void) 175921afaf18SBorislav Petkov { 176021afaf18SBorislav Petkov enum mcp_flags m_fl = 0; 176121afaf18SBorislav Petkov mce_banks_t all_banks; 176221afaf18SBorislav Petkov u64 cap; 176321afaf18SBorislav Petkov 176421afaf18SBorislav Petkov if (!mca_cfg.bootlog) 176521afaf18SBorislav Petkov m_fl = MCP_DONTLOG; 176621afaf18SBorislav Petkov 176721afaf18SBorislav Petkov /* 17683bff147bSBorislav Petkov * Log the machine checks left over from the previous reset. Log them 17693bff147bSBorislav Petkov * only, do not start processing them. That will happen in mcheck_late_init() 17703bff147bSBorislav Petkov * when all consumers have been registered on the notifier chain. 177121afaf18SBorislav Petkov */ 177221afaf18SBorislav Petkov bitmap_fill(all_banks, MAX_NR_BANKS); 17733bff147bSBorislav Petkov machine_check_poll(MCP_UC | MCP_QUEUE_LOG | m_fl, &all_banks); 177421afaf18SBorislav Petkov 177521afaf18SBorislav Petkov cr4_set_bits(X86_CR4_MCE); 177621afaf18SBorislav Petkov 177721afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 177821afaf18SBorislav Petkov if (cap & MCG_CTL_P) 177921afaf18SBorislav Petkov wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); 178021afaf18SBorislav Petkov } 178121afaf18SBorislav Petkov 178221afaf18SBorislav Petkov static void __mcheck_cpu_init_clear_banks(void) 178321afaf18SBorislav Petkov { 1784b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 178521afaf18SBorislav Petkov int i; 178621afaf18SBorislav Petkov 1787c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 178821afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 178921afaf18SBorislav Petkov 179021afaf18SBorislav Petkov if (!b->init) 179121afaf18SBorislav Petkov continue; 17928121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); 17938121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 179421afaf18SBorislav Petkov } 179521afaf18SBorislav Petkov } 179621afaf18SBorislav Petkov 179721afaf18SBorislav Petkov /* 1798068b053dSYazen Ghannam * Do a final check to see if there are any unused/RAZ banks. 1799068b053dSYazen Ghannam * 1800068b053dSYazen Ghannam * This must be done after the banks have been initialized and any quirks have 1801068b053dSYazen Ghannam * been applied. 1802068b053dSYazen Ghannam * 1803068b053dSYazen Ghannam * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs. 1804068b053dSYazen Ghannam * Otherwise, a user who disables a bank will not be able to re-enable it 1805068b053dSYazen Ghannam * without a system reboot. 1806068b053dSYazen Ghannam */ 1807068b053dSYazen Ghannam static void __mcheck_cpu_check_banks(void) 1808068b053dSYazen Ghannam { 1809068b053dSYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1810068b053dSYazen Ghannam u64 msrval; 1811068b053dSYazen Ghannam int i; 1812068b053dSYazen Ghannam 1813068b053dSYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1814068b053dSYazen Ghannam struct mce_bank *b = &mce_banks[i]; 1815068b053dSYazen Ghannam 1816068b053dSYazen Ghannam if (!b->init) 1817068b053dSYazen Ghannam continue; 1818068b053dSYazen Ghannam 18198121b8f9SBorislav Petkov rdmsrl(mca_msr_reg(i, MCA_CTL), msrval); 1820068b053dSYazen Ghannam b->init = !!msrval; 1821068b053dSYazen Ghannam } 1822068b053dSYazen Ghannam } 1823068b053dSYazen Ghannam 182421afaf18SBorislav Petkov /* Add per CPU specific workarounds here */ 182521afaf18SBorislav Petkov static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) 182621afaf18SBorislav Petkov { 1827b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 182821afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 182921afaf18SBorislav Petkov 183021afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_UNKNOWN) { 183121afaf18SBorislav Petkov pr_info("unknown CPU type - not enabling MCE support\n"); 183221afaf18SBorislav Petkov return -EOPNOTSUPP; 183321afaf18SBorislav Petkov } 183421afaf18SBorislav Petkov 183521afaf18SBorislav Petkov /* This should be disabled by the BIOS, but isn't always */ 183621afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD) { 1837c7d314f3SYazen Ghannam if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { 183821afaf18SBorislav Petkov /* 183921afaf18SBorislav Petkov * disable GART TBL walk error reporting, which 184021afaf18SBorislav Petkov * trips off incorrectly with the IOMMU & 3ware 184121afaf18SBorislav Petkov * & Cerberus: 184221afaf18SBorislav Petkov */ 184321afaf18SBorislav Petkov clear_bit(10, (unsigned long *)&mce_banks[4].ctl); 184421afaf18SBorislav Petkov } 184521afaf18SBorislav Petkov if (c->x86 < 0x11 && cfg->bootlog < 0) { 184621afaf18SBorislav Petkov /* 184721afaf18SBorislav Petkov * Lots of broken BIOS around that don't clear them 184821afaf18SBorislav Petkov * by default and leave crap in there. Don't log: 184921afaf18SBorislav Petkov */ 185021afaf18SBorislav Petkov cfg->bootlog = 0; 185121afaf18SBorislav Petkov } 185221afaf18SBorislav Petkov /* 185321afaf18SBorislav Petkov * Various K7s with broken bank 0 around. Always disable 185421afaf18SBorislav Petkov * by default. 185521afaf18SBorislav Petkov */ 1856c7d314f3SYazen Ghannam if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0) 185721afaf18SBorislav Petkov mce_banks[0].ctl = 0; 185821afaf18SBorislav Petkov 185921afaf18SBorislav Petkov /* 186021afaf18SBorislav Petkov * overflow_recov is supported for F15h Models 00h-0fh 186121afaf18SBorislav Petkov * even though we don't have a CPUID bit for it. 186221afaf18SBorislav Petkov */ 186321afaf18SBorislav Petkov if (c->x86 == 0x15 && c->x86_model <= 0xf) 186421afaf18SBorislav Petkov mce_flags.overflow_recov = 1; 186521afaf18SBorislav Petkov 186621afaf18SBorislav Petkov } 186721afaf18SBorislav Petkov 186821afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_INTEL) { 186921afaf18SBorislav Petkov /* 187021afaf18SBorislav Petkov * SDM documents that on family 6 bank 0 should not be written 187121afaf18SBorislav Petkov * because it aliases to another special BIOS controlled 187221afaf18SBorislav Petkov * register. 187321afaf18SBorislav Petkov * But it's not aliased anymore on model 0x1a+ 187421afaf18SBorislav Petkov * Don't ignore bank 0 completely because there could be a 187521afaf18SBorislav Petkov * valid event later, merely don't write CTL0. 187621afaf18SBorislav Petkov */ 187721afaf18SBorislav Petkov 1878c7d314f3SYazen Ghannam if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) 187977080929SKaixu Xia mce_banks[0].init = false; 188021afaf18SBorislav Petkov 188121afaf18SBorislav Petkov /* 188221afaf18SBorislav Petkov * All newer Intel systems support MCE broadcasting. Enable 188321afaf18SBorislav Petkov * synchronization with a one second timeout. 188421afaf18SBorislav Petkov */ 188521afaf18SBorislav Petkov if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && 188621afaf18SBorislav Petkov cfg->monarch_timeout < 0) 188721afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 188821afaf18SBorislav Petkov 188921afaf18SBorislav Petkov /* 189021afaf18SBorislav Petkov * There are also broken BIOSes on some Pentium M and 189121afaf18SBorislav Petkov * earlier systems: 189221afaf18SBorislav Petkov */ 189321afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) 189421afaf18SBorislav Petkov cfg->bootlog = 0; 189521afaf18SBorislav Petkov 189621afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model == 45) 1897cc466666SBorislav Petkov mce_flags.snb_ifu_quirk = 1; 1898*8ca97812SJue Wang 1899*8ca97812SJue Wang /* 1900*8ca97812SJue Wang * Skylake, Cascacde Lake and Cooper Lake require a quirk on 1901*8ca97812SJue Wang * rep movs. 1902*8ca97812SJue Wang */ 1903*8ca97812SJue Wang if (c->x86 == 6 && c->x86_model == INTEL_FAM6_SKYLAKE_X) 1904*8ca97812SJue Wang mce_flags.skx_repmov_quirk = 1; 190521afaf18SBorislav Petkov } 19066e898d2bSTony W Wang-oc 19076e898d2bSTony W Wang-oc if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { 19086e898d2bSTony W Wang-oc /* 19096e898d2bSTony W Wang-oc * All newer Zhaoxin CPUs support MCE broadcasting. Enable 19106e898d2bSTony W Wang-oc * synchronization with a one second timeout. 19116e898d2bSTony W Wang-oc */ 19126e898d2bSTony W Wang-oc if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 19136e898d2bSTony W Wang-oc if (cfg->monarch_timeout < 0) 19146e898d2bSTony W Wang-oc cfg->monarch_timeout = USEC_PER_SEC; 19156e898d2bSTony W Wang-oc } 19166e898d2bSTony W Wang-oc } 19176e898d2bSTony W Wang-oc 191821afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 191921afaf18SBorislav Petkov cfg->monarch_timeout = 0; 192021afaf18SBorislav Petkov if (cfg->bootlog != 0) 192121afaf18SBorislav Petkov cfg->panic_timeout = 30; 192221afaf18SBorislav Petkov 192321afaf18SBorislav Petkov return 0; 192421afaf18SBorislav Petkov } 192521afaf18SBorislav Petkov 192621afaf18SBorislav Petkov static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) 192721afaf18SBorislav Petkov { 192821afaf18SBorislav Petkov if (c->x86 != 5) 192921afaf18SBorislav Petkov return 0; 193021afaf18SBorislav Petkov 193121afaf18SBorislav Petkov switch (c->x86_vendor) { 193221afaf18SBorislav Petkov case X86_VENDOR_INTEL: 193321afaf18SBorislav Petkov intel_p5_mcheck_init(c); 1934cbe1de16SBorislav Petkov mce_flags.p5 = 1; 193521afaf18SBorislav Petkov return 1; 193621afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 193721afaf18SBorislav Petkov winchip_mcheck_init(c); 1938cbe1de16SBorislav Petkov mce_flags.winchip = 1; 193921afaf18SBorislav Petkov return 1; 194021afaf18SBorislav Petkov default: 194121afaf18SBorislav Petkov return 0; 194221afaf18SBorislav Petkov } 194321afaf18SBorislav Petkov 194421afaf18SBorislav Petkov return 0; 194521afaf18SBorislav Petkov } 194621afaf18SBorislav Petkov 194721afaf18SBorislav Petkov /* 194821afaf18SBorislav Petkov * Init basic CPU features needed for early decoding of MCEs. 194921afaf18SBorislav Petkov */ 195021afaf18SBorislav Petkov static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) 195121afaf18SBorislav Petkov { 195221afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) { 195321afaf18SBorislav Petkov mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); 195421afaf18SBorislav Petkov mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); 195521afaf18SBorislav Petkov mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); 1956c9bf318fSThomas Gleixner mce_flags.amd_threshold = 1; 195721afaf18SBorislav Petkov } 195821afaf18SBorislav Petkov } 195921afaf18SBorislav Petkov 196021afaf18SBorislav Petkov static void mce_centaur_feature_init(struct cpuinfo_x86 *c) 196121afaf18SBorislav Petkov { 196221afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 196321afaf18SBorislav Petkov 196421afaf18SBorislav Petkov /* 196521afaf18SBorislav Petkov * All newer Centaur CPUs support MCE broadcasting. Enable 196621afaf18SBorislav Petkov * synchronization with a one second timeout. 196721afaf18SBorislav Petkov */ 196821afaf18SBorislav Petkov if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) || 196921afaf18SBorislav Petkov c->x86 > 6) { 197021afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 197121afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 197221afaf18SBorislav Petkov } 197321afaf18SBorislav Petkov } 197421afaf18SBorislav Petkov 19755a3d56a0STony W Wang-oc static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) 19765a3d56a0STony W Wang-oc { 19775a3d56a0STony W Wang-oc struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 19785a3d56a0STony W Wang-oc 19795a3d56a0STony W Wang-oc /* 19805a3d56a0STony W Wang-oc * These CPUs have MCA bank 8 which reports only one error type called 19815a3d56a0STony W Wang-oc * SVAD (System View Address Decoder). The reporting of that error is 19825a3d56a0STony W Wang-oc * controlled by IA32_MC8.CTL.0. 19835a3d56a0STony W Wang-oc * 19845a3d56a0STony W Wang-oc * If enabled, prefetching on these CPUs will cause SVAD MCE when 19855a3d56a0STony W Wang-oc * virtual machines start and result in a system panic. Always disable 19865a3d56a0STony W Wang-oc * bank 8 SVAD error by default. 19875a3d56a0STony W Wang-oc */ 19885a3d56a0STony W Wang-oc if ((c->x86 == 7 && c->x86_model == 0x1b) || 19895a3d56a0STony W Wang-oc (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 19905a3d56a0STony W Wang-oc if (this_cpu_read(mce_num_banks) > 8) 19915a3d56a0STony W Wang-oc mce_banks[8].ctl = 0; 19925a3d56a0STony W Wang-oc } 19935a3d56a0STony W Wang-oc 19945a3d56a0STony W Wang-oc intel_init_cmci(); 199570f0c230STony W Wang-oc intel_init_lmce(); 19965a3d56a0STony W Wang-oc mce_adjust_timer = cmci_intel_adjust_timer; 19975a3d56a0STony W Wang-oc } 19985a3d56a0STony W Wang-oc 199970f0c230STony W Wang-oc static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) 200070f0c230STony W Wang-oc { 200170f0c230STony W Wang-oc intel_clear_lmce(); 200270f0c230STony W Wang-oc } 200370f0c230STony W Wang-oc 200421afaf18SBorislav Petkov static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) 200521afaf18SBorislav Petkov { 200621afaf18SBorislav Petkov switch (c->x86_vendor) { 200721afaf18SBorislav Petkov case X86_VENDOR_INTEL: 200821afaf18SBorislav Petkov mce_intel_feature_init(c); 200921afaf18SBorislav Petkov mce_adjust_timer = cmci_intel_adjust_timer; 201021afaf18SBorislav Petkov break; 201121afaf18SBorislav Petkov 201221afaf18SBorislav Petkov case X86_VENDOR_AMD: { 201321afaf18SBorislav Petkov mce_amd_feature_init(c); 201421afaf18SBorislav Petkov break; 201521afaf18SBorislav Petkov } 201621afaf18SBorislav Petkov 201721afaf18SBorislav Petkov case X86_VENDOR_HYGON: 201821afaf18SBorislav Petkov mce_hygon_feature_init(c); 201921afaf18SBorislav Petkov break; 202021afaf18SBorislav Petkov 202121afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 202221afaf18SBorislav Petkov mce_centaur_feature_init(c); 202321afaf18SBorislav Petkov break; 202421afaf18SBorislav Petkov 20255a3d56a0STony W Wang-oc case X86_VENDOR_ZHAOXIN: 20265a3d56a0STony W Wang-oc mce_zhaoxin_feature_init(c); 20275a3d56a0STony W Wang-oc break; 20285a3d56a0STony W Wang-oc 202921afaf18SBorislav Petkov default: 203021afaf18SBorislav Petkov break; 203121afaf18SBorislav Petkov } 203221afaf18SBorislav Petkov } 203321afaf18SBorislav Petkov 203421afaf18SBorislav Petkov static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) 203521afaf18SBorislav Petkov { 203621afaf18SBorislav Petkov switch (c->x86_vendor) { 203721afaf18SBorislav Petkov case X86_VENDOR_INTEL: 203821afaf18SBorislav Petkov mce_intel_feature_clear(c); 203921afaf18SBorislav Petkov break; 204070f0c230STony W Wang-oc 204170f0c230STony W Wang-oc case X86_VENDOR_ZHAOXIN: 204270f0c230STony W Wang-oc mce_zhaoxin_feature_clear(c); 204370f0c230STony W Wang-oc break; 204470f0c230STony W Wang-oc 204521afaf18SBorislav Petkov default: 204621afaf18SBorislav Petkov break; 204721afaf18SBorislav Petkov } 204821afaf18SBorislav Petkov } 204921afaf18SBorislav Petkov 205021afaf18SBorislav Petkov static void mce_start_timer(struct timer_list *t) 205121afaf18SBorislav Petkov { 205221afaf18SBorislav Petkov unsigned long iv = check_interval * HZ; 205321afaf18SBorislav Petkov 205421afaf18SBorislav Petkov if (mca_cfg.ignore_ce || !iv) 205521afaf18SBorislav Petkov return; 205621afaf18SBorislav Petkov 205721afaf18SBorislav Petkov this_cpu_write(mce_next_interval, iv); 205821afaf18SBorislav Petkov __start_timer(t, iv); 205921afaf18SBorislav Petkov } 206021afaf18SBorislav Petkov 206121afaf18SBorislav Petkov static void __mcheck_cpu_setup_timer(void) 206221afaf18SBorislav Petkov { 206321afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 206421afaf18SBorislav Petkov 206521afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 206621afaf18SBorislav Petkov } 206721afaf18SBorislav Petkov 206821afaf18SBorislav Petkov static void __mcheck_cpu_init_timer(void) 206921afaf18SBorislav Petkov { 207021afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 207121afaf18SBorislav Petkov 207221afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 207321afaf18SBorislav Petkov mce_start_timer(t); 207421afaf18SBorislav Petkov } 207521afaf18SBorislav Petkov 207645d4b7b9SYazen Ghannam bool filter_mce(struct mce *m) 207745d4b7b9SYazen Ghannam { 207871a84402SYazen Ghannam if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 207971a84402SYazen Ghannam return amd_filter_mce(m); 20802976908eSPrarit Bhargava if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 20812976908eSPrarit Bhargava return intel_filter_mce(m); 208271a84402SYazen Ghannam 208345d4b7b9SYazen Ghannam return false; 208445d4b7b9SYazen Ghannam } 208545d4b7b9SYazen Ghannam 20864c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_kernel(struct pt_regs *regs) 208721afaf18SBorislav Petkov { 2088b6be002bSThomas Gleixner irqentry_state_t irq_state; 2089bc21a291SThomas Gleixner 209013cbc0cdSAndy Lutomirski WARN_ON_ONCE(user_mode(regs)); 209113cbc0cdSAndy Lutomirski 20924c0dcd83SThomas Gleixner /* 20934c0dcd83SThomas Gleixner * Only required when from kernel mode. See 20944c0dcd83SThomas Gleixner * mce_check_crashing_cpu() for details. 20954c0dcd83SThomas Gleixner */ 2096cbe1de16SBorislav Petkov if (mca_cfg.initialized && mce_check_crashing_cpu()) 209794a46d31SThomas Gleixner return; 209894a46d31SThomas Gleixner 2099b6be002bSThomas Gleixner irq_state = irqentry_nmi_enter(regs); 210073749536SPeter Zijlstra 2101cbe1de16SBorislav Petkov do_machine_check(regs); 210273749536SPeter Zijlstra 2103b6be002bSThomas Gleixner irqentry_nmi_exit(regs, irq_state); 210421afaf18SBorislav Petkov } 210521afaf18SBorislav Petkov 21064c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_user(struct pt_regs *regs) 21074c0dcd83SThomas Gleixner { 2108517e4992SThomas Gleixner irqentry_enter_from_user_mode(regs); 210973749536SPeter Zijlstra 2110cbe1de16SBorislav Petkov do_machine_check(regs); 211173749536SPeter Zijlstra 2112517e4992SThomas Gleixner irqentry_exit_to_user_mode(regs); 21134c0dcd83SThomas Gleixner } 21144c0dcd83SThomas Gleixner 21154c0dcd83SThomas Gleixner #ifdef CONFIG_X86_64 21164c0dcd83SThomas Gleixner /* MCE hit kernel mode */ 21174c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE(exc_machine_check) 21184c0dcd83SThomas Gleixner { 2119cd840e42SPeter Zijlstra unsigned long dr7; 2120cd840e42SPeter Zijlstra 2121cd840e42SPeter Zijlstra dr7 = local_db_save(); 21224c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 2123cd840e42SPeter Zijlstra local_db_restore(dr7); 21244c0dcd83SThomas Gleixner } 21254c0dcd83SThomas Gleixner 21264c0dcd83SThomas Gleixner /* The user mode variant. */ 21274c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE_USER(exc_machine_check) 21284c0dcd83SThomas Gleixner { 2129cd840e42SPeter Zijlstra unsigned long dr7; 2130cd840e42SPeter Zijlstra 2131cd840e42SPeter Zijlstra dr7 = local_db_save(); 21324c0dcd83SThomas Gleixner exc_machine_check_user(regs); 2133cd840e42SPeter Zijlstra local_db_restore(dr7); 21344c0dcd83SThomas Gleixner } 21354c0dcd83SThomas Gleixner #else 21364c0dcd83SThomas Gleixner /* 32bit unified entry point */ 213713cbc0cdSAndy Lutomirski DEFINE_IDTENTRY_RAW(exc_machine_check) 21384c0dcd83SThomas Gleixner { 2139cd840e42SPeter Zijlstra unsigned long dr7; 2140cd840e42SPeter Zijlstra 2141cd840e42SPeter Zijlstra dr7 = local_db_save(); 21424c0dcd83SThomas Gleixner if (user_mode(regs)) 21434c0dcd83SThomas Gleixner exc_machine_check_user(regs); 21444c0dcd83SThomas Gleixner else 21454c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 2146cd840e42SPeter Zijlstra local_db_restore(dr7); 21474c0dcd83SThomas Gleixner } 21484c0dcd83SThomas Gleixner #endif 214921afaf18SBorislav Petkov 215021afaf18SBorislav Petkov /* 215121afaf18SBorislav Petkov * Called for each booted CPU to set up machine checks. 215221afaf18SBorislav Petkov * Must be called with preempt off: 215321afaf18SBorislav Petkov */ 215421afaf18SBorislav Petkov void mcheck_cpu_init(struct cpuinfo_x86 *c) 215521afaf18SBorislav Petkov { 215621afaf18SBorislav Petkov if (mca_cfg.disabled) 215721afaf18SBorislav Petkov return; 215821afaf18SBorislav Petkov 215921afaf18SBorislav Petkov if (__mcheck_cpu_ancient_init(c)) 216021afaf18SBorislav Petkov return; 216121afaf18SBorislav Petkov 216221afaf18SBorislav Petkov if (!mce_available(c)) 216321afaf18SBorislav Petkov return; 216421afaf18SBorislav Petkov 2165b4914508SYazen Ghannam __mcheck_cpu_cap_init(); 2166b4914508SYazen Ghannam 2167b4914508SYazen Ghannam if (__mcheck_cpu_apply_quirks(c) < 0) { 216821afaf18SBorislav Petkov mca_cfg.disabled = 1; 216921afaf18SBorislav Petkov return; 217021afaf18SBorislav Petkov } 217121afaf18SBorislav Petkov 217221afaf18SBorislav Petkov if (mce_gen_pool_init()) { 217321afaf18SBorislav Petkov mca_cfg.disabled = 1; 217421afaf18SBorislav Petkov pr_emerg("Couldn't allocate MCE records pool!\n"); 217521afaf18SBorislav Petkov return; 217621afaf18SBorislav Petkov } 217721afaf18SBorislav Petkov 2178cbe1de16SBorislav Petkov mca_cfg.initialized = 1; 217921afaf18SBorislav Petkov 218021afaf18SBorislav Petkov __mcheck_cpu_init_early(c); 218121afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 218221afaf18SBorislav Petkov __mcheck_cpu_init_vendor(c); 218321afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 2184068b053dSYazen Ghannam __mcheck_cpu_check_banks(); 218521afaf18SBorislav Petkov __mcheck_cpu_setup_timer(); 218621afaf18SBorislav Petkov } 218721afaf18SBorislav Petkov 218821afaf18SBorislav Petkov /* 218921afaf18SBorislav Petkov * Called for each booted CPU to clear some machine checks opt-ins 219021afaf18SBorislav Petkov */ 219121afaf18SBorislav Petkov void mcheck_cpu_clear(struct cpuinfo_x86 *c) 219221afaf18SBorislav Petkov { 219321afaf18SBorislav Petkov if (mca_cfg.disabled) 219421afaf18SBorislav Petkov return; 219521afaf18SBorislav Petkov 219621afaf18SBorislav Petkov if (!mce_available(c)) 219721afaf18SBorislav Petkov return; 219821afaf18SBorislav Petkov 219921afaf18SBorislav Petkov /* 220021afaf18SBorislav Petkov * Possibly to clear general settings generic to x86 220121afaf18SBorislav Petkov * __mcheck_cpu_clear_generic(c); 220221afaf18SBorislav Petkov */ 220321afaf18SBorislav Petkov __mcheck_cpu_clear_vendor(c); 220421afaf18SBorislav Petkov 220521afaf18SBorislav Petkov } 220621afaf18SBorislav Petkov 220721afaf18SBorislav Petkov static void __mce_disable_bank(void *arg) 220821afaf18SBorislav Petkov { 220921afaf18SBorislav Petkov int bank = *((int *)arg); 221021afaf18SBorislav Petkov __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); 221121afaf18SBorislav Petkov cmci_disable_bank(bank); 221221afaf18SBorislav Petkov } 221321afaf18SBorislav Petkov 221421afaf18SBorislav Petkov void mce_disable_bank(int bank) 221521afaf18SBorislav Petkov { 2216c7d314f3SYazen Ghannam if (bank >= this_cpu_read(mce_num_banks)) { 221721afaf18SBorislav Petkov pr_warn(FW_BUG 221821afaf18SBorislav Petkov "Ignoring request to disable invalid MCA bank %d.\n", 221921afaf18SBorislav Petkov bank); 222021afaf18SBorislav Petkov return; 222121afaf18SBorislav Petkov } 222221afaf18SBorislav Petkov set_bit(bank, mce_banks_ce_disabled); 222321afaf18SBorislav Petkov on_each_cpu(__mce_disable_bank, &bank, 1); 222421afaf18SBorislav Petkov } 222521afaf18SBorislav Petkov 222621afaf18SBorislav Petkov /* 222721afaf18SBorislav Petkov * mce=off Disables machine check 222821afaf18SBorislav Petkov * mce=no_cmci Disables CMCI 222921afaf18SBorislav Petkov * mce=no_lmce Disables LMCE 223021afaf18SBorislav Petkov * mce=dont_log_ce Clears corrected events silently, no log created for CEs. 223143505646STony Luck * mce=print_all Print all machine check logs to console 223221afaf18SBorislav Petkov * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. 223321afaf18SBorislav Petkov * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) 223421afaf18SBorislav Petkov * monarchtimeout is how long to wait for other CPUs on machine 223521afaf18SBorislav Petkov * check, or 0 to not wait 223621afaf18SBorislav Petkov * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h 223721afaf18SBorislav Petkov and older. 223821afaf18SBorislav Petkov * mce=nobootlog Don't log MCEs from before booting. 223921afaf18SBorislav Petkov * mce=bios_cmci_threshold Don't program the CMCI threshold 2240ec6347bbSDan Williams * mce=recovery force enable copy_mc_fragile() 224121afaf18SBorislav Petkov */ 224221afaf18SBorislav Petkov static int __init mcheck_enable(char *str) 224321afaf18SBorislav Petkov { 224421afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 224521afaf18SBorislav Petkov 224621afaf18SBorislav Petkov if (*str == 0) { 224721afaf18SBorislav Petkov enable_p5_mce(); 224821afaf18SBorislav Petkov return 1; 224921afaf18SBorislav Petkov } 225021afaf18SBorislav Petkov if (*str == '=') 225121afaf18SBorislav Petkov str++; 225221afaf18SBorislav Petkov if (!strcmp(str, "off")) 225321afaf18SBorislav Petkov cfg->disabled = 1; 225421afaf18SBorislav Petkov else if (!strcmp(str, "no_cmci")) 225521afaf18SBorislav Petkov cfg->cmci_disabled = true; 225621afaf18SBorislav Petkov else if (!strcmp(str, "no_lmce")) 225721afaf18SBorislav Petkov cfg->lmce_disabled = 1; 225821afaf18SBorislav Petkov else if (!strcmp(str, "dont_log_ce")) 225921afaf18SBorislav Petkov cfg->dont_log_ce = true; 226043505646STony Luck else if (!strcmp(str, "print_all")) 226143505646STony Luck cfg->print_all = true; 226221afaf18SBorislav Petkov else if (!strcmp(str, "ignore_ce")) 226321afaf18SBorislav Petkov cfg->ignore_ce = true; 226421afaf18SBorislav Petkov else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) 226521afaf18SBorislav Petkov cfg->bootlog = (str[0] == 'b'); 226621afaf18SBorislav Petkov else if (!strcmp(str, "bios_cmci_threshold")) 226721afaf18SBorislav Petkov cfg->bios_cmci_threshold = 1; 226821afaf18SBorislav Petkov else if (!strcmp(str, "recovery")) 226921afaf18SBorislav Petkov cfg->recovery = 1; 227021afaf18SBorislav Petkov else if (isdigit(str[0])) { 227121afaf18SBorislav Petkov if (get_option(&str, &cfg->tolerant) == 2) 227221afaf18SBorislav Petkov get_option(&str, &(cfg->monarch_timeout)); 227321afaf18SBorislav Petkov } else { 227421afaf18SBorislav Petkov pr_info("mce argument %s ignored. Please use /sys\n", str); 227521afaf18SBorislav Petkov return 0; 227621afaf18SBorislav Petkov } 227721afaf18SBorislav Petkov return 1; 227821afaf18SBorislav Petkov } 227921afaf18SBorislav Petkov __setup("mce", mcheck_enable); 228021afaf18SBorislav Petkov 228121afaf18SBorislav Petkov int __init mcheck_init(void) 228221afaf18SBorislav Petkov { 2283c9c6d216STony Luck mce_register_decode_chain(&early_nb); 22848438b84aSJan H. Schönherr mce_register_decode_chain(&mce_uc_nb); 228521afaf18SBorislav Petkov mce_register_decode_chain(&mce_default_nb); 228621afaf18SBorislav Petkov 228721afaf18SBorislav Petkov INIT_WORK(&mce_work, mce_gen_pool_process); 228821afaf18SBorislav Petkov init_irq_work(&mce_irq_work, mce_irq_work_cb); 228921afaf18SBorislav Petkov 229021afaf18SBorislav Petkov return 0; 229121afaf18SBorislav Petkov } 229221afaf18SBorislav Petkov 229321afaf18SBorislav Petkov /* 229421afaf18SBorislav Petkov * mce_syscore: PM support 229521afaf18SBorislav Petkov */ 229621afaf18SBorislav Petkov 229721afaf18SBorislav Petkov /* 229821afaf18SBorislav Petkov * Disable machine checks on suspend and shutdown. We can't really handle 229921afaf18SBorislav Petkov * them later. 230021afaf18SBorislav Petkov */ 230121afaf18SBorislav Petkov static void mce_disable_error_reporting(void) 230221afaf18SBorislav Petkov { 2303b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 230421afaf18SBorislav Petkov int i; 230521afaf18SBorislav Petkov 2306c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 230721afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 230821afaf18SBorislav Petkov 230921afaf18SBorislav Petkov if (b->init) 23108121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), 0); 231121afaf18SBorislav Petkov } 231221afaf18SBorislav Petkov return; 231321afaf18SBorislav Petkov } 231421afaf18SBorislav Petkov 231521afaf18SBorislav Petkov static void vendor_disable_error_reporting(void) 231621afaf18SBorislav Petkov { 231721afaf18SBorislav Petkov /* 23186e898d2bSTony W Wang-oc * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these 23196e898d2bSTony W Wang-oc * MSRs are socket-wide. Disabling them for just a single offlined CPU 23206e898d2bSTony W Wang-oc * is bad, since it will inhibit reporting for all shared resources on 23216e898d2bSTony W Wang-oc * the socket like the last level cache (LLC), the integrated memory 23226e898d2bSTony W Wang-oc * controller (iMC), etc. 232321afaf18SBorislav Petkov */ 232421afaf18SBorislav Petkov if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || 232521afaf18SBorislav Petkov boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || 23266e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 23276e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) 232821afaf18SBorislav Petkov return; 232921afaf18SBorislav Petkov 233021afaf18SBorislav Petkov mce_disable_error_reporting(); 233121afaf18SBorislav Petkov } 233221afaf18SBorislav Petkov 233321afaf18SBorislav Petkov static int mce_syscore_suspend(void) 233421afaf18SBorislav Petkov { 233521afaf18SBorislav Petkov vendor_disable_error_reporting(); 233621afaf18SBorislav Petkov return 0; 233721afaf18SBorislav Petkov } 233821afaf18SBorislav Petkov 233921afaf18SBorislav Petkov static void mce_syscore_shutdown(void) 234021afaf18SBorislav Petkov { 234121afaf18SBorislav Petkov vendor_disable_error_reporting(); 234221afaf18SBorislav Petkov } 234321afaf18SBorislav Petkov 234421afaf18SBorislav Petkov /* 234521afaf18SBorislav Petkov * On resume clear all MCE state. Don't want to see leftovers from the BIOS. 234621afaf18SBorislav Petkov * Only one CPU is active at this time, the others get re-added later using 234721afaf18SBorislav Petkov * CPU hotplug: 234821afaf18SBorislav Petkov */ 234921afaf18SBorislav Petkov static void mce_syscore_resume(void) 235021afaf18SBorislav Petkov { 235121afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 235221afaf18SBorislav Petkov __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); 235321afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 235421afaf18SBorislav Petkov } 235521afaf18SBorislav Petkov 235621afaf18SBorislav Petkov static struct syscore_ops mce_syscore_ops = { 235721afaf18SBorislav Petkov .suspend = mce_syscore_suspend, 235821afaf18SBorislav Petkov .shutdown = mce_syscore_shutdown, 235921afaf18SBorislav Petkov .resume = mce_syscore_resume, 236021afaf18SBorislav Petkov }; 236121afaf18SBorislav Petkov 236221afaf18SBorislav Petkov /* 236321afaf18SBorislav Petkov * mce_device: Sysfs support 236421afaf18SBorislav Petkov */ 236521afaf18SBorislav Petkov 236621afaf18SBorislav Petkov static void mce_cpu_restart(void *data) 236721afaf18SBorislav Petkov { 236821afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 236921afaf18SBorislav Petkov return; 237021afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 237121afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 237221afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 237321afaf18SBorislav Petkov } 237421afaf18SBorislav Petkov 237521afaf18SBorislav Petkov /* Reinit MCEs after user configuration changes */ 237621afaf18SBorislav Petkov static void mce_restart(void) 237721afaf18SBorislav Petkov { 237821afaf18SBorislav Petkov mce_timer_delete_all(); 237921afaf18SBorislav Petkov on_each_cpu(mce_cpu_restart, NULL, 1); 238021afaf18SBorislav Petkov } 238121afaf18SBorislav Petkov 238221afaf18SBorislav Petkov /* Toggle features for corrected errors */ 238321afaf18SBorislav Petkov static void mce_disable_cmci(void *data) 238421afaf18SBorislav Petkov { 238521afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 238621afaf18SBorislav Petkov return; 238721afaf18SBorislav Petkov cmci_clear(); 238821afaf18SBorislav Petkov } 238921afaf18SBorislav Petkov 239021afaf18SBorislav Petkov static void mce_enable_ce(void *all) 239121afaf18SBorislav Petkov { 239221afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 239321afaf18SBorislav Petkov return; 239421afaf18SBorislav Petkov cmci_reenable(); 239521afaf18SBorislav Petkov cmci_recheck(); 239621afaf18SBorislav Petkov if (all) 239721afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 239821afaf18SBorislav Petkov } 239921afaf18SBorislav Petkov 240021afaf18SBorislav Petkov static struct bus_type mce_subsys = { 240121afaf18SBorislav Petkov .name = "machinecheck", 240221afaf18SBorislav Petkov .dev_name = "machinecheck", 240321afaf18SBorislav Petkov }; 240421afaf18SBorislav Petkov 240521afaf18SBorislav Petkov DEFINE_PER_CPU(struct device *, mce_device); 240621afaf18SBorislav Petkov 2407b4914508SYazen Ghannam static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr) 240821afaf18SBorislav Petkov { 2409b4914508SYazen Ghannam return container_of(attr, struct mce_bank_dev, attr); 241021afaf18SBorislav Petkov } 241121afaf18SBorislav Petkov 241221afaf18SBorislav Petkov static ssize_t show_bank(struct device *s, struct device_attribute *attr, 241321afaf18SBorislav Petkov char *buf) 241421afaf18SBorislav Petkov { 2415b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2416b4914508SYazen Ghannam struct mce_bank *b; 2417b4914508SYazen Ghannam 2418c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2419b4914508SYazen Ghannam return -EINVAL; 2420b4914508SYazen Ghannam 2421b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2422b4914508SYazen Ghannam 2423068b053dSYazen Ghannam if (!b->init) 2424068b053dSYazen Ghannam return -ENODEV; 2425068b053dSYazen Ghannam 2426b4914508SYazen Ghannam return sprintf(buf, "%llx\n", b->ctl); 242721afaf18SBorislav Petkov } 242821afaf18SBorislav Petkov 242921afaf18SBorislav Petkov static ssize_t set_bank(struct device *s, struct device_attribute *attr, 243021afaf18SBorislav Petkov const char *buf, size_t size) 243121afaf18SBorislav Petkov { 2432b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2433b4914508SYazen Ghannam struct mce_bank *b; 243421afaf18SBorislav Petkov u64 new; 243521afaf18SBorislav Petkov 243621afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 243721afaf18SBorislav Petkov return -EINVAL; 243821afaf18SBorislav Petkov 2439c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2440b4914508SYazen Ghannam return -EINVAL; 2441b4914508SYazen Ghannam 2442b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2443b4914508SYazen Ghannam 2444068b053dSYazen Ghannam if (!b->init) 2445068b053dSYazen Ghannam return -ENODEV; 2446068b053dSYazen Ghannam 2447b4914508SYazen Ghannam b->ctl = new; 244821afaf18SBorislav Petkov mce_restart(); 244921afaf18SBorislav Petkov 245021afaf18SBorislav Petkov return size; 245121afaf18SBorislav Petkov } 245221afaf18SBorislav Petkov 245321afaf18SBorislav Petkov static ssize_t set_ignore_ce(struct device *s, 245421afaf18SBorislav Petkov struct device_attribute *attr, 245521afaf18SBorislav Petkov const char *buf, size_t size) 245621afaf18SBorislav Petkov { 245721afaf18SBorislav Petkov u64 new; 245821afaf18SBorislav Petkov 245921afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 246021afaf18SBorislav Petkov return -EINVAL; 246121afaf18SBorislav Petkov 246221afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 246321afaf18SBorislav Petkov if (mca_cfg.ignore_ce ^ !!new) { 246421afaf18SBorislav Petkov if (new) { 246521afaf18SBorislav Petkov /* disable ce features */ 246621afaf18SBorislav Petkov mce_timer_delete_all(); 246721afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 246821afaf18SBorislav Petkov mca_cfg.ignore_ce = true; 246921afaf18SBorislav Petkov } else { 247021afaf18SBorislav Petkov /* enable ce features */ 247121afaf18SBorislav Petkov mca_cfg.ignore_ce = false; 247221afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, (void *)1, 1); 247321afaf18SBorislav Petkov } 247421afaf18SBorislav Petkov } 247521afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 247621afaf18SBorislav Petkov 247721afaf18SBorislav Petkov return size; 247821afaf18SBorislav Petkov } 247921afaf18SBorislav Petkov 248021afaf18SBorislav Petkov static ssize_t set_cmci_disabled(struct device *s, 248121afaf18SBorislav Petkov struct device_attribute *attr, 248221afaf18SBorislav Petkov const char *buf, size_t size) 248321afaf18SBorislav Petkov { 248421afaf18SBorislav Petkov u64 new; 248521afaf18SBorislav Petkov 248621afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 248721afaf18SBorislav Petkov return -EINVAL; 248821afaf18SBorislav Petkov 248921afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 249021afaf18SBorislav Petkov if (mca_cfg.cmci_disabled ^ !!new) { 249121afaf18SBorislav Petkov if (new) { 249221afaf18SBorislav Petkov /* disable cmci */ 249321afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 249421afaf18SBorislav Petkov mca_cfg.cmci_disabled = true; 249521afaf18SBorislav Petkov } else { 249621afaf18SBorislav Petkov /* enable cmci */ 249721afaf18SBorislav Petkov mca_cfg.cmci_disabled = false; 249821afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, NULL, 1); 249921afaf18SBorislav Petkov } 250021afaf18SBorislav Petkov } 250121afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 250221afaf18SBorislav Petkov 250321afaf18SBorislav Petkov return size; 250421afaf18SBorislav Petkov } 250521afaf18SBorislav Petkov 250621afaf18SBorislav Petkov static ssize_t store_int_with_restart(struct device *s, 250721afaf18SBorislav Petkov struct device_attribute *attr, 250821afaf18SBorislav Petkov const char *buf, size_t size) 250921afaf18SBorislav Petkov { 251021afaf18SBorislav Petkov unsigned long old_check_interval = check_interval; 251121afaf18SBorislav Petkov ssize_t ret = device_store_ulong(s, attr, buf, size); 251221afaf18SBorislav Petkov 251321afaf18SBorislav Petkov if (check_interval == old_check_interval) 251421afaf18SBorislav Petkov return ret; 251521afaf18SBorislav Petkov 251621afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 251721afaf18SBorislav Petkov mce_restart(); 251821afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 251921afaf18SBorislav Petkov 252021afaf18SBorislav Petkov return ret; 252121afaf18SBorislav Petkov } 252221afaf18SBorislav Petkov 252321afaf18SBorislav Petkov static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); 252421afaf18SBorislav Petkov static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); 252521afaf18SBorislav Petkov static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); 252643505646STony Luck static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all); 252721afaf18SBorislav Petkov 252821afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_check_interval = { 252921afaf18SBorislav Petkov __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), 253021afaf18SBorislav Petkov &check_interval 253121afaf18SBorislav Petkov }; 253221afaf18SBorislav Petkov 253321afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_ignore_ce = { 253421afaf18SBorislav Petkov __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), 253521afaf18SBorislav Petkov &mca_cfg.ignore_ce 253621afaf18SBorislav Petkov }; 253721afaf18SBorislav Petkov 253821afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_cmci_disabled = { 253921afaf18SBorislav Petkov __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), 254021afaf18SBorislav Petkov &mca_cfg.cmci_disabled 254121afaf18SBorislav Petkov }; 254221afaf18SBorislav Petkov 254321afaf18SBorislav Petkov static struct device_attribute *mce_device_attrs[] = { 254421afaf18SBorislav Petkov &dev_attr_tolerant.attr, 254521afaf18SBorislav Petkov &dev_attr_check_interval.attr, 254621afaf18SBorislav Petkov #ifdef CONFIG_X86_MCELOG_LEGACY 254721afaf18SBorislav Petkov &dev_attr_trigger, 254821afaf18SBorislav Petkov #endif 254921afaf18SBorislav Petkov &dev_attr_monarch_timeout.attr, 255021afaf18SBorislav Petkov &dev_attr_dont_log_ce.attr, 255143505646STony Luck &dev_attr_print_all.attr, 255221afaf18SBorislav Petkov &dev_attr_ignore_ce.attr, 255321afaf18SBorislav Petkov &dev_attr_cmci_disabled.attr, 255421afaf18SBorislav Petkov NULL 255521afaf18SBorislav Petkov }; 255621afaf18SBorislav Petkov 255721afaf18SBorislav Petkov static cpumask_var_t mce_device_initialized; 255821afaf18SBorislav Petkov 255921afaf18SBorislav Petkov static void mce_device_release(struct device *dev) 256021afaf18SBorislav Petkov { 256121afaf18SBorislav Petkov kfree(dev); 256221afaf18SBorislav Petkov } 256321afaf18SBorislav Petkov 2564b4914508SYazen Ghannam /* Per CPU device init. All of the CPUs still share the same bank device: */ 256521afaf18SBorislav Petkov static int mce_device_create(unsigned int cpu) 256621afaf18SBorislav Petkov { 256721afaf18SBorislav Petkov struct device *dev; 256821afaf18SBorislav Petkov int err; 256921afaf18SBorislav Petkov int i, j; 257021afaf18SBorislav Petkov 257121afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) 257221afaf18SBorislav Petkov return -EIO; 257321afaf18SBorislav Petkov 257421afaf18SBorislav Petkov dev = per_cpu(mce_device, cpu); 257521afaf18SBorislav Petkov if (dev) 257621afaf18SBorislav Petkov return 0; 257721afaf18SBorislav Petkov 257821afaf18SBorislav Petkov dev = kzalloc(sizeof(*dev), GFP_KERNEL); 257921afaf18SBorislav Petkov if (!dev) 258021afaf18SBorislav Petkov return -ENOMEM; 258121afaf18SBorislav Petkov dev->id = cpu; 258221afaf18SBorislav Petkov dev->bus = &mce_subsys; 258321afaf18SBorislav Petkov dev->release = &mce_device_release; 258421afaf18SBorislav Petkov 258521afaf18SBorislav Petkov err = device_register(dev); 258621afaf18SBorislav Petkov if (err) { 258721afaf18SBorislav Petkov put_device(dev); 258821afaf18SBorislav Petkov return err; 258921afaf18SBorislav Petkov } 259021afaf18SBorislav Petkov 259121afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) { 259221afaf18SBorislav Petkov err = device_create_file(dev, mce_device_attrs[i]); 259321afaf18SBorislav Petkov if (err) 259421afaf18SBorislav Petkov goto error; 259521afaf18SBorislav Petkov } 2596c7d314f3SYazen Ghannam for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) { 2597b4914508SYazen Ghannam err = device_create_file(dev, &mce_bank_devs[j].attr); 259821afaf18SBorislav Petkov if (err) 259921afaf18SBorislav Petkov goto error2; 260021afaf18SBorislav Petkov } 260121afaf18SBorislav Petkov cpumask_set_cpu(cpu, mce_device_initialized); 260221afaf18SBorislav Petkov per_cpu(mce_device, cpu) = dev; 260321afaf18SBorislav Petkov 260421afaf18SBorislav Petkov return 0; 260521afaf18SBorislav Petkov error2: 260621afaf18SBorislav Petkov while (--j >= 0) 2607b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[j].attr); 260821afaf18SBorislav Petkov error: 260921afaf18SBorislav Petkov while (--i >= 0) 261021afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 261121afaf18SBorislav Petkov 261221afaf18SBorislav Petkov device_unregister(dev); 261321afaf18SBorislav Petkov 261421afaf18SBorislav Petkov return err; 261521afaf18SBorislav Petkov } 261621afaf18SBorislav Petkov 261721afaf18SBorislav Petkov static void mce_device_remove(unsigned int cpu) 261821afaf18SBorislav Petkov { 261921afaf18SBorislav Petkov struct device *dev = per_cpu(mce_device, cpu); 262021afaf18SBorislav Petkov int i; 262121afaf18SBorislav Petkov 262221afaf18SBorislav Petkov if (!cpumask_test_cpu(cpu, mce_device_initialized)) 262321afaf18SBorislav Petkov return; 262421afaf18SBorislav Petkov 262521afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) 262621afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 262721afaf18SBorislav Petkov 2628c7d314f3SYazen Ghannam for (i = 0; i < per_cpu(mce_num_banks, cpu); i++) 2629b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[i].attr); 263021afaf18SBorislav Petkov 263121afaf18SBorislav Petkov device_unregister(dev); 263221afaf18SBorislav Petkov cpumask_clear_cpu(cpu, mce_device_initialized); 263321afaf18SBorislav Petkov per_cpu(mce_device, cpu) = NULL; 263421afaf18SBorislav Petkov } 263521afaf18SBorislav Petkov 263621afaf18SBorislav Petkov /* Make sure there are no machine checks on offlined CPUs. */ 263721afaf18SBorislav Petkov static void mce_disable_cpu(void) 263821afaf18SBorislav Petkov { 263921afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 264021afaf18SBorislav Petkov return; 264121afaf18SBorislav Petkov 264221afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 264321afaf18SBorislav Petkov cmci_clear(); 264421afaf18SBorislav Petkov 264521afaf18SBorislav Petkov vendor_disable_error_reporting(); 264621afaf18SBorislav Petkov } 264721afaf18SBorislav Petkov 264821afaf18SBorislav Petkov static void mce_reenable_cpu(void) 264921afaf18SBorislav Petkov { 2650b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 265121afaf18SBorislav Petkov int i; 265221afaf18SBorislav Petkov 265321afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 265421afaf18SBorislav Petkov return; 265521afaf18SBorislav Petkov 265621afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 265721afaf18SBorislav Petkov cmci_reenable(); 2658c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 265921afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 266021afaf18SBorislav Petkov 266121afaf18SBorislav Petkov if (b->init) 26628121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); 266321afaf18SBorislav Petkov } 266421afaf18SBorislav Petkov } 266521afaf18SBorislav Petkov 266621afaf18SBorislav Petkov static int mce_cpu_dead(unsigned int cpu) 266721afaf18SBorislav Petkov { 266821afaf18SBorislav Petkov mce_intel_hcpu_update(cpu); 266921afaf18SBorislav Petkov 267021afaf18SBorislav Petkov /* intentionally ignoring frozen here */ 267121afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 267221afaf18SBorislav Petkov cmci_rediscover(); 267321afaf18SBorislav Petkov return 0; 267421afaf18SBorislav Petkov } 267521afaf18SBorislav Petkov 267621afaf18SBorislav Petkov static int mce_cpu_online(unsigned int cpu) 267721afaf18SBorislav Petkov { 267821afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 267921afaf18SBorislav Petkov int ret; 268021afaf18SBorislav Petkov 268121afaf18SBorislav Petkov mce_device_create(cpu); 268221afaf18SBorislav Petkov 268321afaf18SBorislav Petkov ret = mce_threshold_create_device(cpu); 268421afaf18SBorislav Petkov if (ret) { 268521afaf18SBorislav Petkov mce_device_remove(cpu); 268621afaf18SBorislav Petkov return ret; 268721afaf18SBorislav Petkov } 268821afaf18SBorislav Petkov mce_reenable_cpu(); 268921afaf18SBorislav Petkov mce_start_timer(t); 269021afaf18SBorislav Petkov return 0; 269121afaf18SBorislav Petkov } 269221afaf18SBorislav Petkov 269321afaf18SBorislav Petkov static int mce_cpu_pre_down(unsigned int cpu) 269421afaf18SBorislav Petkov { 269521afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 269621afaf18SBorislav Petkov 269721afaf18SBorislav Petkov mce_disable_cpu(); 269821afaf18SBorislav Petkov del_timer_sync(t); 269921afaf18SBorislav Petkov mce_threshold_remove_device(cpu); 270021afaf18SBorislav Petkov mce_device_remove(cpu); 270121afaf18SBorislav Petkov return 0; 270221afaf18SBorislav Petkov } 270321afaf18SBorislav Petkov 270421afaf18SBorislav Petkov static __init void mce_init_banks(void) 270521afaf18SBorislav Petkov { 270621afaf18SBorislav Petkov int i; 270721afaf18SBorislav Petkov 2708b4914508SYazen Ghannam for (i = 0; i < MAX_NR_BANKS; i++) { 2709b4914508SYazen Ghannam struct mce_bank_dev *b = &mce_bank_devs[i]; 271021afaf18SBorislav Petkov struct device_attribute *a = &b->attr; 271121afaf18SBorislav Petkov 2712b4914508SYazen Ghannam b->bank = i; 2713b4914508SYazen Ghannam 271421afaf18SBorislav Petkov sysfs_attr_init(&a->attr); 271521afaf18SBorislav Petkov a->attr.name = b->attrname; 271621afaf18SBorislav Petkov snprintf(b->attrname, ATTR_LEN, "bank%d", i); 271721afaf18SBorislav Petkov 271821afaf18SBorislav Petkov a->attr.mode = 0644; 271921afaf18SBorislav Petkov a->show = show_bank; 272021afaf18SBorislav Petkov a->store = set_bank; 272121afaf18SBorislav Petkov } 272221afaf18SBorislav Petkov } 272321afaf18SBorislav Petkov 27246e7a41c6SThomas Gleixner /* 27256e7a41c6SThomas Gleixner * When running on XEN, this initcall is ordered against the XEN mcelog 27266e7a41c6SThomas Gleixner * initcall: 27276e7a41c6SThomas Gleixner * 27286e7a41c6SThomas Gleixner * device_initcall(xen_late_init_mcelog); 27296e7a41c6SThomas Gleixner * device_initcall_sync(mcheck_init_device); 27306e7a41c6SThomas Gleixner */ 273121afaf18SBorislav Petkov static __init int mcheck_init_device(void) 273221afaf18SBorislav Petkov { 273321afaf18SBorislav Petkov int err; 273421afaf18SBorislav Petkov 273521afaf18SBorislav Petkov /* 273621afaf18SBorislav Petkov * Check if we have a spare virtual bit. This will only become 273721afaf18SBorislav Petkov * a problem if/when we move beyond 5-level page tables. 273821afaf18SBorislav Petkov */ 273921afaf18SBorislav Petkov MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63); 274021afaf18SBorislav Petkov 274121afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) { 274221afaf18SBorislav Petkov err = -EIO; 274321afaf18SBorislav Petkov goto err_out; 274421afaf18SBorislav Petkov } 274521afaf18SBorislav Petkov 274621afaf18SBorislav Petkov if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { 274721afaf18SBorislav Petkov err = -ENOMEM; 274821afaf18SBorislav Petkov goto err_out; 274921afaf18SBorislav Petkov } 275021afaf18SBorislav Petkov 275121afaf18SBorislav Petkov mce_init_banks(); 275221afaf18SBorislav Petkov 275321afaf18SBorislav Petkov err = subsys_system_register(&mce_subsys, NULL); 275421afaf18SBorislav Petkov if (err) 275521afaf18SBorislav Petkov goto err_out_mem; 275621afaf18SBorislav Petkov 275721afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL, 275821afaf18SBorislav Petkov mce_cpu_dead); 275921afaf18SBorislav Petkov if (err) 276021afaf18SBorislav Petkov goto err_out_mem; 276121afaf18SBorislav Petkov 27626e7a41c6SThomas Gleixner /* 27636e7a41c6SThomas Gleixner * Invokes mce_cpu_online() on all CPUs which are online when 27646e7a41c6SThomas Gleixner * the state is installed. 27656e7a41c6SThomas Gleixner */ 276621afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online", 276721afaf18SBorislav Petkov mce_cpu_online, mce_cpu_pre_down); 276821afaf18SBorislav Petkov if (err < 0) 276921afaf18SBorislav Petkov goto err_out_online; 277021afaf18SBorislav Petkov 277121afaf18SBorislav Petkov register_syscore_ops(&mce_syscore_ops); 277221afaf18SBorislav Petkov 277321afaf18SBorislav Petkov return 0; 277421afaf18SBorislav Petkov 277521afaf18SBorislav Petkov err_out_online: 277621afaf18SBorislav Petkov cpuhp_remove_state(CPUHP_X86_MCE_DEAD); 277721afaf18SBorislav Petkov 277821afaf18SBorislav Petkov err_out_mem: 277921afaf18SBorislav Petkov free_cpumask_var(mce_device_initialized); 278021afaf18SBorislav Petkov 278121afaf18SBorislav Petkov err_out: 278221afaf18SBorislav Petkov pr_err("Unable to init MCE device (rc: %d)\n", err); 278321afaf18SBorislav Petkov 278421afaf18SBorislav Petkov return err; 278521afaf18SBorislav Petkov } 278621afaf18SBorislav Petkov device_initcall_sync(mcheck_init_device); 278721afaf18SBorislav Petkov 278821afaf18SBorislav Petkov /* 278921afaf18SBorislav Petkov * Old style boot options parsing. Only for compatibility. 279021afaf18SBorislav Petkov */ 279121afaf18SBorislav Petkov static int __init mcheck_disable(char *str) 279221afaf18SBorislav Petkov { 279321afaf18SBorislav Petkov mca_cfg.disabled = 1; 279421afaf18SBorislav Petkov return 1; 279521afaf18SBorislav Petkov } 279621afaf18SBorislav Petkov __setup("nomce", mcheck_disable); 279721afaf18SBorislav Petkov 279821afaf18SBorislav Petkov #ifdef CONFIG_DEBUG_FS 279921afaf18SBorislav Petkov struct dentry *mce_get_debugfs_dir(void) 280021afaf18SBorislav Petkov { 280121afaf18SBorislav Petkov static struct dentry *dmce; 280221afaf18SBorislav Petkov 280321afaf18SBorislav Petkov if (!dmce) 280421afaf18SBorislav Petkov dmce = debugfs_create_dir("mce", NULL); 280521afaf18SBorislav Petkov 280621afaf18SBorislav Petkov return dmce; 280721afaf18SBorislav Petkov } 280821afaf18SBorislav Petkov 280921afaf18SBorislav Petkov static void mce_reset(void) 281021afaf18SBorislav Petkov { 281121afaf18SBorislav Petkov atomic_set(&mce_fake_panicked, 0); 281221afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 281321afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 281421afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 28157bb39313SPaul E. McKenney cpumask_setall(&mce_missing_cpus); 281621afaf18SBorislav Petkov } 281721afaf18SBorislav Petkov 281821afaf18SBorislav Petkov static int fake_panic_get(void *data, u64 *val) 281921afaf18SBorislav Petkov { 282021afaf18SBorislav Petkov *val = fake_panic; 282121afaf18SBorislav Petkov return 0; 282221afaf18SBorislav Petkov } 282321afaf18SBorislav Petkov 282421afaf18SBorislav Petkov static int fake_panic_set(void *data, u64 val) 282521afaf18SBorislav Petkov { 282621afaf18SBorislav Petkov mce_reset(); 282721afaf18SBorislav Petkov fake_panic = val; 282821afaf18SBorislav Petkov return 0; 282921afaf18SBorislav Petkov } 283021afaf18SBorislav Petkov 283128156d76SYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set, 283228156d76SYueHaibing "%llu\n"); 283321afaf18SBorislav Petkov 28346e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) 283521afaf18SBorislav Petkov { 28366e4f929eSGreg Kroah-Hartman struct dentry *dmce; 283721afaf18SBorislav Petkov 283821afaf18SBorislav Petkov dmce = mce_get_debugfs_dir(); 28396e4f929eSGreg Kroah-Hartman debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL, 28406e4f929eSGreg Kroah-Hartman &fake_panic_fops); 284121afaf18SBorislav Petkov } 284221afaf18SBorislav Petkov #else 28436e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) { } 284421afaf18SBorislav Petkov #endif 284521afaf18SBorislav Petkov 284621afaf18SBorislav Petkov static int __init mcheck_late_init(void) 284721afaf18SBorislav Petkov { 284821afaf18SBorislav Petkov if (mca_cfg.recovery) 2849ec6347bbSDan Williams enable_copy_mc_fragile(); 285021afaf18SBorislav Petkov 285121afaf18SBorislav Petkov mcheck_debugfs_init(); 285221afaf18SBorislav Petkov 285321afaf18SBorislav Petkov /* 285421afaf18SBorislav Petkov * Flush out everything that has been logged during early boot, now that 285521afaf18SBorislav Petkov * everything has been initialized (workqueues, decoders, ...). 285621afaf18SBorislav Petkov */ 285721afaf18SBorislav Petkov mce_schedule_work(); 285821afaf18SBorislav Petkov 285921afaf18SBorislav Petkov return 0; 286021afaf18SBorislav Petkov } 286121afaf18SBorislav Petkov late_initcall(mcheck_late_init); 2862