1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 221afaf18SBorislav Petkov /* 321afaf18SBorislav Petkov * Machine check handler. 421afaf18SBorislav Petkov * 521afaf18SBorislav Petkov * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. 621afaf18SBorislav Petkov * Rest from unknown author(s). 721afaf18SBorislav Petkov * 2004 Andi Kleen. Rewrote most of it. 821afaf18SBorislav Petkov * Copyright 2008 Intel Corporation 921afaf18SBorislav Petkov * Author: Andi Kleen 1021afaf18SBorislav Petkov */ 1121afaf18SBorislav Petkov 1221afaf18SBorislav Petkov #include <linux/thread_info.h> 1321afaf18SBorislav Petkov #include <linux/capability.h> 1421afaf18SBorislav Petkov #include <linux/miscdevice.h> 1521afaf18SBorislav Petkov #include <linux/ratelimit.h> 1621afaf18SBorislav Petkov #include <linux/rcupdate.h> 1721afaf18SBorislav Petkov #include <linux/kobject.h> 1821afaf18SBorislav Petkov #include <linux/uaccess.h> 1921afaf18SBorislav Petkov #include <linux/kdebug.h> 2021afaf18SBorislav Petkov #include <linux/kernel.h> 2121afaf18SBorislav Petkov #include <linux/percpu.h> 2221afaf18SBorislav Petkov #include <linux/string.h> 2321afaf18SBorislav Petkov #include <linux/device.h> 2421afaf18SBorislav Petkov #include <linux/syscore_ops.h> 2521afaf18SBorislav Petkov #include <linux/delay.h> 2621afaf18SBorislav Petkov #include <linux/ctype.h> 2721afaf18SBorislav Petkov #include <linux/sched.h> 2821afaf18SBorislav Petkov #include <linux/sysfs.h> 2921afaf18SBorislav Petkov #include <linux/types.h> 3021afaf18SBorislav Petkov #include <linux/slab.h> 3121afaf18SBorislav Petkov #include <linux/init.h> 3221afaf18SBorislav Petkov #include <linux/kmod.h> 3321afaf18SBorislav Petkov #include <linux/poll.h> 3421afaf18SBorislav Petkov #include <linux/nmi.h> 3521afaf18SBorislav Petkov #include <linux/cpu.h> 3621afaf18SBorislav Petkov #include <linux/ras.h> 3721afaf18SBorislav Petkov #include <linux/smp.h> 3821afaf18SBorislav Petkov #include <linux/fs.h> 3921afaf18SBorislav Petkov #include <linux/mm.h> 4021afaf18SBorislav Petkov #include <linux/debugfs.h> 4121afaf18SBorislav Petkov #include <linux/irq_work.h> 4221afaf18SBorislav Petkov #include <linux/export.h> 4321afaf18SBorislav Petkov #include <linux/set_memory.h> 449998a983SRicardo Neri #include <linux/sync_core.h> 455567d11cSPeter Zijlstra #include <linux/task_work.h> 460d00449cSPeter Zijlstra #include <linux/hardirq.h> 4721afaf18SBorislav Petkov 4821afaf18SBorislav Petkov #include <asm/intel-family.h> 4921afaf18SBorislav Petkov #include <asm/processor.h> 5021afaf18SBorislav Petkov #include <asm/traps.h> 5121afaf18SBorislav Petkov #include <asm/tlbflush.h> 5221afaf18SBorislav Petkov #include <asm/mce.h> 5321afaf18SBorislav Petkov #include <asm/msr.h> 5421afaf18SBorislav Petkov #include <asm/reboot.h> 5521afaf18SBorislav Petkov 5621afaf18SBorislav Petkov #include "internal.h" 5721afaf18SBorislav Petkov 5821afaf18SBorislav Petkov /* sysfs synchronization */ 5921afaf18SBorislav Petkov static DEFINE_MUTEX(mce_sysfs_mutex); 6021afaf18SBorislav Petkov 6121afaf18SBorislav Petkov #define CREATE_TRACE_POINTS 6221afaf18SBorislav Petkov #include <trace/events/mce.h> 6321afaf18SBorislav Petkov 6421afaf18SBorislav Petkov #define SPINUNIT 100 /* 100ns */ 6521afaf18SBorislav Petkov 6621afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_exception_count); 6721afaf18SBorislav Petkov 68c7d314f3SYazen Ghannam DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks); 69c7d314f3SYazen Ghannam 7095fdce6bSYazen Ghannam struct mce_bank { 7195fdce6bSYazen Ghannam u64 ctl; /* subevents to enable */ 7295fdce6bSYazen Ghannam bool init; /* initialise bank? */ 73b4914508SYazen Ghannam }; 74b4914508SYazen Ghannam static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); 75b4914508SYazen Ghannam 76b4914508SYazen Ghannam #define ATTR_LEN 16 77b4914508SYazen Ghannam /* One object for each MCE bank, shared by all CPUs */ 78b4914508SYazen Ghannam struct mce_bank_dev { 7995fdce6bSYazen Ghannam struct device_attribute attr; /* device attribute */ 8095fdce6bSYazen Ghannam char attrname[ATTR_LEN]; /* attribute name */ 81b4914508SYazen Ghannam u8 bank; /* bank number */ 8295fdce6bSYazen Ghannam }; 83b4914508SYazen Ghannam static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS]; 8495fdce6bSYazen Ghannam 8521afaf18SBorislav Petkov struct mce_vendor_flags mce_flags __read_mostly; 8621afaf18SBorislav Petkov 8721afaf18SBorislav Petkov struct mca_config mca_cfg __read_mostly = { 8821afaf18SBorislav Petkov .bootlog = -1, 8921afaf18SBorislav Petkov /* 9021afaf18SBorislav Petkov * Tolerant levels: 9121afaf18SBorislav Petkov * 0: always panic on uncorrected errors, log corrected errors 9221afaf18SBorislav Petkov * 1: panic or SIGBUS on uncorrected errors, log corrected errors 9321afaf18SBorislav Petkov * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors 9421afaf18SBorislav Petkov * 3: never panic or SIGBUS, log all errors (for testing only) 9521afaf18SBorislav Petkov */ 9621afaf18SBorislav Petkov .tolerant = 1, 9721afaf18SBorislav Petkov .monarch_timeout = -1 9821afaf18SBorislav Petkov }; 9921afaf18SBorislav Petkov 10021afaf18SBorislav Petkov static DEFINE_PER_CPU(struct mce, mces_seen); 10121afaf18SBorislav Petkov static unsigned long mce_need_notify; 10221afaf18SBorislav Petkov static int cpu_missing; 10321afaf18SBorislav Petkov 10421afaf18SBorislav Petkov /* 10521afaf18SBorislav Petkov * MCA banks polled by the period polling timer for corrected events. 10621afaf18SBorislav Petkov * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). 10721afaf18SBorislav Petkov */ 10821afaf18SBorislav Petkov DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { 10921afaf18SBorislav Petkov [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL 11021afaf18SBorislav Petkov }; 11121afaf18SBorislav Petkov 11221afaf18SBorislav Petkov /* 11321afaf18SBorislav Petkov * MCA banks controlled through firmware first for corrected errors. 11421afaf18SBorislav Petkov * This is a global list of banks for which we won't enable CMCI and we 11521afaf18SBorislav Petkov * won't poll. Firmware controls these banks and is responsible for 11621afaf18SBorislav Petkov * reporting corrected errors through GHES. Uncorrected/recoverable 11721afaf18SBorislav Petkov * errors are still notified through a machine check. 11821afaf18SBorislav Petkov */ 11921afaf18SBorislav Petkov mce_banks_t mce_banks_ce_disabled; 12021afaf18SBorislav Petkov 12121afaf18SBorislav Petkov static struct work_struct mce_work; 12221afaf18SBorislav Petkov static struct irq_work mce_irq_work; 12321afaf18SBorislav Petkov 12421afaf18SBorislav Petkov static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); 12521afaf18SBorislav Petkov 12621afaf18SBorislav Petkov /* 12721afaf18SBorislav Petkov * CPU/chipset specific EDAC code can register a notifier call here to print 12821afaf18SBorislav Petkov * MCE errors in a human-readable form. 12921afaf18SBorislav Petkov */ 13021afaf18SBorislav Petkov BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); 13121afaf18SBorislav Petkov 13221afaf18SBorislav Petkov /* Do initial initialization of a struct mce */ 133865d3a9aSThomas Gleixner noinstr void mce_setup(struct mce *m) 13421afaf18SBorislav Petkov { 13521afaf18SBorislav Petkov memset(m, 0, sizeof(struct mce)); 13621afaf18SBorislav Petkov m->cpu = m->extcpu = smp_processor_id(); 13721afaf18SBorislav Petkov /* need the internal __ version to avoid deadlocks */ 13821afaf18SBorislav Petkov m->time = __ktime_get_real_seconds(); 13921afaf18SBorislav Petkov m->cpuvendor = boot_cpu_data.x86_vendor; 14021afaf18SBorislav Petkov m->cpuid = cpuid_eax(1); 14121afaf18SBorislav Petkov m->socketid = cpu_data(m->extcpu).phys_proc_id; 14221afaf18SBorislav Petkov m->apicid = cpu_data(m->extcpu).initial_apicid; 143865d3a9aSThomas Gleixner m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); 14421afaf18SBorislav Petkov 14521afaf18SBorislav Petkov if (this_cpu_has(X86_FEATURE_INTEL_PPIN)) 146865d3a9aSThomas Gleixner m->ppin = __rdmsr(MSR_PPIN); 147077168e2SWei Huang else if (this_cpu_has(X86_FEATURE_AMD_PPIN)) 148865d3a9aSThomas Gleixner m->ppin = __rdmsr(MSR_AMD_PPIN); 14921afaf18SBorislav Petkov 15021afaf18SBorislav Petkov m->microcode = boot_cpu_data.microcode; 15121afaf18SBorislav Petkov } 15221afaf18SBorislav Petkov 15321afaf18SBorislav Petkov DEFINE_PER_CPU(struct mce, injectm); 15421afaf18SBorislav Petkov EXPORT_PER_CPU_SYMBOL_GPL(injectm); 15521afaf18SBorislav Petkov 15621afaf18SBorislav Petkov void mce_log(struct mce *m) 15721afaf18SBorislav Petkov { 15821afaf18SBorislav Petkov if (!mce_gen_pool_add(m)) 15921afaf18SBorislav Petkov irq_work_queue(&mce_irq_work); 16021afaf18SBorislav Petkov } 16181736abdSJan H. Schönherr EXPORT_SYMBOL_GPL(mce_log); 16221afaf18SBorislav Petkov 16321afaf18SBorislav Petkov void mce_register_decode_chain(struct notifier_block *nb) 16421afaf18SBorislav Petkov { 16515af3659SZhen Lei if (WARN_ON(nb->priority < MCE_PRIO_LOWEST || 16615af3659SZhen Lei nb->priority > MCE_PRIO_HIGHEST)) 16721afaf18SBorislav Petkov return; 16821afaf18SBorislav Petkov 16921afaf18SBorislav Petkov blocking_notifier_chain_register(&x86_mce_decoder_chain, nb); 17021afaf18SBorislav Petkov } 17121afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_register_decode_chain); 17221afaf18SBorislav Petkov 17321afaf18SBorislav Petkov void mce_unregister_decode_chain(struct notifier_block *nb) 17421afaf18SBorislav Petkov { 17521afaf18SBorislav Petkov blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb); 17621afaf18SBorislav Petkov } 17721afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); 17821afaf18SBorislav Petkov 179*8121b8f9SBorislav Petkov u32 mca_msr_reg(int bank, enum mca_msr reg) 18021afaf18SBorislav Petkov { 181*8121b8f9SBorislav Petkov if (mce_flags.smca) { 182*8121b8f9SBorislav Petkov switch (reg) { 183*8121b8f9SBorislav Petkov case MCA_CTL: return MSR_AMD64_SMCA_MCx_CTL(bank); 184*8121b8f9SBorislav Petkov case MCA_ADDR: return MSR_AMD64_SMCA_MCx_ADDR(bank); 185*8121b8f9SBorislav Petkov case MCA_MISC: return MSR_AMD64_SMCA_MCx_MISC(bank); 186*8121b8f9SBorislav Petkov case MCA_STATUS: return MSR_AMD64_SMCA_MCx_STATUS(bank); 187*8121b8f9SBorislav Petkov } 18821afaf18SBorislav Petkov } 18921afaf18SBorislav Petkov 190*8121b8f9SBorislav Petkov switch (reg) { 191*8121b8f9SBorislav Petkov case MCA_CTL: return MSR_IA32_MCx_CTL(bank); 192*8121b8f9SBorislav Petkov case MCA_ADDR: return MSR_IA32_MCx_ADDR(bank); 193*8121b8f9SBorislav Petkov case MCA_MISC: return MSR_IA32_MCx_MISC(bank); 194*8121b8f9SBorislav Petkov case MCA_STATUS: return MSR_IA32_MCx_STATUS(bank); 19521afaf18SBorislav Petkov } 19621afaf18SBorislav Petkov 197*8121b8f9SBorislav Petkov return 0; 19821afaf18SBorislav Petkov } 19921afaf18SBorislav Petkov 20021afaf18SBorislav Petkov static void __print_mce(struct mce *m) 20121afaf18SBorislav Petkov { 20221afaf18SBorislav Petkov pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", 20321afaf18SBorislav Petkov m->extcpu, 20421afaf18SBorislav Petkov (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""), 20521afaf18SBorislav Petkov m->mcgstatus, m->bank, m->status); 20621afaf18SBorislav Petkov 20721afaf18SBorislav Petkov if (m->ip) { 20821afaf18SBorislav Petkov pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", 20921afaf18SBorislav Petkov !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", 21021afaf18SBorislav Petkov m->cs, m->ip); 21121afaf18SBorislav Petkov 21221afaf18SBorislav Petkov if (m->cs == __KERNEL_CS) 21321afaf18SBorislav Petkov pr_cont("{%pS}", (void *)(unsigned long)m->ip); 21421afaf18SBorislav Petkov pr_cont("\n"); 21521afaf18SBorislav Petkov } 21621afaf18SBorislav Petkov 21721afaf18SBorislav Petkov pr_emerg(HW_ERR "TSC %llx ", m->tsc); 21821afaf18SBorislav Petkov if (m->addr) 21921afaf18SBorislav Petkov pr_cont("ADDR %llx ", m->addr); 22021afaf18SBorislav Petkov if (m->misc) 22121afaf18SBorislav Petkov pr_cont("MISC %llx ", m->misc); 222bb2de0adSSmita Koralahalli if (m->ppin) 223bb2de0adSSmita Koralahalli pr_cont("PPIN %llx ", m->ppin); 22421afaf18SBorislav Petkov 22521afaf18SBorislav Petkov if (mce_flags.smca) { 22621afaf18SBorislav Petkov if (m->synd) 22721afaf18SBorislav Petkov pr_cont("SYND %llx ", m->synd); 22821afaf18SBorislav Petkov if (m->ipid) 22921afaf18SBorislav Petkov pr_cont("IPID %llx ", m->ipid); 23021afaf18SBorislav Petkov } 23121afaf18SBorislav Petkov 23221afaf18SBorislav Petkov pr_cont("\n"); 233925946cfSTony Luck 23421afaf18SBorislav Petkov /* 23521afaf18SBorislav Petkov * Note this output is parsed by external tools and old fields 23621afaf18SBorislav Petkov * should not be changed. 23721afaf18SBorislav Petkov */ 23821afaf18SBorislav Petkov pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", 23921afaf18SBorislav Petkov m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, 24021afaf18SBorislav Petkov m->microcode); 24121afaf18SBorislav Petkov } 24221afaf18SBorislav Petkov 24321afaf18SBorislav Petkov static void print_mce(struct mce *m) 24421afaf18SBorislav Petkov { 24521afaf18SBorislav Petkov __print_mce(m); 24621afaf18SBorislav Petkov 24721afaf18SBorislav Petkov if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON) 24821afaf18SBorislav Petkov pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); 24921afaf18SBorislav Petkov } 25021afaf18SBorislav Petkov 25121afaf18SBorislav Petkov #define PANIC_TIMEOUT 5 /* 5 seconds */ 25221afaf18SBorislav Petkov 25321afaf18SBorislav Petkov static atomic_t mce_panicked; 25421afaf18SBorislav Petkov 25521afaf18SBorislav Petkov static int fake_panic; 25621afaf18SBorislav Petkov static atomic_t mce_fake_panicked; 25721afaf18SBorislav Petkov 25821afaf18SBorislav Petkov /* Panic in progress. Enable interrupts and wait for final IPI */ 25921afaf18SBorislav Petkov static void wait_for_panic(void) 26021afaf18SBorislav Petkov { 26121afaf18SBorislav Petkov long timeout = PANIC_TIMEOUT*USEC_PER_SEC; 26221afaf18SBorislav Petkov 26321afaf18SBorislav Petkov preempt_disable(); 26421afaf18SBorislav Petkov local_irq_enable(); 26521afaf18SBorislav Petkov while (timeout-- > 0) 26621afaf18SBorislav Petkov udelay(1); 26721afaf18SBorislav Petkov if (panic_timeout == 0) 26821afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 26921afaf18SBorislav Petkov panic("Panicing machine check CPU died"); 27021afaf18SBorislav Petkov } 27121afaf18SBorislav Petkov 27221afaf18SBorislav Petkov static void mce_panic(const char *msg, struct mce *final, char *exp) 27321afaf18SBorislav Petkov { 27421afaf18SBorislav Petkov int apei_err = 0; 27521afaf18SBorislav Petkov struct llist_node *pending; 27621afaf18SBorislav Petkov struct mce_evt_llist *l; 27721afaf18SBorislav Petkov 27821afaf18SBorislav Petkov if (!fake_panic) { 27921afaf18SBorislav Petkov /* 28021afaf18SBorislav Petkov * Make sure only one CPU runs in machine check panic 28121afaf18SBorislav Petkov */ 28221afaf18SBorislav Petkov if (atomic_inc_return(&mce_panicked) > 1) 28321afaf18SBorislav Petkov wait_for_panic(); 28421afaf18SBorislav Petkov barrier(); 28521afaf18SBorislav Petkov 28621afaf18SBorislav Petkov bust_spinlocks(1); 28721afaf18SBorislav Petkov console_verbose(); 28821afaf18SBorislav Petkov } else { 28921afaf18SBorislav Petkov /* Don't log too much for fake panic */ 29021afaf18SBorislav Petkov if (atomic_inc_return(&mce_fake_panicked) > 1) 29121afaf18SBorislav Petkov return; 29221afaf18SBorislav Petkov } 29321afaf18SBorislav Petkov pending = mce_gen_pool_prepare_records(); 29421afaf18SBorislav Petkov /* First print corrected ones that are still unlogged */ 29521afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 29621afaf18SBorislav Petkov struct mce *m = &l->mce; 29721afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) { 29821afaf18SBorislav Petkov print_mce(m); 29921afaf18SBorislav Petkov if (!apei_err) 30021afaf18SBorislav Petkov apei_err = apei_write_mce(m); 30121afaf18SBorislav Petkov } 30221afaf18SBorislav Petkov } 30321afaf18SBorislav Petkov /* Now print uncorrected but with the final one last */ 30421afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 30521afaf18SBorislav Petkov struct mce *m = &l->mce; 30621afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) 30721afaf18SBorislav Petkov continue; 30821afaf18SBorislav Petkov if (!final || mce_cmp(m, final)) { 30921afaf18SBorislav Petkov print_mce(m); 31021afaf18SBorislav Petkov if (!apei_err) 31121afaf18SBorislav Petkov apei_err = apei_write_mce(m); 31221afaf18SBorislav Petkov } 31321afaf18SBorislav Petkov } 31421afaf18SBorislav Petkov if (final) { 31521afaf18SBorislav Petkov print_mce(final); 31621afaf18SBorislav Petkov if (!apei_err) 31721afaf18SBorislav Petkov apei_err = apei_write_mce(final); 31821afaf18SBorislav Petkov } 31921afaf18SBorislav Petkov if (cpu_missing) 32021afaf18SBorislav Petkov pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); 32121afaf18SBorislav Petkov if (exp) 32221afaf18SBorislav Petkov pr_emerg(HW_ERR "Machine check: %s\n", exp); 32321afaf18SBorislav Petkov if (!fake_panic) { 32421afaf18SBorislav Petkov if (panic_timeout == 0) 32521afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 32621afaf18SBorislav Petkov panic(msg); 32721afaf18SBorislav Petkov } else 32821afaf18SBorislav Petkov pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); 32921afaf18SBorislav Petkov } 33021afaf18SBorislav Petkov 33121afaf18SBorislav Petkov /* Support code for software error injection */ 33221afaf18SBorislav Petkov 33321afaf18SBorislav Petkov static int msr_to_offset(u32 msr) 33421afaf18SBorislav Petkov { 33521afaf18SBorislav Petkov unsigned bank = __this_cpu_read(injectm.bank); 33621afaf18SBorislav Petkov 33721afaf18SBorislav Petkov if (msr == mca_cfg.rip_msr) 33821afaf18SBorislav Petkov return offsetof(struct mce, ip); 339*8121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_STATUS)) 34021afaf18SBorislav Petkov return offsetof(struct mce, status); 341*8121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_ADDR)) 34221afaf18SBorislav Petkov return offsetof(struct mce, addr); 343*8121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_MISC)) 34421afaf18SBorislav Petkov return offsetof(struct mce, misc); 34521afaf18SBorislav Petkov if (msr == MSR_IA32_MCG_STATUS) 34621afaf18SBorislav Petkov return offsetof(struct mce, mcgstatus); 34721afaf18SBorislav Petkov return -1; 34821afaf18SBorislav Petkov } 34921afaf18SBorislav Petkov 350e2def7d4SBorislav Petkov __visible bool ex_handler_rdmsr_fault(const struct exception_table_entry *fixup, 351e2def7d4SBorislav Petkov struct pt_regs *regs, int trapnr, 352e2def7d4SBorislav Petkov unsigned long error_code, 353e2def7d4SBorislav Petkov unsigned long fault_addr) 354e2def7d4SBorislav Petkov { 355e2def7d4SBorislav Petkov pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n", 356e2def7d4SBorislav Petkov (unsigned int)regs->cx, regs->ip, (void *)regs->ip); 357e2def7d4SBorislav Petkov 358e2def7d4SBorislav Petkov show_stack_regs(regs); 359e2def7d4SBorislav Petkov 360e2def7d4SBorislav Petkov panic("MCA architectural violation!\n"); 361e2def7d4SBorislav Petkov 362e2def7d4SBorislav Petkov while (true) 363e2def7d4SBorislav Petkov cpu_relax(); 364e2def7d4SBorislav Petkov 365e2def7d4SBorislav Petkov return true; 366e2def7d4SBorislav Petkov } 367e2def7d4SBorislav Petkov 36821afaf18SBorislav Petkov /* MSR access wrappers used for error injection */ 369e1007770SBorislav Petkov static noinstr u64 mce_rdmsrl(u32 msr) 37021afaf18SBorislav Petkov { 371e2def7d4SBorislav Petkov DECLARE_ARGS(val, low, high); 37221afaf18SBorislav Petkov 37321afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 374e1007770SBorislav Petkov int offset; 375e1007770SBorislav Petkov u64 ret; 37621afaf18SBorislav Petkov 377e1007770SBorislav Petkov instrumentation_begin(); 378e1007770SBorislav Petkov 379e1007770SBorislav Petkov offset = msr_to_offset(msr); 38021afaf18SBorislav Petkov if (offset < 0) 381e1007770SBorislav Petkov ret = 0; 382e1007770SBorislav Petkov else 383e1007770SBorislav Petkov ret = *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); 384e1007770SBorislav Petkov 385e1007770SBorislav Petkov instrumentation_end(); 386e1007770SBorislav Petkov 387e1007770SBorislav Petkov return ret; 38821afaf18SBorislav Petkov } 38921afaf18SBorislav Petkov 39021afaf18SBorislav Petkov /* 391e2def7d4SBorislav Petkov * RDMSR on MCA MSRs should not fault. If they do, this is very much an 392e2def7d4SBorislav Petkov * architectural violation and needs to be reported to hw vendor. Panic 393e2def7d4SBorislav Petkov * the box to not allow any further progress. 39421afaf18SBorislav Petkov */ 395e2def7d4SBorislav Petkov asm volatile("1: rdmsr\n" 396e2def7d4SBorislav Petkov "2:\n" 397e2def7d4SBorislav Petkov _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_rdmsr_fault) 398e2def7d4SBorislav Petkov : EAX_EDX_RET(val, low, high) : "c" (msr)); 399e2def7d4SBorislav Petkov 400e2def7d4SBorislav Petkov 401e2def7d4SBorislav Petkov return EAX_EDX_VAL(val, low, high); 40221afaf18SBorislav Petkov } 40321afaf18SBorislav Petkov 404e2def7d4SBorislav Petkov __visible bool ex_handler_wrmsr_fault(const struct exception_table_entry *fixup, 405e2def7d4SBorislav Petkov struct pt_regs *regs, int trapnr, 406e2def7d4SBorislav Petkov unsigned long error_code, 407e2def7d4SBorislav Petkov unsigned long fault_addr) 40821afaf18SBorislav Petkov { 409e2def7d4SBorislav Petkov pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n", 410e2def7d4SBorislav Petkov (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax, 411e2def7d4SBorislav Petkov regs->ip, (void *)regs->ip); 41221afaf18SBorislav Petkov 413e2def7d4SBorislav Petkov show_stack_regs(regs); 414e2def7d4SBorislav Petkov 415e2def7d4SBorislav Petkov panic("MCA architectural violation!\n"); 416e2def7d4SBorislav Petkov 417e2def7d4SBorislav Petkov while (true) 418e2def7d4SBorislav Petkov cpu_relax(); 419e2def7d4SBorislav Petkov 420e2def7d4SBorislav Petkov return true; 42121afaf18SBorislav Petkov } 42221afaf18SBorislav Petkov 423e1007770SBorislav Petkov static noinstr void mce_wrmsrl(u32 msr, u64 v) 42421afaf18SBorislav Petkov { 425e2def7d4SBorislav Petkov u32 low, high; 426e2def7d4SBorislav Petkov 42721afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 428e1007770SBorislav Petkov int offset; 42921afaf18SBorislav Petkov 430e1007770SBorislav Petkov instrumentation_begin(); 431e1007770SBorislav Petkov 432e1007770SBorislav Petkov offset = msr_to_offset(msr); 43321afaf18SBorislav Petkov if (offset >= 0) 43421afaf18SBorislav Petkov *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; 435e1007770SBorislav Petkov 436e1007770SBorislav Petkov instrumentation_end(); 437e1007770SBorislav Petkov 43821afaf18SBorislav Petkov return; 43921afaf18SBorislav Petkov } 440e2def7d4SBorislav Petkov 441e2def7d4SBorislav Petkov low = (u32)v; 442e2def7d4SBorislav Petkov high = (u32)(v >> 32); 443e2def7d4SBorislav Petkov 444e2def7d4SBorislav Petkov /* See comment in mce_rdmsrl() */ 445e2def7d4SBorislav Petkov asm volatile("1: wrmsr\n" 446e2def7d4SBorislav Petkov "2:\n" 447e2def7d4SBorislav Petkov _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wrmsr_fault) 448e2def7d4SBorislav Petkov : : "c" (msr), "a"(low), "d" (high) : "memory"); 44921afaf18SBorislav Petkov } 45021afaf18SBorislav Petkov 45121afaf18SBorislav Petkov /* 45221afaf18SBorislav Petkov * Collect all global (w.r.t. this processor) status about this machine 45321afaf18SBorislav Petkov * check into our "mce" struct so that we can use it later to assess 45421afaf18SBorislav Petkov * the severity of the problem as we read per-bank specific details. 45521afaf18SBorislav Petkov */ 45621afaf18SBorislav Petkov static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) 45721afaf18SBorislav Petkov { 45821afaf18SBorislav Petkov mce_setup(m); 45921afaf18SBorislav Petkov 46021afaf18SBorislav Petkov m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 46121afaf18SBorislav Petkov if (regs) { 46221afaf18SBorislav Petkov /* 46321afaf18SBorislav Petkov * Get the address of the instruction at the time of 46421afaf18SBorislav Petkov * the machine check error. 46521afaf18SBorislav Petkov */ 46621afaf18SBorislav Petkov if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { 46721afaf18SBorislav Petkov m->ip = regs->ip; 46821afaf18SBorislav Petkov m->cs = regs->cs; 46921afaf18SBorislav Petkov 47021afaf18SBorislav Petkov /* 47121afaf18SBorislav Petkov * When in VM86 mode make the cs look like ring 3 47221afaf18SBorislav Petkov * always. This is a lie, but it's better than passing 47321afaf18SBorislav Petkov * the additional vm86 bit around everywhere. 47421afaf18SBorislav Petkov */ 47521afaf18SBorislav Petkov if (v8086_mode(regs)) 47621afaf18SBorislav Petkov m->cs |= 3; 47721afaf18SBorislav Petkov } 47821afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 47921afaf18SBorislav Petkov if (mca_cfg.rip_msr) 48021afaf18SBorislav Petkov m->ip = mce_rdmsrl(mca_cfg.rip_msr); 48121afaf18SBorislav Petkov } 48221afaf18SBorislav Petkov } 48321afaf18SBorislav Petkov 48421afaf18SBorislav Petkov int mce_available(struct cpuinfo_x86 *c) 48521afaf18SBorislav Petkov { 48621afaf18SBorislav Petkov if (mca_cfg.disabled) 48721afaf18SBorislav Petkov return 0; 48821afaf18SBorislav Petkov return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); 48921afaf18SBorislav Petkov } 49021afaf18SBorislav Petkov 49121afaf18SBorislav Petkov static void mce_schedule_work(void) 49221afaf18SBorislav Petkov { 49321afaf18SBorislav Petkov if (!mce_gen_pool_empty()) 49421afaf18SBorislav Petkov schedule_work(&mce_work); 49521afaf18SBorislav Petkov } 49621afaf18SBorislav Petkov 49721afaf18SBorislav Petkov static void mce_irq_work_cb(struct irq_work *entry) 49821afaf18SBorislav Petkov { 49921afaf18SBorislav Petkov mce_schedule_work(); 50021afaf18SBorislav Petkov } 50121afaf18SBorislav Petkov 50221afaf18SBorislav Petkov /* 50321afaf18SBorislav Petkov * Check if the address reported by the CPU is in a format we can parse. 50421afaf18SBorislav Petkov * It would be possible to add code for most other cases, but all would 50521afaf18SBorislav Petkov * be somewhat complicated (e.g. segment offset would require an instruction 506d9f6e12fSIngo Molnar * parser). So only support physical addresses up to page granularity for now. 50721afaf18SBorislav Petkov */ 50821afaf18SBorislav Petkov int mce_usable_address(struct mce *m) 50921afaf18SBorislav Petkov { 51021afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_ADDRV)) 51121afaf18SBorislav Petkov return 0; 51221afaf18SBorislav Petkov 5136e898d2bSTony W Wang-oc /* Checks after this one are Intel/Zhaoxin-specific: */ 5146e898d2bSTony W Wang-oc if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && 5156e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) 51621afaf18SBorislav Petkov return 1; 51721afaf18SBorislav Petkov 51821afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_MISCV)) 51921afaf18SBorislav Petkov return 0; 52021afaf18SBorislav Petkov 52121afaf18SBorislav Petkov if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) 52221afaf18SBorislav Petkov return 0; 52321afaf18SBorislav Petkov 52421afaf18SBorislav Petkov if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) 52521afaf18SBorislav Petkov return 0; 52621afaf18SBorislav Petkov 52721afaf18SBorislav Petkov return 1; 52821afaf18SBorislav Petkov } 52921afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_usable_address); 53021afaf18SBorislav Petkov 53121afaf18SBorislav Petkov bool mce_is_memory_error(struct mce *m) 53221afaf18SBorislav Petkov { 5336e898d2bSTony W Wang-oc switch (m->cpuvendor) { 5346e898d2bSTony W Wang-oc case X86_VENDOR_AMD: 5356e898d2bSTony W Wang-oc case X86_VENDOR_HYGON: 53621afaf18SBorislav Petkov return amd_mce_is_memory_error(m); 5376e898d2bSTony W Wang-oc 5386e898d2bSTony W Wang-oc case X86_VENDOR_INTEL: 5396e898d2bSTony W Wang-oc case X86_VENDOR_ZHAOXIN: 54021afaf18SBorislav Petkov /* 54121afaf18SBorislav Petkov * Intel SDM Volume 3B - 15.9.2 Compound Error Codes 54221afaf18SBorislav Petkov * 54321afaf18SBorislav Petkov * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for 54421afaf18SBorislav Petkov * indicating a memory error. Bit 8 is used for indicating a 54521afaf18SBorislav Petkov * cache hierarchy error. The combination of bit 2 and bit 3 54621afaf18SBorislav Petkov * is used for indicating a `generic' cache hierarchy error 54721afaf18SBorislav Petkov * But we can't just blindly check the above bits, because if 54821afaf18SBorislav Petkov * bit 11 is set, then it is a bus/interconnect error - and 54921afaf18SBorislav Petkov * either way the above bits just gives more detail on what 55021afaf18SBorislav Petkov * bus/interconnect error happened. Note that bit 12 can be 55121afaf18SBorislav Petkov * ignored, as it's the "filter" bit. 55221afaf18SBorislav Petkov */ 55321afaf18SBorislav Petkov return (m->status & 0xef80) == BIT(7) || 55421afaf18SBorislav Petkov (m->status & 0xef00) == BIT(8) || 55521afaf18SBorislav Petkov (m->status & 0xeffc) == 0xc; 55621afaf18SBorislav Petkov 5576e898d2bSTony W Wang-oc default: 55821afaf18SBorislav Petkov return false; 55921afaf18SBorislav Petkov } 5606e898d2bSTony W Wang-oc } 56121afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_memory_error); 56221afaf18SBorislav Petkov 56317fae129STony Luck static bool whole_page(struct mce *m) 56417fae129STony Luck { 56517fae129STony Luck if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV)) 56617fae129STony Luck return true; 56717fae129STony Luck 56817fae129STony Luck return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT; 56917fae129STony Luck } 57017fae129STony Luck 57121afaf18SBorislav Petkov bool mce_is_correctable(struct mce *m) 57221afaf18SBorislav Petkov { 57321afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED) 57421afaf18SBorislav Petkov return false; 57521afaf18SBorislav Petkov 57621afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED) 57721afaf18SBorislav Petkov return false; 57821afaf18SBorislav Petkov 57921afaf18SBorislav Petkov if (m->status & MCI_STATUS_UC) 58021afaf18SBorislav Petkov return false; 58121afaf18SBorislav Petkov 58221afaf18SBorislav Petkov return true; 58321afaf18SBorislav Petkov } 58421afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_correctable); 58521afaf18SBorislav Petkov 586c9c6d216STony Luck static int mce_early_notifier(struct notifier_block *nb, unsigned long val, 58721afaf18SBorislav Petkov void *data) 58821afaf18SBorislav Petkov { 58921afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 59021afaf18SBorislav Petkov 59121afaf18SBorislav Petkov if (!m) 59221afaf18SBorislav Petkov return NOTIFY_DONE; 59321afaf18SBorislav Petkov 59421afaf18SBorislav Petkov /* Emit the trace record: */ 59521afaf18SBorislav Petkov trace_mce_record(m); 59621afaf18SBorislav Petkov 59721afaf18SBorislav Petkov set_bit(0, &mce_need_notify); 59821afaf18SBorislav Petkov 59921afaf18SBorislav Petkov mce_notify_irq(); 60021afaf18SBorislav Petkov 60121afaf18SBorislav Petkov return NOTIFY_DONE; 60221afaf18SBorislav Petkov } 60321afaf18SBorislav Petkov 604c9c6d216STony Luck static struct notifier_block early_nb = { 605c9c6d216STony Luck .notifier_call = mce_early_notifier, 606c9c6d216STony Luck .priority = MCE_PRIO_EARLY, 60721afaf18SBorislav Petkov }; 60821afaf18SBorislav Petkov 6098438b84aSJan H. Schönherr static int uc_decode_notifier(struct notifier_block *nb, unsigned long val, 61021afaf18SBorislav Petkov void *data) 61121afaf18SBorislav Petkov { 61221afaf18SBorislav Petkov struct mce *mce = (struct mce *)data; 61321afaf18SBorislav Petkov unsigned long pfn; 61421afaf18SBorislav Petkov 6158438b84aSJan H. Schönherr if (!mce || !mce_usable_address(mce)) 61621afaf18SBorislav Petkov return NOTIFY_DONE; 61721afaf18SBorislav Petkov 6188438b84aSJan H. Schönherr if (mce->severity != MCE_AO_SEVERITY && 6198438b84aSJan H. Schönherr mce->severity != MCE_DEFERRED_SEVERITY) 6208438b84aSJan H. Schönherr return NOTIFY_DONE; 6218438b84aSJan H. Schönherr 62221afaf18SBorislav Petkov pfn = mce->addr >> PAGE_SHIFT; 62323ba710aSTony Luck if (!memory_failure(pfn, 0)) { 62417fae129STony Luck set_mce_nospec(pfn, whole_page(mce)); 62523ba710aSTony Luck mce->kflags |= MCE_HANDLED_UC; 62623ba710aSTony Luck } 62721afaf18SBorislav Petkov 62821afaf18SBorislav Petkov return NOTIFY_OK; 62921afaf18SBorislav Petkov } 6308438b84aSJan H. Schönherr 6318438b84aSJan H. Schönherr static struct notifier_block mce_uc_nb = { 6328438b84aSJan H. Schönherr .notifier_call = uc_decode_notifier, 6338438b84aSJan H. Schönherr .priority = MCE_PRIO_UC, 63421afaf18SBorislav Petkov }; 63521afaf18SBorislav Petkov 63621afaf18SBorislav Petkov static int mce_default_notifier(struct notifier_block *nb, unsigned long val, 63721afaf18SBorislav Petkov void *data) 63821afaf18SBorislav Petkov { 63921afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 64021afaf18SBorislav Petkov 64121afaf18SBorislav Petkov if (!m) 64221afaf18SBorislav Petkov return NOTIFY_DONE; 64321afaf18SBorislav Petkov 64443505646STony Luck if (mca_cfg.print_all || !m->kflags) 64521afaf18SBorislav Petkov __print_mce(m); 64621afaf18SBorislav Petkov 64721afaf18SBorislav Petkov return NOTIFY_DONE; 64821afaf18SBorislav Petkov } 64921afaf18SBorislav Petkov 65021afaf18SBorislav Petkov static struct notifier_block mce_default_nb = { 65121afaf18SBorislav Petkov .notifier_call = mce_default_notifier, 65221afaf18SBorislav Petkov /* lowest prio, we want it to run last. */ 65321afaf18SBorislav Petkov .priority = MCE_PRIO_LOWEST, 65421afaf18SBorislav Petkov }; 65521afaf18SBorislav Petkov 65621afaf18SBorislav Petkov /* 65721afaf18SBorislav Petkov * Read ADDR and MISC registers. 65821afaf18SBorislav Petkov */ 65921afaf18SBorislav Petkov static void mce_read_aux(struct mce *m, int i) 66021afaf18SBorislav Petkov { 66121afaf18SBorislav Petkov if (m->status & MCI_STATUS_MISCV) 662*8121b8f9SBorislav Petkov m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC)); 66321afaf18SBorislav Petkov 66421afaf18SBorislav Petkov if (m->status & MCI_STATUS_ADDRV) { 665*8121b8f9SBorislav Petkov m->addr = mce_rdmsrl(mca_msr_reg(i, MCA_ADDR)); 66621afaf18SBorislav Petkov 66721afaf18SBorislav Petkov /* 66821afaf18SBorislav Petkov * Mask the reported address by the reported granularity. 66921afaf18SBorislav Petkov */ 67021afaf18SBorislav Petkov if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { 67121afaf18SBorislav Petkov u8 shift = MCI_MISC_ADDR_LSB(m->misc); 67221afaf18SBorislav Petkov m->addr >>= shift; 67321afaf18SBorislav Petkov m->addr <<= shift; 67421afaf18SBorislav Petkov } 67521afaf18SBorislav Petkov 67621afaf18SBorislav Petkov /* 67721afaf18SBorislav Petkov * Extract [55:<lsb>] where lsb is the least significant 67821afaf18SBorislav Petkov * *valid* bit of the address bits. 67921afaf18SBorislav Petkov */ 68021afaf18SBorislav Petkov if (mce_flags.smca) { 68121afaf18SBorislav Petkov u8 lsb = (m->addr >> 56) & 0x3f; 68221afaf18SBorislav Petkov 68321afaf18SBorislav Petkov m->addr &= GENMASK_ULL(55, lsb); 68421afaf18SBorislav Petkov } 68521afaf18SBorislav Petkov } 68621afaf18SBorislav Petkov 68721afaf18SBorislav Petkov if (mce_flags.smca) { 68821afaf18SBorislav Petkov m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); 68921afaf18SBorislav Petkov 69021afaf18SBorislav Petkov if (m->status & MCI_STATUS_SYNDV) 69121afaf18SBorislav Petkov m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); 69221afaf18SBorislav Petkov } 69321afaf18SBorislav Petkov } 69421afaf18SBorislav Petkov 69521afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_poll_count); 69621afaf18SBorislav Petkov 69721afaf18SBorislav Petkov /* 69821afaf18SBorislav Petkov * Poll for corrected events or events that happened before reset. 69921afaf18SBorislav Petkov * Those are just logged through /dev/mcelog. 70021afaf18SBorislav Petkov * 70121afaf18SBorislav Petkov * This is executed in standard interrupt context. 70221afaf18SBorislav Petkov * 70321afaf18SBorislav Petkov * Note: spec recommends to panic for fatal unsignalled 70421afaf18SBorislav Petkov * errors here. However this would be quite problematic -- 70521afaf18SBorislav Petkov * we would need to reimplement the Monarch handling and 70621afaf18SBorislav Petkov * it would mess up the exclusion between exception handler 707312a4661SLinus Torvalds * and poll handler -- * so we skip this for now. 70821afaf18SBorislav Petkov * These cases should not happen anyways, or only when the CPU 70921afaf18SBorislav Petkov * is already totally * confused. In this case it's likely it will 71021afaf18SBorislav Petkov * not fully execute the machine check handler either. 71121afaf18SBorislav Petkov */ 71221afaf18SBorislav Petkov bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) 71321afaf18SBorislav Petkov { 714b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 71521afaf18SBorislav Petkov bool error_seen = false; 71621afaf18SBorislav Petkov struct mce m; 71721afaf18SBorislav Petkov int i; 71821afaf18SBorislav Petkov 71921afaf18SBorislav Petkov this_cpu_inc(mce_poll_count); 72021afaf18SBorislav Petkov 72121afaf18SBorislav Petkov mce_gather_info(&m, NULL); 72221afaf18SBorislav Petkov 72321afaf18SBorislav Petkov if (flags & MCP_TIMESTAMP) 72421afaf18SBorislav Petkov m.tsc = rdtsc(); 72521afaf18SBorislav Petkov 726c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 72721afaf18SBorislav Petkov if (!mce_banks[i].ctl || !test_bit(i, *b)) 72821afaf18SBorislav Petkov continue; 72921afaf18SBorislav Petkov 73021afaf18SBorislav Petkov m.misc = 0; 73121afaf18SBorislav Petkov m.addr = 0; 73221afaf18SBorislav Petkov m.bank = i; 73321afaf18SBorislav Petkov 73421afaf18SBorislav Petkov barrier(); 735*8121b8f9SBorislav Petkov m.status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 736f19501aaSTony Luck 737f19501aaSTony Luck /* If this entry is not valid, ignore it */ 73821afaf18SBorislav Petkov if (!(m.status & MCI_STATUS_VAL)) 73921afaf18SBorislav Petkov continue; 74021afaf18SBorislav Petkov 74121afaf18SBorislav Petkov /* 742f19501aaSTony Luck * If we are logging everything (at CPU online) or this 743f19501aaSTony Luck * is a corrected error, then we must log it. 74421afaf18SBorislav Petkov */ 745f19501aaSTony Luck if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC)) 746f19501aaSTony Luck goto log_it; 747f19501aaSTony Luck 748f19501aaSTony Luck /* 749f19501aaSTony Luck * Newer Intel systems that support software error 750f19501aaSTony Luck * recovery need to make additional checks. Other 751f19501aaSTony Luck * CPUs should skip over uncorrected errors, but log 752f19501aaSTony Luck * everything else. 753f19501aaSTony Luck */ 754f19501aaSTony Luck if (!mca_cfg.ser) { 755f19501aaSTony Luck if (m.status & MCI_STATUS_UC) 756f19501aaSTony Luck continue; 757f19501aaSTony Luck goto log_it; 758f19501aaSTony Luck } 759f19501aaSTony Luck 760f19501aaSTony Luck /* Log "not enabled" (speculative) errors */ 761f19501aaSTony Luck if (!(m.status & MCI_STATUS_EN)) 762f19501aaSTony Luck goto log_it; 763f19501aaSTony Luck 764f19501aaSTony Luck /* 765f19501aaSTony Luck * Log UCNA (SDM: 15.6.3 "UCR Error Classification") 766f19501aaSTony Luck * UC == 1 && PCC == 0 && S == 0 767f19501aaSTony Luck */ 768f19501aaSTony Luck if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S)) 769f19501aaSTony Luck goto log_it; 770f19501aaSTony Luck 771f19501aaSTony Luck /* 772f19501aaSTony Luck * Skip anything else. Presumption is that our read of this 773f19501aaSTony Luck * bank is racing with a machine check. Leave the log alone 774f19501aaSTony Luck * for do_machine_check() to deal with it. 775f19501aaSTony Luck */ 77621afaf18SBorislav Petkov continue; 77721afaf18SBorislav Petkov 778f19501aaSTony Luck log_it: 77921afaf18SBorislav Petkov error_seen = true; 78021afaf18SBorislav Petkov 78190454e49SJan H. Schönherr if (flags & MCP_DONTLOG) 78290454e49SJan H. Schönherr goto clear_it; 78390454e49SJan H. Schönherr 78421afaf18SBorislav Petkov mce_read_aux(&m, i); 78541ce0564SYouquan Song m.severity = mce_severity(&m, NULL, mca_cfg.tolerant, NULL, false); 78621afaf18SBorislav Petkov /* 78721afaf18SBorislav Petkov * Don't get the IP here because it's unlikely to 78821afaf18SBorislav Petkov * have anything to do with the actual error location. 78921afaf18SBorislav Petkov */ 79021afaf18SBorislav Petkov 79190454e49SJan H. Schönherr if (mca_cfg.dont_log_ce && !mce_usable_address(&m)) 79290454e49SJan H. Schönherr goto clear_it; 79390454e49SJan H. Schönherr 7943bff147bSBorislav Petkov if (flags & MCP_QUEUE_LOG) 7953bff147bSBorislav Petkov mce_gen_pool_add(&m); 7963bff147bSBorislav Petkov else 79790454e49SJan H. Schönherr mce_log(&m); 79890454e49SJan H. Schönherr 79990454e49SJan H. Schönherr clear_it: 80021afaf18SBorislav Petkov /* 80121afaf18SBorislav Petkov * Clear state for this bank. 80221afaf18SBorislav Petkov */ 803*8121b8f9SBorislav Petkov mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 80421afaf18SBorislav Petkov } 80521afaf18SBorislav Petkov 80621afaf18SBorislav Petkov /* 80721afaf18SBorislav Petkov * Don't clear MCG_STATUS here because it's only defined for 80821afaf18SBorislav Petkov * exceptions. 80921afaf18SBorislav Petkov */ 81021afaf18SBorislav Petkov 81121afaf18SBorislav Petkov sync_core(); 81221afaf18SBorislav Petkov 81321afaf18SBorislav Petkov return error_seen; 81421afaf18SBorislav Petkov } 81521afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(machine_check_poll); 81621afaf18SBorislav Petkov 81721afaf18SBorislav Petkov /* 81821afaf18SBorislav Petkov * Do a quick check if any of the events requires a panic. 81921afaf18SBorislav Petkov * This decides if we keep the events around or clear them. 82021afaf18SBorislav Petkov */ 82121afaf18SBorislav Petkov static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, 82221afaf18SBorislav Petkov struct pt_regs *regs) 82321afaf18SBorislav Petkov { 8247a8bc2b0SJan H. Schönherr char *tmp = *msg; 82521afaf18SBorislav Petkov int i; 82621afaf18SBorislav Petkov 827c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 828*8121b8f9SBorislav Petkov m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 82921afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 83021afaf18SBorislav Petkov continue; 83121afaf18SBorislav Petkov 83221afaf18SBorislav Petkov __set_bit(i, validp); 83321afaf18SBorislav Petkov if (quirk_no_way_out) 83421afaf18SBorislav Petkov quirk_no_way_out(i, m, regs); 83521afaf18SBorislav Petkov 836d28af26fSTony Luck m->bank = i; 83741ce0564SYouquan Song if (mce_severity(m, regs, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) { 83821afaf18SBorislav Petkov mce_read_aux(m, i); 83921afaf18SBorislav Petkov *msg = tmp; 84021afaf18SBorislav Petkov return 1; 84121afaf18SBorislav Petkov } 84221afaf18SBorislav Petkov } 84321afaf18SBorislav Petkov return 0; 84421afaf18SBorislav Petkov } 84521afaf18SBorislav Petkov 84621afaf18SBorislav Petkov /* 84721afaf18SBorislav Petkov * Variable to establish order between CPUs while scanning. 84821afaf18SBorislav Petkov * Each CPU spins initially until executing is equal its number. 84921afaf18SBorislav Petkov */ 85021afaf18SBorislav Petkov static atomic_t mce_executing; 85121afaf18SBorislav Petkov 85221afaf18SBorislav Petkov /* 85321afaf18SBorislav Petkov * Defines order of CPUs on entry. First CPU becomes Monarch. 85421afaf18SBorislav Petkov */ 85521afaf18SBorislav Petkov static atomic_t mce_callin; 85621afaf18SBorislav Petkov 85721afaf18SBorislav Petkov /* 8587bb39313SPaul E. McKenney * Track which CPUs entered the MCA broadcast synchronization and which not in 8597bb39313SPaul E. McKenney * order to print holdouts. 8607bb39313SPaul E. McKenney */ 8617bb39313SPaul E. McKenney static cpumask_t mce_missing_cpus = CPU_MASK_ALL; 8627bb39313SPaul E. McKenney 8637bb39313SPaul E. McKenney /* 86421afaf18SBorislav Petkov * Check if a timeout waiting for other CPUs happened. 86521afaf18SBorislav Petkov */ 86621afaf18SBorislav Petkov static int mce_timed_out(u64 *t, const char *msg) 86721afaf18SBorislav Petkov { 86821afaf18SBorislav Petkov /* 86921afaf18SBorislav Petkov * The others already did panic for some reason. 87021afaf18SBorislav Petkov * Bail out like in a timeout. 87121afaf18SBorislav Petkov * rmb() to tell the compiler that system_state 87221afaf18SBorislav Petkov * might have been modified by someone else. 87321afaf18SBorislav Petkov */ 87421afaf18SBorislav Petkov rmb(); 87521afaf18SBorislav Petkov if (atomic_read(&mce_panicked)) 87621afaf18SBorislav Petkov wait_for_panic(); 87721afaf18SBorislav Petkov if (!mca_cfg.monarch_timeout) 87821afaf18SBorislav Petkov goto out; 87921afaf18SBorislav Petkov if ((s64)*t < SPINUNIT) { 8807bb39313SPaul E. McKenney if (mca_cfg.tolerant <= 1) { 8817bb39313SPaul E. McKenney if (cpumask_and(&mce_missing_cpus, cpu_online_mask, &mce_missing_cpus)) 8827bb39313SPaul E. McKenney pr_emerg("CPUs not responding to MCE broadcast (may include false positives): %*pbl\n", 8837bb39313SPaul E. McKenney cpumask_pr_args(&mce_missing_cpus)); 88421afaf18SBorislav Petkov mce_panic(msg, NULL, NULL); 8857bb39313SPaul E. McKenney } 88621afaf18SBorislav Petkov cpu_missing = 1; 88721afaf18SBorislav Petkov return 1; 88821afaf18SBorislav Petkov } 88921afaf18SBorislav Petkov *t -= SPINUNIT; 89021afaf18SBorislav Petkov out: 89121afaf18SBorislav Petkov touch_nmi_watchdog(); 89221afaf18SBorislav Petkov return 0; 89321afaf18SBorislav Petkov } 89421afaf18SBorislav Petkov 89521afaf18SBorislav Petkov /* 89621afaf18SBorislav Petkov * The Monarch's reign. The Monarch is the CPU who entered 89721afaf18SBorislav Petkov * the machine check handler first. It waits for the others to 89821afaf18SBorislav Petkov * raise the exception too and then grades them. When any 89921afaf18SBorislav Petkov * error is fatal panic. Only then let the others continue. 90021afaf18SBorislav Petkov * 90121afaf18SBorislav Petkov * The other CPUs entering the MCE handler will be controlled by the 90221afaf18SBorislav Petkov * Monarch. They are called Subjects. 90321afaf18SBorislav Petkov * 90421afaf18SBorislav Petkov * This way we prevent any potential data corruption in a unrecoverable case 90521afaf18SBorislav Petkov * and also makes sure always all CPU's errors are examined. 90621afaf18SBorislav Petkov * 90721afaf18SBorislav Petkov * Also this detects the case of a machine check event coming from outer 90821afaf18SBorislav Petkov * space (not detected by any CPUs) In this case some external agent wants 90921afaf18SBorislav Petkov * us to shut down, so panic too. 91021afaf18SBorislav Petkov * 91121afaf18SBorislav Petkov * The other CPUs might still decide to panic if the handler happens 91221afaf18SBorislav Petkov * in a unrecoverable place, but in this case the system is in a semi-stable 91321afaf18SBorislav Petkov * state and won't corrupt anything by itself. It's ok to let the others 91421afaf18SBorislav Petkov * continue for a bit first. 91521afaf18SBorislav Petkov * 91621afaf18SBorislav Petkov * All the spin loops have timeouts; when a timeout happens a CPU 91721afaf18SBorislav Petkov * typically elects itself to be Monarch. 91821afaf18SBorislav Petkov */ 91921afaf18SBorislav Petkov static void mce_reign(void) 92021afaf18SBorislav Petkov { 92121afaf18SBorislav Petkov int cpu; 92221afaf18SBorislav Petkov struct mce *m = NULL; 92321afaf18SBorislav Petkov int global_worst = 0; 92421afaf18SBorislav Petkov char *msg = NULL; 92521afaf18SBorislav Petkov 92621afaf18SBorislav Petkov /* 92721afaf18SBorislav Petkov * This CPU is the Monarch and the other CPUs have run 92821afaf18SBorislav Petkov * through their handlers. 92921afaf18SBorislav Petkov * Grade the severity of the errors of all the CPUs. 93021afaf18SBorislav Petkov */ 93121afaf18SBorislav Petkov for_each_possible_cpu(cpu) { 93213c877f4STony Luck struct mce *mtmp = &per_cpu(mces_seen, cpu); 93313c877f4STony Luck 93413c877f4STony Luck if (mtmp->severity > global_worst) { 93513c877f4STony Luck global_worst = mtmp->severity; 93621afaf18SBorislav Petkov m = &per_cpu(mces_seen, cpu); 93721afaf18SBorislav Petkov } 93821afaf18SBorislav Petkov } 93921afaf18SBorislav Petkov 94021afaf18SBorislav Petkov /* 94121afaf18SBorislav Petkov * Cannot recover? Panic here then. 94221afaf18SBorislav Petkov * This dumps all the mces in the log buffer and stops the 94321afaf18SBorislav Petkov * other CPUs. 94421afaf18SBorislav Petkov */ 94513c877f4STony Luck if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) { 94613c877f4STony Luck /* call mce_severity() to get "msg" for panic */ 94741ce0564SYouquan Song mce_severity(m, NULL, mca_cfg.tolerant, &msg, true); 94821afaf18SBorislav Petkov mce_panic("Fatal machine check", m, msg); 94913c877f4STony Luck } 95021afaf18SBorislav Petkov 95121afaf18SBorislav Petkov /* 95221afaf18SBorislav Petkov * For UC somewhere we let the CPU who detects it handle it. 95321afaf18SBorislav Petkov * Also must let continue the others, otherwise the handling 95421afaf18SBorislav Petkov * CPU could deadlock on a lock. 95521afaf18SBorislav Petkov */ 95621afaf18SBorislav Petkov 95721afaf18SBorislav Petkov /* 95821afaf18SBorislav Petkov * No machine check event found. Must be some external 95921afaf18SBorislav Petkov * source or one CPU is hung. Panic. 96021afaf18SBorislav Petkov */ 96121afaf18SBorislav Petkov if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) 96221afaf18SBorislav Petkov mce_panic("Fatal machine check from unknown source", NULL, NULL); 96321afaf18SBorislav Petkov 96421afaf18SBorislav Petkov /* 96521afaf18SBorislav Petkov * Now clear all the mces_seen so that they don't reappear on 96621afaf18SBorislav Petkov * the next mce. 96721afaf18SBorislav Petkov */ 96821afaf18SBorislav Petkov for_each_possible_cpu(cpu) 96921afaf18SBorislav Petkov memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); 97021afaf18SBorislav Petkov } 97121afaf18SBorislav Petkov 97221afaf18SBorislav Petkov static atomic_t global_nwo; 97321afaf18SBorislav Petkov 97421afaf18SBorislav Petkov /* 97521afaf18SBorislav Petkov * Start of Monarch synchronization. This waits until all CPUs have 97621afaf18SBorislav Petkov * entered the exception handler and then determines if any of them 97721afaf18SBorislav Petkov * saw a fatal event that requires panic. Then it executes them 97821afaf18SBorislav Petkov * in the entry order. 97921afaf18SBorislav Petkov * TBD double check parallel CPU hotunplug 98021afaf18SBorislav Petkov */ 98121afaf18SBorislav Petkov static int mce_start(int *no_way_out) 98221afaf18SBorislav Petkov { 98321afaf18SBorislav Petkov int order; 98421afaf18SBorislav Petkov int cpus = num_online_cpus(); 98521afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 98621afaf18SBorislav Petkov 98721afaf18SBorislav Petkov if (!timeout) 98821afaf18SBorislav Petkov return -1; 98921afaf18SBorislav Petkov 99021afaf18SBorislav Petkov atomic_add(*no_way_out, &global_nwo); 99121afaf18SBorislav Petkov /* 99221afaf18SBorislav Petkov * Rely on the implied barrier below, such that global_nwo 99321afaf18SBorislav Petkov * is updated before mce_callin. 99421afaf18SBorislav Petkov */ 99521afaf18SBorislav Petkov order = atomic_inc_return(&mce_callin); 9967bb39313SPaul E. McKenney cpumask_clear_cpu(smp_processor_id(), &mce_missing_cpus); 99721afaf18SBorislav Petkov 99821afaf18SBorislav Petkov /* 99921afaf18SBorislav Petkov * Wait for everyone. 100021afaf18SBorislav Petkov */ 100121afaf18SBorislav Petkov while (atomic_read(&mce_callin) != cpus) { 100221afaf18SBorislav Petkov if (mce_timed_out(&timeout, 100321afaf18SBorislav Petkov "Timeout: Not all CPUs entered broadcast exception handler")) { 100421afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 100521afaf18SBorislav Petkov return -1; 100621afaf18SBorislav Petkov } 100721afaf18SBorislav Petkov ndelay(SPINUNIT); 100821afaf18SBorislav Petkov } 100921afaf18SBorislav Petkov 101021afaf18SBorislav Petkov /* 101121afaf18SBorislav Petkov * mce_callin should be read before global_nwo 101221afaf18SBorislav Petkov */ 101321afaf18SBorislav Petkov smp_rmb(); 101421afaf18SBorislav Petkov 101521afaf18SBorislav Petkov if (order == 1) { 101621afaf18SBorislav Petkov /* 101721afaf18SBorislav Petkov * Monarch: Starts executing now, the others wait. 101821afaf18SBorislav Petkov */ 101921afaf18SBorislav Petkov atomic_set(&mce_executing, 1); 102021afaf18SBorislav Petkov } else { 102121afaf18SBorislav Petkov /* 102221afaf18SBorislav Petkov * Subject: Now start the scanning loop one by one in 102321afaf18SBorislav Petkov * the original callin order. 102421afaf18SBorislav Petkov * This way when there are any shared banks it will be 102521afaf18SBorislav Petkov * only seen by one CPU before cleared, avoiding duplicates. 102621afaf18SBorislav Petkov */ 102721afaf18SBorislav Petkov while (atomic_read(&mce_executing) < order) { 102821afaf18SBorislav Petkov if (mce_timed_out(&timeout, 102921afaf18SBorislav Petkov "Timeout: Subject CPUs unable to finish machine check processing")) { 103021afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 103121afaf18SBorislav Petkov return -1; 103221afaf18SBorislav Petkov } 103321afaf18SBorislav Petkov ndelay(SPINUNIT); 103421afaf18SBorislav Petkov } 103521afaf18SBorislav Petkov } 103621afaf18SBorislav Petkov 103721afaf18SBorislav Petkov /* 103821afaf18SBorislav Petkov * Cache the global no_way_out state. 103921afaf18SBorislav Petkov */ 104021afaf18SBorislav Petkov *no_way_out = atomic_read(&global_nwo); 104121afaf18SBorislav Petkov 104221afaf18SBorislav Petkov return order; 104321afaf18SBorislav Petkov } 104421afaf18SBorislav Petkov 104521afaf18SBorislav Petkov /* 104621afaf18SBorislav Petkov * Synchronize between CPUs after main scanning loop. 104721afaf18SBorislav Petkov * This invokes the bulk of the Monarch processing. 104821afaf18SBorislav Petkov */ 104921afaf18SBorislav Petkov static int mce_end(int order) 105021afaf18SBorislav Petkov { 105121afaf18SBorislav Petkov int ret = -1; 105221afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 105321afaf18SBorislav Petkov 105421afaf18SBorislav Petkov if (!timeout) 105521afaf18SBorislav Petkov goto reset; 105621afaf18SBorislav Petkov if (order < 0) 105721afaf18SBorislav Petkov goto reset; 105821afaf18SBorislav Petkov 105921afaf18SBorislav Petkov /* 106021afaf18SBorislav Petkov * Allow others to run. 106121afaf18SBorislav Petkov */ 106221afaf18SBorislav Petkov atomic_inc(&mce_executing); 106321afaf18SBorislav Petkov 106421afaf18SBorislav Petkov if (order == 1) { 106521afaf18SBorislav Petkov /* CHECKME: Can this race with a parallel hotplug? */ 106621afaf18SBorislav Petkov int cpus = num_online_cpus(); 106721afaf18SBorislav Petkov 106821afaf18SBorislav Petkov /* 106921afaf18SBorislav Petkov * Monarch: Wait for everyone to go through their scanning 107021afaf18SBorislav Petkov * loops. 107121afaf18SBorislav Petkov */ 107221afaf18SBorislav Petkov while (atomic_read(&mce_executing) <= cpus) { 107321afaf18SBorislav Petkov if (mce_timed_out(&timeout, 107421afaf18SBorislav Petkov "Timeout: Monarch CPU unable to finish machine check processing")) 107521afaf18SBorislav Petkov goto reset; 107621afaf18SBorislav Petkov ndelay(SPINUNIT); 107721afaf18SBorislav Petkov } 107821afaf18SBorislav Petkov 107921afaf18SBorislav Petkov mce_reign(); 108021afaf18SBorislav Petkov barrier(); 108121afaf18SBorislav Petkov ret = 0; 108221afaf18SBorislav Petkov } else { 108321afaf18SBorislav Petkov /* 108421afaf18SBorislav Petkov * Subject: Wait for Monarch to finish. 108521afaf18SBorislav Petkov */ 108621afaf18SBorislav Petkov while (atomic_read(&mce_executing) != 0) { 108721afaf18SBorislav Petkov if (mce_timed_out(&timeout, 108821afaf18SBorislav Petkov "Timeout: Monarch CPU did not finish machine check processing")) 108921afaf18SBorislav Petkov goto reset; 109021afaf18SBorislav Petkov ndelay(SPINUNIT); 109121afaf18SBorislav Petkov } 109221afaf18SBorislav Petkov 109321afaf18SBorislav Petkov /* 109421afaf18SBorislav Petkov * Don't reset anything. That's done by the Monarch. 109521afaf18SBorislav Petkov */ 109621afaf18SBorislav Petkov return 0; 109721afaf18SBorislav Petkov } 109821afaf18SBorislav Petkov 109921afaf18SBorislav Petkov /* 110021afaf18SBorislav Petkov * Reset all global state. 110121afaf18SBorislav Petkov */ 110221afaf18SBorislav Petkov reset: 110321afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 110421afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 11057bb39313SPaul E. McKenney cpumask_setall(&mce_missing_cpus); 110621afaf18SBorislav Petkov barrier(); 110721afaf18SBorislav Petkov 110821afaf18SBorislav Petkov /* 110921afaf18SBorislav Petkov * Let others run again. 111021afaf18SBorislav Petkov */ 111121afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 111221afaf18SBorislav Petkov return ret; 111321afaf18SBorislav Petkov } 111421afaf18SBorislav Petkov 111521afaf18SBorislav Petkov static void mce_clear_state(unsigned long *toclear) 111621afaf18SBorislav Petkov { 111721afaf18SBorislav Petkov int i; 111821afaf18SBorislav Petkov 1119c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 112021afaf18SBorislav Petkov if (test_bit(i, toclear)) 1121*8121b8f9SBorislav Petkov mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 112221afaf18SBorislav Petkov } 112321afaf18SBorislav Petkov } 112421afaf18SBorislav Petkov 112521afaf18SBorislav Petkov /* 112621afaf18SBorislav Petkov * Cases where we avoid rendezvous handler timeout: 112721afaf18SBorislav Petkov * 1) If this CPU is offline. 112821afaf18SBorislav Petkov * 112921afaf18SBorislav Petkov * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to 113021afaf18SBorislav Petkov * skip those CPUs which remain looping in the 1st kernel - see 113121afaf18SBorislav Petkov * crash_nmi_callback(). 113221afaf18SBorislav Petkov * 113321afaf18SBorislav Petkov * Note: there still is a small window between kexec-ing and the new, 113421afaf18SBorislav Petkov * kdump kernel establishing a new #MC handler where a broadcasted MCE 113521afaf18SBorislav Petkov * might not get handled properly. 113621afaf18SBorislav Petkov */ 113794a46d31SThomas Gleixner static noinstr bool mce_check_crashing_cpu(void) 113821afaf18SBorislav Petkov { 113994a46d31SThomas Gleixner unsigned int cpu = smp_processor_id(); 114094a46d31SThomas Gleixner 114114d3b376SPeter Zijlstra if (arch_cpu_is_offline(cpu) || 114221afaf18SBorislav Petkov (crashing_cpu != -1 && crashing_cpu != cpu)) { 114321afaf18SBorislav Petkov u64 mcgstatus; 114421afaf18SBorislav Petkov 1145aedbdeabSThomas Gleixner mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS); 114670f0c230STony W Wang-oc 114770f0c230STony W Wang-oc if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { 114870f0c230STony W Wang-oc if (mcgstatus & MCG_STATUS_LMCES) 114970f0c230STony W Wang-oc return false; 115070f0c230STony W Wang-oc } 115170f0c230STony W Wang-oc 115221afaf18SBorislav Petkov if (mcgstatus & MCG_STATUS_RIPV) { 1153aedbdeabSThomas Gleixner __wrmsr(MSR_IA32_MCG_STATUS, 0, 0); 115421afaf18SBorislav Petkov return true; 115521afaf18SBorislav Petkov } 115621afaf18SBorislav Petkov } 115721afaf18SBorislav Petkov return false; 115821afaf18SBorislav Petkov } 115921afaf18SBorislav Petkov 116041ce0564SYouquan Song static void __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final, 116121afaf18SBorislav Petkov unsigned long *toclear, unsigned long *valid_banks, 116221afaf18SBorislav Petkov int no_way_out, int *worst) 116321afaf18SBorislav Petkov { 1164b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 116521afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 116621afaf18SBorislav Petkov int severity, i; 116721afaf18SBorislav Petkov 1168c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 116921afaf18SBorislav Petkov __clear_bit(i, toclear); 117021afaf18SBorislav Petkov if (!test_bit(i, valid_banks)) 117121afaf18SBorislav Petkov continue; 117221afaf18SBorislav Petkov 117321afaf18SBorislav Petkov if (!mce_banks[i].ctl) 117421afaf18SBorislav Petkov continue; 117521afaf18SBorislav Petkov 117621afaf18SBorislav Petkov m->misc = 0; 117721afaf18SBorislav Petkov m->addr = 0; 117821afaf18SBorislav Petkov m->bank = i; 117921afaf18SBorislav Petkov 1180*8121b8f9SBorislav Petkov m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 118121afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 118221afaf18SBorislav Petkov continue; 118321afaf18SBorislav Petkov 118421afaf18SBorislav Petkov /* 118521afaf18SBorislav Petkov * Corrected or non-signaled errors are handled by 118621afaf18SBorislav Petkov * machine_check_poll(). Leave them alone, unless this panics. 118721afaf18SBorislav Petkov */ 118821afaf18SBorislav Petkov if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && 118921afaf18SBorislav Petkov !no_way_out) 119021afaf18SBorislav Petkov continue; 119121afaf18SBorislav Petkov 119221afaf18SBorislav Petkov /* Set taint even when machine check was not enabled. */ 119321afaf18SBorislav Petkov add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 119421afaf18SBorislav Petkov 119541ce0564SYouquan Song severity = mce_severity(m, regs, cfg->tolerant, NULL, true); 119621afaf18SBorislav Petkov 119721afaf18SBorislav Petkov /* 119821afaf18SBorislav Petkov * When machine check was for corrected/deferred handler don't 119921afaf18SBorislav Petkov * touch, unless we're panicking. 120021afaf18SBorislav Petkov */ 120121afaf18SBorislav Petkov if ((severity == MCE_KEEP_SEVERITY || 120221afaf18SBorislav Petkov severity == MCE_UCNA_SEVERITY) && !no_way_out) 120321afaf18SBorislav Petkov continue; 120421afaf18SBorislav Petkov 120521afaf18SBorislav Petkov __set_bit(i, toclear); 120621afaf18SBorislav Petkov 120721afaf18SBorislav Petkov /* Machine check event was not enabled. Clear, but ignore. */ 120821afaf18SBorislav Petkov if (severity == MCE_NO_SEVERITY) 120921afaf18SBorislav Petkov continue; 121021afaf18SBorislav Petkov 121121afaf18SBorislav Petkov mce_read_aux(m, i); 121221afaf18SBorislav Petkov 121321afaf18SBorislav Petkov /* assuming valid severity level != 0 */ 121421afaf18SBorislav Petkov m->severity = severity; 121521afaf18SBorislav Petkov 121621afaf18SBorislav Petkov mce_log(m); 121721afaf18SBorislav Petkov 121821afaf18SBorislav Petkov if (severity > *worst) { 121921afaf18SBorislav Petkov *final = *m; 122021afaf18SBorislav Petkov *worst = severity; 122121afaf18SBorislav Petkov } 122221afaf18SBorislav Petkov } 122321afaf18SBorislav Petkov 122421afaf18SBorislav Petkov /* mce_clear_state will clear *final, save locally for use later */ 122521afaf18SBorislav Petkov *m = *final; 122621afaf18SBorislav Petkov } 122721afaf18SBorislav Petkov 12285567d11cSPeter Zijlstra static void kill_me_now(struct callback_head *ch) 12295567d11cSPeter Zijlstra { 123081065b35STony Luck struct task_struct *p = container_of(ch, struct task_struct, mce_kill_me); 123181065b35STony Luck 123281065b35STony Luck p->mce_count = 0; 12335567d11cSPeter Zijlstra force_sig(SIGBUS); 12345567d11cSPeter Zijlstra } 12355567d11cSPeter Zijlstra 12365567d11cSPeter Zijlstra static void kill_me_maybe(struct callback_head *cb) 12375567d11cSPeter Zijlstra { 12385567d11cSPeter Zijlstra struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me); 12395567d11cSPeter Zijlstra int flags = MF_ACTION_REQUIRED; 1240a3f5d80eSNaoya Horiguchi int ret; 12415567d11cSPeter Zijlstra 124281065b35STony Luck p->mce_count = 0; 12435567d11cSPeter Zijlstra pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr); 124417fae129STony Luck 124517fae129STony Luck if (!p->mce_ripv) 12465567d11cSPeter Zijlstra flags |= MF_MUST_KILL; 12475567d11cSPeter Zijlstra 1248a3f5d80eSNaoya Horiguchi ret = memory_failure(p->mce_addr >> PAGE_SHIFT, flags); 1249a6e3cf70STony Luck if (!ret) { 125017fae129STony Luck set_mce_nospec(p->mce_addr >> PAGE_SHIFT, p->mce_whole_page); 12511e36d9c6STony Luck sync_core(); 12525567d11cSPeter Zijlstra return; 12535567d11cSPeter Zijlstra } 12545567d11cSPeter Zijlstra 1255a3f5d80eSNaoya Horiguchi /* 1256a3f5d80eSNaoya Horiguchi * -EHWPOISON from memory_failure() means that it already sent SIGBUS 1257a3f5d80eSNaoya Horiguchi * to the current process with the proper error info, so no need to 1258a3f5d80eSNaoya Horiguchi * send SIGBUS here again. 1259a3f5d80eSNaoya Horiguchi */ 1260a3f5d80eSNaoya Horiguchi if (ret == -EHWPOISON) 1261a3f5d80eSNaoya Horiguchi return; 1262a3f5d80eSNaoya Horiguchi 12635567d11cSPeter Zijlstra pr_err("Memory error not recovered"); 12645567d11cSPeter Zijlstra kill_me_now(cb); 12655567d11cSPeter Zijlstra } 1266a6e3cf70STony Luck 1267a6e3cf70STony Luck static void kill_me_never(struct callback_head *cb) 1268a6e3cf70STony Luck { 1269a6e3cf70STony Luck struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me); 1270a6e3cf70STony Luck 1271a6e3cf70STony Luck p->mce_count = 0; 1272a6e3cf70STony Luck pr_err("Kernel accessed poison in user space at %llx\n", p->mce_addr); 1273a6e3cf70STony Luck if (!memory_failure(p->mce_addr >> PAGE_SHIFT, 0)) 1274a6e3cf70STony Luck set_mce_nospec(p->mce_addr >> PAGE_SHIFT, p->mce_whole_page); 127530063810STony Luck } 12765567d11cSPeter Zijlstra 1277a6e3cf70STony Luck static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callback_head *)) 1278c0ab7ffcSTony Luck { 127981065b35STony Luck int count = ++current->mce_count; 128081065b35STony Luck 128181065b35STony Luck /* First call, save all the details */ 128281065b35STony Luck if (count == 1) { 1283c0ab7ffcSTony Luck current->mce_addr = m->addr; 1284c0ab7ffcSTony Luck current->mce_kflags = m->kflags; 1285c0ab7ffcSTony Luck current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV); 1286c0ab7ffcSTony Luck current->mce_whole_page = whole_page(m); 1287a6e3cf70STony Luck current->mce_kill_me.func = func; 128881065b35STony Luck } 128981065b35STony Luck 129081065b35STony Luck /* Ten is likely overkill. Don't expect more than two faults before task_work() */ 129181065b35STony Luck if (count > 10) 129281065b35STony Luck mce_panic("Too many consecutive machine checks while accessing user data", m, msg); 129381065b35STony Luck 129481065b35STony Luck /* Second or later call, make sure page address matches the one from first call */ 129581065b35STony Luck if (count > 1 && (current->mce_addr >> PAGE_SHIFT) != (m->addr >> PAGE_SHIFT)) 129681065b35STony Luck mce_panic("Consecutive machine checks to different user pages", m, msg); 129781065b35STony Luck 129881065b35STony Luck /* Do not call task_work_add() more than once */ 129981065b35STony Luck if (count > 1) 130081065b35STony Luck return; 1301c0ab7ffcSTony Luck 130291989c70SJens Axboe task_work_add(current, ¤t->mce_kill_me, TWA_RESUME); 1303c0ab7ffcSTony Luck } 130421afaf18SBorislav Petkov 1305cbe1de16SBorislav Petkov /* Handle unconfigured int18 (should never happen) */ 1306cbe1de16SBorislav Petkov static noinstr void unexpected_machine_check(struct pt_regs *regs) 1307cbe1de16SBorislav Petkov { 1308cbe1de16SBorislav Petkov instrumentation_begin(); 1309cbe1de16SBorislav Petkov pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", 1310cbe1de16SBorislav Petkov smp_processor_id()); 1311cbe1de16SBorislav Petkov instrumentation_end(); 1312cbe1de16SBorislav Petkov } 1313cbe1de16SBorislav Petkov 131421afaf18SBorislav Petkov /* 131521afaf18SBorislav Petkov * The actual machine check handler. This only handles real 131621afaf18SBorislav Petkov * exceptions when something got corrupted coming in through int 18. 131721afaf18SBorislav Petkov * 131821afaf18SBorislav Petkov * This is executed in NMI context not subject to normal locking rules. This 131921afaf18SBorislav Petkov * implies that most kernel services cannot be safely used. Don't even 132021afaf18SBorislav Petkov * think about putting a printk in there! 132121afaf18SBorislav Petkov * 132221afaf18SBorislav Petkov * On Intel systems this is entered on all CPUs in parallel through 132321afaf18SBorislav Petkov * MCE broadcast. However some CPUs might be broken beyond repair, 132421afaf18SBorislav Petkov * so be always careful when synchronizing with others. 132555ba18d6SAndy Lutomirski * 132655ba18d6SAndy Lutomirski * Tracing and kprobes are disabled: if we interrupted a kernel context 132755ba18d6SAndy Lutomirski * with IF=1, we need to minimize stack usage. There are also recursion 132855ba18d6SAndy Lutomirski * issues: if the machine check was due to a failure of the memory 132955ba18d6SAndy Lutomirski * backing the user stack, tracing that reads the user stack will cause 133055ba18d6SAndy Lutomirski * potentially infinite recursion. 133121afaf18SBorislav Petkov */ 13327f6fa101SIra Weiny noinstr void do_machine_check(struct pt_regs *regs) 133321afaf18SBorislav Petkov { 1334cbe1de16SBorislav Petkov int worst = 0, order, no_way_out, kill_current_task, lmce; 133521afaf18SBorislav Petkov DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); 133621afaf18SBorislav Petkov DECLARE_BITMAP(toclear, MAX_NR_BANKS); 133721afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 133821afaf18SBorislav Petkov struct mce m, *final; 13397a8bc2b0SJan H. Schönherr char *msg = NULL; 1340cbe1de16SBorislav Petkov 1341cbe1de16SBorislav Petkov if (unlikely(mce_flags.p5)) 1342cbe1de16SBorislav Petkov return pentium_machine_check(regs); 1343cbe1de16SBorislav Petkov else if (unlikely(mce_flags.winchip)) 1344cbe1de16SBorislav Petkov return winchip_machine_check(regs); 1345cbe1de16SBorislav Petkov else if (unlikely(!mca_cfg.initialized)) 1346cbe1de16SBorislav Petkov return unexpected_machine_check(regs); 134721afaf18SBorislav Petkov 134821afaf18SBorislav Petkov /* 134921afaf18SBorislav Petkov * Establish sequential order between the CPUs entering the machine 135021afaf18SBorislav Petkov * check handler. 135121afaf18SBorislav Petkov */ 1352cbe1de16SBorislav Petkov order = -1; 135321afaf18SBorislav Petkov 135421afaf18SBorislav Petkov /* 135521afaf18SBorislav Petkov * If no_way_out gets set, there is no safe way to recover from this 135621afaf18SBorislav Petkov * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. 135721afaf18SBorislav Petkov */ 1358cbe1de16SBorislav Petkov no_way_out = 0; 135921afaf18SBorislav Petkov 136021afaf18SBorislav Petkov /* 1361e1c06d23SGabriele Paoloni * If kill_current_task is not set, there might be a way to recover from this 136221afaf18SBorislav Petkov * error. 136321afaf18SBorislav Petkov */ 1364cbe1de16SBorislav Petkov kill_current_task = 0; 136521afaf18SBorislav Petkov 136621afaf18SBorislav Petkov /* 136721afaf18SBorislav Petkov * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES 136821afaf18SBorislav Petkov * on Intel. 136921afaf18SBorislav Petkov */ 1370cbe1de16SBorislav Petkov lmce = 1; 137121afaf18SBorislav Petkov 137221afaf18SBorislav Petkov this_cpu_inc(mce_exception_count); 137321afaf18SBorislav Petkov 137421afaf18SBorislav Petkov mce_gather_info(&m, regs); 137521afaf18SBorislav Petkov m.tsc = rdtsc(); 137621afaf18SBorislav Petkov 137721afaf18SBorislav Petkov final = this_cpu_ptr(&mces_seen); 137821afaf18SBorislav Petkov *final = m; 137921afaf18SBorislav Petkov 138021afaf18SBorislav Petkov memset(valid_banks, 0, sizeof(valid_banks)); 138121afaf18SBorislav Petkov no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); 138221afaf18SBorislav Petkov 138321afaf18SBorislav Petkov barrier(); 138421afaf18SBorislav Petkov 138521afaf18SBorislav Petkov /* 138621afaf18SBorislav Petkov * When no restart IP might need to kill or panic. 138721afaf18SBorislav Petkov * Assume the worst for now, but if we find the 138821afaf18SBorislav Petkov * severity is MCE_AR_SEVERITY we have other options. 138921afaf18SBorislav Petkov */ 139021afaf18SBorislav Petkov if (!(m.mcgstatus & MCG_STATUS_RIPV)) 1391e1c06d23SGabriele Paoloni kill_current_task = (cfg->tolerant == 3) ? 0 : 1; 139221afaf18SBorislav Petkov /* 139321afaf18SBorislav Petkov * Check if this MCE is signaled to only this logical processor, 139470f0c230STony W Wang-oc * on Intel, Zhaoxin only. 139521afaf18SBorislav Petkov */ 139670f0c230STony W Wang-oc if (m.cpuvendor == X86_VENDOR_INTEL || 139770f0c230STony W Wang-oc m.cpuvendor == X86_VENDOR_ZHAOXIN) 139821afaf18SBorislav Petkov lmce = m.mcgstatus & MCG_STATUS_LMCES; 139921afaf18SBorislav Petkov 140021afaf18SBorislav Petkov /* 140121afaf18SBorislav Petkov * Local machine check may already know that we have to panic. 140221afaf18SBorislav Petkov * Broadcast machine check begins rendezvous in mce_start() 140321afaf18SBorislav Petkov * Go through all banks in exclusion of the other CPUs. This way we 140421afaf18SBorislav Petkov * don't report duplicated events on shared banks because the first one 140521afaf18SBorislav Petkov * to see it will clear it. 140621afaf18SBorislav Petkov */ 140721afaf18SBorislav Petkov if (lmce) { 14083a866b16SGabriele Paoloni if (no_way_out && cfg->tolerant < 3) 140921afaf18SBorislav Petkov mce_panic("Fatal local machine check", &m, msg); 141021afaf18SBorislav Petkov } else { 141121afaf18SBorislav Petkov order = mce_start(&no_way_out); 141221afaf18SBorislav Petkov } 141321afaf18SBorislav Petkov 141441ce0564SYouquan Song __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst); 141521afaf18SBorislav Petkov 141621afaf18SBorislav Petkov if (!no_way_out) 141721afaf18SBorislav Petkov mce_clear_state(toclear); 141821afaf18SBorislav Petkov 141921afaf18SBorislav Petkov /* 142021afaf18SBorislav Petkov * Do most of the synchronization with other CPUs. 142121afaf18SBorislav Petkov * When there's any problem use only local no_way_out state. 142221afaf18SBorislav Petkov */ 142321afaf18SBorislav Petkov if (!lmce) { 142425bc65d8SGabriele Paoloni if (mce_end(order) < 0) { 142525bc65d8SGabriele Paoloni if (!no_way_out) 142621afaf18SBorislav Petkov no_way_out = worst >= MCE_PANIC_SEVERITY; 1427e273e6e1SGabriele Paoloni 1428e273e6e1SGabriele Paoloni if (no_way_out && cfg->tolerant < 3) 1429e273e6e1SGabriele Paoloni mce_panic("Fatal machine check on current CPU", &m, msg); 143025bc65d8SGabriele Paoloni } 143121afaf18SBorislav Petkov } else { 143221afaf18SBorislav Petkov /* 143321afaf18SBorislav Petkov * If there was a fatal machine check we should have 143421afaf18SBorislav Petkov * already called mce_panic earlier in this function. 143521afaf18SBorislav Petkov * Since we re-read the banks, we might have found 143621afaf18SBorislav Petkov * something new. Check again to see if we found a 143721afaf18SBorislav Petkov * fatal error. We call "mce_severity()" again to 143821afaf18SBorislav Petkov * make sure we have the right "msg". 143921afaf18SBorislav Petkov */ 144021afaf18SBorislav Petkov if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) { 144141ce0564SYouquan Song mce_severity(&m, regs, cfg->tolerant, &msg, true); 144221afaf18SBorislav Petkov mce_panic("Local fatal machine check!", &m, msg); 144321afaf18SBorislav Petkov } 144421afaf18SBorislav Petkov } 144521afaf18SBorislav Petkov 1446e1c06d23SGabriele Paoloni if (worst != MCE_AR_SEVERITY && !kill_current_task) 14471e36d9c6STony Luck goto out; 144821afaf18SBorislav Petkov 144921afaf18SBorislav Petkov /* Fault was in user mode and we need to take some action */ 145021afaf18SBorislav Petkov if ((m.cs & 3) == 3) { 1451b052df3dSThomas Gleixner /* If this triggers there is no way to recover. Die hard. */ 1452b052df3dSThomas Gleixner BUG_ON(!on_thread_stack() || !user_mode(regs)); 145321afaf18SBorislav Petkov 1454a6e3cf70STony Luck if (kill_current_task) 1455a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_now); 1456a6e3cf70STony Luck else 1457a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_maybe); 1458c0ab7ffcSTony Luck 145921afaf18SBorislav Petkov } else { 14601df73b21SBorislav Petkov /* 14611df73b21SBorislav Petkov * Handle an MCE which has happened in kernel space but from 14621df73b21SBorislav Petkov * which the kernel can recover: ex_has_fault_handler() has 14631df73b21SBorislav Petkov * already verified that the rIP at which the error happened is 14641df73b21SBorislav Petkov * a rIP from which the kernel can recover (by jumping to 14651df73b21SBorislav Petkov * recovery code specified in _ASM_EXTABLE_FAULT()) and the 14661df73b21SBorislav Petkov * corresponding exception handler which would do that is the 14671df73b21SBorislav Petkov * proper one. 14681df73b21SBorislav Petkov */ 14691df73b21SBorislav Petkov if (m.kflags & MCE_IN_KERNEL_RECOV) { 14708cd501c1SThomas Gleixner if (!fixup_exception(regs, X86_TRAP_MC, 0, 0)) 14712d806d07SJan H. Schönherr mce_panic("Failed kernel mode recovery", &m, msg); 147221afaf18SBorislav Petkov } 1473c0ab7ffcSTony Luck 1474c0ab7ffcSTony Luck if (m.kflags & MCE_IN_KERNEL_COPYIN) 1475a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_never); 14761df73b21SBorislav Petkov } 14771e36d9c6STony Luck out: 14781e36d9c6STony Luck mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); 147921afaf18SBorislav Petkov } 148021afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(do_machine_check); 148121afaf18SBorislav Petkov 148221afaf18SBorislav Petkov #ifndef CONFIG_MEMORY_FAILURE 148321afaf18SBorislav Petkov int memory_failure(unsigned long pfn, int flags) 148421afaf18SBorislav Petkov { 148521afaf18SBorislav Petkov /* mce_severity() should not hand us an ACTION_REQUIRED error */ 148621afaf18SBorislav Petkov BUG_ON(flags & MF_ACTION_REQUIRED); 148721afaf18SBorislav Petkov pr_err("Uncorrected memory error in page 0x%lx ignored\n" 148821afaf18SBorislav Petkov "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", 148921afaf18SBorislav Petkov pfn); 149021afaf18SBorislav Petkov 149121afaf18SBorislav Petkov return 0; 149221afaf18SBorislav Petkov } 149321afaf18SBorislav Petkov #endif 149421afaf18SBorislav Petkov 149521afaf18SBorislav Petkov /* 149621afaf18SBorislav Petkov * Periodic polling timer for "silent" machine check errors. If the 149721afaf18SBorislav Petkov * poller finds an MCE, poll 2x faster. When the poller finds no more 149821afaf18SBorislav Petkov * errors, poll 2x slower (up to check_interval seconds). 149921afaf18SBorislav Petkov */ 150021afaf18SBorislav Petkov static unsigned long check_interval = INITIAL_CHECK_INTERVAL; 150121afaf18SBorislav Petkov 150221afaf18SBorislav Petkov static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ 150321afaf18SBorislav Petkov static DEFINE_PER_CPU(struct timer_list, mce_timer); 150421afaf18SBorislav Petkov 150521afaf18SBorislav Petkov static unsigned long mce_adjust_timer_default(unsigned long interval) 150621afaf18SBorislav Petkov { 150721afaf18SBorislav Petkov return interval; 150821afaf18SBorislav Petkov } 150921afaf18SBorislav Petkov 151021afaf18SBorislav Petkov static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; 151121afaf18SBorislav Petkov 151221afaf18SBorislav Petkov static void __start_timer(struct timer_list *t, unsigned long interval) 151321afaf18SBorislav Petkov { 151421afaf18SBorislav Petkov unsigned long when = jiffies + interval; 151521afaf18SBorislav Petkov unsigned long flags; 151621afaf18SBorislav Petkov 151721afaf18SBorislav Petkov local_irq_save(flags); 151821afaf18SBorislav Petkov 151921afaf18SBorislav Petkov if (!timer_pending(t) || time_before(when, t->expires)) 152021afaf18SBorislav Petkov mod_timer(t, round_jiffies(when)); 152121afaf18SBorislav Petkov 152221afaf18SBorislav Petkov local_irq_restore(flags); 152321afaf18SBorislav Petkov } 152421afaf18SBorislav Petkov 152521afaf18SBorislav Petkov static void mce_timer_fn(struct timer_list *t) 152621afaf18SBorislav Petkov { 152721afaf18SBorislav Petkov struct timer_list *cpu_t = this_cpu_ptr(&mce_timer); 152821afaf18SBorislav Petkov unsigned long iv; 152921afaf18SBorislav Petkov 153021afaf18SBorislav Petkov WARN_ON(cpu_t != t); 153121afaf18SBorislav Petkov 153221afaf18SBorislav Petkov iv = __this_cpu_read(mce_next_interval); 153321afaf18SBorislav Petkov 153421afaf18SBorislav Petkov if (mce_available(this_cpu_ptr(&cpu_info))) { 153521afaf18SBorislav Petkov machine_check_poll(0, this_cpu_ptr(&mce_poll_banks)); 153621afaf18SBorislav Petkov 153721afaf18SBorislav Petkov if (mce_intel_cmci_poll()) { 153821afaf18SBorislav Petkov iv = mce_adjust_timer(iv); 153921afaf18SBorislav Petkov goto done; 154021afaf18SBorislav Petkov } 154121afaf18SBorislav Petkov } 154221afaf18SBorislav Petkov 154321afaf18SBorislav Petkov /* 154421afaf18SBorislav Petkov * Alert userspace if needed. If we logged an MCE, reduce the polling 154521afaf18SBorislav Petkov * interval, otherwise increase the polling interval. 154621afaf18SBorislav Petkov */ 154721afaf18SBorislav Petkov if (mce_notify_irq()) 154821afaf18SBorislav Petkov iv = max(iv / 2, (unsigned long) HZ/100); 154921afaf18SBorislav Petkov else 155021afaf18SBorislav Petkov iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); 155121afaf18SBorislav Petkov 155221afaf18SBorislav Petkov done: 155321afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, iv); 155421afaf18SBorislav Petkov __start_timer(t, iv); 155521afaf18SBorislav Petkov } 155621afaf18SBorislav Petkov 155721afaf18SBorislav Petkov /* 155821afaf18SBorislav Petkov * Ensure that the timer is firing in @interval from now. 155921afaf18SBorislav Petkov */ 156021afaf18SBorislav Petkov void mce_timer_kick(unsigned long interval) 156121afaf18SBorislav Petkov { 156221afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 156321afaf18SBorislav Petkov unsigned long iv = __this_cpu_read(mce_next_interval); 156421afaf18SBorislav Petkov 156521afaf18SBorislav Petkov __start_timer(t, interval); 156621afaf18SBorislav Petkov 156721afaf18SBorislav Petkov if (interval < iv) 156821afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, interval); 156921afaf18SBorislav Petkov } 157021afaf18SBorislav Petkov 157121afaf18SBorislav Petkov /* Must not be called in IRQ context where del_timer_sync() can deadlock */ 157221afaf18SBorislav Petkov static void mce_timer_delete_all(void) 157321afaf18SBorislav Petkov { 157421afaf18SBorislav Petkov int cpu; 157521afaf18SBorislav Petkov 157621afaf18SBorislav Petkov for_each_online_cpu(cpu) 157721afaf18SBorislav Petkov del_timer_sync(&per_cpu(mce_timer, cpu)); 157821afaf18SBorislav Petkov } 157921afaf18SBorislav Petkov 158021afaf18SBorislav Petkov /* 158121afaf18SBorislav Petkov * Notify the user(s) about new machine check events. 158221afaf18SBorislav Petkov * Can be called from interrupt context, but not from machine check/NMI 158321afaf18SBorislav Petkov * context. 158421afaf18SBorislav Petkov */ 158521afaf18SBorislav Petkov int mce_notify_irq(void) 158621afaf18SBorislav Petkov { 158721afaf18SBorislav Petkov /* Not more than two messages every minute */ 158821afaf18SBorislav Petkov static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); 158921afaf18SBorislav Petkov 159021afaf18SBorislav Petkov if (test_and_clear_bit(0, &mce_need_notify)) { 159121afaf18SBorislav Petkov mce_work_trigger(); 159221afaf18SBorislav Petkov 159321afaf18SBorislav Petkov if (__ratelimit(&ratelimit)) 159421afaf18SBorislav Petkov pr_info(HW_ERR "Machine check events logged\n"); 159521afaf18SBorislav Petkov 159621afaf18SBorislav Petkov return 1; 159721afaf18SBorislav Petkov } 159821afaf18SBorislav Petkov return 0; 159921afaf18SBorislav Petkov } 160021afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_notify_irq); 160121afaf18SBorislav Petkov 1602b4914508SYazen Ghannam static void __mcheck_cpu_mce_banks_init(void) 160321afaf18SBorislav Petkov { 1604b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1605c7d314f3SYazen Ghannam u8 n_banks = this_cpu_read(mce_num_banks); 160621afaf18SBorislav Petkov int i; 160721afaf18SBorislav Petkov 1608c7d314f3SYazen Ghannam for (i = 0; i < n_banks; i++) { 160921afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 161021afaf18SBorislav Petkov 1611068b053dSYazen Ghannam /* 1612068b053dSYazen Ghannam * Init them all, __mcheck_cpu_apply_quirks() is going to apply 1613068b053dSYazen Ghannam * the required vendor quirks before 1614068b053dSYazen Ghannam * __mcheck_cpu_init_clear_banks() does the final bank setup. 1615068b053dSYazen Ghannam */ 161621afaf18SBorislav Petkov b->ctl = -1ULL; 161777080929SKaixu Xia b->init = true; 161821afaf18SBorislav Petkov } 161921afaf18SBorislav Petkov } 162021afaf18SBorislav Petkov 162121afaf18SBorislav Petkov /* 162221afaf18SBorislav Petkov * Initialize Machine Checks for a CPU. 162321afaf18SBorislav Petkov */ 1624b4914508SYazen Ghannam static void __mcheck_cpu_cap_init(void) 162521afaf18SBorislav Petkov { 162621afaf18SBorislav Petkov u64 cap; 1627006c0770SYazen Ghannam u8 b; 162821afaf18SBorislav Petkov 162921afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 163021afaf18SBorislav Petkov 163121afaf18SBorislav Petkov b = cap & MCG_BANKCNT_MASK; 163221afaf18SBorislav Petkov 1633c7d314f3SYazen Ghannam if (b > MAX_NR_BANKS) { 1634c7d314f3SYazen Ghannam pr_warn("CPU%d: Using only %u machine check banks out of %u\n", 1635c7d314f3SYazen Ghannam smp_processor_id(), MAX_NR_BANKS, b); 1636c7d314f3SYazen Ghannam b = MAX_NR_BANKS; 1637c7d314f3SYazen Ghannam } 1638c7d314f3SYazen Ghannam 1639c7d314f3SYazen Ghannam this_cpu_write(mce_num_banks, b); 164021afaf18SBorislav Petkov 1641b4914508SYazen Ghannam __mcheck_cpu_mce_banks_init(); 164221afaf18SBorislav Petkov 164321afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 164421afaf18SBorislav Petkov if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) 164521afaf18SBorislav Petkov mca_cfg.rip_msr = MSR_IA32_MCG_EIP; 164621afaf18SBorislav Petkov 164721afaf18SBorislav Petkov if (cap & MCG_SER_P) 164821afaf18SBorislav Petkov mca_cfg.ser = 1; 164921afaf18SBorislav Petkov } 165021afaf18SBorislav Petkov 165121afaf18SBorislav Petkov static void __mcheck_cpu_init_generic(void) 165221afaf18SBorislav Petkov { 165321afaf18SBorislav Petkov enum mcp_flags m_fl = 0; 165421afaf18SBorislav Petkov mce_banks_t all_banks; 165521afaf18SBorislav Petkov u64 cap; 165621afaf18SBorislav Petkov 165721afaf18SBorislav Petkov if (!mca_cfg.bootlog) 165821afaf18SBorislav Petkov m_fl = MCP_DONTLOG; 165921afaf18SBorislav Petkov 166021afaf18SBorislav Petkov /* 16613bff147bSBorislav Petkov * Log the machine checks left over from the previous reset. Log them 16623bff147bSBorislav Petkov * only, do not start processing them. That will happen in mcheck_late_init() 16633bff147bSBorislav Petkov * when all consumers have been registered on the notifier chain. 166421afaf18SBorislav Petkov */ 166521afaf18SBorislav Petkov bitmap_fill(all_banks, MAX_NR_BANKS); 16663bff147bSBorislav Petkov machine_check_poll(MCP_UC | MCP_QUEUE_LOG | m_fl, &all_banks); 166721afaf18SBorislav Petkov 166821afaf18SBorislav Petkov cr4_set_bits(X86_CR4_MCE); 166921afaf18SBorislav Petkov 167021afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 167121afaf18SBorislav Petkov if (cap & MCG_CTL_P) 167221afaf18SBorislav Petkov wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); 167321afaf18SBorislav Petkov } 167421afaf18SBorislav Petkov 167521afaf18SBorislav Petkov static void __mcheck_cpu_init_clear_banks(void) 167621afaf18SBorislav Petkov { 1677b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 167821afaf18SBorislav Petkov int i; 167921afaf18SBorislav Petkov 1680c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 168121afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 168221afaf18SBorislav Petkov 168321afaf18SBorislav Petkov if (!b->init) 168421afaf18SBorislav Petkov continue; 1685*8121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); 1686*8121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 168721afaf18SBorislav Petkov } 168821afaf18SBorislav Petkov } 168921afaf18SBorislav Petkov 169021afaf18SBorislav Petkov /* 1691068b053dSYazen Ghannam * Do a final check to see if there are any unused/RAZ banks. 1692068b053dSYazen Ghannam * 1693068b053dSYazen Ghannam * This must be done after the banks have been initialized and any quirks have 1694068b053dSYazen Ghannam * been applied. 1695068b053dSYazen Ghannam * 1696068b053dSYazen Ghannam * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs. 1697068b053dSYazen Ghannam * Otherwise, a user who disables a bank will not be able to re-enable it 1698068b053dSYazen Ghannam * without a system reboot. 1699068b053dSYazen Ghannam */ 1700068b053dSYazen Ghannam static void __mcheck_cpu_check_banks(void) 1701068b053dSYazen Ghannam { 1702068b053dSYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1703068b053dSYazen Ghannam u64 msrval; 1704068b053dSYazen Ghannam int i; 1705068b053dSYazen Ghannam 1706068b053dSYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1707068b053dSYazen Ghannam struct mce_bank *b = &mce_banks[i]; 1708068b053dSYazen Ghannam 1709068b053dSYazen Ghannam if (!b->init) 1710068b053dSYazen Ghannam continue; 1711068b053dSYazen Ghannam 1712*8121b8f9SBorislav Petkov rdmsrl(mca_msr_reg(i, MCA_CTL), msrval); 1713068b053dSYazen Ghannam b->init = !!msrval; 1714068b053dSYazen Ghannam } 1715068b053dSYazen Ghannam } 1716068b053dSYazen Ghannam 1717068b053dSYazen Ghannam /* 171821afaf18SBorislav Petkov * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and 171921afaf18SBorislav Petkov * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM 172021afaf18SBorislav Petkov * Vol 3B Table 15-20). But this confuses both the code that determines 172121afaf18SBorislav Petkov * whether the machine check occurred in kernel or user mode, and also 172221afaf18SBorislav Petkov * the severity assessment code. Pretend that EIPV was set, and take the 172321afaf18SBorislav Petkov * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. 172421afaf18SBorislav Petkov */ 172521afaf18SBorislav Petkov static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) 172621afaf18SBorislav Petkov { 172721afaf18SBorislav Petkov if (bank != 0) 172821afaf18SBorislav Petkov return; 172921afaf18SBorislav Petkov if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) 173021afaf18SBorislav Petkov return; 173121afaf18SBorislav Petkov if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| 173221afaf18SBorislav Petkov MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| 173321afaf18SBorislav Petkov MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| 173421afaf18SBorislav Petkov MCACOD)) != 173521afaf18SBorislav Petkov (MCI_STATUS_UC|MCI_STATUS_EN| 173621afaf18SBorislav Petkov MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| 173721afaf18SBorislav Petkov MCI_STATUS_AR|MCACOD_INSTR)) 173821afaf18SBorislav Petkov return; 173921afaf18SBorislav Petkov 174021afaf18SBorislav Petkov m->mcgstatus |= MCG_STATUS_EIPV; 174121afaf18SBorislav Petkov m->ip = regs->ip; 174221afaf18SBorislav Petkov m->cs = regs->cs; 174321afaf18SBorislav Petkov } 174421afaf18SBorislav Petkov 174521afaf18SBorislav Petkov /* Add per CPU specific workarounds here */ 174621afaf18SBorislav Petkov static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) 174721afaf18SBorislav Petkov { 1748b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 174921afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 175021afaf18SBorislav Petkov 175121afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_UNKNOWN) { 175221afaf18SBorislav Petkov pr_info("unknown CPU type - not enabling MCE support\n"); 175321afaf18SBorislav Petkov return -EOPNOTSUPP; 175421afaf18SBorislav Petkov } 175521afaf18SBorislav Petkov 175621afaf18SBorislav Petkov /* This should be disabled by the BIOS, but isn't always */ 175721afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD) { 1758c7d314f3SYazen Ghannam if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { 175921afaf18SBorislav Petkov /* 176021afaf18SBorislav Petkov * disable GART TBL walk error reporting, which 176121afaf18SBorislav Petkov * trips off incorrectly with the IOMMU & 3ware 176221afaf18SBorislav Petkov * & Cerberus: 176321afaf18SBorislav Petkov */ 176421afaf18SBorislav Petkov clear_bit(10, (unsigned long *)&mce_banks[4].ctl); 176521afaf18SBorislav Petkov } 176621afaf18SBorislav Petkov if (c->x86 < 0x11 && cfg->bootlog < 0) { 176721afaf18SBorislav Petkov /* 176821afaf18SBorislav Petkov * Lots of broken BIOS around that don't clear them 176921afaf18SBorislav Petkov * by default and leave crap in there. Don't log: 177021afaf18SBorislav Petkov */ 177121afaf18SBorislav Petkov cfg->bootlog = 0; 177221afaf18SBorislav Petkov } 177321afaf18SBorislav Petkov /* 177421afaf18SBorislav Petkov * Various K7s with broken bank 0 around. Always disable 177521afaf18SBorislav Petkov * by default. 177621afaf18SBorislav Petkov */ 1777c7d314f3SYazen Ghannam if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0) 177821afaf18SBorislav Petkov mce_banks[0].ctl = 0; 177921afaf18SBorislav Petkov 178021afaf18SBorislav Petkov /* 178121afaf18SBorislav Petkov * overflow_recov is supported for F15h Models 00h-0fh 178221afaf18SBorislav Petkov * even though we don't have a CPUID bit for it. 178321afaf18SBorislav Petkov */ 178421afaf18SBorislav Petkov if (c->x86 == 0x15 && c->x86_model <= 0xf) 178521afaf18SBorislav Petkov mce_flags.overflow_recov = 1; 178621afaf18SBorislav Petkov 178721afaf18SBorislav Petkov } 178821afaf18SBorislav Petkov 178921afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_INTEL) { 179021afaf18SBorislav Petkov /* 179121afaf18SBorislav Petkov * SDM documents that on family 6 bank 0 should not be written 179221afaf18SBorislav Petkov * because it aliases to another special BIOS controlled 179321afaf18SBorislav Petkov * register. 179421afaf18SBorislav Petkov * But it's not aliased anymore on model 0x1a+ 179521afaf18SBorislav Petkov * Don't ignore bank 0 completely because there could be a 179621afaf18SBorislav Petkov * valid event later, merely don't write CTL0. 179721afaf18SBorislav Petkov */ 179821afaf18SBorislav Petkov 1799c7d314f3SYazen Ghannam if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) 180077080929SKaixu Xia mce_banks[0].init = false; 180121afaf18SBorislav Petkov 180221afaf18SBorislav Petkov /* 180321afaf18SBorislav Petkov * All newer Intel systems support MCE broadcasting. Enable 180421afaf18SBorislav Petkov * synchronization with a one second timeout. 180521afaf18SBorislav Petkov */ 180621afaf18SBorislav Petkov if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && 180721afaf18SBorislav Petkov cfg->monarch_timeout < 0) 180821afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 180921afaf18SBorislav Petkov 181021afaf18SBorislav Petkov /* 181121afaf18SBorislav Petkov * There are also broken BIOSes on some Pentium M and 181221afaf18SBorislav Petkov * earlier systems: 181321afaf18SBorislav Petkov */ 181421afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) 181521afaf18SBorislav Petkov cfg->bootlog = 0; 181621afaf18SBorislav Petkov 181721afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model == 45) 181821afaf18SBorislav Petkov quirk_no_way_out = quirk_sandybridge_ifu; 181921afaf18SBorislav Petkov } 18206e898d2bSTony W Wang-oc 18216e898d2bSTony W Wang-oc if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { 18226e898d2bSTony W Wang-oc /* 18236e898d2bSTony W Wang-oc * All newer Zhaoxin CPUs support MCE broadcasting. Enable 18246e898d2bSTony W Wang-oc * synchronization with a one second timeout. 18256e898d2bSTony W Wang-oc */ 18266e898d2bSTony W Wang-oc if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 18276e898d2bSTony W Wang-oc if (cfg->monarch_timeout < 0) 18286e898d2bSTony W Wang-oc cfg->monarch_timeout = USEC_PER_SEC; 18296e898d2bSTony W Wang-oc } 18306e898d2bSTony W Wang-oc } 18316e898d2bSTony W Wang-oc 183221afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 183321afaf18SBorislav Petkov cfg->monarch_timeout = 0; 183421afaf18SBorislav Petkov if (cfg->bootlog != 0) 183521afaf18SBorislav Petkov cfg->panic_timeout = 30; 183621afaf18SBorislav Petkov 183721afaf18SBorislav Petkov return 0; 183821afaf18SBorislav Petkov } 183921afaf18SBorislav Petkov 184021afaf18SBorislav Petkov static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) 184121afaf18SBorislav Petkov { 184221afaf18SBorislav Petkov if (c->x86 != 5) 184321afaf18SBorislav Petkov return 0; 184421afaf18SBorislav Petkov 184521afaf18SBorislav Petkov switch (c->x86_vendor) { 184621afaf18SBorislav Petkov case X86_VENDOR_INTEL: 184721afaf18SBorislav Petkov intel_p5_mcheck_init(c); 1848cbe1de16SBorislav Petkov mce_flags.p5 = 1; 184921afaf18SBorislav Petkov return 1; 185021afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 185121afaf18SBorislav Petkov winchip_mcheck_init(c); 1852cbe1de16SBorislav Petkov mce_flags.winchip = 1; 185321afaf18SBorislav Petkov return 1; 185421afaf18SBorislav Petkov default: 185521afaf18SBorislav Petkov return 0; 185621afaf18SBorislav Petkov } 185721afaf18SBorislav Petkov 185821afaf18SBorislav Petkov return 0; 185921afaf18SBorislav Petkov } 186021afaf18SBorislav Petkov 186121afaf18SBorislav Petkov /* 186221afaf18SBorislav Petkov * Init basic CPU features needed for early decoding of MCEs. 186321afaf18SBorislav Petkov */ 186421afaf18SBorislav Petkov static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) 186521afaf18SBorislav Petkov { 186621afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) { 186721afaf18SBorislav Petkov mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); 186821afaf18SBorislav Petkov mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); 186921afaf18SBorislav Petkov mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); 1870c9bf318fSThomas Gleixner mce_flags.amd_threshold = 1; 187121afaf18SBorislav Petkov } 187221afaf18SBorislav Petkov } 187321afaf18SBorislav Petkov 187421afaf18SBorislav Petkov static void mce_centaur_feature_init(struct cpuinfo_x86 *c) 187521afaf18SBorislav Petkov { 187621afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 187721afaf18SBorislav Petkov 187821afaf18SBorislav Petkov /* 187921afaf18SBorislav Petkov * All newer Centaur CPUs support MCE broadcasting. Enable 188021afaf18SBorislav Petkov * synchronization with a one second timeout. 188121afaf18SBorislav Petkov */ 188221afaf18SBorislav Petkov if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) || 188321afaf18SBorislav Petkov c->x86 > 6) { 188421afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 188521afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 188621afaf18SBorislav Petkov } 188721afaf18SBorislav Petkov } 188821afaf18SBorislav Petkov 18895a3d56a0STony W Wang-oc static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) 18905a3d56a0STony W Wang-oc { 18915a3d56a0STony W Wang-oc struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 18925a3d56a0STony W Wang-oc 18935a3d56a0STony W Wang-oc /* 18945a3d56a0STony W Wang-oc * These CPUs have MCA bank 8 which reports only one error type called 18955a3d56a0STony W Wang-oc * SVAD (System View Address Decoder). The reporting of that error is 18965a3d56a0STony W Wang-oc * controlled by IA32_MC8.CTL.0. 18975a3d56a0STony W Wang-oc * 18985a3d56a0STony W Wang-oc * If enabled, prefetching on these CPUs will cause SVAD MCE when 18995a3d56a0STony W Wang-oc * virtual machines start and result in a system panic. Always disable 19005a3d56a0STony W Wang-oc * bank 8 SVAD error by default. 19015a3d56a0STony W Wang-oc */ 19025a3d56a0STony W Wang-oc if ((c->x86 == 7 && c->x86_model == 0x1b) || 19035a3d56a0STony W Wang-oc (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 19045a3d56a0STony W Wang-oc if (this_cpu_read(mce_num_banks) > 8) 19055a3d56a0STony W Wang-oc mce_banks[8].ctl = 0; 19065a3d56a0STony W Wang-oc } 19075a3d56a0STony W Wang-oc 19085a3d56a0STony W Wang-oc intel_init_cmci(); 190970f0c230STony W Wang-oc intel_init_lmce(); 19105a3d56a0STony W Wang-oc mce_adjust_timer = cmci_intel_adjust_timer; 19115a3d56a0STony W Wang-oc } 19125a3d56a0STony W Wang-oc 191370f0c230STony W Wang-oc static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) 191470f0c230STony W Wang-oc { 191570f0c230STony W Wang-oc intel_clear_lmce(); 191670f0c230STony W Wang-oc } 191770f0c230STony W Wang-oc 191821afaf18SBorislav Petkov static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) 191921afaf18SBorislav Petkov { 192021afaf18SBorislav Petkov switch (c->x86_vendor) { 192121afaf18SBorislav Petkov case X86_VENDOR_INTEL: 192221afaf18SBorislav Petkov mce_intel_feature_init(c); 192321afaf18SBorislav Petkov mce_adjust_timer = cmci_intel_adjust_timer; 192421afaf18SBorislav Petkov break; 192521afaf18SBorislav Petkov 192621afaf18SBorislav Petkov case X86_VENDOR_AMD: { 192721afaf18SBorislav Petkov mce_amd_feature_init(c); 192821afaf18SBorislav Petkov break; 192921afaf18SBorislav Petkov } 193021afaf18SBorislav Petkov 193121afaf18SBorislav Petkov case X86_VENDOR_HYGON: 193221afaf18SBorislav Petkov mce_hygon_feature_init(c); 193321afaf18SBorislav Petkov break; 193421afaf18SBorislav Petkov 193521afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 193621afaf18SBorislav Petkov mce_centaur_feature_init(c); 193721afaf18SBorislav Petkov break; 193821afaf18SBorislav Petkov 19395a3d56a0STony W Wang-oc case X86_VENDOR_ZHAOXIN: 19405a3d56a0STony W Wang-oc mce_zhaoxin_feature_init(c); 19415a3d56a0STony W Wang-oc break; 19425a3d56a0STony W Wang-oc 194321afaf18SBorislav Petkov default: 194421afaf18SBorislav Petkov break; 194521afaf18SBorislav Petkov } 194621afaf18SBorislav Petkov } 194721afaf18SBorislav Petkov 194821afaf18SBorislav Petkov static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) 194921afaf18SBorislav Petkov { 195021afaf18SBorislav Petkov switch (c->x86_vendor) { 195121afaf18SBorislav Petkov case X86_VENDOR_INTEL: 195221afaf18SBorislav Petkov mce_intel_feature_clear(c); 195321afaf18SBorislav Petkov break; 195470f0c230STony W Wang-oc 195570f0c230STony W Wang-oc case X86_VENDOR_ZHAOXIN: 195670f0c230STony W Wang-oc mce_zhaoxin_feature_clear(c); 195770f0c230STony W Wang-oc break; 195870f0c230STony W Wang-oc 195921afaf18SBorislav Petkov default: 196021afaf18SBorislav Petkov break; 196121afaf18SBorislav Petkov } 196221afaf18SBorislav Petkov } 196321afaf18SBorislav Petkov 196421afaf18SBorislav Petkov static void mce_start_timer(struct timer_list *t) 196521afaf18SBorislav Petkov { 196621afaf18SBorislav Petkov unsigned long iv = check_interval * HZ; 196721afaf18SBorislav Petkov 196821afaf18SBorislav Petkov if (mca_cfg.ignore_ce || !iv) 196921afaf18SBorislav Petkov return; 197021afaf18SBorislav Petkov 197121afaf18SBorislav Petkov this_cpu_write(mce_next_interval, iv); 197221afaf18SBorislav Petkov __start_timer(t, iv); 197321afaf18SBorislav Petkov } 197421afaf18SBorislav Petkov 197521afaf18SBorislav Petkov static void __mcheck_cpu_setup_timer(void) 197621afaf18SBorislav Petkov { 197721afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 197821afaf18SBorislav Petkov 197921afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 198021afaf18SBorislav Petkov } 198121afaf18SBorislav Petkov 198221afaf18SBorislav Petkov static void __mcheck_cpu_init_timer(void) 198321afaf18SBorislav Petkov { 198421afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 198521afaf18SBorislav Petkov 198621afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 198721afaf18SBorislav Petkov mce_start_timer(t); 198821afaf18SBorislav Petkov } 198921afaf18SBorislav Petkov 199045d4b7b9SYazen Ghannam bool filter_mce(struct mce *m) 199145d4b7b9SYazen Ghannam { 199271a84402SYazen Ghannam if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 199371a84402SYazen Ghannam return amd_filter_mce(m); 19942976908eSPrarit Bhargava if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 19952976908eSPrarit Bhargava return intel_filter_mce(m); 199671a84402SYazen Ghannam 199745d4b7b9SYazen Ghannam return false; 199845d4b7b9SYazen Ghannam } 199945d4b7b9SYazen Ghannam 20004c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_kernel(struct pt_regs *regs) 200121afaf18SBorislav Petkov { 2002b6be002bSThomas Gleixner irqentry_state_t irq_state; 2003bc21a291SThomas Gleixner 200413cbc0cdSAndy Lutomirski WARN_ON_ONCE(user_mode(regs)); 200513cbc0cdSAndy Lutomirski 20064c0dcd83SThomas Gleixner /* 20074c0dcd83SThomas Gleixner * Only required when from kernel mode. See 20084c0dcd83SThomas Gleixner * mce_check_crashing_cpu() for details. 20094c0dcd83SThomas Gleixner */ 2010cbe1de16SBorislav Petkov if (mca_cfg.initialized && mce_check_crashing_cpu()) 201194a46d31SThomas Gleixner return; 201294a46d31SThomas Gleixner 2013b6be002bSThomas Gleixner irq_state = irqentry_nmi_enter(regs); 201473749536SPeter Zijlstra 2015cbe1de16SBorislav Petkov do_machine_check(regs); 201673749536SPeter Zijlstra 2017b6be002bSThomas Gleixner irqentry_nmi_exit(regs, irq_state); 201821afaf18SBorislav Petkov } 201921afaf18SBorislav Petkov 20204c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_user(struct pt_regs *regs) 20214c0dcd83SThomas Gleixner { 2022517e4992SThomas Gleixner irqentry_enter_from_user_mode(regs); 202373749536SPeter Zijlstra 2024cbe1de16SBorislav Petkov do_machine_check(regs); 202573749536SPeter Zijlstra 2026517e4992SThomas Gleixner irqentry_exit_to_user_mode(regs); 20274c0dcd83SThomas Gleixner } 20284c0dcd83SThomas Gleixner 20294c0dcd83SThomas Gleixner #ifdef CONFIG_X86_64 20304c0dcd83SThomas Gleixner /* MCE hit kernel mode */ 20314c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE(exc_machine_check) 20324c0dcd83SThomas Gleixner { 2033cd840e42SPeter Zijlstra unsigned long dr7; 2034cd840e42SPeter Zijlstra 2035cd840e42SPeter Zijlstra dr7 = local_db_save(); 20364c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 2037cd840e42SPeter Zijlstra local_db_restore(dr7); 20384c0dcd83SThomas Gleixner } 20394c0dcd83SThomas Gleixner 20404c0dcd83SThomas Gleixner /* The user mode variant. */ 20414c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE_USER(exc_machine_check) 20424c0dcd83SThomas Gleixner { 2043cd840e42SPeter Zijlstra unsigned long dr7; 2044cd840e42SPeter Zijlstra 2045cd840e42SPeter Zijlstra dr7 = local_db_save(); 20464c0dcd83SThomas Gleixner exc_machine_check_user(regs); 2047cd840e42SPeter Zijlstra local_db_restore(dr7); 20484c0dcd83SThomas Gleixner } 20494c0dcd83SThomas Gleixner #else 20504c0dcd83SThomas Gleixner /* 32bit unified entry point */ 205113cbc0cdSAndy Lutomirski DEFINE_IDTENTRY_RAW(exc_machine_check) 20524c0dcd83SThomas Gleixner { 2053cd840e42SPeter Zijlstra unsigned long dr7; 2054cd840e42SPeter Zijlstra 2055cd840e42SPeter Zijlstra dr7 = local_db_save(); 20564c0dcd83SThomas Gleixner if (user_mode(regs)) 20574c0dcd83SThomas Gleixner exc_machine_check_user(regs); 20584c0dcd83SThomas Gleixner else 20594c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 2060cd840e42SPeter Zijlstra local_db_restore(dr7); 20614c0dcd83SThomas Gleixner } 20624c0dcd83SThomas Gleixner #endif 206321afaf18SBorislav Petkov 206421afaf18SBorislav Petkov /* 206521afaf18SBorislav Petkov * Called for each booted CPU to set up machine checks. 206621afaf18SBorislav Petkov * Must be called with preempt off: 206721afaf18SBorislav Petkov */ 206821afaf18SBorislav Petkov void mcheck_cpu_init(struct cpuinfo_x86 *c) 206921afaf18SBorislav Petkov { 207021afaf18SBorislav Petkov if (mca_cfg.disabled) 207121afaf18SBorislav Petkov return; 207221afaf18SBorislav Petkov 207321afaf18SBorislav Petkov if (__mcheck_cpu_ancient_init(c)) 207421afaf18SBorislav Petkov return; 207521afaf18SBorislav Petkov 207621afaf18SBorislav Petkov if (!mce_available(c)) 207721afaf18SBorislav Petkov return; 207821afaf18SBorislav Petkov 2079b4914508SYazen Ghannam __mcheck_cpu_cap_init(); 2080b4914508SYazen Ghannam 2081b4914508SYazen Ghannam if (__mcheck_cpu_apply_quirks(c) < 0) { 208221afaf18SBorislav Petkov mca_cfg.disabled = 1; 208321afaf18SBorislav Petkov return; 208421afaf18SBorislav Petkov } 208521afaf18SBorislav Petkov 208621afaf18SBorislav Petkov if (mce_gen_pool_init()) { 208721afaf18SBorislav Petkov mca_cfg.disabled = 1; 208821afaf18SBorislav Petkov pr_emerg("Couldn't allocate MCE records pool!\n"); 208921afaf18SBorislav Petkov return; 209021afaf18SBorislav Petkov } 209121afaf18SBorislav Petkov 2092cbe1de16SBorislav Petkov mca_cfg.initialized = 1; 209321afaf18SBorislav Petkov 209421afaf18SBorislav Petkov __mcheck_cpu_init_early(c); 209521afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 209621afaf18SBorislav Petkov __mcheck_cpu_init_vendor(c); 209721afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 2098068b053dSYazen Ghannam __mcheck_cpu_check_banks(); 209921afaf18SBorislav Petkov __mcheck_cpu_setup_timer(); 210021afaf18SBorislav Petkov } 210121afaf18SBorislav Petkov 210221afaf18SBorislav Petkov /* 210321afaf18SBorislav Petkov * Called for each booted CPU to clear some machine checks opt-ins 210421afaf18SBorislav Petkov */ 210521afaf18SBorislav Petkov void mcheck_cpu_clear(struct cpuinfo_x86 *c) 210621afaf18SBorislav Petkov { 210721afaf18SBorislav Petkov if (mca_cfg.disabled) 210821afaf18SBorislav Petkov return; 210921afaf18SBorislav Petkov 211021afaf18SBorislav Petkov if (!mce_available(c)) 211121afaf18SBorislav Petkov return; 211221afaf18SBorislav Petkov 211321afaf18SBorislav Petkov /* 211421afaf18SBorislav Petkov * Possibly to clear general settings generic to x86 211521afaf18SBorislav Petkov * __mcheck_cpu_clear_generic(c); 211621afaf18SBorislav Petkov */ 211721afaf18SBorislav Petkov __mcheck_cpu_clear_vendor(c); 211821afaf18SBorislav Petkov 211921afaf18SBorislav Petkov } 212021afaf18SBorislav Petkov 212121afaf18SBorislav Petkov static void __mce_disable_bank(void *arg) 212221afaf18SBorislav Petkov { 212321afaf18SBorislav Petkov int bank = *((int *)arg); 212421afaf18SBorislav Petkov __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); 212521afaf18SBorislav Petkov cmci_disable_bank(bank); 212621afaf18SBorislav Petkov } 212721afaf18SBorislav Petkov 212821afaf18SBorislav Petkov void mce_disable_bank(int bank) 212921afaf18SBorislav Petkov { 2130c7d314f3SYazen Ghannam if (bank >= this_cpu_read(mce_num_banks)) { 213121afaf18SBorislav Petkov pr_warn(FW_BUG 213221afaf18SBorislav Petkov "Ignoring request to disable invalid MCA bank %d.\n", 213321afaf18SBorislav Petkov bank); 213421afaf18SBorislav Petkov return; 213521afaf18SBorislav Petkov } 213621afaf18SBorislav Petkov set_bit(bank, mce_banks_ce_disabled); 213721afaf18SBorislav Petkov on_each_cpu(__mce_disable_bank, &bank, 1); 213821afaf18SBorislav Petkov } 213921afaf18SBorislav Petkov 214021afaf18SBorislav Petkov /* 214121afaf18SBorislav Petkov * mce=off Disables machine check 214221afaf18SBorislav Petkov * mce=no_cmci Disables CMCI 214321afaf18SBorislav Petkov * mce=no_lmce Disables LMCE 214421afaf18SBorislav Petkov * mce=dont_log_ce Clears corrected events silently, no log created for CEs. 214543505646STony Luck * mce=print_all Print all machine check logs to console 214621afaf18SBorislav Petkov * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. 214721afaf18SBorislav Petkov * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) 214821afaf18SBorislav Petkov * monarchtimeout is how long to wait for other CPUs on machine 214921afaf18SBorislav Petkov * check, or 0 to not wait 215021afaf18SBorislav Petkov * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h 215121afaf18SBorislav Petkov and older. 215221afaf18SBorislav Petkov * mce=nobootlog Don't log MCEs from before booting. 215321afaf18SBorislav Petkov * mce=bios_cmci_threshold Don't program the CMCI threshold 2154ec6347bbSDan Williams * mce=recovery force enable copy_mc_fragile() 215521afaf18SBorislav Petkov */ 215621afaf18SBorislav Petkov static int __init mcheck_enable(char *str) 215721afaf18SBorislav Petkov { 215821afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 215921afaf18SBorislav Petkov 216021afaf18SBorislav Petkov if (*str == 0) { 216121afaf18SBorislav Petkov enable_p5_mce(); 216221afaf18SBorislav Petkov return 1; 216321afaf18SBorislav Petkov } 216421afaf18SBorislav Petkov if (*str == '=') 216521afaf18SBorislav Petkov str++; 216621afaf18SBorislav Petkov if (!strcmp(str, "off")) 216721afaf18SBorislav Petkov cfg->disabled = 1; 216821afaf18SBorislav Petkov else if (!strcmp(str, "no_cmci")) 216921afaf18SBorislav Petkov cfg->cmci_disabled = true; 217021afaf18SBorislav Petkov else if (!strcmp(str, "no_lmce")) 217121afaf18SBorislav Petkov cfg->lmce_disabled = 1; 217221afaf18SBorislav Petkov else if (!strcmp(str, "dont_log_ce")) 217321afaf18SBorislav Petkov cfg->dont_log_ce = true; 217443505646STony Luck else if (!strcmp(str, "print_all")) 217543505646STony Luck cfg->print_all = true; 217621afaf18SBorislav Petkov else if (!strcmp(str, "ignore_ce")) 217721afaf18SBorislav Petkov cfg->ignore_ce = true; 217821afaf18SBorislav Petkov else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) 217921afaf18SBorislav Petkov cfg->bootlog = (str[0] == 'b'); 218021afaf18SBorislav Petkov else if (!strcmp(str, "bios_cmci_threshold")) 218121afaf18SBorislav Petkov cfg->bios_cmci_threshold = 1; 218221afaf18SBorislav Petkov else if (!strcmp(str, "recovery")) 218321afaf18SBorislav Petkov cfg->recovery = 1; 218421afaf18SBorislav Petkov else if (isdigit(str[0])) { 218521afaf18SBorislav Petkov if (get_option(&str, &cfg->tolerant) == 2) 218621afaf18SBorislav Petkov get_option(&str, &(cfg->monarch_timeout)); 218721afaf18SBorislav Petkov } else { 218821afaf18SBorislav Petkov pr_info("mce argument %s ignored. Please use /sys\n", str); 218921afaf18SBorislav Petkov return 0; 219021afaf18SBorislav Petkov } 219121afaf18SBorislav Petkov return 1; 219221afaf18SBorislav Petkov } 219321afaf18SBorislav Petkov __setup("mce", mcheck_enable); 219421afaf18SBorislav Petkov 219521afaf18SBorislav Petkov int __init mcheck_init(void) 219621afaf18SBorislav Petkov { 2197c9c6d216STony Luck mce_register_decode_chain(&early_nb); 21988438b84aSJan H. Schönherr mce_register_decode_chain(&mce_uc_nb); 219921afaf18SBorislav Petkov mce_register_decode_chain(&mce_default_nb); 220021afaf18SBorislav Petkov 220121afaf18SBorislav Petkov INIT_WORK(&mce_work, mce_gen_pool_process); 220221afaf18SBorislav Petkov init_irq_work(&mce_irq_work, mce_irq_work_cb); 220321afaf18SBorislav Petkov 220421afaf18SBorislav Petkov return 0; 220521afaf18SBorislav Petkov } 220621afaf18SBorislav Petkov 220721afaf18SBorislav Petkov /* 220821afaf18SBorislav Petkov * mce_syscore: PM support 220921afaf18SBorislav Petkov */ 221021afaf18SBorislav Petkov 221121afaf18SBorislav Petkov /* 221221afaf18SBorislav Petkov * Disable machine checks on suspend and shutdown. We can't really handle 221321afaf18SBorislav Petkov * them later. 221421afaf18SBorislav Petkov */ 221521afaf18SBorislav Petkov static void mce_disable_error_reporting(void) 221621afaf18SBorislav Petkov { 2217b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 221821afaf18SBorislav Petkov int i; 221921afaf18SBorislav Petkov 2220c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 222121afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 222221afaf18SBorislav Petkov 222321afaf18SBorislav Petkov if (b->init) 2224*8121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), 0); 222521afaf18SBorislav Petkov } 222621afaf18SBorislav Petkov return; 222721afaf18SBorislav Petkov } 222821afaf18SBorislav Petkov 222921afaf18SBorislav Petkov static void vendor_disable_error_reporting(void) 223021afaf18SBorislav Petkov { 223121afaf18SBorislav Petkov /* 22326e898d2bSTony W Wang-oc * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these 22336e898d2bSTony W Wang-oc * MSRs are socket-wide. Disabling them for just a single offlined CPU 22346e898d2bSTony W Wang-oc * is bad, since it will inhibit reporting for all shared resources on 22356e898d2bSTony W Wang-oc * the socket like the last level cache (LLC), the integrated memory 22366e898d2bSTony W Wang-oc * controller (iMC), etc. 223721afaf18SBorislav Petkov */ 223821afaf18SBorislav Petkov if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || 223921afaf18SBorislav Petkov boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || 22406e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 22416e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) 224221afaf18SBorislav Petkov return; 224321afaf18SBorislav Petkov 224421afaf18SBorislav Petkov mce_disable_error_reporting(); 224521afaf18SBorislav Petkov } 224621afaf18SBorislav Petkov 224721afaf18SBorislav Petkov static int mce_syscore_suspend(void) 224821afaf18SBorislav Petkov { 224921afaf18SBorislav Petkov vendor_disable_error_reporting(); 225021afaf18SBorislav Petkov return 0; 225121afaf18SBorislav Petkov } 225221afaf18SBorislav Petkov 225321afaf18SBorislav Petkov static void mce_syscore_shutdown(void) 225421afaf18SBorislav Petkov { 225521afaf18SBorislav Petkov vendor_disable_error_reporting(); 225621afaf18SBorislav Petkov } 225721afaf18SBorislav Petkov 225821afaf18SBorislav Petkov /* 225921afaf18SBorislav Petkov * On resume clear all MCE state. Don't want to see leftovers from the BIOS. 226021afaf18SBorislav Petkov * Only one CPU is active at this time, the others get re-added later using 226121afaf18SBorislav Petkov * CPU hotplug: 226221afaf18SBorislav Petkov */ 226321afaf18SBorislav Petkov static void mce_syscore_resume(void) 226421afaf18SBorislav Petkov { 226521afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 226621afaf18SBorislav Petkov __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); 226721afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 226821afaf18SBorislav Petkov } 226921afaf18SBorislav Petkov 227021afaf18SBorislav Petkov static struct syscore_ops mce_syscore_ops = { 227121afaf18SBorislav Petkov .suspend = mce_syscore_suspend, 227221afaf18SBorislav Petkov .shutdown = mce_syscore_shutdown, 227321afaf18SBorislav Petkov .resume = mce_syscore_resume, 227421afaf18SBorislav Petkov }; 227521afaf18SBorislav Petkov 227621afaf18SBorislav Petkov /* 227721afaf18SBorislav Petkov * mce_device: Sysfs support 227821afaf18SBorislav Petkov */ 227921afaf18SBorislav Petkov 228021afaf18SBorislav Petkov static void mce_cpu_restart(void *data) 228121afaf18SBorislav Petkov { 228221afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 228321afaf18SBorislav Petkov return; 228421afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 228521afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 228621afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 228721afaf18SBorislav Petkov } 228821afaf18SBorislav Petkov 228921afaf18SBorislav Petkov /* Reinit MCEs after user configuration changes */ 229021afaf18SBorislav Petkov static void mce_restart(void) 229121afaf18SBorislav Petkov { 229221afaf18SBorislav Petkov mce_timer_delete_all(); 229321afaf18SBorislav Petkov on_each_cpu(mce_cpu_restart, NULL, 1); 229421afaf18SBorislav Petkov } 229521afaf18SBorislav Petkov 229621afaf18SBorislav Petkov /* Toggle features for corrected errors */ 229721afaf18SBorislav Petkov static void mce_disable_cmci(void *data) 229821afaf18SBorislav Petkov { 229921afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 230021afaf18SBorislav Petkov return; 230121afaf18SBorislav Petkov cmci_clear(); 230221afaf18SBorislav Petkov } 230321afaf18SBorislav Petkov 230421afaf18SBorislav Petkov static void mce_enable_ce(void *all) 230521afaf18SBorislav Petkov { 230621afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 230721afaf18SBorislav Petkov return; 230821afaf18SBorislav Petkov cmci_reenable(); 230921afaf18SBorislav Petkov cmci_recheck(); 231021afaf18SBorislav Petkov if (all) 231121afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 231221afaf18SBorislav Petkov } 231321afaf18SBorislav Petkov 231421afaf18SBorislav Petkov static struct bus_type mce_subsys = { 231521afaf18SBorislav Petkov .name = "machinecheck", 231621afaf18SBorislav Petkov .dev_name = "machinecheck", 231721afaf18SBorislav Petkov }; 231821afaf18SBorislav Petkov 231921afaf18SBorislav Petkov DEFINE_PER_CPU(struct device *, mce_device); 232021afaf18SBorislav Petkov 2321b4914508SYazen Ghannam static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr) 232221afaf18SBorislav Petkov { 2323b4914508SYazen Ghannam return container_of(attr, struct mce_bank_dev, attr); 232421afaf18SBorislav Petkov } 232521afaf18SBorislav Petkov 232621afaf18SBorislav Petkov static ssize_t show_bank(struct device *s, struct device_attribute *attr, 232721afaf18SBorislav Petkov char *buf) 232821afaf18SBorislav Petkov { 2329b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2330b4914508SYazen Ghannam struct mce_bank *b; 2331b4914508SYazen Ghannam 2332c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2333b4914508SYazen Ghannam return -EINVAL; 2334b4914508SYazen Ghannam 2335b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2336b4914508SYazen Ghannam 2337068b053dSYazen Ghannam if (!b->init) 2338068b053dSYazen Ghannam return -ENODEV; 2339068b053dSYazen Ghannam 2340b4914508SYazen Ghannam return sprintf(buf, "%llx\n", b->ctl); 234121afaf18SBorislav Petkov } 234221afaf18SBorislav Petkov 234321afaf18SBorislav Petkov static ssize_t set_bank(struct device *s, struct device_attribute *attr, 234421afaf18SBorislav Petkov const char *buf, size_t size) 234521afaf18SBorislav Petkov { 2346b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2347b4914508SYazen Ghannam struct mce_bank *b; 234821afaf18SBorislav Petkov u64 new; 234921afaf18SBorislav Petkov 235021afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 235121afaf18SBorislav Petkov return -EINVAL; 235221afaf18SBorislav Petkov 2353c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2354b4914508SYazen Ghannam return -EINVAL; 2355b4914508SYazen Ghannam 2356b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2357b4914508SYazen Ghannam 2358068b053dSYazen Ghannam if (!b->init) 2359068b053dSYazen Ghannam return -ENODEV; 2360068b053dSYazen Ghannam 2361b4914508SYazen Ghannam b->ctl = new; 236221afaf18SBorislav Petkov mce_restart(); 236321afaf18SBorislav Petkov 236421afaf18SBorislav Petkov return size; 236521afaf18SBorislav Petkov } 236621afaf18SBorislav Petkov 236721afaf18SBorislav Petkov static ssize_t set_ignore_ce(struct device *s, 236821afaf18SBorislav Petkov struct device_attribute *attr, 236921afaf18SBorislav Petkov const char *buf, size_t size) 237021afaf18SBorislav Petkov { 237121afaf18SBorislav Petkov u64 new; 237221afaf18SBorislav Petkov 237321afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 237421afaf18SBorislav Petkov return -EINVAL; 237521afaf18SBorislav Petkov 237621afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 237721afaf18SBorislav Petkov if (mca_cfg.ignore_ce ^ !!new) { 237821afaf18SBorislav Petkov if (new) { 237921afaf18SBorislav Petkov /* disable ce features */ 238021afaf18SBorislav Petkov mce_timer_delete_all(); 238121afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 238221afaf18SBorislav Petkov mca_cfg.ignore_ce = true; 238321afaf18SBorislav Petkov } else { 238421afaf18SBorislav Petkov /* enable ce features */ 238521afaf18SBorislav Petkov mca_cfg.ignore_ce = false; 238621afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, (void *)1, 1); 238721afaf18SBorislav Petkov } 238821afaf18SBorislav Petkov } 238921afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 239021afaf18SBorislav Petkov 239121afaf18SBorislav Petkov return size; 239221afaf18SBorislav Petkov } 239321afaf18SBorislav Petkov 239421afaf18SBorislav Petkov static ssize_t set_cmci_disabled(struct device *s, 239521afaf18SBorislav Petkov struct device_attribute *attr, 239621afaf18SBorislav Petkov const char *buf, size_t size) 239721afaf18SBorislav Petkov { 239821afaf18SBorislav Petkov u64 new; 239921afaf18SBorislav Petkov 240021afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 240121afaf18SBorislav Petkov return -EINVAL; 240221afaf18SBorislav Petkov 240321afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 240421afaf18SBorislav Petkov if (mca_cfg.cmci_disabled ^ !!new) { 240521afaf18SBorislav Petkov if (new) { 240621afaf18SBorislav Petkov /* disable cmci */ 240721afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 240821afaf18SBorislav Petkov mca_cfg.cmci_disabled = true; 240921afaf18SBorislav Petkov } else { 241021afaf18SBorislav Petkov /* enable cmci */ 241121afaf18SBorislav Petkov mca_cfg.cmci_disabled = false; 241221afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, NULL, 1); 241321afaf18SBorislav Petkov } 241421afaf18SBorislav Petkov } 241521afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 241621afaf18SBorislav Petkov 241721afaf18SBorislav Petkov return size; 241821afaf18SBorislav Petkov } 241921afaf18SBorislav Petkov 242021afaf18SBorislav Petkov static ssize_t store_int_with_restart(struct device *s, 242121afaf18SBorislav Petkov struct device_attribute *attr, 242221afaf18SBorislav Petkov const char *buf, size_t size) 242321afaf18SBorislav Petkov { 242421afaf18SBorislav Petkov unsigned long old_check_interval = check_interval; 242521afaf18SBorislav Petkov ssize_t ret = device_store_ulong(s, attr, buf, size); 242621afaf18SBorislav Petkov 242721afaf18SBorislav Petkov if (check_interval == old_check_interval) 242821afaf18SBorislav Petkov return ret; 242921afaf18SBorislav Petkov 243021afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 243121afaf18SBorislav Petkov mce_restart(); 243221afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 243321afaf18SBorislav Petkov 243421afaf18SBorislav Petkov return ret; 243521afaf18SBorislav Petkov } 243621afaf18SBorislav Petkov 243721afaf18SBorislav Petkov static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); 243821afaf18SBorislav Petkov static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); 243921afaf18SBorislav Petkov static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); 244043505646STony Luck static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all); 244121afaf18SBorislav Petkov 244221afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_check_interval = { 244321afaf18SBorislav Petkov __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), 244421afaf18SBorislav Petkov &check_interval 244521afaf18SBorislav Petkov }; 244621afaf18SBorislav Petkov 244721afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_ignore_ce = { 244821afaf18SBorislav Petkov __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), 244921afaf18SBorislav Petkov &mca_cfg.ignore_ce 245021afaf18SBorislav Petkov }; 245121afaf18SBorislav Petkov 245221afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_cmci_disabled = { 245321afaf18SBorislav Petkov __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), 245421afaf18SBorislav Petkov &mca_cfg.cmci_disabled 245521afaf18SBorislav Petkov }; 245621afaf18SBorislav Petkov 245721afaf18SBorislav Petkov static struct device_attribute *mce_device_attrs[] = { 245821afaf18SBorislav Petkov &dev_attr_tolerant.attr, 245921afaf18SBorislav Petkov &dev_attr_check_interval.attr, 246021afaf18SBorislav Petkov #ifdef CONFIG_X86_MCELOG_LEGACY 246121afaf18SBorislav Petkov &dev_attr_trigger, 246221afaf18SBorislav Petkov #endif 246321afaf18SBorislav Petkov &dev_attr_monarch_timeout.attr, 246421afaf18SBorislav Petkov &dev_attr_dont_log_ce.attr, 246543505646STony Luck &dev_attr_print_all.attr, 246621afaf18SBorislav Petkov &dev_attr_ignore_ce.attr, 246721afaf18SBorislav Petkov &dev_attr_cmci_disabled.attr, 246821afaf18SBorislav Petkov NULL 246921afaf18SBorislav Petkov }; 247021afaf18SBorislav Petkov 247121afaf18SBorislav Petkov static cpumask_var_t mce_device_initialized; 247221afaf18SBorislav Petkov 247321afaf18SBorislav Petkov static void mce_device_release(struct device *dev) 247421afaf18SBorislav Petkov { 247521afaf18SBorislav Petkov kfree(dev); 247621afaf18SBorislav Petkov } 247721afaf18SBorislav Petkov 2478b4914508SYazen Ghannam /* Per CPU device init. All of the CPUs still share the same bank device: */ 247921afaf18SBorislav Petkov static int mce_device_create(unsigned int cpu) 248021afaf18SBorislav Petkov { 248121afaf18SBorislav Petkov struct device *dev; 248221afaf18SBorislav Petkov int err; 248321afaf18SBorislav Petkov int i, j; 248421afaf18SBorislav Petkov 248521afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) 248621afaf18SBorislav Petkov return -EIO; 248721afaf18SBorislav Petkov 248821afaf18SBorislav Petkov dev = per_cpu(mce_device, cpu); 248921afaf18SBorislav Petkov if (dev) 249021afaf18SBorislav Petkov return 0; 249121afaf18SBorislav Petkov 249221afaf18SBorislav Petkov dev = kzalloc(sizeof(*dev), GFP_KERNEL); 249321afaf18SBorislav Petkov if (!dev) 249421afaf18SBorislav Petkov return -ENOMEM; 249521afaf18SBorislav Petkov dev->id = cpu; 249621afaf18SBorislav Petkov dev->bus = &mce_subsys; 249721afaf18SBorislav Petkov dev->release = &mce_device_release; 249821afaf18SBorislav Petkov 249921afaf18SBorislav Petkov err = device_register(dev); 250021afaf18SBorislav Petkov if (err) { 250121afaf18SBorislav Petkov put_device(dev); 250221afaf18SBorislav Petkov return err; 250321afaf18SBorislav Petkov } 250421afaf18SBorislav Petkov 250521afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) { 250621afaf18SBorislav Petkov err = device_create_file(dev, mce_device_attrs[i]); 250721afaf18SBorislav Petkov if (err) 250821afaf18SBorislav Petkov goto error; 250921afaf18SBorislav Petkov } 2510c7d314f3SYazen Ghannam for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) { 2511b4914508SYazen Ghannam err = device_create_file(dev, &mce_bank_devs[j].attr); 251221afaf18SBorislav Petkov if (err) 251321afaf18SBorislav Petkov goto error2; 251421afaf18SBorislav Petkov } 251521afaf18SBorislav Petkov cpumask_set_cpu(cpu, mce_device_initialized); 251621afaf18SBorislav Petkov per_cpu(mce_device, cpu) = dev; 251721afaf18SBorislav Petkov 251821afaf18SBorislav Petkov return 0; 251921afaf18SBorislav Petkov error2: 252021afaf18SBorislav Petkov while (--j >= 0) 2521b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[j].attr); 252221afaf18SBorislav Petkov error: 252321afaf18SBorislav Petkov while (--i >= 0) 252421afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 252521afaf18SBorislav Petkov 252621afaf18SBorislav Petkov device_unregister(dev); 252721afaf18SBorislav Petkov 252821afaf18SBorislav Petkov return err; 252921afaf18SBorislav Petkov } 253021afaf18SBorislav Petkov 253121afaf18SBorislav Petkov static void mce_device_remove(unsigned int cpu) 253221afaf18SBorislav Petkov { 253321afaf18SBorislav Petkov struct device *dev = per_cpu(mce_device, cpu); 253421afaf18SBorislav Petkov int i; 253521afaf18SBorislav Petkov 253621afaf18SBorislav Petkov if (!cpumask_test_cpu(cpu, mce_device_initialized)) 253721afaf18SBorislav Petkov return; 253821afaf18SBorislav Petkov 253921afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) 254021afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 254121afaf18SBorislav Petkov 2542c7d314f3SYazen Ghannam for (i = 0; i < per_cpu(mce_num_banks, cpu); i++) 2543b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[i].attr); 254421afaf18SBorislav Petkov 254521afaf18SBorislav Petkov device_unregister(dev); 254621afaf18SBorislav Petkov cpumask_clear_cpu(cpu, mce_device_initialized); 254721afaf18SBorislav Petkov per_cpu(mce_device, cpu) = NULL; 254821afaf18SBorislav Petkov } 254921afaf18SBorislav Petkov 255021afaf18SBorislav Petkov /* Make sure there are no machine checks on offlined CPUs. */ 255121afaf18SBorislav Petkov static void mce_disable_cpu(void) 255221afaf18SBorislav Petkov { 255321afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 255421afaf18SBorislav Petkov return; 255521afaf18SBorislav Petkov 255621afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 255721afaf18SBorislav Petkov cmci_clear(); 255821afaf18SBorislav Petkov 255921afaf18SBorislav Petkov vendor_disable_error_reporting(); 256021afaf18SBorislav Petkov } 256121afaf18SBorislav Petkov 256221afaf18SBorislav Petkov static void mce_reenable_cpu(void) 256321afaf18SBorislav Petkov { 2564b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 256521afaf18SBorislav Petkov int i; 256621afaf18SBorislav Petkov 256721afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 256821afaf18SBorislav Petkov return; 256921afaf18SBorislav Petkov 257021afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 257121afaf18SBorislav Petkov cmci_reenable(); 2572c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 257321afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 257421afaf18SBorislav Petkov 257521afaf18SBorislav Petkov if (b->init) 2576*8121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); 257721afaf18SBorislav Petkov } 257821afaf18SBorislav Petkov } 257921afaf18SBorislav Petkov 258021afaf18SBorislav Petkov static int mce_cpu_dead(unsigned int cpu) 258121afaf18SBorislav Petkov { 258221afaf18SBorislav Petkov mce_intel_hcpu_update(cpu); 258321afaf18SBorislav Petkov 258421afaf18SBorislav Petkov /* intentionally ignoring frozen here */ 258521afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 258621afaf18SBorislav Petkov cmci_rediscover(); 258721afaf18SBorislav Petkov return 0; 258821afaf18SBorislav Petkov } 258921afaf18SBorislav Petkov 259021afaf18SBorislav Petkov static int mce_cpu_online(unsigned int cpu) 259121afaf18SBorislav Petkov { 259221afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 259321afaf18SBorislav Petkov int ret; 259421afaf18SBorislav Petkov 259521afaf18SBorislav Petkov mce_device_create(cpu); 259621afaf18SBorislav Petkov 259721afaf18SBorislav Petkov ret = mce_threshold_create_device(cpu); 259821afaf18SBorislav Petkov if (ret) { 259921afaf18SBorislav Petkov mce_device_remove(cpu); 260021afaf18SBorislav Petkov return ret; 260121afaf18SBorislav Petkov } 260221afaf18SBorislav Petkov mce_reenable_cpu(); 260321afaf18SBorislav Petkov mce_start_timer(t); 260421afaf18SBorislav Petkov return 0; 260521afaf18SBorislav Petkov } 260621afaf18SBorislav Petkov 260721afaf18SBorislav Petkov static int mce_cpu_pre_down(unsigned int cpu) 260821afaf18SBorislav Petkov { 260921afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 261021afaf18SBorislav Petkov 261121afaf18SBorislav Petkov mce_disable_cpu(); 261221afaf18SBorislav Petkov del_timer_sync(t); 261321afaf18SBorislav Petkov mce_threshold_remove_device(cpu); 261421afaf18SBorislav Petkov mce_device_remove(cpu); 261521afaf18SBorislav Petkov return 0; 261621afaf18SBorislav Petkov } 261721afaf18SBorislav Petkov 261821afaf18SBorislav Petkov static __init void mce_init_banks(void) 261921afaf18SBorislav Petkov { 262021afaf18SBorislav Petkov int i; 262121afaf18SBorislav Petkov 2622b4914508SYazen Ghannam for (i = 0; i < MAX_NR_BANKS; i++) { 2623b4914508SYazen Ghannam struct mce_bank_dev *b = &mce_bank_devs[i]; 262421afaf18SBorislav Petkov struct device_attribute *a = &b->attr; 262521afaf18SBorislav Petkov 2626b4914508SYazen Ghannam b->bank = i; 2627b4914508SYazen Ghannam 262821afaf18SBorislav Petkov sysfs_attr_init(&a->attr); 262921afaf18SBorislav Petkov a->attr.name = b->attrname; 263021afaf18SBorislav Petkov snprintf(b->attrname, ATTR_LEN, "bank%d", i); 263121afaf18SBorislav Petkov 263221afaf18SBorislav Petkov a->attr.mode = 0644; 263321afaf18SBorislav Petkov a->show = show_bank; 263421afaf18SBorislav Petkov a->store = set_bank; 263521afaf18SBorislav Petkov } 263621afaf18SBorislav Petkov } 263721afaf18SBorislav Petkov 26386e7a41c6SThomas Gleixner /* 26396e7a41c6SThomas Gleixner * When running on XEN, this initcall is ordered against the XEN mcelog 26406e7a41c6SThomas Gleixner * initcall: 26416e7a41c6SThomas Gleixner * 26426e7a41c6SThomas Gleixner * device_initcall(xen_late_init_mcelog); 26436e7a41c6SThomas Gleixner * device_initcall_sync(mcheck_init_device); 26446e7a41c6SThomas Gleixner */ 264521afaf18SBorislav Petkov static __init int mcheck_init_device(void) 264621afaf18SBorislav Petkov { 264721afaf18SBorislav Petkov int err; 264821afaf18SBorislav Petkov 264921afaf18SBorislav Petkov /* 265021afaf18SBorislav Petkov * Check if we have a spare virtual bit. This will only become 265121afaf18SBorislav Petkov * a problem if/when we move beyond 5-level page tables. 265221afaf18SBorislav Petkov */ 265321afaf18SBorislav Petkov MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63); 265421afaf18SBorislav Petkov 265521afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) { 265621afaf18SBorislav Petkov err = -EIO; 265721afaf18SBorislav Petkov goto err_out; 265821afaf18SBorislav Petkov } 265921afaf18SBorislav Petkov 266021afaf18SBorislav Petkov if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { 266121afaf18SBorislav Petkov err = -ENOMEM; 266221afaf18SBorislav Petkov goto err_out; 266321afaf18SBorislav Petkov } 266421afaf18SBorislav Petkov 266521afaf18SBorislav Petkov mce_init_banks(); 266621afaf18SBorislav Petkov 266721afaf18SBorislav Petkov err = subsys_system_register(&mce_subsys, NULL); 266821afaf18SBorislav Petkov if (err) 266921afaf18SBorislav Petkov goto err_out_mem; 267021afaf18SBorislav Petkov 267121afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL, 267221afaf18SBorislav Petkov mce_cpu_dead); 267321afaf18SBorislav Petkov if (err) 267421afaf18SBorislav Petkov goto err_out_mem; 267521afaf18SBorislav Petkov 26766e7a41c6SThomas Gleixner /* 26776e7a41c6SThomas Gleixner * Invokes mce_cpu_online() on all CPUs which are online when 26786e7a41c6SThomas Gleixner * the state is installed. 26796e7a41c6SThomas Gleixner */ 268021afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online", 268121afaf18SBorislav Petkov mce_cpu_online, mce_cpu_pre_down); 268221afaf18SBorislav Petkov if (err < 0) 268321afaf18SBorislav Petkov goto err_out_online; 268421afaf18SBorislav Petkov 268521afaf18SBorislav Petkov register_syscore_ops(&mce_syscore_ops); 268621afaf18SBorislav Petkov 268721afaf18SBorislav Petkov return 0; 268821afaf18SBorislav Petkov 268921afaf18SBorislav Petkov err_out_online: 269021afaf18SBorislav Petkov cpuhp_remove_state(CPUHP_X86_MCE_DEAD); 269121afaf18SBorislav Petkov 269221afaf18SBorislav Petkov err_out_mem: 269321afaf18SBorislav Petkov free_cpumask_var(mce_device_initialized); 269421afaf18SBorislav Petkov 269521afaf18SBorislav Petkov err_out: 269621afaf18SBorislav Petkov pr_err("Unable to init MCE device (rc: %d)\n", err); 269721afaf18SBorislav Petkov 269821afaf18SBorislav Petkov return err; 269921afaf18SBorislav Petkov } 270021afaf18SBorislav Petkov device_initcall_sync(mcheck_init_device); 270121afaf18SBorislav Petkov 270221afaf18SBorislav Petkov /* 270321afaf18SBorislav Petkov * Old style boot options parsing. Only for compatibility. 270421afaf18SBorislav Petkov */ 270521afaf18SBorislav Petkov static int __init mcheck_disable(char *str) 270621afaf18SBorislav Petkov { 270721afaf18SBorislav Petkov mca_cfg.disabled = 1; 270821afaf18SBorislav Petkov return 1; 270921afaf18SBorislav Petkov } 271021afaf18SBorislav Petkov __setup("nomce", mcheck_disable); 271121afaf18SBorislav Petkov 271221afaf18SBorislav Petkov #ifdef CONFIG_DEBUG_FS 271321afaf18SBorislav Petkov struct dentry *mce_get_debugfs_dir(void) 271421afaf18SBorislav Petkov { 271521afaf18SBorislav Petkov static struct dentry *dmce; 271621afaf18SBorislav Petkov 271721afaf18SBorislav Petkov if (!dmce) 271821afaf18SBorislav Petkov dmce = debugfs_create_dir("mce", NULL); 271921afaf18SBorislav Petkov 272021afaf18SBorislav Petkov return dmce; 272121afaf18SBorislav Petkov } 272221afaf18SBorislav Petkov 272321afaf18SBorislav Petkov static void mce_reset(void) 272421afaf18SBorislav Petkov { 272521afaf18SBorislav Petkov cpu_missing = 0; 272621afaf18SBorislav Petkov atomic_set(&mce_fake_panicked, 0); 272721afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 272821afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 272921afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 27307bb39313SPaul E. McKenney cpumask_setall(&mce_missing_cpus); 273121afaf18SBorislav Petkov } 273221afaf18SBorislav Petkov 273321afaf18SBorislav Petkov static int fake_panic_get(void *data, u64 *val) 273421afaf18SBorislav Petkov { 273521afaf18SBorislav Petkov *val = fake_panic; 273621afaf18SBorislav Petkov return 0; 273721afaf18SBorislav Petkov } 273821afaf18SBorislav Petkov 273921afaf18SBorislav Petkov static int fake_panic_set(void *data, u64 val) 274021afaf18SBorislav Petkov { 274121afaf18SBorislav Petkov mce_reset(); 274221afaf18SBorislav Petkov fake_panic = val; 274321afaf18SBorislav Petkov return 0; 274421afaf18SBorislav Petkov } 274521afaf18SBorislav Petkov 274628156d76SYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set, 274728156d76SYueHaibing "%llu\n"); 274821afaf18SBorislav Petkov 27496e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) 275021afaf18SBorislav Petkov { 27516e4f929eSGreg Kroah-Hartman struct dentry *dmce; 275221afaf18SBorislav Petkov 275321afaf18SBorislav Petkov dmce = mce_get_debugfs_dir(); 27546e4f929eSGreg Kroah-Hartman debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL, 27556e4f929eSGreg Kroah-Hartman &fake_panic_fops); 275621afaf18SBorislav Petkov } 275721afaf18SBorislav Petkov #else 27586e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) { } 275921afaf18SBorislav Petkov #endif 276021afaf18SBorislav Petkov 276121afaf18SBorislav Petkov static int __init mcheck_late_init(void) 276221afaf18SBorislav Petkov { 276321afaf18SBorislav Petkov if (mca_cfg.recovery) 2764ec6347bbSDan Williams enable_copy_mc_fragile(); 276521afaf18SBorislav Petkov 276621afaf18SBorislav Petkov mcheck_debugfs_init(); 276721afaf18SBorislav Petkov 276821afaf18SBorislav Petkov /* 276921afaf18SBorislav Petkov * Flush out everything that has been logged during early boot, now that 277021afaf18SBorislav Petkov * everything has been initialized (workqueues, decoders, ...). 277121afaf18SBorislav Petkov */ 277221afaf18SBorislav Petkov mce_schedule_work(); 277321afaf18SBorislav Petkov 277421afaf18SBorislav Petkov return 0; 277521afaf18SBorislav Petkov } 277621afaf18SBorislav Petkov late_initcall(mcheck_late_init); 2777