1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 221afaf18SBorislav Petkov /* 321afaf18SBorislav Petkov * Machine check handler. 421afaf18SBorislav Petkov * 521afaf18SBorislav Petkov * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. 621afaf18SBorislav Petkov * Rest from unknown author(s). 721afaf18SBorislav Petkov * 2004 Andi Kleen. Rewrote most of it. 821afaf18SBorislav Petkov * Copyright 2008 Intel Corporation 921afaf18SBorislav Petkov * Author: Andi Kleen 1021afaf18SBorislav Petkov */ 1121afaf18SBorislav Petkov 1221afaf18SBorislav Petkov #include <linux/thread_info.h> 1321afaf18SBorislav Petkov #include <linux/capability.h> 1421afaf18SBorislav Petkov #include <linux/miscdevice.h> 1521afaf18SBorislav Petkov #include <linux/ratelimit.h> 1621afaf18SBorislav Petkov #include <linux/rcupdate.h> 1721afaf18SBorislav Petkov #include <linux/kobject.h> 1821afaf18SBorislav Petkov #include <linux/uaccess.h> 1921afaf18SBorislav Petkov #include <linux/kdebug.h> 2021afaf18SBorislav Petkov #include <linux/kernel.h> 2121afaf18SBorislav Petkov #include <linux/percpu.h> 2221afaf18SBorislav Petkov #include <linux/string.h> 2321afaf18SBorislav Petkov #include <linux/device.h> 2421afaf18SBorislav Petkov #include <linux/syscore_ops.h> 2521afaf18SBorislav Petkov #include <linux/delay.h> 2621afaf18SBorislav Petkov #include <linux/ctype.h> 2721afaf18SBorislav Petkov #include <linux/sched.h> 2821afaf18SBorislav Petkov #include <linux/sysfs.h> 2921afaf18SBorislav Petkov #include <linux/types.h> 3021afaf18SBorislav Petkov #include <linux/slab.h> 3121afaf18SBorislav Petkov #include <linux/init.h> 3221afaf18SBorislav Petkov #include <linux/kmod.h> 3321afaf18SBorislav Petkov #include <linux/poll.h> 3421afaf18SBorislav Petkov #include <linux/nmi.h> 3521afaf18SBorislav Petkov #include <linux/cpu.h> 3621afaf18SBorislav Petkov #include <linux/ras.h> 3721afaf18SBorislav Petkov #include <linux/smp.h> 3821afaf18SBorislav Petkov #include <linux/fs.h> 3921afaf18SBorislav Petkov #include <linux/mm.h> 4021afaf18SBorislav Petkov #include <linux/debugfs.h> 4121afaf18SBorislav Petkov #include <linux/irq_work.h> 4221afaf18SBorislav Petkov #include <linux/export.h> 4321afaf18SBorislav Petkov #include <linux/set_memory.h> 449998a983SRicardo Neri #include <linux/sync_core.h> 455567d11cSPeter Zijlstra #include <linux/task_work.h> 460d00449cSPeter Zijlstra #include <linux/hardirq.h> 4721afaf18SBorislav Petkov 4821afaf18SBorislav Petkov #include <asm/intel-family.h> 4921afaf18SBorislav Petkov #include <asm/processor.h> 5021afaf18SBorislav Petkov #include <asm/traps.h> 5121afaf18SBorislav Petkov #include <asm/tlbflush.h> 5221afaf18SBorislav Petkov #include <asm/mce.h> 5321afaf18SBorislav Petkov #include <asm/msr.h> 5421afaf18SBorislav Petkov #include <asm/reboot.h> 5521afaf18SBorislav Petkov 5621afaf18SBorislav Petkov #include "internal.h" 5721afaf18SBorislav Petkov 5821afaf18SBorislav Petkov /* sysfs synchronization */ 5921afaf18SBorislav Petkov static DEFINE_MUTEX(mce_sysfs_mutex); 6021afaf18SBorislav Petkov 6121afaf18SBorislav Petkov #define CREATE_TRACE_POINTS 6221afaf18SBorislav Petkov #include <trace/events/mce.h> 6321afaf18SBorislav Petkov 6421afaf18SBorislav Petkov #define SPINUNIT 100 /* 100ns */ 6521afaf18SBorislav Petkov 6621afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_exception_count); 6721afaf18SBorislav Petkov 68c7d314f3SYazen Ghannam DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks); 69c7d314f3SYazen Ghannam 7095fdce6bSYazen Ghannam struct mce_bank { 7195fdce6bSYazen Ghannam u64 ctl; /* subevents to enable */ 7295fdce6bSYazen Ghannam bool init; /* initialise bank? */ 73b4914508SYazen Ghannam }; 74b4914508SYazen Ghannam static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); 75b4914508SYazen Ghannam 76b4914508SYazen Ghannam #define ATTR_LEN 16 77b4914508SYazen Ghannam /* One object for each MCE bank, shared by all CPUs */ 78b4914508SYazen Ghannam struct mce_bank_dev { 7995fdce6bSYazen Ghannam struct device_attribute attr; /* device attribute */ 8095fdce6bSYazen Ghannam char attrname[ATTR_LEN]; /* attribute name */ 81b4914508SYazen Ghannam u8 bank; /* bank number */ 8295fdce6bSYazen Ghannam }; 83b4914508SYazen Ghannam static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS]; 8495fdce6bSYazen Ghannam 8521afaf18SBorislav Petkov struct mce_vendor_flags mce_flags __read_mostly; 8621afaf18SBorislav Petkov 8721afaf18SBorislav Petkov struct mca_config mca_cfg __read_mostly = { 8821afaf18SBorislav Petkov .bootlog = -1, 8921afaf18SBorislav Petkov .monarch_timeout = -1 9021afaf18SBorislav Petkov }; 9121afaf18SBorislav Petkov 9221afaf18SBorislav Petkov static DEFINE_PER_CPU(struct mce, mces_seen); 9321afaf18SBorislav Petkov static unsigned long mce_need_notify; 9421afaf18SBorislav Petkov 9521afaf18SBorislav Petkov /* 9621afaf18SBorislav Petkov * MCA banks polled by the period polling timer for corrected events. 9721afaf18SBorislav Petkov * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). 9821afaf18SBorislav Petkov */ 9921afaf18SBorislav Petkov DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { 10021afaf18SBorislav Petkov [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL 10121afaf18SBorislav Petkov }; 10221afaf18SBorislav Petkov 10321afaf18SBorislav Petkov /* 10421afaf18SBorislav Petkov * MCA banks controlled through firmware first for corrected errors. 10521afaf18SBorislav Petkov * This is a global list of banks for which we won't enable CMCI and we 10621afaf18SBorislav Petkov * won't poll. Firmware controls these banks and is responsible for 10721afaf18SBorislav Petkov * reporting corrected errors through GHES. Uncorrected/recoverable 10821afaf18SBorislav Petkov * errors are still notified through a machine check. 10921afaf18SBorislav Petkov */ 11021afaf18SBorislav Petkov mce_banks_t mce_banks_ce_disabled; 11121afaf18SBorislav Petkov 11221afaf18SBorislav Petkov static struct work_struct mce_work; 11321afaf18SBorislav Petkov static struct irq_work mce_irq_work; 11421afaf18SBorislav Petkov 11521afaf18SBorislav Petkov /* 11621afaf18SBorislav Petkov * CPU/chipset specific EDAC code can register a notifier call here to print 11721afaf18SBorislav Petkov * MCE errors in a human-readable form. 11821afaf18SBorislav Petkov */ 11921afaf18SBorislav Petkov BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); 12021afaf18SBorislav Petkov 12121afaf18SBorislav Petkov /* Do initial initialization of a struct mce */ 122487d654dSBorislav Petkov void mce_setup(struct mce *m) 12321afaf18SBorislav Petkov { 12421afaf18SBorislav Petkov memset(m, 0, sizeof(struct mce)); 12521afaf18SBorislav Petkov m->cpu = m->extcpu = smp_processor_id(); 12621afaf18SBorislav Petkov /* need the internal __ version to avoid deadlocks */ 12721afaf18SBorislav Petkov m->time = __ktime_get_real_seconds(); 12821afaf18SBorislav Petkov m->cpuvendor = boot_cpu_data.x86_vendor; 12921afaf18SBorislav Petkov m->cpuid = cpuid_eax(1); 13021afaf18SBorislav Petkov m->socketid = cpu_data(m->extcpu).phys_proc_id; 13121afaf18SBorislav Petkov m->apicid = cpu_data(m->extcpu).initial_apicid; 132865d3a9aSThomas Gleixner m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); 133822ccfadSTony Luck m->ppin = cpu_data(m->extcpu).ppin; 13421afaf18SBorislav Petkov m->microcode = boot_cpu_data.microcode; 13521afaf18SBorislav Petkov } 13621afaf18SBorislav Petkov 13721afaf18SBorislav Petkov DEFINE_PER_CPU(struct mce, injectm); 13821afaf18SBorislav Petkov EXPORT_PER_CPU_SYMBOL_GPL(injectm); 13921afaf18SBorislav Petkov 14021afaf18SBorislav Petkov void mce_log(struct mce *m) 14121afaf18SBorislav Petkov { 14221afaf18SBorislav Petkov if (!mce_gen_pool_add(m)) 14321afaf18SBorislav Petkov irq_work_queue(&mce_irq_work); 14421afaf18SBorislav Petkov } 14581736abdSJan H. Schönherr EXPORT_SYMBOL_GPL(mce_log); 14621afaf18SBorislav Petkov 14721afaf18SBorislav Petkov void mce_register_decode_chain(struct notifier_block *nb) 14821afaf18SBorislav Petkov { 14915af3659SZhen Lei if (WARN_ON(nb->priority < MCE_PRIO_LOWEST || 15015af3659SZhen Lei nb->priority > MCE_PRIO_HIGHEST)) 15121afaf18SBorislav Petkov return; 15221afaf18SBorislav Petkov 15321afaf18SBorislav Petkov blocking_notifier_chain_register(&x86_mce_decoder_chain, nb); 15421afaf18SBorislav Petkov } 15521afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_register_decode_chain); 15621afaf18SBorislav Petkov 15721afaf18SBorislav Petkov void mce_unregister_decode_chain(struct notifier_block *nb) 15821afaf18SBorislav Petkov { 15921afaf18SBorislav Petkov blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb); 16021afaf18SBorislav Petkov } 16121afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); 16221afaf18SBorislav Petkov 16321afaf18SBorislav Petkov static void __print_mce(struct mce *m) 16421afaf18SBorislav Petkov { 16521afaf18SBorislav Petkov pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", 16621afaf18SBorislav Petkov m->extcpu, 16721afaf18SBorislav Petkov (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""), 16821afaf18SBorislav Petkov m->mcgstatus, m->bank, m->status); 16921afaf18SBorislav Petkov 17021afaf18SBorislav Petkov if (m->ip) { 17121afaf18SBorislav Petkov pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", 17221afaf18SBorislav Petkov !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", 17321afaf18SBorislav Petkov m->cs, m->ip); 17421afaf18SBorislav Petkov 17521afaf18SBorislav Petkov if (m->cs == __KERNEL_CS) 17621afaf18SBorislav Petkov pr_cont("{%pS}", (void *)(unsigned long)m->ip); 17721afaf18SBorislav Petkov pr_cont("\n"); 17821afaf18SBorislav Petkov } 17921afaf18SBorislav Petkov 18021afaf18SBorislav Petkov pr_emerg(HW_ERR "TSC %llx ", m->tsc); 18121afaf18SBorislav Petkov if (m->addr) 18221afaf18SBorislav Petkov pr_cont("ADDR %llx ", m->addr); 18321afaf18SBorislav Petkov if (m->misc) 18421afaf18SBorislav Petkov pr_cont("MISC %llx ", m->misc); 185bb2de0adSSmita Koralahalli if (m->ppin) 186bb2de0adSSmita Koralahalli pr_cont("PPIN %llx ", m->ppin); 18721afaf18SBorislav Petkov 18821afaf18SBorislav Petkov if (mce_flags.smca) { 18921afaf18SBorislav Petkov if (m->synd) 19021afaf18SBorislav Petkov pr_cont("SYND %llx ", m->synd); 19121afaf18SBorislav Petkov if (m->ipid) 19221afaf18SBorislav Petkov pr_cont("IPID %llx ", m->ipid); 19321afaf18SBorislav Petkov } 19421afaf18SBorislav Petkov 19521afaf18SBorislav Petkov pr_cont("\n"); 196925946cfSTony Luck 19721afaf18SBorislav Petkov /* 19821afaf18SBorislav Petkov * Note this output is parsed by external tools and old fields 19921afaf18SBorislav Petkov * should not be changed. 20021afaf18SBorislav Petkov */ 20121afaf18SBorislav Petkov pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", 20221afaf18SBorislav Petkov m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, 20321afaf18SBorislav Petkov m->microcode); 20421afaf18SBorislav Petkov } 20521afaf18SBorislav Petkov 20621afaf18SBorislav Petkov static void print_mce(struct mce *m) 20721afaf18SBorislav Petkov { 20821afaf18SBorislav Petkov __print_mce(m); 20921afaf18SBorislav Petkov 21021afaf18SBorislav Petkov if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON) 21121afaf18SBorislav Petkov pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); 21221afaf18SBorislav Petkov } 21321afaf18SBorislav Petkov 21421afaf18SBorislav Petkov #define PANIC_TIMEOUT 5 /* 5 seconds */ 21521afaf18SBorislav Petkov 21621afaf18SBorislav Petkov static atomic_t mce_panicked; 21721afaf18SBorislav Petkov 21821afaf18SBorislav Petkov static int fake_panic; 21921afaf18SBorislav Petkov static atomic_t mce_fake_panicked; 22021afaf18SBorislav Petkov 22121afaf18SBorislav Petkov /* Panic in progress. Enable interrupts and wait for final IPI */ 22221afaf18SBorislav Petkov static void wait_for_panic(void) 22321afaf18SBorislav Petkov { 22421afaf18SBorislav Petkov long timeout = PANIC_TIMEOUT*USEC_PER_SEC; 22521afaf18SBorislav Petkov 22621afaf18SBorislav Petkov preempt_disable(); 22721afaf18SBorislav Petkov local_irq_enable(); 22821afaf18SBorislav Petkov while (timeout-- > 0) 22921afaf18SBorislav Petkov udelay(1); 23021afaf18SBorislav Petkov if (panic_timeout == 0) 23121afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 23221afaf18SBorislav Petkov panic("Panicing machine check CPU died"); 23321afaf18SBorislav Petkov } 23421afaf18SBorislav Petkov 2353c7ce80aSBorislav Petkov static noinstr void mce_panic(const char *msg, struct mce *final, char *exp) 23621afaf18SBorislav Petkov { 23721afaf18SBorislav Petkov struct llist_node *pending; 23821afaf18SBorislav Petkov struct mce_evt_llist *l; 2393c7ce80aSBorislav Petkov int apei_err = 0; 2403c7ce80aSBorislav Petkov 2413c7ce80aSBorislav Petkov /* 2423c7ce80aSBorislav Petkov * Allow instrumentation around external facilities usage. Not that it 2433c7ce80aSBorislav Petkov * matters a whole lot since the machine is going to panic anyway. 2443c7ce80aSBorislav Petkov */ 2453c7ce80aSBorislav Petkov instrumentation_begin(); 24621afaf18SBorislav Petkov 24721afaf18SBorislav Petkov if (!fake_panic) { 24821afaf18SBorislav Petkov /* 24921afaf18SBorislav Petkov * Make sure only one CPU runs in machine check panic 25021afaf18SBorislav Petkov */ 25121afaf18SBorislav Petkov if (atomic_inc_return(&mce_panicked) > 1) 25221afaf18SBorislav Petkov wait_for_panic(); 25321afaf18SBorislav Petkov barrier(); 25421afaf18SBorislav Petkov 25521afaf18SBorislav Petkov bust_spinlocks(1); 25621afaf18SBorislav Petkov console_verbose(); 25721afaf18SBorislav Petkov } else { 25821afaf18SBorislav Petkov /* Don't log too much for fake panic */ 25921afaf18SBorislav Petkov if (atomic_inc_return(&mce_fake_panicked) > 1) 2603c7ce80aSBorislav Petkov goto out; 26121afaf18SBorislav Petkov } 26221afaf18SBorislav Petkov pending = mce_gen_pool_prepare_records(); 26321afaf18SBorislav Petkov /* First print corrected ones that are still unlogged */ 26421afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 26521afaf18SBorislav Petkov struct mce *m = &l->mce; 26621afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) { 26721afaf18SBorislav Petkov print_mce(m); 26821afaf18SBorislav Petkov if (!apei_err) 26921afaf18SBorislav Petkov apei_err = apei_write_mce(m); 27021afaf18SBorislav Petkov } 27121afaf18SBorislav Petkov } 27221afaf18SBorislav Petkov /* Now print uncorrected but with the final one last */ 27321afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 27421afaf18SBorislav Petkov struct mce *m = &l->mce; 27521afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) 27621afaf18SBorislav Petkov continue; 27721afaf18SBorislav Petkov if (!final || mce_cmp(m, final)) { 27821afaf18SBorislav Petkov print_mce(m); 27921afaf18SBorislav Petkov if (!apei_err) 28021afaf18SBorislav Petkov apei_err = apei_write_mce(m); 28121afaf18SBorislav Petkov } 28221afaf18SBorislav Petkov } 28321afaf18SBorislav Petkov if (final) { 28421afaf18SBorislav Petkov print_mce(final); 28521afaf18SBorislav Petkov if (!apei_err) 28621afaf18SBorislav Petkov apei_err = apei_write_mce(final); 28721afaf18SBorislav Petkov } 28821afaf18SBorislav Petkov if (exp) 28921afaf18SBorislav Petkov pr_emerg(HW_ERR "Machine check: %s\n", exp); 29021afaf18SBorislav Petkov if (!fake_panic) { 29121afaf18SBorislav Petkov if (panic_timeout == 0) 29221afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 29321afaf18SBorislav Petkov panic(msg); 29421afaf18SBorislav Petkov } else 29521afaf18SBorislav Petkov pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); 2963c7ce80aSBorislav Petkov 2973c7ce80aSBorislav Petkov out: 2983c7ce80aSBorislav Petkov instrumentation_end(); 29921afaf18SBorislav Petkov } 30021afaf18SBorislav Petkov 30121afaf18SBorislav Petkov /* Support code for software error injection */ 30221afaf18SBorislav Petkov 30321afaf18SBorislav Petkov static int msr_to_offset(u32 msr) 30421afaf18SBorislav Petkov { 30521afaf18SBorislav Petkov unsigned bank = __this_cpu_read(injectm.bank); 30621afaf18SBorislav Petkov 30721afaf18SBorislav Petkov if (msr == mca_cfg.rip_msr) 30821afaf18SBorislav Petkov return offsetof(struct mce, ip); 3098121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_STATUS)) 31021afaf18SBorislav Petkov return offsetof(struct mce, status); 3118121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_ADDR)) 31221afaf18SBorislav Petkov return offsetof(struct mce, addr); 3138121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_MISC)) 31421afaf18SBorislav Petkov return offsetof(struct mce, misc); 31521afaf18SBorislav Petkov if (msr == MSR_IA32_MCG_STATUS) 31621afaf18SBorislav Petkov return offsetof(struct mce, mcgstatus); 31721afaf18SBorislav Petkov return -1; 31821afaf18SBorislav Petkov } 31921afaf18SBorislav Petkov 32046d28947SThomas Gleixner void ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr) 321e2def7d4SBorislav Petkov { 322e42404afSThomas Gleixner if (wrmsr) { 323e42404afSThomas Gleixner pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n", 324e42404afSThomas Gleixner (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax, 325e42404afSThomas Gleixner regs->ip, (void *)regs->ip); 326e42404afSThomas Gleixner } else { 327e2def7d4SBorislav Petkov pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n", 328e2def7d4SBorislav Petkov (unsigned int)regs->cx, regs->ip, (void *)regs->ip); 329e42404afSThomas Gleixner } 330e2def7d4SBorislav Petkov 331e2def7d4SBorislav Petkov show_stack_regs(regs); 332e2def7d4SBorislav Petkov 333e2def7d4SBorislav Petkov panic("MCA architectural violation!\n"); 334e2def7d4SBorislav Petkov 335e2def7d4SBorislav Petkov while (true) 336e2def7d4SBorislav Petkov cpu_relax(); 337e42404afSThomas Gleixner } 338e2def7d4SBorislav Petkov 33921afaf18SBorislav Petkov /* MSR access wrappers used for error injection */ 34088f66a42SBorislav Petkov noinstr u64 mce_rdmsrl(u32 msr) 34121afaf18SBorislav Petkov { 342e2def7d4SBorislav Petkov DECLARE_ARGS(val, low, high); 34321afaf18SBorislav Petkov 34421afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 345e1007770SBorislav Petkov int offset; 346e1007770SBorislav Petkov u64 ret; 34721afaf18SBorislav Petkov 348e1007770SBorislav Petkov instrumentation_begin(); 349e1007770SBorislav Petkov 350e1007770SBorislav Petkov offset = msr_to_offset(msr); 35121afaf18SBorislav Petkov if (offset < 0) 352e1007770SBorislav Petkov ret = 0; 353e1007770SBorislav Petkov else 354e1007770SBorislav Petkov ret = *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); 355e1007770SBorislav Petkov 356e1007770SBorislav Petkov instrumentation_end(); 357e1007770SBorislav Petkov 358e1007770SBorislav Petkov return ret; 35921afaf18SBorislav Petkov } 36021afaf18SBorislav Petkov 36121afaf18SBorislav Petkov /* 362e2def7d4SBorislav Petkov * RDMSR on MCA MSRs should not fault. If they do, this is very much an 363e2def7d4SBorislav Petkov * architectural violation and needs to be reported to hw vendor. Panic 364e2def7d4SBorislav Petkov * the box to not allow any further progress. 36521afaf18SBorislav Petkov */ 366e2def7d4SBorislav Petkov asm volatile("1: rdmsr\n" 367e2def7d4SBorislav Petkov "2:\n" 36846d28947SThomas Gleixner _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR_IN_MCE) 369e2def7d4SBorislav Petkov : EAX_EDX_RET(val, low, high) : "c" (msr)); 370e2def7d4SBorislav Petkov 371e2def7d4SBorislav Petkov 372e2def7d4SBorislav Petkov return EAX_EDX_VAL(val, low, high); 37321afaf18SBorislav Petkov } 37421afaf18SBorislav Petkov 375e1007770SBorislav Petkov static noinstr void mce_wrmsrl(u32 msr, u64 v) 37621afaf18SBorislav Petkov { 377e2def7d4SBorislav Petkov u32 low, high; 378e2def7d4SBorislav Petkov 37921afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 380e1007770SBorislav Petkov int offset; 38121afaf18SBorislav Petkov 382e1007770SBorislav Petkov instrumentation_begin(); 383e1007770SBorislav Petkov 384e1007770SBorislav Petkov offset = msr_to_offset(msr); 38521afaf18SBorislav Petkov if (offset >= 0) 38621afaf18SBorislav Petkov *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; 387e1007770SBorislav Petkov 388e1007770SBorislav Petkov instrumentation_end(); 389e1007770SBorislav Petkov 39021afaf18SBorislav Petkov return; 39121afaf18SBorislav Petkov } 392e2def7d4SBorislav Petkov 393e2def7d4SBorislav Petkov low = (u32)v; 394e2def7d4SBorislav Petkov high = (u32)(v >> 32); 395e2def7d4SBorislav Petkov 396e2def7d4SBorislav Petkov /* See comment in mce_rdmsrl() */ 397e2def7d4SBorislav Petkov asm volatile("1: wrmsr\n" 398e2def7d4SBorislav Petkov "2:\n" 39946d28947SThomas Gleixner _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR_IN_MCE) 400e2def7d4SBorislav Petkov : : "c" (msr), "a"(low), "d" (high) : "memory"); 40121afaf18SBorislav Petkov } 40221afaf18SBorislav Petkov 40321afaf18SBorislav Petkov /* 40421afaf18SBorislav Petkov * Collect all global (w.r.t. this processor) status about this machine 40521afaf18SBorislav Petkov * check into our "mce" struct so that we can use it later to assess 40621afaf18SBorislav Petkov * the severity of the problem as we read per-bank specific details. 40721afaf18SBorislav Petkov */ 408487d654dSBorislav Petkov static noinstr void mce_gather_info(struct mce *m, struct pt_regs *regs) 40921afaf18SBorislav Petkov { 410487d654dSBorislav Petkov /* 411487d654dSBorislav Petkov * Enable instrumentation around mce_setup() which calls external 412487d654dSBorislav Petkov * facilities. 413487d654dSBorislav Petkov */ 414487d654dSBorislav Petkov instrumentation_begin(); 41521afaf18SBorislav Petkov mce_setup(m); 416487d654dSBorislav Petkov instrumentation_end(); 41721afaf18SBorislav Petkov 41821afaf18SBorislav Petkov m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 41921afaf18SBorislav Petkov if (regs) { 42021afaf18SBorislav Petkov /* 42121afaf18SBorislav Petkov * Get the address of the instruction at the time of 42221afaf18SBorislav Petkov * the machine check error. 42321afaf18SBorislav Petkov */ 42421afaf18SBorislav Petkov if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { 42521afaf18SBorislav Petkov m->ip = regs->ip; 42621afaf18SBorislav Petkov m->cs = regs->cs; 42721afaf18SBorislav Petkov 42821afaf18SBorislav Petkov /* 42921afaf18SBorislav Petkov * When in VM86 mode make the cs look like ring 3 43021afaf18SBorislav Petkov * always. This is a lie, but it's better than passing 43121afaf18SBorislav Petkov * the additional vm86 bit around everywhere. 43221afaf18SBorislav Petkov */ 43321afaf18SBorislav Petkov if (v8086_mode(regs)) 43421afaf18SBorislav Petkov m->cs |= 3; 43521afaf18SBorislav Petkov } 43621afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 43721afaf18SBorislav Petkov if (mca_cfg.rip_msr) 43821afaf18SBorislav Petkov m->ip = mce_rdmsrl(mca_cfg.rip_msr); 43921afaf18SBorislav Petkov } 44021afaf18SBorislav Petkov } 44121afaf18SBorislav Petkov 44221afaf18SBorislav Petkov int mce_available(struct cpuinfo_x86 *c) 44321afaf18SBorislav Petkov { 44421afaf18SBorislav Petkov if (mca_cfg.disabled) 44521afaf18SBorislav Petkov return 0; 44621afaf18SBorislav Petkov return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); 44721afaf18SBorislav Petkov } 44821afaf18SBorislav Petkov 44921afaf18SBorislav Petkov static void mce_schedule_work(void) 45021afaf18SBorislav Petkov { 45121afaf18SBorislav Petkov if (!mce_gen_pool_empty()) 45221afaf18SBorislav Petkov schedule_work(&mce_work); 45321afaf18SBorislav Petkov } 45421afaf18SBorislav Petkov 45521afaf18SBorislav Petkov static void mce_irq_work_cb(struct irq_work *entry) 45621afaf18SBorislav Petkov { 45721afaf18SBorislav Petkov mce_schedule_work(); 45821afaf18SBorislav Petkov } 45921afaf18SBorislav Petkov 46021afaf18SBorislav Petkov /* 46121afaf18SBorislav Petkov * Check if the address reported by the CPU is in a format we can parse. 46221afaf18SBorislav Petkov * It would be possible to add code for most other cases, but all would 46321afaf18SBorislav Petkov * be somewhat complicated (e.g. segment offset would require an instruction 464d9f6e12fSIngo Molnar * parser). So only support physical addresses up to page granularity for now. 46521afaf18SBorislav Petkov */ 46621afaf18SBorislav Petkov int mce_usable_address(struct mce *m) 46721afaf18SBorislav Petkov { 46821afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_ADDRV)) 46921afaf18SBorislav Petkov return 0; 47021afaf18SBorislav Petkov 4716e898d2bSTony W Wang-oc /* Checks after this one are Intel/Zhaoxin-specific: */ 4726e898d2bSTony W Wang-oc if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && 4736e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) 47421afaf18SBorislav Petkov return 1; 47521afaf18SBorislav Petkov 47621afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_MISCV)) 47721afaf18SBorislav Petkov return 0; 47821afaf18SBorislav Petkov 47921afaf18SBorislav Petkov if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) 48021afaf18SBorislav Petkov return 0; 48121afaf18SBorislav Petkov 48221afaf18SBorislav Petkov if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) 48321afaf18SBorislav Petkov return 0; 48421afaf18SBorislav Petkov 48521afaf18SBorislav Petkov return 1; 48621afaf18SBorislav Petkov } 48721afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_usable_address); 48821afaf18SBorislav Petkov 48921afaf18SBorislav Petkov bool mce_is_memory_error(struct mce *m) 49021afaf18SBorislav Petkov { 4916e898d2bSTony W Wang-oc switch (m->cpuvendor) { 4926e898d2bSTony W Wang-oc case X86_VENDOR_AMD: 4936e898d2bSTony W Wang-oc case X86_VENDOR_HYGON: 49421afaf18SBorislav Petkov return amd_mce_is_memory_error(m); 4956e898d2bSTony W Wang-oc 4966e898d2bSTony W Wang-oc case X86_VENDOR_INTEL: 4976e898d2bSTony W Wang-oc case X86_VENDOR_ZHAOXIN: 49821afaf18SBorislav Petkov /* 49921afaf18SBorislav Petkov * Intel SDM Volume 3B - 15.9.2 Compound Error Codes 50021afaf18SBorislav Petkov * 50121afaf18SBorislav Petkov * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for 50221afaf18SBorislav Petkov * indicating a memory error. Bit 8 is used for indicating a 50321afaf18SBorislav Petkov * cache hierarchy error. The combination of bit 2 and bit 3 50421afaf18SBorislav Petkov * is used for indicating a `generic' cache hierarchy error 50521afaf18SBorislav Petkov * But we can't just blindly check the above bits, because if 50621afaf18SBorislav Petkov * bit 11 is set, then it is a bus/interconnect error - and 50721afaf18SBorislav Petkov * either way the above bits just gives more detail on what 50821afaf18SBorislav Petkov * bus/interconnect error happened. Note that bit 12 can be 50921afaf18SBorislav Petkov * ignored, as it's the "filter" bit. 51021afaf18SBorislav Petkov */ 51121afaf18SBorislav Petkov return (m->status & 0xef80) == BIT(7) || 51221afaf18SBorislav Petkov (m->status & 0xef00) == BIT(8) || 51321afaf18SBorislav Petkov (m->status & 0xeffc) == 0xc; 51421afaf18SBorislav Petkov 5156e898d2bSTony W Wang-oc default: 51621afaf18SBorislav Petkov return false; 51721afaf18SBorislav Petkov } 5186e898d2bSTony W Wang-oc } 51921afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_memory_error); 52021afaf18SBorislav Petkov 52117fae129STony Luck static bool whole_page(struct mce *m) 52217fae129STony Luck { 52317fae129STony Luck if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV)) 52417fae129STony Luck return true; 52517fae129STony Luck 52617fae129STony Luck return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT; 52717fae129STony Luck } 52817fae129STony Luck 52921afaf18SBorislav Petkov bool mce_is_correctable(struct mce *m) 53021afaf18SBorislav Petkov { 53121afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED) 53221afaf18SBorislav Petkov return false; 53321afaf18SBorislav Petkov 53421afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED) 53521afaf18SBorislav Petkov return false; 53621afaf18SBorislav Petkov 53721afaf18SBorislav Petkov if (m->status & MCI_STATUS_UC) 53821afaf18SBorislav Petkov return false; 53921afaf18SBorislav Petkov 54021afaf18SBorislav Petkov return true; 54121afaf18SBorislav Petkov } 54221afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_correctable); 54321afaf18SBorislav Petkov 544c9c6d216STony Luck static int mce_early_notifier(struct notifier_block *nb, unsigned long val, 54521afaf18SBorislav Petkov void *data) 54621afaf18SBorislav Petkov { 54721afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 54821afaf18SBorislav Petkov 54921afaf18SBorislav Petkov if (!m) 55021afaf18SBorislav Petkov return NOTIFY_DONE; 55121afaf18SBorislav Petkov 55221afaf18SBorislav Petkov /* Emit the trace record: */ 55321afaf18SBorislav Petkov trace_mce_record(m); 55421afaf18SBorislav Petkov 55521afaf18SBorislav Petkov set_bit(0, &mce_need_notify); 55621afaf18SBorislav Petkov 55721afaf18SBorislav Petkov mce_notify_irq(); 55821afaf18SBorislav Petkov 55921afaf18SBorislav Petkov return NOTIFY_DONE; 56021afaf18SBorislav Petkov } 56121afaf18SBorislav Petkov 562c9c6d216STony Luck static struct notifier_block early_nb = { 563c9c6d216STony Luck .notifier_call = mce_early_notifier, 564c9c6d216STony Luck .priority = MCE_PRIO_EARLY, 56521afaf18SBorislav Petkov }; 56621afaf18SBorislav Petkov 5678438b84aSJan H. Schönherr static int uc_decode_notifier(struct notifier_block *nb, unsigned long val, 56821afaf18SBorislav Petkov void *data) 56921afaf18SBorislav Petkov { 57021afaf18SBorislav Petkov struct mce *mce = (struct mce *)data; 57121afaf18SBorislav Petkov unsigned long pfn; 57221afaf18SBorislav Petkov 5738438b84aSJan H. Schönherr if (!mce || !mce_usable_address(mce)) 57421afaf18SBorislav Petkov return NOTIFY_DONE; 57521afaf18SBorislav Petkov 5768438b84aSJan H. Schönherr if (mce->severity != MCE_AO_SEVERITY && 5778438b84aSJan H. Schönherr mce->severity != MCE_DEFERRED_SEVERITY) 5788438b84aSJan H. Schönherr return NOTIFY_DONE; 5798438b84aSJan H. Schönherr 58021afaf18SBorislav Petkov pfn = mce->addr >> PAGE_SHIFT; 58123ba710aSTony Luck if (!memory_failure(pfn, 0)) { 582*5898b43aSJane Chu set_mce_nospec(pfn); 58323ba710aSTony Luck mce->kflags |= MCE_HANDLED_UC; 58423ba710aSTony Luck } 58521afaf18SBorislav Petkov 58621afaf18SBorislav Petkov return NOTIFY_OK; 58721afaf18SBorislav Petkov } 5888438b84aSJan H. Schönherr 5898438b84aSJan H. Schönherr static struct notifier_block mce_uc_nb = { 5908438b84aSJan H. Schönherr .notifier_call = uc_decode_notifier, 5918438b84aSJan H. Schönherr .priority = MCE_PRIO_UC, 59221afaf18SBorislav Petkov }; 59321afaf18SBorislav Petkov 59421afaf18SBorislav Petkov static int mce_default_notifier(struct notifier_block *nb, unsigned long val, 59521afaf18SBorislav Petkov void *data) 59621afaf18SBorislav Petkov { 59721afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 59821afaf18SBorislav Petkov 59921afaf18SBorislav Petkov if (!m) 60021afaf18SBorislav Petkov return NOTIFY_DONE; 60121afaf18SBorislav Petkov 60243505646STony Luck if (mca_cfg.print_all || !m->kflags) 60321afaf18SBorislav Petkov __print_mce(m); 60421afaf18SBorislav Petkov 60521afaf18SBorislav Petkov return NOTIFY_DONE; 60621afaf18SBorislav Petkov } 60721afaf18SBorislav Petkov 60821afaf18SBorislav Petkov static struct notifier_block mce_default_nb = { 60921afaf18SBorislav Petkov .notifier_call = mce_default_notifier, 61021afaf18SBorislav Petkov /* lowest prio, we want it to run last. */ 61121afaf18SBorislav Petkov .priority = MCE_PRIO_LOWEST, 61221afaf18SBorislav Petkov }; 61321afaf18SBorislav Petkov 61421afaf18SBorislav Petkov /* 61521afaf18SBorislav Petkov * Read ADDR and MISC registers. 61621afaf18SBorislav Petkov */ 617db6c996dSBorislav Petkov static noinstr void mce_read_aux(struct mce *m, int i) 61821afaf18SBorislav Petkov { 61921afaf18SBorislav Petkov if (m->status & MCI_STATUS_MISCV) 6208121b8f9SBorislav Petkov m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC)); 62121afaf18SBorislav Petkov 62221afaf18SBorislav Petkov if (m->status & MCI_STATUS_ADDRV) { 6238121b8f9SBorislav Petkov m->addr = mce_rdmsrl(mca_msr_reg(i, MCA_ADDR)); 62421afaf18SBorislav Petkov 62521afaf18SBorislav Petkov /* 62621afaf18SBorislav Petkov * Mask the reported address by the reported granularity. 62721afaf18SBorislav Petkov */ 62821afaf18SBorislav Petkov if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { 62921afaf18SBorislav Petkov u8 shift = MCI_MISC_ADDR_LSB(m->misc); 63021afaf18SBorislav Petkov m->addr >>= shift; 63121afaf18SBorislav Petkov m->addr <<= shift; 63221afaf18SBorislav Petkov } 63321afaf18SBorislav Petkov 63421afaf18SBorislav Petkov /* 63521afaf18SBorislav Petkov * Extract [55:<lsb>] where lsb is the least significant 63621afaf18SBorislav Petkov * *valid* bit of the address bits. 63721afaf18SBorislav Petkov */ 63821afaf18SBorislav Petkov if (mce_flags.smca) { 63921afaf18SBorislav Petkov u8 lsb = (m->addr >> 56) & 0x3f; 64021afaf18SBorislav Petkov 64121afaf18SBorislav Petkov m->addr &= GENMASK_ULL(55, lsb); 64221afaf18SBorislav Petkov } 64321afaf18SBorislav Petkov } 64421afaf18SBorislav Petkov 64521afaf18SBorislav Petkov if (mce_flags.smca) { 64621afaf18SBorislav Petkov m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); 64721afaf18SBorislav Petkov 64821afaf18SBorislav Petkov if (m->status & MCI_STATUS_SYNDV) 64921afaf18SBorislav Petkov m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); 65021afaf18SBorislav Petkov } 65121afaf18SBorislav Petkov } 65221afaf18SBorislav Petkov 65321afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_poll_count); 65421afaf18SBorislav Petkov 65521afaf18SBorislav Petkov /* 65621afaf18SBorislav Petkov * Poll for corrected events or events that happened before reset. 65721afaf18SBorislav Petkov * Those are just logged through /dev/mcelog. 65821afaf18SBorislav Petkov * 65921afaf18SBorislav Petkov * This is executed in standard interrupt context. 66021afaf18SBorislav Petkov * 66121afaf18SBorislav Petkov * Note: spec recommends to panic for fatal unsignalled 66221afaf18SBorislav Petkov * errors here. However this would be quite problematic -- 66321afaf18SBorislav Petkov * we would need to reimplement the Monarch handling and 66421afaf18SBorislav Petkov * it would mess up the exclusion between exception handler 665312a4661SLinus Torvalds * and poll handler -- * so we skip this for now. 66621afaf18SBorislav Petkov * These cases should not happen anyways, or only when the CPU 66721afaf18SBorislav Petkov * is already totally * confused. In this case it's likely it will 66821afaf18SBorislav Petkov * not fully execute the machine check handler either. 66921afaf18SBorislav Petkov */ 67021afaf18SBorislav Petkov bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) 67121afaf18SBorislav Petkov { 672b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 67321afaf18SBorislav Petkov bool error_seen = false; 67421afaf18SBorislav Petkov struct mce m; 67521afaf18SBorislav Petkov int i; 67621afaf18SBorislav Petkov 67721afaf18SBorislav Petkov this_cpu_inc(mce_poll_count); 67821afaf18SBorislav Petkov 67921afaf18SBorislav Petkov mce_gather_info(&m, NULL); 68021afaf18SBorislav Petkov 68121afaf18SBorislav Petkov if (flags & MCP_TIMESTAMP) 68221afaf18SBorislav Petkov m.tsc = rdtsc(); 68321afaf18SBorislav Petkov 684c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 68521afaf18SBorislav Petkov if (!mce_banks[i].ctl || !test_bit(i, *b)) 68621afaf18SBorislav Petkov continue; 68721afaf18SBorislav Petkov 68821afaf18SBorislav Petkov m.misc = 0; 68921afaf18SBorislav Petkov m.addr = 0; 69021afaf18SBorislav Petkov m.bank = i; 69121afaf18SBorislav Petkov 69221afaf18SBorislav Petkov barrier(); 6938121b8f9SBorislav Petkov m.status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 694f19501aaSTony Luck 695f19501aaSTony Luck /* If this entry is not valid, ignore it */ 69621afaf18SBorislav Petkov if (!(m.status & MCI_STATUS_VAL)) 69721afaf18SBorislav Petkov continue; 69821afaf18SBorislav Petkov 69921afaf18SBorislav Petkov /* 700f19501aaSTony Luck * If we are logging everything (at CPU online) or this 701f19501aaSTony Luck * is a corrected error, then we must log it. 70221afaf18SBorislav Petkov */ 703f19501aaSTony Luck if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC)) 704f19501aaSTony Luck goto log_it; 705f19501aaSTony Luck 706f19501aaSTony Luck /* 707f19501aaSTony Luck * Newer Intel systems that support software error 708f19501aaSTony Luck * recovery need to make additional checks. Other 709f19501aaSTony Luck * CPUs should skip over uncorrected errors, but log 710f19501aaSTony Luck * everything else. 711f19501aaSTony Luck */ 712f19501aaSTony Luck if (!mca_cfg.ser) { 713f19501aaSTony Luck if (m.status & MCI_STATUS_UC) 714f19501aaSTony Luck continue; 715f19501aaSTony Luck goto log_it; 716f19501aaSTony Luck } 717f19501aaSTony Luck 718f19501aaSTony Luck /* Log "not enabled" (speculative) errors */ 719f19501aaSTony Luck if (!(m.status & MCI_STATUS_EN)) 720f19501aaSTony Luck goto log_it; 721f19501aaSTony Luck 722f19501aaSTony Luck /* 723f19501aaSTony Luck * Log UCNA (SDM: 15.6.3 "UCR Error Classification") 724f19501aaSTony Luck * UC == 1 && PCC == 0 && S == 0 725f19501aaSTony Luck */ 726f19501aaSTony Luck if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S)) 727f19501aaSTony Luck goto log_it; 728f19501aaSTony Luck 729f19501aaSTony Luck /* 730f19501aaSTony Luck * Skip anything else. Presumption is that our read of this 731f19501aaSTony Luck * bank is racing with a machine check. Leave the log alone 732f19501aaSTony Luck * for do_machine_check() to deal with it. 733f19501aaSTony Luck */ 73421afaf18SBorislav Petkov continue; 73521afaf18SBorislav Petkov 736f19501aaSTony Luck log_it: 73721afaf18SBorislav Petkov error_seen = true; 73821afaf18SBorislav Petkov 73990454e49SJan H. Schönherr if (flags & MCP_DONTLOG) 74090454e49SJan H. Schönherr goto clear_it; 74190454e49SJan H. Schönherr 74221afaf18SBorislav Petkov mce_read_aux(&m, i); 7437f1b8e0dSBorislav Petkov m.severity = mce_severity(&m, NULL, NULL, false); 74421afaf18SBorislav Petkov /* 74521afaf18SBorislav Petkov * Don't get the IP here because it's unlikely to 74621afaf18SBorislav Petkov * have anything to do with the actual error location. 74721afaf18SBorislav Petkov */ 74821afaf18SBorislav Petkov 74990454e49SJan H. Schönherr if (mca_cfg.dont_log_ce && !mce_usable_address(&m)) 75090454e49SJan H. Schönherr goto clear_it; 75190454e49SJan H. Schönherr 7523bff147bSBorislav Petkov if (flags & MCP_QUEUE_LOG) 7533bff147bSBorislav Petkov mce_gen_pool_add(&m); 7543bff147bSBorislav Petkov else 75590454e49SJan H. Schönherr mce_log(&m); 75690454e49SJan H. Schönherr 75790454e49SJan H. Schönherr clear_it: 75821afaf18SBorislav Petkov /* 75921afaf18SBorislav Petkov * Clear state for this bank. 76021afaf18SBorislav Petkov */ 7618121b8f9SBorislav Petkov mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 76221afaf18SBorislav Petkov } 76321afaf18SBorislav Petkov 76421afaf18SBorislav Petkov /* 76521afaf18SBorislav Petkov * Don't clear MCG_STATUS here because it's only defined for 76621afaf18SBorislav Petkov * exceptions. 76721afaf18SBorislav Petkov */ 76821afaf18SBorislav Petkov 76921afaf18SBorislav Petkov sync_core(); 77021afaf18SBorislav Petkov 77121afaf18SBorislav Petkov return error_seen; 77221afaf18SBorislav Petkov } 77321afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(machine_check_poll); 77421afaf18SBorislav Petkov 77521afaf18SBorislav Petkov /* 776cc466666SBorislav Petkov * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and 777cc466666SBorislav Petkov * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM 778cc466666SBorislav Petkov * Vol 3B Table 15-20). But this confuses both the code that determines 779cc466666SBorislav Petkov * whether the machine check occurred in kernel or user mode, and also 780cc466666SBorislav Petkov * the severity assessment code. Pretend that EIPV was set, and take the 781cc466666SBorislav Petkov * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. 782cc466666SBorislav Petkov */ 783f11445baSBorislav Petkov static __always_inline void 784f11445baSBorislav Petkov quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) 785cc466666SBorislav Petkov { 786cc466666SBorislav Petkov if (bank != 0) 787cc466666SBorislav Petkov return; 788cc466666SBorislav Petkov if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) 789cc466666SBorislav Petkov return; 790cc466666SBorislav Petkov if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| 791cc466666SBorislav Petkov MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| 792cc466666SBorislav Petkov MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| 793cc466666SBorislav Petkov MCACOD)) != 794cc466666SBorislav Petkov (MCI_STATUS_UC|MCI_STATUS_EN| 795cc466666SBorislav Petkov MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| 796cc466666SBorislav Petkov MCI_STATUS_AR|MCACOD_INSTR)) 797cc466666SBorislav Petkov return; 798cc466666SBorislav Petkov 799cc466666SBorislav Petkov m->mcgstatus |= MCG_STATUS_EIPV; 800cc466666SBorislav Petkov m->ip = regs->ip; 801cc466666SBorislav Petkov m->cs = regs->cs; 802cc466666SBorislav Petkov } 803cc466666SBorislav Petkov 804cc466666SBorislav Petkov /* 8058ca97812SJue Wang * Disable fast string copy and return from the MCE handler upon the first SRAR 8068ca97812SJue Wang * MCE on bank 1 due to a CPU erratum on Intel Skylake/Cascade Lake/Cooper Lake 8078ca97812SJue Wang * CPUs. 8088ca97812SJue Wang * The fast string copy instructions ("REP; MOVS*") could consume an 8098ca97812SJue Wang * uncorrectable memory error in the cache line _right after_ the desired region 8108ca97812SJue Wang * to copy and raise an MCE with RIP pointing to the instruction _after_ the 8118ca97812SJue Wang * "REP; MOVS*". 8128ca97812SJue Wang * This mitigation addresses the issue completely with the caveat of performance 8138ca97812SJue Wang * degradation on the CPU affected. This is still better than the OS crashing on 8148ca97812SJue Wang * MCEs raised on an irrelevant process due to "REP; MOVS*" accesses from a 8158ca97812SJue Wang * kernel context (e.g., copy_page). 8168ca97812SJue Wang * 8178ca97812SJue Wang * Returns true when fast string copy on CPU has been disabled. 8188ca97812SJue Wang */ 8198ca97812SJue Wang static noinstr bool quirk_skylake_repmov(void) 8208ca97812SJue Wang { 8218ca97812SJue Wang u64 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 8228ca97812SJue Wang u64 misc_enable = mce_rdmsrl(MSR_IA32_MISC_ENABLE); 8238ca97812SJue Wang u64 mc1_status; 8248ca97812SJue Wang 8258ca97812SJue Wang /* 8268ca97812SJue Wang * Apply the quirk only to local machine checks, i.e., no broadcast 8278ca97812SJue Wang * sync is needed. 8288ca97812SJue Wang */ 8298ca97812SJue Wang if (!(mcgstatus & MCG_STATUS_LMCES) || 8308ca97812SJue Wang !(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) 8318ca97812SJue Wang return false; 8328ca97812SJue Wang 8338ca97812SJue Wang mc1_status = mce_rdmsrl(MSR_IA32_MCx_STATUS(1)); 8348ca97812SJue Wang 8358ca97812SJue Wang /* Check for a software-recoverable data fetch error. */ 8368ca97812SJue Wang if ((mc1_status & 8378ca97812SJue Wang (MCI_STATUS_VAL | MCI_STATUS_OVER | MCI_STATUS_UC | MCI_STATUS_EN | 8388ca97812SJue Wang MCI_STATUS_ADDRV | MCI_STATUS_MISCV | MCI_STATUS_PCC | 8398ca97812SJue Wang MCI_STATUS_AR | MCI_STATUS_S)) == 8408ca97812SJue Wang (MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | 8418ca97812SJue Wang MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 8428ca97812SJue Wang MCI_STATUS_AR | MCI_STATUS_S)) { 8438ca97812SJue Wang misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING; 8448ca97812SJue Wang mce_wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 8458ca97812SJue Wang mce_wrmsrl(MSR_IA32_MCx_STATUS(1), 0); 8468ca97812SJue Wang 8478ca97812SJue Wang instrumentation_begin(); 8488ca97812SJue Wang pr_err_once("Erratum detected, disable fast string copy instructions.\n"); 8498ca97812SJue Wang instrumentation_end(); 8508ca97812SJue Wang 8518ca97812SJue Wang return true; 8528ca97812SJue Wang } 8538ca97812SJue Wang 8548ca97812SJue Wang return false; 8558ca97812SJue Wang } 8568ca97812SJue Wang 8578ca97812SJue Wang /* 85821afaf18SBorislav Petkov * Do a quick check if any of the events requires a panic. 85921afaf18SBorislav Petkov * This decides if we keep the events around or clear them. 86021afaf18SBorislav Petkov */ 861f11445baSBorislav Petkov static __always_inline int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, 86221afaf18SBorislav Petkov struct pt_regs *regs) 86321afaf18SBorislav Petkov { 8647a8bc2b0SJan H. Schönherr char *tmp = *msg; 86521afaf18SBorislav Petkov int i; 86621afaf18SBorislav Petkov 867c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 8688121b8f9SBorislav Petkov m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 86921afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 87021afaf18SBorislav Petkov continue; 87121afaf18SBorislav Petkov 872f11445baSBorislav Petkov arch___set_bit(i, validp); 873cc466666SBorislav Petkov if (mce_flags.snb_ifu_quirk) 874cc466666SBorislav Petkov quirk_sandybridge_ifu(i, m, regs); 87521afaf18SBorislav Petkov 876d28af26fSTony Luck m->bank = i; 8777f1b8e0dSBorislav Petkov if (mce_severity(m, regs, &tmp, true) >= MCE_PANIC_SEVERITY) { 87821afaf18SBorislav Petkov mce_read_aux(m, i); 87921afaf18SBorislav Petkov *msg = tmp; 88021afaf18SBorislav Petkov return 1; 88121afaf18SBorislav Petkov } 88221afaf18SBorislav Petkov } 88321afaf18SBorislav Petkov return 0; 88421afaf18SBorislav Petkov } 88521afaf18SBorislav Petkov 88621afaf18SBorislav Petkov /* 88721afaf18SBorislav Petkov * Variable to establish order between CPUs while scanning. 88821afaf18SBorislav Petkov * Each CPU spins initially until executing is equal its number. 88921afaf18SBorislav Petkov */ 89021afaf18SBorislav Petkov static atomic_t mce_executing; 89121afaf18SBorislav Petkov 89221afaf18SBorislav Petkov /* 89321afaf18SBorislav Petkov * Defines order of CPUs on entry. First CPU becomes Monarch. 89421afaf18SBorislav Petkov */ 89521afaf18SBorislav Petkov static atomic_t mce_callin; 89621afaf18SBorislav Petkov 89721afaf18SBorislav Petkov /* 8987bb39313SPaul E. McKenney * Track which CPUs entered the MCA broadcast synchronization and which not in 8997bb39313SPaul E. McKenney * order to print holdouts. 9007bb39313SPaul E. McKenney */ 9017bb39313SPaul E. McKenney static cpumask_t mce_missing_cpus = CPU_MASK_ALL; 9027bb39313SPaul E. McKenney 9037bb39313SPaul E. McKenney /* 90421afaf18SBorislav Petkov * Check if a timeout waiting for other CPUs happened. 90521afaf18SBorislav Petkov */ 906edb3d07eSBorislav Petkov static noinstr int mce_timed_out(u64 *t, const char *msg) 90721afaf18SBorislav Petkov { 908edb3d07eSBorislav Petkov int ret = 0; 909edb3d07eSBorislav Petkov 910edb3d07eSBorislav Petkov /* Enable instrumentation around calls to external facilities */ 911edb3d07eSBorislav Petkov instrumentation_begin(); 912edb3d07eSBorislav Petkov 91321afaf18SBorislav Petkov /* 91421afaf18SBorislav Petkov * The others already did panic for some reason. 91521afaf18SBorislav Petkov * Bail out like in a timeout. 91621afaf18SBorislav Petkov * rmb() to tell the compiler that system_state 91721afaf18SBorislav Petkov * might have been modified by someone else. 91821afaf18SBorislav Petkov */ 91921afaf18SBorislav Petkov rmb(); 92021afaf18SBorislav Petkov if (atomic_read(&mce_panicked)) 92121afaf18SBorislav Petkov wait_for_panic(); 92221afaf18SBorislav Petkov if (!mca_cfg.monarch_timeout) 92321afaf18SBorislav Petkov goto out; 92421afaf18SBorislav Petkov if ((s64)*t < SPINUNIT) { 9257bb39313SPaul E. McKenney if (cpumask_and(&mce_missing_cpus, cpu_online_mask, &mce_missing_cpus)) 9267bb39313SPaul E. McKenney pr_emerg("CPUs not responding to MCE broadcast (may include false positives): %*pbl\n", 9277bb39313SPaul E. McKenney cpumask_pr_args(&mce_missing_cpus)); 92821afaf18SBorislav Petkov mce_panic(msg, NULL, NULL); 9297f1b8e0dSBorislav Petkov 930edb3d07eSBorislav Petkov ret = 1; 931edb3d07eSBorislav Petkov goto out; 93221afaf18SBorislav Petkov } 93321afaf18SBorislav Petkov *t -= SPINUNIT; 934edb3d07eSBorislav Petkov 93521afaf18SBorislav Petkov out: 93621afaf18SBorislav Petkov touch_nmi_watchdog(); 937edb3d07eSBorislav Petkov 938edb3d07eSBorislav Petkov instrumentation_end(); 939edb3d07eSBorislav Petkov 940edb3d07eSBorislav Petkov return ret; 94121afaf18SBorislav Petkov } 94221afaf18SBorislav Petkov 94321afaf18SBorislav Petkov /* 94421afaf18SBorislav Petkov * The Monarch's reign. The Monarch is the CPU who entered 94521afaf18SBorislav Petkov * the machine check handler first. It waits for the others to 94621afaf18SBorislav Petkov * raise the exception too and then grades them. When any 94721afaf18SBorislav Petkov * error is fatal panic. Only then let the others continue. 94821afaf18SBorislav Petkov * 94921afaf18SBorislav Petkov * The other CPUs entering the MCE handler will be controlled by the 95021afaf18SBorislav Petkov * Monarch. They are called Subjects. 95121afaf18SBorislav Petkov * 95221afaf18SBorislav Petkov * This way we prevent any potential data corruption in a unrecoverable case 95321afaf18SBorislav Petkov * and also makes sure always all CPU's errors are examined. 95421afaf18SBorislav Petkov * 95521afaf18SBorislav Petkov * Also this detects the case of a machine check event coming from outer 95621afaf18SBorislav Petkov * space (not detected by any CPUs) In this case some external agent wants 95721afaf18SBorislav Petkov * us to shut down, so panic too. 95821afaf18SBorislav Petkov * 95921afaf18SBorislav Petkov * The other CPUs might still decide to panic if the handler happens 96021afaf18SBorislav Petkov * in a unrecoverable place, but in this case the system is in a semi-stable 96121afaf18SBorislav Petkov * state and won't corrupt anything by itself. It's ok to let the others 96221afaf18SBorislav Petkov * continue for a bit first. 96321afaf18SBorislav Petkov * 96421afaf18SBorislav Petkov * All the spin loops have timeouts; when a timeout happens a CPU 96521afaf18SBorislav Petkov * typically elects itself to be Monarch. 96621afaf18SBorislav Petkov */ 96721afaf18SBorislav Petkov static void mce_reign(void) 96821afaf18SBorislav Petkov { 96921afaf18SBorislav Petkov int cpu; 97021afaf18SBorislav Petkov struct mce *m = NULL; 97121afaf18SBorislav Petkov int global_worst = 0; 97221afaf18SBorislav Petkov char *msg = NULL; 97321afaf18SBorislav Petkov 97421afaf18SBorislav Petkov /* 97521afaf18SBorislav Petkov * This CPU is the Monarch and the other CPUs have run 97621afaf18SBorislav Petkov * through their handlers. 97721afaf18SBorislav Petkov * Grade the severity of the errors of all the CPUs. 97821afaf18SBorislav Petkov */ 97921afaf18SBorislav Petkov for_each_possible_cpu(cpu) { 98013c877f4STony Luck struct mce *mtmp = &per_cpu(mces_seen, cpu); 98113c877f4STony Luck 98213c877f4STony Luck if (mtmp->severity > global_worst) { 98313c877f4STony Luck global_worst = mtmp->severity; 98421afaf18SBorislav Petkov m = &per_cpu(mces_seen, cpu); 98521afaf18SBorislav Petkov } 98621afaf18SBorislav Petkov } 98721afaf18SBorislav Petkov 98821afaf18SBorislav Petkov /* 98921afaf18SBorislav Petkov * Cannot recover? Panic here then. 99021afaf18SBorislav Petkov * This dumps all the mces in the log buffer and stops the 99121afaf18SBorislav Petkov * other CPUs. 99221afaf18SBorislav Petkov */ 9937f1b8e0dSBorislav Petkov if (m && global_worst >= MCE_PANIC_SEVERITY) { 99413c877f4STony Luck /* call mce_severity() to get "msg" for panic */ 9957f1b8e0dSBorislav Petkov mce_severity(m, NULL, &msg, true); 99621afaf18SBorislav Petkov mce_panic("Fatal machine check", m, msg); 99713c877f4STony Luck } 99821afaf18SBorislav Petkov 99921afaf18SBorislav Petkov /* 100021afaf18SBorislav Petkov * For UC somewhere we let the CPU who detects it handle it. 100121afaf18SBorislav Petkov * Also must let continue the others, otherwise the handling 100221afaf18SBorislav Petkov * CPU could deadlock on a lock. 100321afaf18SBorislav Petkov */ 100421afaf18SBorislav Petkov 100521afaf18SBorislav Petkov /* 100621afaf18SBorislav Petkov * No machine check event found. Must be some external 100721afaf18SBorislav Petkov * source or one CPU is hung. Panic. 100821afaf18SBorislav Petkov */ 10097f1b8e0dSBorislav Petkov if (global_worst <= MCE_KEEP_SEVERITY) 101021afaf18SBorislav Petkov mce_panic("Fatal machine check from unknown source", NULL, NULL); 101121afaf18SBorislav Petkov 101221afaf18SBorislav Petkov /* 101321afaf18SBorislav Petkov * Now clear all the mces_seen so that they don't reappear on 101421afaf18SBorislav Petkov * the next mce. 101521afaf18SBorislav Petkov */ 101621afaf18SBorislav Petkov for_each_possible_cpu(cpu) 101721afaf18SBorislav Petkov memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); 101821afaf18SBorislav Petkov } 101921afaf18SBorislav Petkov 102021afaf18SBorislav Petkov static atomic_t global_nwo; 102121afaf18SBorislav Petkov 102221afaf18SBorislav Petkov /* 102321afaf18SBorislav Petkov * Start of Monarch synchronization. This waits until all CPUs have 102421afaf18SBorislav Petkov * entered the exception handler and then determines if any of them 102521afaf18SBorislav Petkov * saw a fatal event that requires panic. Then it executes them 102621afaf18SBorislav Petkov * in the entry order. 102721afaf18SBorislav Petkov * TBD double check parallel CPU hotunplug 102821afaf18SBorislav Petkov */ 1029e3d72e8eSBorislav Petkov static noinstr int mce_start(int *no_way_out) 103021afaf18SBorislav Petkov { 103121afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 1032e3d72e8eSBorislav Petkov int order, ret = -1; 103321afaf18SBorislav Petkov 103421afaf18SBorislav Petkov if (!timeout) 1035e3d72e8eSBorislav Petkov return ret; 103621afaf18SBorislav Petkov 1037f11445baSBorislav Petkov arch_atomic_add(*no_way_out, &global_nwo); 103821afaf18SBorislav Petkov /* 103921afaf18SBorislav Petkov * Rely on the implied barrier below, such that global_nwo 104021afaf18SBorislav Petkov * is updated before mce_callin. 104121afaf18SBorislav Petkov */ 1042f11445baSBorislav Petkov order = arch_atomic_inc_return(&mce_callin); 1043f11445baSBorislav Petkov arch_cpumask_clear_cpu(smp_processor_id(), &mce_missing_cpus); 104421afaf18SBorislav Petkov 1045e3d72e8eSBorislav Petkov /* Enable instrumentation around calls to external facilities */ 1046e3d72e8eSBorislav Petkov instrumentation_begin(); 1047e3d72e8eSBorislav Petkov 104821afaf18SBorislav Petkov /* 104921afaf18SBorislav Petkov * Wait for everyone. 105021afaf18SBorislav Petkov */ 1051f11445baSBorislav Petkov while (arch_atomic_read(&mce_callin) != num_online_cpus()) { 105221afaf18SBorislav Petkov if (mce_timed_out(&timeout, 105321afaf18SBorislav Petkov "Timeout: Not all CPUs entered broadcast exception handler")) { 1054f11445baSBorislav Petkov arch_atomic_set(&global_nwo, 0); 1055e3d72e8eSBorislav Petkov goto out; 105621afaf18SBorislav Petkov } 105721afaf18SBorislav Petkov ndelay(SPINUNIT); 105821afaf18SBorislav Petkov } 105921afaf18SBorislav Petkov 106021afaf18SBorislav Petkov /* 106121afaf18SBorislav Petkov * mce_callin should be read before global_nwo 106221afaf18SBorislav Petkov */ 106321afaf18SBorislav Petkov smp_rmb(); 106421afaf18SBorislav Petkov 106521afaf18SBorislav Petkov if (order == 1) { 106621afaf18SBorislav Petkov /* 106721afaf18SBorislav Petkov * Monarch: Starts executing now, the others wait. 106821afaf18SBorislav Petkov */ 1069f11445baSBorislav Petkov arch_atomic_set(&mce_executing, 1); 107021afaf18SBorislav Petkov } else { 107121afaf18SBorislav Petkov /* 107221afaf18SBorislav Petkov * Subject: Now start the scanning loop one by one in 107321afaf18SBorislav Petkov * the original callin order. 107421afaf18SBorislav Petkov * This way when there are any shared banks it will be 107521afaf18SBorislav Petkov * only seen by one CPU before cleared, avoiding duplicates. 107621afaf18SBorislav Petkov */ 1077f11445baSBorislav Petkov while (arch_atomic_read(&mce_executing) < order) { 107821afaf18SBorislav Petkov if (mce_timed_out(&timeout, 107921afaf18SBorislav Petkov "Timeout: Subject CPUs unable to finish machine check processing")) { 1080f11445baSBorislav Petkov arch_atomic_set(&global_nwo, 0); 1081e3d72e8eSBorislav Petkov goto out; 108221afaf18SBorislav Petkov } 108321afaf18SBorislav Petkov ndelay(SPINUNIT); 108421afaf18SBorislav Petkov } 108521afaf18SBorislav Petkov } 108621afaf18SBorislav Petkov 108721afaf18SBorislav Petkov /* 108821afaf18SBorislav Petkov * Cache the global no_way_out state. 108921afaf18SBorislav Petkov */ 1090f11445baSBorislav Petkov *no_way_out = arch_atomic_read(&global_nwo); 109121afaf18SBorislav Petkov 1092e3d72e8eSBorislav Petkov ret = order; 1093e3d72e8eSBorislav Petkov 1094e3d72e8eSBorislav Petkov out: 1095e3d72e8eSBorislav Petkov instrumentation_end(); 1096e3d72e8eSBorislav Petkov 1097e3d72e8eSBorislav Petkov return ret; 109821afaf18SBorislav Petkov } 109921afaf18SBorislav Petkov 110021afaf18SBorislav Petkov /* 110121afaf18SBorislav Petkov * Synchronize between CPUs after main scanning loop. 110221afaf18SBorislav Petkov * This invokes the bulk of the Monarch processing. 110321afaf18SBorislav Petkov */ 1104b4813539SBorislav Petkov static noinstr int mce_end(int order) 110521afaf18SBorislav Petkov { 110621afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 1107b4813539SBorislav Petkov int ret = -1; 1108b4813539SBorislav Petkov 1109b4813539SBorislav Petkov /* Allow instrumentation around external facilities. */ 1110b4813539SBorislav Petkov instrumentation_begin(); 111121afaf18SBorislav Petkov 111221afaf18SBorislav Petkov if (!timeout) 111321afaf18SBorislav Petkov goto reset; 111421afaf18SBorislav Petkov if (order < 0) 111521afaf18SBorislav Petkov goto reset; 111621afaf18SBorislav Petkov 111721afaf18SBorislav Petkov /* 111821afaf18SBorislav Petkov * Allow others to run. 111921afaf18SBorislav Petkov */ 112021afaf18SBorislav Petkov atomic_inc(&mce_executing); 112121afaf18SBorislav Petkov 112221afaf18SBorislav Petkov if (order == 1) { 112321afaf18SBorislav Petkov /* 112421afaf18SBorislav Petkov * Monarch: Wait for everyone to go through their scanning 112521afaf18SBorislav Petkov * loops. 112621afaf18SBorislav Petkov */ 1127ad669ec1SBorislav Petkov while (atomic_read(&mce_executing) <= num_online_cpus()) { 112821afaf18SBorislav Petkov if (mce_timed_out(&timeout, 112921afaf18SBorislav Petkov "Timeout: Monarch CPU unable to finish machine check processing")) 113021afaf18SBorislav Petkov goto reset; 113121afaf18SBorislav Petkov ndelay(SPINUNIT); 113221afaf18SBorislav Petkov } 113321afaf18SBorislav Petkov 113421afaf18SBorislav Petkov mce_reign(); 113521afaf18SBorislav Petkov barrier(); 113621afaf18SBorislav Petkov ret = 0; 113721afaf18SBorislav Petkov } else { 113821afaf18SBorislav Petkov /* 113921afaf18SBorislav Petkov * Subject: Wait for Monarch to finish. 114021afaf18SBorislav Petkov */ 114121afaf18SBorislav Petkov while (atomic_read(&mce_executing) != 0) { 114221afaf18SBorislav Petkov if (mce_timed_out(&timeout, 114321afaf18SBorislav Petkov "Timeout: Monarch CPU did not finish machine check processing")) 114421afaf18SBorislav Petkov goto reset; 114521afaf18SBorislav Petkov ndelay(SPINUNIT); 114621afaf18SBorislav Petkov } 114721afaf18SBorislav Petkov 114821afaf18SBorislav Petkov /* 114921afaf18SBorislav Petkov * Don't reset anything. That's done by the Monarch. 115021afaf18SBorislav Petkov */ 1151b4813539SBorislav Petkov ret = 0; 1152b4813539SBorislav Petkov goto out; 115321afaf18SBorislav Petkov } 115421afaf18SBorislav Petkov 115521afaf18SBorislav Petkov /* 115621afaf18SBorislav Petkov * Reset all global state. 115721afaf18SBorislav Petkov */ 115821afaf18SBorislav Petkov reset: 115921afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 116021afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 11617bb39313SPaul E. McKenney cpumask_setall(&mce_missing_cpus); 116221afaf18SBorislav Petkov barrier(); 116321afaf18SBorislav Petkov 116421afaf18SBorislav Petkov /* 116521afaf18SBorislav Petkov * Let others run again. 116621afaf18SBorislav Petkov */ 116721afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 1168b4813539SBorislav Petkov 1169b4813539SBorislav Petkov out: 1170b4813539SBorislav Petkov instrumentation_end(); 1171b4813539SBorislav Petkov 117221afaf18SBorislav Petkov return ret; 117321afaf18SBorislav Petkov } 117421afaf18SBorislav Petkov 1175f11445baSBorislav Petkov static __always_inline void mce_clear_state(unsigned long *toclear) 117621afaf18SBorislav Petkov { 117721afaf18SBorislav Petkov int i; 117821afaf18SBorislav Petkov 1179c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1180f11445baSBorislav Petkov if (arch_test_bit(i, toclear)) 11818121b8f9SBorislav Petkov mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 118221afaf18SBorislav Petkov } 118321afaf18SBorislav Petkov } 118421afaf18SBorislav Petkov 118521afaf18SBorislav Petkov /* 118621afaf18SBorislav Petkov * Cases where we avoid rendezvous handler timeout: 118721afaf18SBorislav Petkov * 1) If this CPU is offline. 118821afaf18SBorislav Petkov * 118921afaf18SBorislav Petkov * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to 119021afaf18SBorislav Petkov * skip those CPUs which remain looping in the 1st kernel - see 119121afaf18SBorislav Petkov * crash_nmi_callback(). 119221afaf18SBorislav Petkov * 119321afaf18SBorislav Petkov * Note: there still is a small window between kexec-ing and the new, 119421afaf18SBorislav Petkov * kdump kernel establishing a new #MC handler where a broadcasted MCE 119521afaf18SBorislav Petkov * might not get handled properly. 119621afaf18SBorislav Petkov */ 119794a46d31SThomas Gleixner static noinstr bool mce_check_crashing_cpu(void) 119821afaf18SBorislav Petkov { 119994a46d31SThomas Gleixner unsigned int cpu = smp_processor_id(); 120094a46d31SThomas Gleixner 120114d3b376SPeter Zijlstra if (arch_cpu_is_offline(cpu) || 120221afaf18SBorislav Petkov (crashing_cpu != -1 && crashing_cpu != cpu)) { 120321afaf18SBorislav Petkov u64 mcgstatus; 120421afaf18SBorislav Petkov 1205aedbdeabSThomas Gleixner mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS); 120670f0c230STony W Wang-oc 120770f0c230STony W Wang-oc if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { 120870f0c230STony W Wang-oc if (mcgstatus & MCG_STATUS_LMCES) 120970f0c230STony W Wang-oc return false; 121070f0c230STony W Wang-oc } 121170f0c230STony W Wang-oc 121221afaf18SBorislav Petkov if (mcgstatus & MCG_STATUS_RIPV) { 1213aedbdeabSThomas Gleixner __wrmsr(MSR_IA32_MCG_STATUS, 0, 0); 121421afaf18SBorislav Petkov return true; 121521afaf18SBorislav Petkov } 121621afaf18SBorislav Petkov } 121721afaf18SBorislav Petkov return false; 121821afaf18SBorislav Petkov } 121921afaf18SBorislav Petkov 122075581a20SBorislav Petkov static __always_inline int 122175581a20SBorislav Petkov __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final, 122275581a20SBorislav Petkov unsigned long *toclear, unsigned long *valid_banks, int no_way_out, 122375581a20SBorislav Petkov int *worst) 122421afaf18SBorislav Petkov { 1225b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 122621afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 122775581a20SBorislav Petkov int severity, i, taint = 0; 122821afaf18SBorislav Petkov 1229c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1230f11445baSBorislav Petkov arch___clear_bit(i, toclear); 1231f11445baSBorislav Petkov if (!arch_test_bit(i, valid_banks)) 123221afaf18SBorislav Petkov continue; 123321afaf18SBorislav Petkov 123421afaf18SBorislav Petkov if (!mce_banks[i].ctl) 123521afaf18SBorislav Petkov continue; 123621afaf18SBorislav Petkov 123721afaf18SBorislav Petkov m->misc = 0; 123821afaf18SBorislav Petkov m->addr = 0; 123921afaf18SBorislav Petkov m->bank = i; 124021afaf18SBorislav Petkov 12418121b8f9SBorislav Petkov m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 124221afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 124321afaf18SBorislav Petkov continue; 124421afaf18SBorislav Petkov 124521afaf18SBorislav Petkov /* 124621afaf18SBorislav Petkov * Corrected or non-signaled errors are handled by 124721afaf18SBorislav Petkov * machine_check_poll(). Leave them alone, unless this panics. 124821afaf18SBorislav Petkov */ 124921afaf18SBorislav Petkov if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && 125021afaf18SBorislav Petkov !no_way_out) 125121afaf18SBorislav Petkov continue; 125221afaf18SBorislav Petkov 125321afaf18SBorislav Petkov /* Set taint even when machine check was not enabled. */ 125475581a20SBorislav Petkov taint++; 125521afaf18SBorislav Petkov 12567f1b8e0dSBorislav Petkov severity = mce_severity(m, regs, NULL, true); 125721afaf18SBorislav Petkov 125821afaf18SBorislav Petkov /* 125921afaf18SBorislav Petkov * When machine check was for corrected/deferred handler don't 126021afaf18SBorislav Petkov * touch, unless we're panicking. 126121afaf18SBorislav Petkov */ 126221afaf18SBorislav Petkov if ((severity == MCE_KEEP_SEVERITY || 126321afaf18SBorislav Petkov severity == MCE_UCNA_SEVERITY) && !no_way_out) 126421afaf18SBorislav Petkov continue; 126521afaf18SBorislav Petkov 1266f11445baSBorislav Petkov arch___set_bit(i, toclear); 126721afaf18SBorislav Petkov 126821afaf18SBorislav Petkov /* Machine check event was not enabled. Clear, but ignore. */ 126921afaf18SBorislav Petkov if (severity == MCE_NO_SEVERITY) 127021afaf18SBorislav Petkov continue; 127121afaf18SBorislav Petkov 127221afaf18SBorislav Petkov mce_read_aux(m, i); 127321afaf18SBorislav Petkov 127421afaf18SBorislav Petkov /* assuming valid severity level != 0 */ 127521afaf18SBorislav Petkov m->severity = severity; 127621afaf18SBorislav Petkov 127775581a20SBorislav Petkov /* 127875581a20SBorislav Petkov * Enable instrumentation around the mce_log() call which is 127975581a20SBorislav Petkov * done in #MC context, where instrumentation is disabled. 128075581a20SBorislav Petkov */ 128175581a20SBorislav Petkov instrumentation_begin(); 128221afaf18SBorislav Petkov mce_log(m); 128375581a20SBorislav Petkov instrumentation_end(); 128421afaf18SBorislav Petkov 128521afaf18SBorislav Petkov if (severity > *worst) { 128621afaf18SBorislav Petkov *final = *m; 128721afaf18SBorislav Petkov *worst = severity; 128821afaf18SBorislav Petkov } 128921afaf18SBorislav Petkov } 129021afaf18SBorislav Petkov 129121afaf18SBorislav Petkov /* mce_clear_state will clear *final, save locally for use later */ 129221afaf18SBorislav Petkov *m = *final; 129375581a20SBorislav Petkov 129475581a20SBorislav Petkov return taint; 129521afaf18SBorislav Petkov } 129621afaf18SBorislav Petkov 12975567d11cSPeter Zijlstra static void kill_me_now(struct callback_head *ch) 12985567d11cSPeter Zijlstra { 129981065b35STony Luck struct task_struct *p = container_of(ch, struct task_struct, mce_kill_me); 130081065b35STony Luck 130181065b35STony Luck p->mce_count = 0; 13025567d11cSPeter Zijlstra force_sig(SIGBUS); 13035567d11cSPeter Zijlstra } 13045567d11cSPeter Zijlstra 13055567d11cSPeter Zijlstra static void kill_me_maybe(struct callback_head *cb) 13065567d11cSPeter Zijlstra { 13075567d11cSPeter Zijlstra struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me); 13085567d11cSPeter Zijlstra int flags = MF_ACTION_REQUIRED; 1309a3f5d80eSNaoya Horiguchi int ret; 13105567d11cSPeter Zijlstra 131181065b35STony Luck p->mce_count = 0; 13125567d11cSPeter Zijlstra pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr); 131317fae129STony Luck 131417fae129STony Luck if (!p->mce_ripv) 13155567d11cSPeter Zijlstra flags |= MF_MUST_KILL; 13165567d11cSPeter Zijlstra 1317a3f5d80eSNaoya Horiguchi ret = memory_failure(p->mce_addr >> PAGE_SHIFT, flags); 1318a6e3cf70STony Luck if (!ret) { 1319*5898b43aSJane Chu set_mce_nospec(p->mce_addr >> PAGE_SHIFT); 13201e36d9c6STony Luck sync_core(); 13215567d11cSPeter Zijlstra return; 13225567d11cSPeter Zijlstra } 13235567d11cSPeter Zijlstra 1324a3f5d80eSNaoya Horiguchi /* 1325a3f5d80eSNaoya Horiguchi * -EHWPOISON from memory_failure() means that it already sent SIGBUS 1326d1fe111fSluofei * to the current process with the proper error info, 1327d1fe111fSluofei * -EOPNOTSUPP means hwpoison_filter() filtered the error event, 1328d1fe111fSluofei * 1329d1fe111fSluofei * In both cases, no further processing is required. 1330a3f5d80eSNaoya Horiguchi */ 1331d1fe111fSluofei if (ret == -EHWPOISON || ret == -EOPNOTSUPP) 1332a3f5d80eSNaoya Horiguchi return; 1333a3f5d80eSNaoya Horiguchi 13345567d11cSPeter Zijlstra pr_err("Memory error not recovered"); 13355567d11cSPeter Zijlstra kill_me_now(cb); 13365567d11cSPeter Zijlstra } 1337a6e3cf70STony Luck 1338a6e3cf70STony Luck static void kill_me_never(struct callback_head *cb) 1339a6e3cf70STony Luck { 1340a6e3cf70STony Luck struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me); 1341a6e3cf70STony Luck 1342a6e3cf70STony Luck p->mce_count = 0; 1343a6e3cf70STony Luck pr_err("Kernel accessed poison in user space at %llx\n", p->mce_addr); 1344a6e3cf70STony Luck if (!memory_failure(p->mce_addr >> PAGE_SHIFT, 0)) 1345*5898b43aSJane Chu set_mce_nospec(p->mce_addr >> PAGE_SHIFT); 134630063810STony Luck } 13475567d11cSPeter Zijlstra 1348a6e3cf70STony Luck static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callback_head *)) 1349c0ab7ffcSTony Luck { 135081065b35STony Luck int count = ++current->mce_count; 135181065b35STony Luck 135281065b35STony Luck /* First call, save all the details */ 135381065b35STony Luck if (count == 1) { 1354c0ab7ffcSTony Luck current->mce_addr = m->addr; 1355c0ab7ffcSTony Luck current->mce_kflags = m->kflags; 1356c0ab7ffcSTony Luck current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV); 1357c0ab7ffcSTony Luck current->mce_whole_page = whole_page(m); 1358a6e3cf70STony Luck current->mce_kill_me.func = func; 135981065b35STony Luck } 136081065b35STony Luck 136181065b35STony Luck /* Ten is likely overkill. Don't expect more than two faults before task_work() */ 136281065b35STony Luck if (count > 10) 136381065b35STony Luck mce_panic("Too many consecutive machine checks while accessing user data", m, msg); 136481065b35STony Luck 136581065b35STony Luck /* Second or later call, make sure page address matches the one from first call */ 136681065b35STony Luck if (count > 1 && (current->mce_addr >> PAGE_SHIFT) != (m->addr >> PAGE_SHIFT)) 136781065b35STony Luck mce_panic("Consecutive machine checks to different user pages", m, msg); 136881065b35STony Luck 136981065b35STony Luck /* Do not call task_work_add() more than once */ 137081065b35STony Luck if (count > 1) 137181065b35STony Luck return; 1372c0ab7ffcSTony Luck 137391989c70SJens Axboe task_work_add(current, ¤t->mce_kill_me, TWA_RESUME); 1374c0ab7ffcSTony Luck } 137521afaf18SBorislav Petkov 1376cbe1de16SBorislav Petkov /* Handle unconfigured int18 (should never happen) */ 1377cbe1de16SBorislav Petkov static noinstr void unexpected_machine_check(struct pt_regs *regs) 1378cbe1de16SBorislav Petkov { 1379cbe1de16SBorislav Petkov instrumentation_begin(); 1380cbe1de16SBorislav Petkov pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", 1381cbe1de16SBorislav Petkov smp_processor_id()); 1382cbe1de16SBorislav Petkov instrumentation_end(); 1383cbe1de16SBorislav Petkov } 1384cbe1de16SBorislav Petkov 138521afaf18SBorislav Petkov /* 1386487d654dSBorislav Petkov * The actual machine check handler. This only handles real exceptions when 1387487d654dSBorislav Petkov * something got corrupted coming in through int 18. 138821afaf18SBorislav Petkov * 1389487d654dSBorislav Petkov * This is executed in #MC context not subject to normal locking rules. 1390487d654dSBorislav Petkov * This implies that most kernel services cannot be safely used. Don't even 139121afaf18SBorislav Petkov * think about putting a printk in there! 139221afaf18SBorislav Petkov * 139321afaf18SBorislav Petkov * On Intel systems this is entered on all CPUs in parallel through 139421afaf18SBorislav Petkov * MCE broadcast. However some CPUs might be broken beyond repair, 139521afaf18SBorislav Petkov * so be always careful when synchronizing with others. 139655ba18d6SAndy Lutomirski * 139755ba18d6SAndy Lutomirski * Tracing and kprobes are disabled: if we interrupted a kernel context 139855ba18d6SAndy Lutomirski * with IF=1, we need to minimize stack usage. There are also recursion 139955ba18d6SAndy Lutomirski * issues: if the machine check was due to a failure of the memory 140055ba18d6SAndy Lutomirski * backing the user stack, tracing that reads the user stack will cause 140155ba18d6SAndy Lutomirski * potentially infinite recursion. 1402487d654dSBorislav Petkov * 1403487d654dSBorislav Petkov * Currently, the #MC handler calls out to a number of external facilities 1404487d654dSBorislav Petkov * and, therefore, allows instrumentation around them. The optimal thing to 1405487d654dSBorislav Petkov * have would be to do the absolutely minimal work required in #MC context 1406487d654dSBorislav Petkov * and have instrumentation disabled only around that. Further processing can 1407487d654dSBorislav Petkov * then happen in process context where instrumentation is allowed. Achieving 1408487d654dSBorislav Petkov * that requires careful auditing and modifications. Until then, the code 1409487d654dSBorislav Petkov * allows instrumentation temporarily, where required. * 141021afaf18SBorislav Petkov */ 14117f6fa101SIra Weiny noinstr void do_machine_check(struct pt_regs *regs) 141221afaf18SBorislav Petkov { 141375581a20SBorislav Petkov int worst = 0, order, no_way_out, kill_current_task, lmce, taint = 0; 1414cd5e0d1fSBorislav Petkov DECLARE_BITMAP(valid_banks, MAX_NR_BANKS) = { 0 }; 1415cd5e0d1fSBorislav Petkov DECLARE_BITMAP(toclear, MAX_NR_BANKS) = { 0 }; 141621afaf18SBorislav Petkov struct mce m, *final; 14177a8bc2b0SJan H. Schönherr char *msg = NULL; 1418cbe1de16SBorislav Petkov 1419cbe1de16SBorislav Petkov if (unlikely(mce_flags.p5)) 1420cbe1de16SBorislav Petkov return pentium_machine_check(regs); 1421cbe1de16SBorislav Petkov else if (unlikely(mce_flags.winchip)) 1422cbe1de16SBorislav Petkov return winchip_machine_check(regs); 1423cbe1de16SBorislav Petkov else if (unlikely(!mca_cfg.initialized)) 1424cbe1de16SBorislav Petkov return unexpected_machine_check(regs); 142521afaf18SBorislav Petkov 14268ca97812SJue Wang if (mce_flags.skx_repmov_quirk && quirk_skylake_repmov()) 14278ca97812SJue Wang goto clear; 14288ca97812SJue Wang 142921afaf18SBorislav Petkov /* 143021afaf18SBorislav Petkov * Establish sequential order between the CPUs entering the machine 143121afaf18SBorislav Petkov * check handler. 143221afaf18SBorislav Petkov */ 1433cbe1de16SBorislav Petkov order = -1; 143421afaf18SBorislav Petkov 143521afaf18SBorislav Petkov /* 143621afaf18SBorislav Petkov * If no_way_out gets set, there is no safe way to recover from this 14377f1b8e0dSBorislav Petkov * MCE. 143821afaf18SBorislav Petkov */ 1439cbe1de16SBorislav Petkov no_way_out = 0; 144021afaf18SBorislav Petkov 144121afaf18SBorislav Petkov /* 1442e1c06d23SGabriele Paoloni * If kill_current_task is not set, there might be a way to recover from this 144321afaf18SBorislav Petkov * error. 144421afaf18SBorislav Petkov */ 1445cbe1de16SBorislav Petkov kill_current_task = 0; 144621afaf18SBorislav Petkov 144721afaf18SBorislav Petkov /* 144821afaf18SBorislav Petkov * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES 144921afaf18SBorislav Petkov * on Intel. 145021afaf18SBorislav Petkov */ 1451cbe1de16SBorislav Petkov lmce = 1; 145221afaf18SBorislav Petkov 145321afaf18SBorislav Petkov this_cpu_inc(mce_exception_count); 145421afaf18SBorislav Petkov 145521afaf18SBorislav Petkov mce_gather_info(&m, regs); 145621afaf18SBorislav Petkov m.tsc = rdtsc(); 145721afaf18SBorislav Petkov 145821afaf18SBorislav Petkov final = this_cpu_ptr(&mces_seen); 145921afaf18SBorislav Petkov *final = m; 146021afaf18SBorislav Petkov 146121afaf18SBorislav Petkov no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); 146221afaf18SBorislav Petkov 146321afaf18SBorislav Petkov barrier(); 146421afaf18SBorislav Petkov 146521afaf18SBorislav Petkov /* 146621afaf18SBorislav Petkov * When no restart IP might need to kill or panic. 146721afaf18SBorislav Petkov * Assume the worst for now, but if we find the 146821afaf18SBorislav Petkov * severity is MCE_AR_SEVERITY we have other options. 146921afaf18SBorislav Petkov */ 147021afaf18SBorislav Petkov if (!(m.mcgstatus & MCG_STATUS_RIPV)) 14717f1b8e0dSBorislav Petkov kill_current_task = 1; 147221afaf18SBorislav Petkov /* 147321afaf18SBorislav Petkov * Check if this MCE is signaled to only this logical processor, 147470f0c230STony W Wang-oc * on Intel, Zhaoxin only. 147521afaf18SBorislav Petkov */ 147670f0c230STony W Wang-oc if (m.cpuvendor == X86_VENDOR_INTEL || 147770f0c230STony W Wang-oc m.cpuvendor == X86_VENDOR_ZHAOXIN) 147821afaf18SBorislav Petkov lmce = m.mcgstatus & MCG_STATUS_LMCES; 147921afaf18SBorislav Petkov 148021afaf18SBorislav Petkov /* 148121afaf18SBorislav Petkov * Local machine check may already know that we have to panic. 148221afaf18SBorislav Petkov * Broadcast machine check begins rendezvous in mce_start() 148321afaf18SBorislav Petkov * Go through all banks in exclusion of the other CPUs. This way we 148421afaf18SBorislav Petkov * don't report duplicated events on shared banks because the first one 148521afaf18SBorislav Petkov * to see it will clear it. 148621afaf18SBorislav Petkov */ 148721afaf18SBorislav Petkov if (lmce) { 14887f1b8e0dSBorislav Petkov if (no_way_out) 148921afaf18SBorislav Petkov mce_panic("Fatal local machine check", &m, msg); 149021afaf18SBorislav Petkov } else { 149121afaf18SBorislav Petkov order = mce_start(&no_way_out); 149221afaf18SBorislav Petkov } 149321afaf18SBorislav Petkov 149475581a20SBorislav Petkov taint = __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst); 149521afaf18SBorislav Petkov 149621afaf18SBorislav Petkov if (!no_way_out) 149721afaf18SBorislav Petkov mce_clear_state(toclear); 149821afaf18SBorislav Petkov 149921afaf18SBorislav Petkov /* 150021afaf18SBorislav Petkov * Do most of the synchronization with other CPUs. 150121afaf18SBorislav Petkov * When there's any problem use only local no_way_out state. 150221afaf18SBorislav Petkov */ 150321afaf18SBorislav Petkov if (!lmce) { 150425bc65d8SGabriele Paoloni if (mce_end(order) < 0) { 150525bc65d8SGabriele Paoloni if (!no_way_out) 150621afaf18SBorislav Petkov no_way_out = worst >= MCE_PANIC_SEVERITY; 1507e273e6e1SGabriele Paoloni 15087f1b8e0dSBorislav Petkov if (no_way_out) 1509e273e6e1SGabriele Paoloni mce_panic("Fatal machine check on current CPU", &m, msg); 151025bc65d8SGabriele Paoloni } 151121afaf18SBorislav Petkov } else { 151221afaf18SBorislav Petkov /* 151321afaf18SBorislav Petkov * If there was a fatal machine check we should have 151421afaf18SBorislav Petkov * already called mce_panic earlier in this function. 151521afaf18SBorislav Petkov * Since we re-read the banks, we might have found 151621afaf18SBorislav Petkov * something new. Check again to see if we found a 151721afaf18SBorislav Petkov * fatal error. We call "mce_severity()" again to 151821afaf18SBorislav Petkov * make sure we have the right "msg". 151921afaf18SBorislav Petkov */ 15207f1b8e0dSBorislav Petkov if (worst >= MCE_PANIC_SEVERITY) { 15217f1b8e0dSBorislav Petkov mce_severity(&m, regs, &msg, true); 152221afaf18SBorislav Petkov mce_panic("Local fatal machine check!", &m, msg); 152321afaf18SBorislav Petkov } 152421afaf18SBorislav Petkov } 152521afaf18SBorislav Petkov 15264fbce464SBorislav Petkov /* 152775581a20SBorislav Petkov * Enable instrumentation around the external facilities like task_work_add() 152875581a20SBorislav Petkov * (via queue_task_work()), fixup_exception() etc. For now, that is. Fixing this 152975581a20SBorislav Petkov * properly would need a lot more involved reorganization. 15304fbce464SBorislav Petkov */ 15314fbce464SBorislav Petkov instrumentation_begin(); 15324fbce464SBorislav Petkov 153375581a20SBorislav Petkov if (taint) 153475581a20SBorislav Petkov add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 153575581a20SBorislav Petkov 153675581a20SBorislav Petkov if (worst != MCE_AR_SEVERITY && !kill_current_task) 153775581a20SBorislav Petkov goto out; 153875581a20SBorislav Petkov 153921afaf18SBorislav Petkov /* Fault was in user mode and we need to take some action */ 154021afaf18SBorislav Petkov if ((m.cs & 3) == 3) { 1541b052df3dSThomas Gleixner /* If this triggers there is no way to recover. Die hard. */ 1542b052df3dSThomas Gleixner BUG_ON(!on_thread_stack() || !user_mode(regs)); 154321afaf18SBorislav Petkov 1544a6e3cf70STony Luck if (kill_current_task) 1545a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_now); 1546a6e3cf70STony Luck else 1547a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_maybe); 1548c0ab7ffcSTony Luck 154921afaf18SBorislav Petkov } else { 15501df73b21SBorislav Petkov /* 15511df73b21SBorislav Petkov * Handle an MCE which has happened in kernel space but from 15521df73b21SBorislav Petkov * which the kernel can recover: ex_has_fault_handler() has 15531df73b21SBorislav Petkov * already verified that the rIP at which the error happened is 15541df73b21SBorislav Petkov * a rIP from which the kernel can recover (by jumping to 15551df73b21SBorislav Petkov * recovery code specified in _ASM_EXTABLE_FAULT()) and the 15561df73b21SBorislav Petkov * corresponding exception handler which would do that is the 15571df73b21SBorislav Petkov * proper one. 15581df73b21SBorislav Petkov */ 15591df73b21SBorislav Petkov if (m.kflags & MCE_IN_KERNEL_RECOV) { 15608cd501c1SThomas Gleixner if (!fixup_exception(regs, X86_TRAP_MC, 0, 0)) 15612d806d07SJan H. Schönherr mce_panic("Failed kernel mode recovery", &m, msg); 156221afaf18SBorislav Petkov } 1563c0ab7ffcSTony Luck 1564c0ab7ffcSTony Luck if (m.kflags & MCE_IN_KERNEL_COPYIN) 1565a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_never); 15661df73b21SBorislav Petkov } 15674fbce464SBorislav Petkov 156875581a20SBorislav Petkov out: 15694fbce464SBorislav Petkov instrumentation_end(); 15704fbce464SBorislav Petkov 15718ca97812SJue Wang clear: 15721e36d9c6STony Luck mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); 157321afaf18SBorislav Petkov } 157421afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(do_machine_check); 157521afaf18SBorislav Petkov 157621afaf18SBorislav Petkov #ifndef CONFIG_MEMORY_FAILURE 157721afaf18SBorislav Petkov int memory_failure(unsigned long pfn, int flags) 157821afaf18SBorislav Petkov { 157921afaf18SBorislav Petkov /* mce_severity() should not hand us an ACTION_REQUIRED error */ 158021afaf18SBorislav Petkov BUG_ON(flags & MF_ACTION_REQUIRED); 158121afaf18SBorislav Petkov pr_err("Uncorrected memory error in page 0x%lx ignored\n" 158221afaf18SBorislav Petkov "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", 158321afaf18SBorislav Petkov pfn); 158421afaf18SBorislav Petkov 158521afaf18SBorislav Petkov return 0; 158621afaf18SBorislav Petkov } 158721afaf18SBorislav Petkov #endif 158821afaf18SBorislav Petkov 158921afaf18SBorislav Petkov /* 159021afaf18SBorislav Petkov * Periodic polling timer for "silent" machine check errors. If the 159121afaf18SBorislav Petkov * poller finds an MCE, poll 2x faster. When the poller finds no more 159221afaf18SBorislav Petkov * errors, poll 2x slower (up to check_interval seconds). 159321afaf18SBorislav Petkov */ 159421afaf18SBorislav Petkov static unsigned long check_interval = INITIAL_CHECK_INTERVAL; 159521afaf18SBorislav Petkov 159621afaf18SBorislav Petkov static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ 159721afaf18SBorislav Petkov static DEFINE_PER_CPU(struct timer_list, mce_timer); 159821afaf18SBorislav Petkov 159921afaf18SBorislav Petkov static unsigned long mce_adjust_timer_default(unsigned long interval) 160021afaf18SBorislav Petkov { 160121afaf18SBorislav Petkov return interval; 160221afaf18SBorislav Petkov } 160321afaf18SBorislav Petkov 160421afaf18SBorislav Petkov static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; 160521afaf18SBorislav Petkov 160621afaf18SBorislav Petkov static void __start_timer(struct timer_list *t, unsigned long interval) 160721afaf18SBorislav Petkov { 160821afaf18SBorislav Petkov unsigned long when = jiffies + interval; 160921afaf18SBorislav Petkov unsigned long flags; 161021afaf18SBorislav Petkov 161121afaf18SBorislav Petkov local_irq_save(flags); 161221afaf18SBorislav Petkov 161321afaf18SBorislav Petkov if (!timer_pending(t) || time_before(when, t->expires)) 161421afaf18SBorislav Petkov mod_timer(t, round_jiffies(when)); 161521afaf18SBorislav Petkov 161621afaf18SBorislav Petkov local_irq_restore(flags); 161721afaf18SBorislav Petkov } 161821afaf18SBorislav Petkov 161921afaf18SBorislav Petkov static void mce_timer_fn(struct timer_list *t) 162021afaf18SBorislav Petkov { 162121afaf18SBorislav Petkov struct timer_list *cpu_t = this_cpu_ptr(&mce_timer); 162221afaf18SBorislav Petkov unsigned long iv; 162321afaf18SBorislav Petkov 162421afaf18SBorislav Petkov WARN_ON(cpu_t != t); 162521afaf18SBorislav Petkov 162621afaf18SBorislav Petkov iv = __this_cpu_read(mce_next_interval); 162721afaf18SBorislav Petkov 162821afaf18SBorislav Petkov if (mce_available(this_cpu_ptr(&cpu_info))) { 162921afaf18SBorislav Petkov machine_check_poll(0, this_cpu_ptr(&mce_poll_banks)); 163021afaf18SBorislav Petkov 163121afaf18SBorislav Petkov if (mce_intel_cmci_poll()) { 163221afaf18SBorislav Petkov iv = mce_adjust_timer(iv); 163321afaf18SBorislav Petkov goto done; 163421afaf18SBorislav Petkov } 163521afaf18SBorislav Petkov } 163621afaf18SBorislav Petkov 163721afaf18SBorislav Petkov /* 163821afaf18SBorislav Petkov * Alert userspace if needed. If we logged an MCE, reduce the polling 163921afaf18SBorislav Petkov * interval, otherwise increase the polling interval. 164021afaf18SBorislav Petkov */ 164121afaf18SBorislav Petkov if (mce_notify_irq()) 164221afaf18SBorislav Petkov iv = max(iv / 2, (unsigned long) HZ/100); 164321afaf18SBorislav Petkov else 164421afaf18SBorislav Petkov iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); 164521afaf18SBorislav Petkov 164621afaf18SBorislav Petkov done: 164721afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, iv); 164821afaf18SBorislav Petkov __start_timer(t, iv); 164921afaf18SBorislav Petkov } 165021afaf18SBorislav Petkov 165121afaf18SBorislav Petkov /* 165221afaf18SBorislav Petkov * Ensure that the timer is firing in @interval from now. 165321afaf18SBorislav Petkov */ 165421afaf18SBorislav Petkov void mce_timer_kick(unsigned long interval) 165521afaf18SBorislav Petkov { 165621afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 165721afaf18SBorislav Petkov unsigned long iv = __this_cpu_read(mce_next_interval); 165821afaf18SBorislav Petkov 165921afaf18SBorislav Petkov __start_timer(t, interval); 166021afaf18SBorislav Petkov 166121afaf18SBorislav Petkov if (interval < iv) 166221afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, interval); 166321afaf18SBorislav Petkov } 166421afaf18SBorislav Petkov 166521afaf18SBorislav Petkov /* Must not be called in IRQ context where del_timer_sync() can deadlock */ 166621afaf18SBorislav Petkov static void mce_timer_delete_all(void) 166721afaf18SBorislav Petkov { 166821afaf18SBorislav Petkov int cpu; 166921afaf18SBorislav Petkov 167021afaf18SBorislav Petkov for_each_online_cpu(cpu) 167121afaf18SBorislav Petkov del_timer_sync(&per_cpu(mce_timer, cpu)); 167221afaf18SBorislav Petkov } 167321afaf18SBorislav Petkov 167421afaf18SBorislav Petkov /* 167521afaf18SBorislav Petkov * Notify the user(s) about new machine check events. 167621afaf18SBorislav Petkov * Can be called from interrupt context, but not from machine check/NMI 167721afaf18SBorislav Petkov * context. 167821afaf18SBorislav Petkov */ 167921afaf18SBorislav Petkov int mce_notify_irq(void) 168021afaf18SBorislav Petkov { 168121afaf18SBorislav Petkov /* Not more than two messages every minute */ 168221afaf18SBorislav Petkov static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); 168321afaf18SBorislav Petkov 168421afaf18SBorislav Petkov if (test_and_clear_bit(0, &mce_need_notify)) { 168521afaf18SBorislav Petkov mce_work_trigger(); 168621afaf18SBorislav Petkov 168721afaf18SBorislav Petkov if (__ratelimit(&ratelimit)) 168821afaf18SBorislav Petkov pr_info(HW_ERR "Machine check events logged\n"); 168921afaf18SBorislav Petkov 169021afaf18SBorislav Petkov return 1; 169121afaf18SBorislav Petkov } 169221afaf18SBorislav Petkov return 0; 169321afaf18SBorislav Petkov } 169421afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_notify_irq); 169521afaf18SBorislav Petkov 1696b4914508SYazen Ghannam static void __mcheck_cpu_mce_banks_init(void) 169721afaf18SBorislav Petkov { 1698b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1699c7d314f3SYazen Ghannam u8 n_banks = this_cpu_read(mce_num_banks); 170021afaf18SBorislav Petkov int i; 170121afaf18SBorislav Petkov 1702c7d314f3SYazen Ghannam for (i = 0; i < n_banks; i++) { 170321afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 170421afaf18SBorislav Petkov 1705068b053dSYazen Ghannam /* 1706068b053dSYazen Ghannam * Init them all, __mcheck_cpu_apply_quirks() is going to apply 1707068b053dSYazen Ghannam * the required vendor quirks before 1708068b053dSYazen Ghannam * __mcheck_cpu_init_clear_banks() does the final bank setup. 1709068b053dSYazen Ghannam */ 171021afaf18SBorislav Petkov b->ctl = -1ULL; 171177080929SKaixu Xia b->init = true; 171221afaf18SBorislav Petkov } 171321afaf18SBorislav Petkov } 171421afaf18SBorislav Petkov 171521afaf18SBorislav Petkov /* 171621afaf18SBorislav Petkov * Initialize Machine Checks for a CPU. 171721afaf18SBorislav Petkov */ 1718b4914508SYazen Ghannam static void __mcheck_cpu_cap_init(void) 171921afaf18SBorislav Petkov { 172021afaf18SBorislav Petkov u64 cap; 1721006c0770SYazen Ghannam u8 b; 172221afaf18SBorislav Petkov 172321afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 172421afaf18SBorislav Petkov 172521afaf18SBorislav Petkov b = cap & MCG_BANKCNT_MASK; 172621afaf18SBorislav Petkov 1727c7d314f3SYazen Ghannam if (b > MAX_NR_BANKS) { 1728c7d314f3SYazen Ghannam pr_warn("CPU%d: Using only %u machine check banks out of %u\n", 1729c7d314f3SYazen Ghannam smp_processor_id(), MAX_NR_BANKS, b); 1730c7d314f3SYazen Ghannam b = MAX_NR_BANKS; 1731c7d314f3SYazen Ghannam } 1732c7d314f3SYazen Ghannam 1733c7d314f3SYazen Ghannam this_cpu_write(mce_num_banks, b); 173421afaf18SBorislav Petkov 1735b4914508SYazen Ghannam __mcheck_cpu_mce_banks_init(); 173621afaf18SBorislav Petkov 173721afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 173821afaf18SBorislav Petkov if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) 173921afaf18SBorislav Petkov mca_cfg.rip_msr = MSR_IA32_MCG_EIP; 174021afaf18SBorislav Petkov 174121afaf18SBorislav Petkov if (cap & MCG_SER_P) 174221afaf18SBorislav Petkov mca_cfg.ser = 1; 174321afaf18SBorislav Petkov } 174421afaf18SBorislav Petkov 174521afaf18SBorislav Petkov static void __mcheck_cpu_init_generic(void) 174621afaf18SBorislav Petkov { 174721afaf18SBorislav Petkov enum mcp_flags m_fl = 0; 174821afaf18SBorislav Petkov mce_banks_t all_banks; 174921afaf18SBorislav Petkov u64 cap; 175021afaf18SBorislav Petkov 175121afaf18SBorislav Petkov if (!mca_cfg.bootlog) 175221afaf18SBorislav Petkov m_fl = MCP_DONTLOG; 175321afaf18SBorislav Petkov 175421afaf18SBorislav Petkov /* 17553bff147bSBorislav Petkov * Log the machine checks left over from the previous reset. Log them 17563bff147bSBorislav Petkov * only, do not start processing them. That will happen in mcheck_late_init() 17573bff147bSBorislav Petkov * when all consumers have been registered on the notifier chain. 175821afaf18SBorislav Petkov */ 175921afaf18SBorislav Petkov bitmap_fill(all_banks, MAX_NR_BANKS); 17603bff147bSBorislav Petkov machine_check_poll(MCP_UC | MCP_QUEUE_LOG | m_fl, &all_banks); 176121afaf18SBorislav Petkov 176221afaf18SBorislav Petkov cr4_set_bits(X86_CR4_MCE); 176321afaf18SBorislav Petkov 176421afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 176521afaf18SBorislav Petkov if (cap & MCG_CTL_P) 176621afaf18SBorislav Petkov wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); 176721afaf18SBorislav Petkov } 176821afaf18SBorislav Petkov 176921afaf18SBorislav Petkov static void __mcheck_cpu_init_clear_banks(void) 177021afaf18SBorislav Petkov { 1771b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 177221afaf18SBorislav Petkov int i; 177321afaf18SBorislav Petkov 1774c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 177521afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 177621afaf18SBorislav Petkov 177721afaf18SBorislav Petkov if (!b->init) 177821afaf18SBorislav Petkov continue; 17798121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); 17808121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 178121afaf18SBorislav Petkov } 178221afaf18SBorislav Petkov } 178321afaf18SBorislav Petkov 178421afaf18SBorislav Petkov /* 1785068b053dSYazen Ghannam * Do a final check to see if there are any unused/RAZ banks. 1786068b053dSYazen Ghannam * 1787068b053dSYazen Ghannam * This must be done after the banks have been initialized and any quirks have 1788068b053dSYazen Ghannam * been applied. 1789068b053dSYazen Ghannam * 1790068b053dSYazen Ghannam * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs. 1791068b053dSYazen Ghannam * Otherwise, a user who disables a bank will not be able to re-enable it 1792068b053dSYazen Ghannam * without a system reboot. 1793068b053dSYazen Ghannam */ 1794068b053dSYazen Ghannam static void __mcheck_cpu_check_banks(void) 1795068b053dSYazen Ghannam { 1796068b053dSYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1797068b053dSYazen Ghannam u64 msrval; 1798068b053dSYazen Ghannam int i; 1799068b053dSYazen Ghannam 1800068b053dSYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1801068b053dSYazen Ghannam struct mce_bank *b = &mce_banks[i]; 1802068b053dSYazen Ghannam 1803068b053dSYazen Ghannam if (!b->init) 1804068b053dSYazen Ghannam continue; 1805068b053dSYazen Ghannam 18068121b8f9SBorislav Petkov rdmsrl(mca_msr_reg(i, MCA_CTL), msrval); 1807068b053dSYazen Ghannam b->init = !!msrval; 1808068b053dSYazen Ghannam } 1809068b053dSYazen Ghannam } 1810068b053dSYazen Ghannam 181121afaf18SBorislav Petkov /* Add per CPU specific workarounds here */ 181221afaf18SBorislav Petkov static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) 181321afaf18SBorislav Petkov { 1814b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 181521afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 181621afaf18SBorislav Petkov 181721afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_UNKNOWN) { 181821afaf18SBorislav Petkov pr_info("unknown CPU type - not enabling MCE support\n"); 181921afaf18SBorislav Petkov return -EOPNOTSUPP; 182021afaf18SBorislav Petkov } 182121afaf18SBorislav Petkov 182221afaf18SBorislav Petkov /* This should be disabled by the BIOS, but isn't always */ 182321afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD) { 1824c7d314f3SYazen Ghannam if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { 182521afaf18SBorislav Petkov /* 182621afaf18SBorislav Petkov * disable GART TBL walk error reporting, which 182721afaf18SBorislav Petkov * trips off incorrectly with the IOMMU & 3ware 182821afaf18SBorislav Petkov * & Cerberus: 182921afaf18SBorislav Petkov */ 183021afaf18SBorislav Petkov clear_bit(10, (unsigned long *)&mce_banks[4].ctl); 183121afaf18SBorislav Petkov } 183221afaf18SBorislav Petkov if (c->x86 < 0x11 && cfg->bootlog < 0) { 183321afaf18SBorislav Petkov /* 183421afaf18SBorislav Petkov * Lots of broken BIOS around that don't clear them 183521afaf18SBorislav Petkov * by default and leave crap in there. Don't log: 183621afaf18SBorislav Petkov */ 183721afaf18SBorislav Petkov cfg->bootlog = 0; 183821afaf18SBorislav Petkov } 183921afaf18SBorislav Petkov /* 184021afaf18SBorislav Petkov * Various K7s with broken bank 0 around. Always disable 184121afaf18SBorislav Petkov * by default. 184221afaf18SBorislav Petkov */ 1843c7d314f3SYazen Ghannam if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0) 184421afaf18SBorislav Petkov mce_banks[0].ctl = 0; 184521afaf18SBorislav Petkov 184621afaf18SBorislav Petkov /* 184721afaf18SBorislav Petkov * overflow_recov is supported for F15h Models 00h-0fh 184821afaf18SBorislav Petkov * even though we don't have a CPUID bit for it. 184921afaf18SBorislav Petkov */ 185021afaf18SBorislav Petkov if (c->x86 == 0x15 && c->x86_model <= 0xf) 185121afaf18SBorislav Petkov mce_flags.overflow_recov = 1; 185221afaf18SBorislav Petkov 185321afaf18SBorislav Petkov } 185421afaf18SBorislav Petkov 185521afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_INTEL) { 185621afaf18SBorislav Petkov /* 185721afaf18SBorislav Petkov * SDM documents that on family 6 bank 0 should not be written 185821afaf18SBorislav Petkov * because it aliases to another special BIOS controlled 185921afaf18SBorislav Petkov * register. 186021afaf18SBorislav Petkov * But it's not aliased anymore on model 0x1a+ 186121afaf18SBorislav Petkov * Don't ignore bank 0 completely because there could be a 186221afaf18SBorislav Petkov * valid event later, merely don't write CTL0. 186321afaf18SBorislav Petkov */ 186421afaf18SBorislav Petkov 1865c7d314f3SYazen Ghannam if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) 186677080929SKaixu Xia mce_banks[0].init = false; 186721afaf18SBorislav Petkov 186821afaf18SBorislav Petkov /* 186921afaf18SBorislav Petkov * All newer Intel systems support MCE broadcasting. Enable 187021afaf18SBorislav Petkov * synchronization with a one second timeout. 187121afaf18SBorislav Petkov */ 187221afaf18SBorislav Petkov if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && 187321afaf18SBorislav Petkov cfg->monarch_timeout < 0) 187421afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 187521afaf18SBorislav Petkov 187621afaf18SBorislav Petkov /* 187721afaf18SBorislav Petkov * There are also broken BIOSes on some Pentium M and 187821afaf18SBorislav Petkov * earlier systems: 187921afaf18SBorislav Petkov */ 188021afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) 188121afaf18SBorislav Petkov cfg->bootlog = 0; 188221afaf18SBorislav Petkov 188321afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model == 45) 1884cc466666SBorislav Petkov mce_flags.snb_ifu_quirk = 1; 18858ca97812SJue Wang 18868ca97812SJue Wang /* 18878ca97812SJue Wang * Skylake, Cascacde Lake and Cooper Lake require a quirk on 18888ca97812SJue Wang * rep movs. 18898ca97812SJue Wang */ 18908ca97812SJue Wang if (c->x86 == 6 && c->x86_model == INTEL_FAM6_SKYLAKE_X) 18918ca97812SJue Wang mce_flags.skx_repmov_quirk = 1; 189221afaf18SBorislav Petkov } 18936e898d2bSTony W Wang-oc 18946e898d2bSTony W Wang-oc if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { 18956e898d2bSTony W Wang-oc /* 18966e898d2bSTony W Wang-oc * All newer Zhaoxin CPUs support MCE broadcasting. Enable 18976e898d2bSTony W Wang-oc * synchronization with a one second timeout. 18986e898d2bSTony W Wang-oc */ 18996e898d2bSTony W Wang-oc if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 19006e898d2bSTony W Wang-oc if (cfg->monarch_timeout < 0) 19016e898d2bSTony W Wang-oc cfg->monarch_timeout = USEC_PER_SEC; 19026e898d2bSTony W Wang-oc } 19036e898d2bSTony W Wang-oc } 19046e898d2bSTony W Wang-oc 190521afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 190621afaf18SBorislav Petkov cfg->monarch_timeout = 0; 190721afaf18SBorislav Petkov if (cfg->bootlog != 0) 190821afaf18SBorislav Petkov cfg->panic_timeout = 30; 190921afaf18SBorislav Petkov 191021afaf18SBorislav Petkov return 0; 191121afaf18SBorislav Petkov } 191221afaf18SBorislav Petkov 191321afaf18SBorislav Petkov static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) 191421afaf18SBorislav Petkov { 191521afaf18SBorislav Petkov if (c->x86 != 5) 191621afaf18SBorislav Petkov return 0; 191721afaf18SBorislav Petkov 191821afaf18SBorislav Petkov switch (c->x86_vendor) { 191921afaf18SBorislav Petkov case X86_VENDOR_INTEL: 192021afaf18SBorislav Petkov intel_p5_mcheck_init(c); 1921cbe1de16SBorislav Petkov mce_flags.p5 = 1; 192221afaf18SBorislav Petkov return 1; 192321afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 192421afaf18SBorislav Petkov winchip_mcheck_init(c); 1925cbe1de16SBorislav Petkov mce_flags.winchip = 1; 192621afaf18SBorislav Petkov return 1; 192721afaf18SBorislav Petkov default: 192821afaf18SBorislav Petkov return 0; 192921afaf18SBorislav Petkov } 193021afaf18SBorislav Petkov 193121afaf18SBorislav Petkov return 0; 193221afaf18SBorislav Petkov } 193321afaf18SBorislav Petkov 193421afaf18SBorislav Petkov /* 193521afaf18SBorislav Petkov * Init basic CPU features needed for early decoding of MCEs. 193621afaf18SBorislav Petkov */ 193721afaf18SBorislav Petkov static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) 193821afaf18SBorislav Petkov { 193921afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) { 194021afaf18SBorislav Petkov mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); 194121afaf18SBorislav Petkov mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); 194221afaf18SBorislav Petkov mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); 1943c9bf318fSThomas Gleixner mce_flags.amd_threshold = 1; 194421afaf18SBorislav Petkov } 194521afaf18SBorislav Petkov } 194621afaf18SBorislav Petkov 194721afaf18SBorislav Petkov static void mce_centaur_feature_init(struct cpuinfo_x86 *c) 194821afaf18SBorislav Petkov { 194921afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 195021afaf18SBorislav Petkov 195121afaf18SBorislav Petkov /* 195221afaf18SBorislav Petkov * All newer Centaur CPUs support MCE broadcasting. Enable 195321afaf18SBorislav Petkov * synchronization with a one second timeout. 195421afaf18SBorislav Petkov */ 195521afaf18SBorislav Petkov if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) || 195621afaf18SBorislav Petkov c->x86 > 6) { 195721afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 195821afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 195921afaf18SBorislav Petkov } 196021afaf18SBorislav Petkov } 196121afaf18SBorislav Petkov 19625a3d56a0STony W Wang-oc static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) 19635a3d56a0STony W Wang-oc { 19645a3d56a0STony W Wang-oc struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 19655a3d56a0STony W Wang-oc 19665a3d56a0STony W Wang-oc /* 19675a3d56a0STony W Wang-oc * These CPUs have MCA bank 8 which reports only one error type called 19685a3d56a0STony W Wang-oc * SVAD (System View Address Decoder). The reporting of that error is 19695a3d56a0STony W Wang-oc * controlled by IA32_MC8.CTL.0. 19705a3d56a0STony W Wang-oc * 19715a3d56a0STony W Wang-oc * If enabled, prefetching on these CPUs will cause SVAD MCE when 19725a3d56a0STony W Wang-oc * virtual machines start and result in a system panic. Always disable 19735a3d56a0STony W Wang-oc * bank 8 SVAD error by default. 19745a3d56a0STony W Wang-oc */ 19755a3d56a0STony W Wang-oc if ((c->x86 == 7 && c->x86_model == 0x1b) || 19765a3d56a0STony W Wang-oc (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 19775a3d56a0STony W Wang-oc if (this_cpu_read(mce_num_banks) > 8) 19785a3d56a0STony W Wang-oc mce_banks[8].ctl = 0; 19795a3d56a0STony W Wang-oc } 19805a3d56a0STony W Wang-oc 19815a3d56a0STony W Wang-oc intel_init_cmci(); 198270f0c230STony W Wang-oc intel_init_lmce(); 19835a3d56a0STony W Wang-oc mce_adjust_timer = cmci_intel_adjust_timer; 19845a3d56a0STony W Wang-oc } 19855a3d56a0STony W Wang-oc 198670f0c230STony W Wang-oc static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) 198770f0c230STony W Wang-oc { 198870f0c230STony W Wang-oc intel_clear_lmce(); 198970f0c230STony W Wang-oc } 199070f0c230STony W Wang-oc 199121afaf18SBorislav Petkov static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) 199221afaf18SBorislav Petkov { 199321afaf18SBorislav Petkov switch (c->x86_vendor) { 199421afaf18SBorislav Petkov case X86_VENDOR_INTEL: 199521afaf18SBorislav Petkov mce_intel_feature_init(c); 199621afaf18SBorislav Petkov mce_adjust_timer = cmci_intel_adjust_timer; 199721afaf18SBorislav Petkov break; 199821afaf18SBorislav Petkov 199921afaf18SBorislav Petkov case X86_VENDOR_AMD: { 200021afaf18SBorislav Petkov mce_amd_feature_init(c); 200121afaf18SBorislav Petkov break; 200221afaf18SBorislav Petkov } 200321afaf18SBorislav Petkov 200421afaf18SBorislav Petkov case X86_VENDOR_HYGON: 200521afaf18SBorislav Petkov mce_hygon_feature_init(c); 200621afaf18SBorislav Petkov break; 200721afaf18SBorislav Petkov 200821afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 200921afaf18SBorislav Petkov mce_centaur_feature_init(c); 201021afaf18SBorislav Petkov break; 201121afaf18SBorislav Petkov 20125a3d56a0STony W Wang-oc case X86_VENDOR_ZHAOXIN: 20135a3d56a0STony W Wang-oc mce_zhaoxin_feature_init(c); 20145a3d56a0STony W Wang-oc break; 20155a3d56a0STony W Wang-oc 201621afaf18SBorislav Petkov default: 201721afaf18SBorislav Petkov break; 201821afaf18SBorislav Petkov } 201921afaf18SBorislav Petkov } 202021afaf18SBorislav Petkov 202121afaf18SBorislav Petkov static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) 202221afaf18SBorislav Petkov { 202321afaf18SBorislav Petkov switch (c->x86_vendor) { 202421afaf18SBorislav Petkov case X86_VENDOR_INTEL: 202521afaf18SBorislav Petkov mce_intel_feature_clear(c); 202621afaf18SBorislav Petkov break; 202770f0c230STony W Wang-oc 202870f0c230STony W Wang-oc case X86_VENDOR_ZHAOXIN: 202970f0c230STony W Wang-oc mce_zhaoxin_feature_clear(c); 203070f0c230STony W Wang-oc break; 203170f0c230STony W Wang-oc 203221afaf18SBorislav Petkov default: 203321afaf18SBorislav Petkov break; 203421afaf18SBorislav Petkov } 203521afaf18SBorislav Petkov } 203621afaf18SBorislav Petkov 203721afaf18SBorislav Petkov static void mce_start_timer(struct timer_list *t) 203821afaf18SBorislav Petkov { 203921afaf18SBorislav Petkov unsigned long iv = check_interval * HZ; 204021afaf18SBorislav Petkov 204121afaf18SBorislav Petkov if (mca_cfg.ignore_ce || !iv) 204221afaf18SBorislav Petkov return; 204321afaf18SBorislav Petkov 204421afaf18SBorislav Petkov this_cpu_write(mce_next_interval, iv); 204521afaf18SBorislav Petkov __start_timer(t, iv); 204621afaf18SBorislav Petkov } 204721afaf18SBorislav Petkov 204821afaf18SBorislav Petkov static void __mcheck_cpu_setup_timer(void) 204921afaf18SBorislav Petkov { 205021afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 205121afaf18SBorislav Petkov 205221afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 205321afaf18SBorislav Petkov } 205421afaf18SBorislav Petkov 205521afaf18SBorislav Petkov static void __mcheck_cpu_init_timer(void) 205621afaf18SBorislav Petkov { 205721afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 205821afaf18SBorislav Petkov 205921afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 206021afaf18SBorislav Petkov mce_start_timer(t); 206121afaf18SBorislav Petkov } 206221afaf18SBorislav Petkov 206345d4b7b9SYazen Ghannam bool filter_mce(struct mce *m) 206445d4b7b9SYazen Ghannam { 206571a84402SYazen Ghannam if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 206671a84402SYazen Ghannam return amd_filter_mce(m); 20672976908eSPrarit Bhargava if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 20682976908eSPrarit Bhargava return intel_filter_mce(m); 206971a84402SYazen Ghannam 207045d4b7b9SYazen Ghannam return false; 207145d4b7b9SYazen Ghannam } 207245d4b7b9SYazen Ghannam 20734c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_kernel(struct pt_regs *regs) 207421afaf18SBorislav Petkov { 2075b6be002bSThomas Gleixner irqentry_state_t irq_state; 2076bc21a291SThomas Gleixner 207713cbc0cdSAndy Lutomirski WARN_ON_ONCE(user_mode(regs)); 207813cbc0cdSAndy Lutomirski 20794c0dcd83SThomas Gleixner /* 20804c0dcd83SThomas Gleixner * Only required when from kernel mode. See 20814c0dcd83SThomas Gleixner * mce_check_crashing_cpu() for details. 20824c0dcd83SThomas Gleixner */ 2083cbe1de16SBorislav Petkov if (mca_cfg.initialized && mce_check_crashing_cpu()) 208494a46d31SThomas Gleixner return; 208594a46d31SThomas Gleixner 2086b6be002bSThomas Gleixner irq_state = irqentry_nmi_enter(regs); 208773749536SPeter Zijlstra 2088cbe1de16SBorislav Petkov do_machine_check(regs); 208973749536SPeter Zijlstra 2090b6be002bSThomas Gleixner irqentry_nmi_exit(regs, irq_state); 209121afaf18SBorislav Petkov } 209221afaf18SBorislav Petkov 20934c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_user(struct pt_regs *regs) 20944c0dcd83SThomas Gleixner { 2095517e4992SThomas Gleixner irqentry_enter_from_user_mode(regs); 209673749536SPeter Zijlstra 2097cbe1de16SBorislav Petkov do_machine_check(regs); 209873749536SPeter Zijlstra 2099517e4992SThomas Gleixner irqentry_exit_to_user_mode(regs); 21004c0dcd83SThomas Gleixner } 21014c0dcd83SThomas Gleixner 21024c0dcd83SThomas Gleixner #ifdef CONFIG_X86_64 21034c0dcd83SThomas Gleixner /* MCE hit kernel mode */ 21044c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE(exc_machine_check) 21054c0dcd83SThomas Gleixner { 2106cd840e42SPeter Zijlstra unsigned long dr7; 2107cd840e42SPeter Zijlstra 2108cd840e42SPeter Zijlstra dr7 = local_db_save(); 21094c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 2110cd840e42SPeter Zijlstra local_db_restore(dr7); 21114c0dcd83SThomas Gleixner } 21124c0dcd83SThomas Gleixner 21134c0dcd83SThomas Gleixner /* The user mode variant. */ 21144c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE_USER(exc_machine_check) 21154c0dcd83SThomas Gleixner { 2116cd840e42SPeter Zijlstra unsigned long dr7; 2117cd840e42SPeter Zijlstra 2118cd840e42SPeter Zijlstra dr7 = local_db_save(); 21194c0dcd83SThomas Gleixner exc_machine_check_user(regs); 2120cd840e42SPeter Zijlstra local_db_restore(dr7); 21214c0dcd83SThomas Gleixner } 21224c0dcd83SThomas Gleixner #else 21234c0dcd83SThomas Gleixner /* 32bit unified entry point */ 212413cbc0cdSAndy Lutomirski DEFINE_IDTENTRY_RAW(exc_machine_check) 21254c0dcd83SThomas Gleixner { 2126cd840e42SPeter Zijlstra unsigned long dr7; 2127cd840e42SPeter Zijlstra 2128cd840e42SPeter Zijlstra dr7 = local_db_save(); 21294c0dcd83SThomas Gleixner if (user_mode(regs)) 21304c0dcd83SThomas Gleixner exc_machine_check_user(regs); 21314c0dcd83SThomas Gleixner else 21324c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 2133cd840e42SPeter Zijlstra local_db_restore(dr7); 21344c0dcd83SThomas Gleixner } 21354c0dcd83SThomas Gleixner #endif 213621afaf18SBorislav Petkov 213721afaf18SBorislav Petkov /* 213821afaf18SBorislav Petkov * Called for each booted CPU to set up machine checks. 213921afaf18SBorislav Petkov * Must be called with preempt off: 214021afaf18SBorislav Petkov */ 214121afaf18SBorislav Petkov void mcheck_cpu_init(struct cpuinfo_x86 *c) 214221afaf18SBorislav Petkov { 214321afaf18SBorislav Petkov if (mca_cfg.disabled) 214421afaf18SBorislav Petkov return; 214521afaf18SBorislav Petkov 214621afaf18SBorislav Petkov if (__mcheck_cpu_ancient_init(c)) 214721afaf18SBorislav Petkov return; 214821afaf18SBorislav Petkov 214921afaf18SBorislav Petkov if (!mce_available(c)) 215021afaf18SBorislav Petkov return; 215121afaf18SBorislav Petkov 2152b4914508SYazen Ghannam __mcheck_cpu_cap_init(); 2153b4914508SYazen Ghannam 2154b4914508SYazen Ghannam if (__mcheck_cpu_apply_quirks(c) < 0) { 215521afaf18SBorislav Petkov mca_cfg.disabled = 1; 215621afaf18SBorislav Petkov return; 215721afaf18SBorislav Petkov } 215821afaf18SBorislav Petkov 215921afaf18SBorislav Petkov if (mce_gen_pool_init()) { 216021afaf18SBorislav Petkov mca_cfg.disabled = 1; 216121afaf18SBorislav Petkov pr_emerg("Couldn't allocate MCE records pool!\n"); 216221afaf18SBorislav Petkov return; 216321afaf18SBorislav Petkov } 216421afaf18SBorislav Petkov 2165cbe1de16SBorislav Petkov mca_cfg.initialized = 1; 216621afaf18SBorislav Petkov 216721afaf18SBorislav Petkov __mcheck_cpu_init_early(c); 216821afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 216921afaf18SBorislav Petkov __mcheck_cpu_init_vendor(c); 217021afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 2171068b053dSYazen Ghannam __mcheck_cpu_check_banks(); 217221afaf18SBorislav Petkov __mcheck_cpu_setup_timer(); 217321afaf18SBorislav Petkov } 217421afaf18SBorislav Petkov 217521afaf18SBorislav Petkov /* 217621afaf18SBorislav Petkov * Called for each booted CPU to clear some machine checks opt-ins 217721afaf18SBorislav Petkov */ 217821afaf18SBorislav Petkov void mcheck_cpu_clear(struct cpuinfo_x86 *c) 217921afaf18SBorislav Petkov { 218021afaf18SBorislav Petkov if (mca_cfg.disabled) 218121afaf18SBorislav Petkov return; 218221afaf18SBorislav Petkov 218321afaf18SBorislav Petkov if (!mce_available(c)) 218421afaf18SBorislav Petkov return; 218521afaf18SBorislav Petkov 218621afaf18SBorislav Petkov /* 218721afaf18SBorislav Petkov * Possibly to clear general settings generic to x86 218821afaf18SBorislav Petkov * __mcheck_cpu_clear_generic(c); 218921afaf18SBorislav Petkov */ 219021afaf18SBorislav Petkov __mcheck_cpu_clear_vendor(c); 219121afaf18SBorislav Petkov 219221afaf18SBorislav Petkov } 219321afaf18SBorislav Petkov 219421afaf18SBorislav Petkov static void __mce_disable_bank(void *arg) 219521afaf18SBorislav Petkov { 219621afaf18SBorislav Petkov int bank = *((int *)arg); 219721afaf18SBorislav Petkov __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); 219821afaf18SBorislav Petkov cmci_disable_bank(bank); 219921afaf18SBorislav Petkov } 220021afaf18SBorislav Petkov 220121afaf18SBorislav Petkov void mce_disable_bank(int bank) 220221afaf18SBorislav Petkov { 2203c7d314f3SYazen Ghannam if (bank >= this_cpu_read(mce_num_banks)) { 220421afaf18SBorislav Petkov pr_warn(FW_BUG 220521afaf18SBorislav Petkov "Ignoring request to disable invalid MCA bank %d.\n", 220621afaf18SBorislav Petkov bank); 220721afaf18SBorislav Petkov return; 220821afaf18SBorislav Petkov } 220921afaf18SBorislav Petkov set_bit(bank, mce_banks_ce_disabled); 221021afaf18SBorislav Petkov on_each_cpu(__mce_disable_bank, &bank, 1); 221121afaf18SBorislav Petkov } 221221afaf18SBorislav Petkov 221321afaf18SBorislav Petkov /* 221421afaf18SBorislav Petkov * mce=off Disables machine check 221521afaf18SBorislav Petkov * mce=no_cmci Disables CMCI 221621afaf18SBorislav Petkov * mce=no_lmce Disables LMCE 221721afaf18SBorislav Petkov * mce=dont_log_ce Clears corrected events silently, no log created for CEs. 221843505646STony Luck * mce=print_all Print all machine check logs to console 221921afaf18SBorislav Petkov * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. 222021afaf18SBorislav Petkov * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) 222121afaf18SBorislav Petkov * monarchtimeout is how long to wait for other CPUs on machine 222221afaf18SBorislav Petkov * check, or 0 to not wait 222321afaf18SBorislav Petkov * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h 222421afaf18SBorislav Petkov and older. 222521afaf18SBorislav Petkov * mce=nobootlog Don't log MCEs from before booting. 222621afaf18SBorislav Petkov * mce=bios_cmci_threshold Don't program the CMCI threshold 2227ec6347bbSDan Williams * mce=recovery force enable copy_mc_fragile() 222821afaf18SBorislav Petkov */ 222921afaf18SBorislav Petkov static int __init mcheck_enable(char *str) 223021afaf18SBorislav Petkov { 223121afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 223221afaf18SBorislav Petkov 223321afaf18SBorislav Petkov if (*str == 0) { 223421afaf18SBorislav Petkov enable_p5_mce(); 223521afaf18SBorislav Petkov return 1; 223621afaf18SBorislav Petkov } 223721afaf18SBorislav Petkov if (*str == '=') 223821afaf18SBorislav Petkov str++; 223921afaf18SBorislav Petkov if (!strcmp(str, "off")) 224021afaf18SBorislav Petkov cfg->disabled = 1; 224121afaf18SBorislav Petkov else if (!strcmp(str, "no_cmci")) 224221afaf18SBorislav Petkov cfg->cmci_disabled = true; 224321afaf18SBorislav Petkov else if (!strcmp(str, "no_lmce")) 224421afaf18SBorislav Petkov cfg->lmce_disabled = 1; 224521afaf18SBorislav Petkov else if (!strcmp(str, "dont_log_ce")) 224621afaf18SBorislav Petkov cfg->dont_log_ce = true; 224743505646STony Luck else if (!strcmp(str, "print_all")) 224843505646STony Luck cfg->print_all = true; 224921afaf18SBorislav Petkov else if (!strcmp(str, "ignore_ce")) 225021afaf18SBorislav Petkov cfg->ignore_ce = true; 225121afaf18SBorislav Petkov else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) 225221afaf18SBorislav Petkov cfg->bootlog = (str[0] == 'b'); 225321afaf18SBorislav Petkov else if (!strcmp(str, "bios_cmci_threshold")) 225421afaf18SBorislav Petkov cfg->bios_cmci_threshold = 1; 225521afaf18SBorislav Petkov else if (!strcmp(str, "recovery")) 225621afaf18SBorislav Petkov cfg->recovery = 1; 22577f1b8e0dSBorislav Petkov else if (isdigit(str[0])) 225821afaf18SBorislav Petkov get_option(&str, &(cfg->monarch_timeout)); 22597f1b8e0dSBorislav Petkov else { 226021afaf18SBorislav Petkov pr_info("mce argument %s ignored. Please use /sys\n", str); 226121afaf18SBorislav Petkov return 0; 226221afaf18SBorislav Petkov } 226321afaf18SBorislav Petkov return 1; 226421afaf18SBorislav Petkov } 226521afaf18SBorislav Petkov __setup("mce", mcheck_enable); 226621afaf18SBorislav Petkov 226721afaf18SBorislav Petkov int __init mcheck_init(void) 226821afaf18SBorislav Petkov { 2269c9c6d216STony Luck mce_register_decode_chain(&early_nb); 22708438b84aSJan H. Schönherr mce_register_decode_chain(&mce_uc_nb); 227121afaf18SBorislav Petkov mce_register_decode_chain(&mce_default_nb); 227221afaf18SBorislav Petkov 227321afaf18SBorislav Petkov INIT_WORK(&mce_work, mce_gen_pool_process); 227421afaf18SBorislav Petkov init_irq_work(&mce_irq_work, mce_irq_work_cb); 227521afaf18SBorislav Petkov 227621afaf18SBorislav Petkov return 0; 227721afaf18SBorislav Petkov } 227821afaf18SBorislav Petkov 227921afaf18SBorislav Petkov /* 228021afaf18SBorislav Petkov * mce_syscore: PM support 228121afaf18SBorislav Petkov */ 228221afaf18SBorislav Petkov 228321afaf18SBorislav Petkov /* 228421afaf18SBorislav Petkov * Disable machine checks on suspend and shutdown. We can't really handle 228521afaf18SBorislav Petkov * them later. 228621afaf18SBorislav Petkov */ 228721afaf18SBorislav Petkov static void mce_disable_error_reporting(void) 228821afaf18SBorislav Petkov { 2289b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 229021afaf18SBorislav Petkov int i; 229121afaf18SBorislav Petkov 2292c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 229321afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 229421afaf18SBorislav Petkov 229521afaf18SBorislav Petkov if (b->init) 22968121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), 0); 229721afaf18SBorislav Petkov } 229821afaf18SBorislav Petkov return; 229921afaf18SBorislav Petkov } 230021afaf18SBorislav Petkov 230121afaf18SBorislav Petkov static void vendor_disable_error_reporting(void) 230221afaf18SBorislav Petkov { 230321afaf18SBorislav Petkov /* 23046e898d2bSTony W Wang-oc * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these 23056e898d2bSTony W Wang-oc * MSRs are socket-wide. Disabling them for just a single offlined CPU 23066e898d2bSTony W Wang-oc * is bad, since it will inhibit reporting for all shared resources on 23076e898d2bSTony W Wang-oc * the socket like the last level cache (LLC), the integrated memory 23086e898d2bSTony W Wang-oc * controller (iMC), etc. 230921afaf18SBorislav Petkov */ 231021afaf18SBorislav Petkov if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || 231121afaf18SBorislav Petkov boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || 23126e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 23136e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) 231421afaf18SBorislav Petkov return; 231521afaf18SBorislav Petkov 231621afaf18SBorislav Petkov mce_disable_error_reporting(); 231721afaf18SBorislav Petkov } 231821afaf18SBorislav Petkov 231921afaf18SBorislav Petkov static int mce_syscore_suspend(void) 232021afaf18SBorislav Petkov { 232121afaf18SBorislav Petkov vendor_disable_error_reporting(); 232221afaf18SBorislav Petkov return 0; 232321afaf18SBorislav Petkov } 232421afaf18SBorislav Petkov 232521afaf18SBorislav Petkov static void mce_syscore_shutdown(void) 232621afaf18SBorislav Petkov { 232721afaf18SBorislav Petkov vendor_disable_error_reporting(); 232821afaf18SBorislav Petkov } 232921afaf18SBorislav Petkov 233021afaf18SBorislav Petkov /* 233121afaf18SBorislav Petkov * On resume clear all MCE state. Don't want to see leftovers from the BIOS. 233221afaf18SBorislav Petkov * Only one CPU is active at this time, the others get re-added later using 233321afaf18SBorislav Petkov * CPU hotplug: 233421afaf18SBorislav Petkov */ 233521afaf18SBorislav Petkov static void mce_syscore_resume(void) 233621afaf18SBorislav Petkov { 233721afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 233821afaf18SBorislav Petkov __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); 233921afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 234021afaf18SBorislav Petkov } 234121afaf18SBorislav Petkov 234221afaf18SBorislav Petkov static struct syscore_ops mce_syscore_ops = { 234321afaf18SBorislav Petkov .suspend = mce_syscore_suspend, 234421afaf18SBorislav Petkov .shutdown = mce_syscore_shutdown, 234521afaf18SBorislav Petkov .resume = mce_syscore_resume, 234621afaf18SBorislav Petkov }; 234721afaf18SBorislav Petkov 234821afaf18SBorislav Petkov /* 234921afaf18SBorislav Petkov * mce_device: Sysfs support 235021afaf18SBorislav Petkov */ 235121afaf18SBorislav Petkov 235221afaf18SBorislav Petkov static void mce_cpu_restart(void *data) 235321afaf18SBorislav Petkov { 235421afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 235521afaf18SBorislav Petkov return; 235621afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 235721afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 235821afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 235921afaf18SBorislav Petkov } 236021afaf18SBorislav Petkov 236121afaf18SBorislav Petkov /* Reinit MCEs after user configuration changes */ 236221afaf18SBorislav Petkov static void mce_restart(void) 236321afaf18SBorislav Petkov { 236421afaf18SBorislav Petkov mce_timer_delete_all(); 236521afaf18SBorislav Petkov on_each_cpu(mce_cpu_restart, NULL, 1); 236621afaf18SBorislav Petkov } 236721afaf18SBorislav Petkov 236821afaf18SBorislav Petkov /* Toggle features for corrected errors */ 236921afaf18SBorislav Petkov static void mce_disable_cmci(void *data) 237021afaf18SBorislav Petkov { 237121afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 237221afaf18SBorislav Petkov return; 237321afaf18SBorislav Petkov cmci_clear(); 237421afaf18SBorislav Petkov } 237521afaf18SBorislav Petkov 237621afaf18SBorislav Petkov static void mce_enable_ce(void *all) 237721afaf18SBorislav Petkov { 237821afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 237921afaf18SBorislav Petkov return; 238021afaf18SBorislav Petkov cmci_reenable(); 238121afaf18SBorislav Petkov cmci_recheck(); 238221afaf18SBorislav Petkov if (all) 238321afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 238421afaf18SBorislav Petkov } 238521afaf18SBorislav Petkov 238621afaf18SBorislav Petkov static struct bus_type mce_subsys = { 238721afaf18SBorislav Petkov .name = "machinecheck", 238821afaf18SBorislav Petkov .dev_name = "machinecheck", 238921afaf18SBorislav Petkov }; 239021afaf18SBorislav Petkov 239121afaf18SBorislav Petkov DEFINE_PER_CPU(struct device *, mce_device); 239221afaf18SBorislav Petkov 2393b4914508SYazen Ghannam static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr) 239421afaf18SBorislav Petkov { 2395b4914508SYazen Ghannam return container_of(attr, struct mce_bank_dev, attr); 239621afaf18SBorislav Petkov } 239721afaf18SBorislav Petkov 239821afaf18SBorislav Petkov static ssize_t show_bank(struct device *s, struct device_attribute *attr, 239921afaf18SBorislav Petkov char *buf) 240021afaf18SBorislav Petkov { 2401b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2402b4914508SYazen Ghannam struct mce_bank *b; 2403b4914508SYazen Ghannam 2404c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2405b4914508SYazen Ghannam return -EINVAL; 2406b4914508SYazen Ghannam 2407b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2408b4914508SYazen Ghannam 2409068b053dSYazen Ghannam if (!b->init) 2410068b053dSYazen Ghannam return -ENODEV; 2411068b053dSYazen Ghannam 2412b4914508SYazen Ghannam return sprintf(buf, "%llx\n", b->ctl); 241321afaf18SBorislav Petkov } 241421afaf18SBorislav Petkov 241521afaf18SBorislav Petkov static ssize_t set_bank(struct device *s, struct device_attribute *attr, 241621afaf18SBorislav Petkov const char *buf, size_t size) 241721afaf18SBorislav Petkov { 2418b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2419b4914508SYazen Ghannam struct mce_bank *b; 242021afaf18SBorislav Petkov u64 new; 242121afaf18SBorislav Petkov 242221afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 242321afaf18SBorislav Petkov return -EINVAL; 242421afaf18SBorislav Petkov 2425c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2426b4914508SYazen Ghannam return -EINVAL; 2427b4914508SYazen Ghannam 2428b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2429b4914508SYazen Ghannam 2430068b053dSYazen Ghannam if (!b->init) 2431068b053dSYazen Ghannam return -ENODEV; 2432068b053dSYazen Ghannam 2433b4914508SYazen Ghannam b->ctl = new; 243421afaf18SBorislav Petkov mce_restart(); 243521afaf18SBorislav Petkov 243621afaf18SBorislav Petkov return size; 243721afaf18SBorislav Petkov } 243821afaf18SBorislav Petkov 243921afaf18SBorislav Petkov static ssize_t set_ignore_ce(struct device *s, 244021afaf18SBorislav Petkov struct device_attribute *attr, 244121afaf18SBorislav Petkov const char *buf, size_t size) 244221afaf18SBorislav Petkov { 244321afaf18SBorislav Petkov u64 new; 244421afaf18SBorislav Petkov 244521afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 244621afaf18SBorislav Petkov return -EINVAL; 244721afaf18SBorislav Petkov 244821afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 244921afaf18SBorislav Petkov if (mca_cfg.ignore_ce ^ !!new) { 245021afaf18SBorislav Petkov if (new) { 245121afaf18SBorislav Petkov /* disable ce features */ 245221afaf18SBorislav Petkov mce_timer_delete_all(); 245321afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 245421afaf18SBorislav Petkov mca_cfg.ignore_ce = true; 245521afaf18SBorislav Petkov } else { 245621afaf18SBorislav Petkov /* enable ce features */ 245721afaf18SBorislav Petkov mca_cfg.ignore_ce = false; 245821afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, (void *)1, 1); 245921afaf18SBorislav Petkov } 246021afaf18SBorislav Petkov } 246121afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 246221afaf18SBorislav Petkov 246321afaf18SBorislav Petkov return size; 246421afaf18SBorislav Petkov } 246521afaf18SBorislav Petkov 246621afaf18SBorislav Petkov static ssize_t set_cmci_disabled(struct device *s, 246721afaf18SBorislav Petkov struct device_attribute *attr, 246821afaf18SBorislav Petkov const char *buf, size_t size) 246921afaf18SBorislav Petkov { 247021afaf18SBorislav Petkov u64 new; 247121afaf18SBorislav Petkov 247221afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 247321afaf18SBorislav Petkov return -EINVAL; 247421afaf18SBorislav Petkov 247521afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 247621afaf18SBorislav Petkov if (mca_cfg.cmci_disabled ^ !!new) { 247721afaf18SBorislav Petkov if (new) { 247821afaf18SBorislav Petkov /* disable cmci */ 247921afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 248021afaf18SBorislav Petkov mca_cfg.cmci_disabled = true; 248121afaf18SBorislav Petkov } else { 248221afaf18SBorislav Petkov /* enable cmci */ 248321afaf18SBorislav Petkov mca_cfg.cmci_disabled = false; 248421afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, NULL, 1); 248521afaf18SBorislav Petkov } 248621afaf18SBorislav Petkov } 248721afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 248821afaf18SBorislav Petkov 248921afaf18SBorislav Petkov return size; 249021afaf18SBorislav Petkov } 249121afaf18SBorislav Petkov 249221afaf18SBorislav Petkov static ssize_t store_int_with_restart(struct device *s, 249321afaf18SBorislav Petkov struct device_attribute *attr, 249421afaf18SBorislav Petkov const char *buf, size_t size) 249521afaf18SBorislav Petkov { 249621afaf18SBorislav Petkov unsigned long old_check_interval = check_interval; 249721afaf18SBorislav Petkov ssize_t ret = device_store_ulong(s, attr, buf, size); 249821afaf18SBorislav Petkov 249921afaf18SBorislav Petkov if (check_interval == old_check_interval) 250021afaf18SBorislav Petkov return ret; 250121afaf18SBorislav Petkov 250221afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 250321afaf18SBorislav Petkov mce_restart(); 250421afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 250521afaf18SBorislav Petkov 250621afaf18SBorislav Petkov return ret; 250721afaf18SBorislav Petkov } 250821afaf18SBorislav Petkov 250921afaf18SBorislav Petkov static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); 251021afaf18SBorislav Petkov static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); 251143505646STony Luck static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all); 251221afaf18SBorislav Petkov 251321afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_check_interval = { 251421afaf18SBorislav Petkov __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), 251521afaf18SBorislav Petkov &check_interval 251621afaf18SBorislav Petkov }; 251721afaf18SBorislav Petkov 251821afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_ignore_ce = { 251921afaf18SBorislav Petkov __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), 252021afaf18SBorislav Petkov &mca_cfg.ignore_ce 252121afaf18SBorislav Petkov }; 252221afaf18SBorislav Petkov 252321afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_cmci_disabled = { 252421afaf18SBorislav Petkov __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), 252521afaf18SBorislav Petkov &mca_cfg.cmci_disabled 252621afaf18SBorislav Petkov }; 252721afaf18SBorislav Petkov 252821afaf18SBorislav Petkov static struct device_attribute *mce_device_attrs[] = { 252921afaf18SBorislav Petkov &dev_attr_check_interval.attr, 253021afaf18SBorislav Petkov #ifdef CONFIG_X86_MCELOG_LEGACY 253121afaf18SBorislav Petkov &dev_attr_trigger, 253221afaf18SBorislav Petkov #endif 253321afaf18SBorislav Petkov &dev_attr_monarch_timeout.attr, 253421afaf18SBorislav Petkov &dev_attr_dont_log_ce.attr, 253543505646STony Luck &dev_attr_print_all.attr, 253621afaf18SBorislav Petkov &dev_attr_ignore_ce.attr, 253721afaf18SBorislav Petkov &dev_attr_cmci_disabled.attr, 253821afaf18SBorislav Petkov NULL 253921afaf18SBorislav Petkov }; 254021afaf18SBorislav Petkov 254121afaf18SBorislav Petkov static cpumask_var_t mce_device_initialized; 254221afaf18SBorislav Petkov 254321afaf18SBorislav Petkov static void mce_device_release(struct device *dev) 254421afaf18SBorislav Petkov { 254521afaf18SBorislav Petkov kfree(dev); 254621afaf18SBorislav Petkov } 254721afaf18SBorislav Petkov 2548b4914508SYazen Ghannam /* Per CPU device init. All of the CPUs still share the same bank device: */ 254921afaf18SBorislav Petkov static int mce_device_create(unsigned int cpu) 255021afaf18SBorislav Petkov { 255121afaf18SBorislav Petkov struct device *dev; 255221afaf18SBorislav Petkov int err; 255321afaf18SBorislav Petkov int i, j; 255421afaf18SBorislav Petkov 255521afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) 255621afaf18SBorislav Petkov return -EIO; 255721afaf18SBorislav Petkov 255821afaf18SBorislav Petkov dev = per_cpu(mce_device, cpu); 255921afaf18SBorislav Petkov if (dev) 256021afaf18SBorislav Petkov return 0; 256121afaf18SBorislav Petkov 256221afaf18SBorislav Petkov dev = kzalloc(sizeof(*dev), GFP_KERNEL); 256321afaf18SBorislav Petkov if (!dev) 256421afaf18SBorislav Petkov return -ENOMEM; 256521afaf18SBorislav Petkov dev->id = cpu; 256621afaf18SBorislav Petkov dev->bus = &mce_subsys; 256721afaf18SBorislav Petkov dev->release = &mce_device_release; 256821afaf18SBorislav Petkov 256921afaf18SBorislav Petkov err = device_register(dev); 257021afaf18SBorislav Petkov if (err) { 257121afaf18SBorislav Petkov put_device(dev); 257221afaf18SBorislav Petkov return err; 257321afaf18SBorislav Petkov } 257421afaf18SBorislav Petkov 257521afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) { 257621afaf18SBorislav Petkov err = device_create_file(dev, mce_device_attrs[i]); 257721afaf18SBorislav Petkov if (err) 257821afaf18SBorislav Petkov goto error; 257921afaf18SBorislav Petkov } 2580c7d314f3SYazen Ghannam for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) { 2581b4914508SYazen Ghannam err = device_create_file(dev, &mce_bank_devs[j].attr); 258221afaf18SBorislav Petkov if (err) 258321afaf18SBorislav Petkov goto error2; 258421afaf18SBorislav Petkov } 258521afaf18SBorislav Petkov cpumask_set_cpu(cpu, mce_device_initialized); 258621afaf18SBorislav Petkov per_cpu(mce_device, cpu) = dev; 258721afaf18SBorislav Petkov 258821afaf18SBorislav Petkov return 0; 258921afaf18SBorislav Petkov error2: 259021afaf18SBorislav Petkov while (--j >= 0) 2591b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[j].attr); 259221afaf18SBorislav Petkov error: 259321afaf18SBorislav Petkov while (--i >= 0) 259421afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 259521afaf18SBorislav Petkov 259621afaf18SBorislav Petkov device_unregister(dev); 259721afaf18SBorislav Petkov 259821afaf18SBorislav Petkov return err; 259921afaf18SBorislav Petkov } 260021afaf18SBorislav Petkov 260121afaf18SBorislav Petkov static void mce_device_remove(unsigned int cpu) 260221afaf18SBorislav Petkov { 260321afaf18SBorislav Petkov struct device *dev = per_cpu(mce_device, cpu); 260421afaf18SBorislav Petkov int i; 260521afaf18SBorislav Petkov 260621afaf18SBorislav Petkov if (!cpumask_test_cpu(cpu, mce_device_initialized)) 260721afaf18SBorislav Petkov return; 260821afaf18SBorislav Petkov 260921afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) 261021afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 261121afaf18SBorislav Petkov 2612c7d314f3SYazen Ghannam for (i = 0; i < per_cpu(mce_num_banks, cpu); i++) 2613b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[i].attr); 261421afaf18SBorislav Petkov 261521afaf18SBorislav Petkov device_unregister(dev); 261621afaf18SBorislav Petkov cpumask_clear_cpu(cpu, mce_device_initialized); 261721afaf18SBorislav Petkov per_cpu(mce_device, cpu) = NULL; 261821afaf18SBorislav Petkov } 261921afaf18SBorislav Petkov 262021afaf18SBorislav Petkov /* Make sure there are no machine checks on offlined CPUs. */ 262121afaf18SBorislav Petkov static void mce_disable_cpu(void) 262221afaf18SBorislav Petkov { 262321afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 262421afaf18SBorislav Petkov return; 262521afaf18SBorislav Petkov 262621afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 262721afaf18SBorislav Petkov cmci_clear(); 262821afaf18SBorislav Petkov 262921afaf18SBorislav Petkov vendor_disable_error_reporting(); 263021afaf18SBorislav Petkov } 263121afaf18SBorislav Petkov 263221afaf18SBorislav Petkov static void mce_reenable_cpu(void) 263321afaf18SBorislav Petkov { 2634b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 263521afaf18SBorislav Petkov int i; 263621afaf18SBorislav Petkov 263721afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 263821afaf18SBorislav Petkov return; 263921afaf18SBorislav Petkov 264021afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 264121afaf18SBorislav Petkov cmci_reenable(); 2642c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 264321afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 264421afaf18SBorislav Petkov 264521afaf18SBorislav Petkov if (b->init) 26468121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); 264721afaf18SBorislav Petkov } 264821afaf18SBorislav Petkov } 264921afaf18SBorislav Petkov 265021afaf18SBorislav Petkov static int mce_cpu_dead(unsigned int cpu) 265121afaf18SBorislav Petkov { 265221afaf18SBorislav Petkov mce_intel_hcpu_update(cpu); 265321afaf18SBorislav Petkov 265421afaf18SBorislav Petkov /* intentionally ignoring frozen here */ 265521afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 265621afaf18SBorislav Petkov cmci_rediscover(); 265721afaf18SBorislav Petkov return 0; 265821afaf18SBorislav Petkov } 265921afaf18SBorislav Petkov 266021afaf18SBorislav Petkov static int mce_cpu_online(unsigned int cpu) 266121afaf18SBorislav Petkov { 266221afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 266321afaf18SBorislav Petkov int ret; 266421afaf18SBorislav Petkov 266521afaf18SBorislav Petkov mce_device_create(cpu); 266621afaf18SBorislav Petkov 266721afaf18SBorislav Petkov ret = mce_threshold_create_device(cpu); 266821afaf18SBorislav Petkov if (ret) { 266921afaf18SBorislav Petkov mce_device_remove(cpu); 267021afaf18SBorislav Petkov return ret; 267121afaf18SBorislav Petkov } 267221afaf18SBorislav Petkov mce_reenable_cpu(); 267321afaf18SBorislav Petkov mce_start_timer(t); 267421afaf18SBorislav Petkov return 0; 267521afaf18SBorislav Petkov } 267621afaf18SBorislav Petkov 267721afaf18SBorislav Petkov static int mce_cpu_pre_down(unsigned int cpu) 267821afaf18SBorislav Petkov { 267921afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 268021afaf18SBorislav Petkov 268121afaf18SBorislav Petkov mce_disable_cpu(); 268221afaf18SBorislav Petkov del_timer_sync(t); 268321afaf18SBorislav Petkov mce_threshold_remove_device(cpu); 268421afaf18SBorislav Petkov mce_device_remove(cpu); 268521afaf18SBorislav Petkov return 0; 268621afaf18SBorislav Petkov } 268721afaf18SBorislav Petkov 268821afaf18SBorislav Petkov static __init void mce_init_banks(void) 268921afaf18SBorislav Petkov { 269021afaf18SBorislav Petkov int i; 269121afaf18SBorislav Petkov 2692b4914508SYazen Ghannam for (i = 0; i < MAX_NR_BANKS; i++) { 2693b4914508SYazen Ghannam struct mce_bank_dev *b = &mce_bank_devs[i]; 269421afaf18SBorislav Petkov struct device_attribute *a = &b->attr; 269521afaf18SBorislav Petkov 2696b4914508SYazen Ghannam b->bank = i; 2697b4914508SYazen Ghannam 269821afaf18SBorislav Petkov sysfs_attr_init(&a->attr); 269921afaf18SBorislav Petkov a->attr.name = b->attrname; 270021afaf18SBorislav Petkov snprintf(b->attrname, ATTR_LEN, "bank%d", i); 270121afaf18SBorislav Petkov 270221afaf18SBorislav Petkov a->attr.mode = 0644; 270321afaf18SBorislav Petkov a->show = show_bank; 270421afaf18SBorislav Petkov a->store = set_bank; 270521afaf18SBorislav Petkov } 270621afaf18SBorislav Petkov } 270721afaf18SBorislav Petkov 27086e7a41c6SThomas Gleixner /* 27096e7a41c6SThomas Gleixner * When running on XEN, this initcall is ordered against the XEN mcelog 27106e7a41c6SThomas Gleixner * initcall: 27116e7a41c6SThomas Gleixner * 27126e7a41c6SThomas Gleixner * device_initcall(xen_late_init_mcelog); 27136e7a41c6SThomas Gleixner * device_initcall_sync(mcheck_init_device); 27146e7a41c6SThomas Gleixner */ 271521afaf18SBorislav Petkov static __init int mcheck_init_device(void) 271621afaf18SBorislav Petkov { 271721afaf18SBorislav Petkov int err; 271821afaf18SBorislav Petkov 271921afaf18SBorislav Petkov /* 272021afaf18SBorislav Petkov * Check if we have a spare virtual bit. This will only become 272121afaf18SBorislav Petkov * a problem if/when we move beyond 5-level page tables. 272221afaf18SBorislav Petkov */ 272321afaf18SBorislav Petkov MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63); 272421afaf18SBorislav Petkov 272521afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) { 272621afaf18SBorislav Petkov err = -EIO; 272721afaf18SBorislav Petkov goto err_out; 272821afaf18SBorislav Petkov } 272921afaf18SBorislav Petkov 273021afaf18SBorislav Petkov if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { 273121afaf18SBorislav Petkov err = -ENOMEM; 273221afaf18SBorislav Petkov goto err_out; 273321afaf18SBorislav Petkov } 273421afaf18SBorislav Petkov 273521afaf18SBorislav Petkov mce_init_banks(); 273621afaf18SBorislav Petkov 273721afaf18SBorislav Petkov err = subsys_system_register(&mce_subsys, NULL); 273821afaf18SBorislav Petkov if (err) 273921afaf18SBorislav Petkov goto err_out_mem; 274021afaf18SBorislav Petkov 274121afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL, 274221afaf18SBorislav Petkov mce_cpu_dead); 274321afaf18SBorislav Petkov if (err) 274421afaf18SBorislav Petkov goto err_out_mem; 274521afaf18SBorislav Petkov 27466e7a41c6SThomas Gleixner /* 27476e7a41c6SThomas Gleixner * Invokes mce_cpu_online() on all CPUs which are online when 27486e7a41c6SThomas Gleixner * the state is installed. 27496e7a41c6SThomas Gleixner */ 275021afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online", 275121afaf18SBorislav Petkov mce_cpu_online, mce_cpu_pre_down); 275221afaf18SBorislav Petkov if (err < 0) 275321afaf18SBorislav Petkov goto err_out_online; 275421afaf18SBorislav Petkov 275521afaf18SBorislav Petkov register_syscore_ops(&mce_syscore_ops); 275621afaf18SBorislav Petkov 275721afaf18SBorislav Petkov return 0; 275821afaf18SBorislav Petkov 275921afaf18SBorislav Petkov err_out_online: 276021afaf18SBorislav Petkov cpuhp_remove_state(CPUHP_X86_MCE_DEAD); 276121afaf18SBorislav Petkov 276221afaf18SBorislav Petkov err_out_mem: 276321afaf18SBorislav Petkov free_cpumask_var(mce_device_initialized); 276421afaf18SBorislav Petkov 276521afaf18SBorislav Petkov err_out: 276621afaf18SBorislav Petkov pr_err("Unable to init MCE device (rc: %d)\n", err); 276721afaf18SBorislav Petkov 276821afaf18SBorislav Petkov return err; 276921afaf18SBorislav Petkov } 277021afaf18SBorislav Petkov device_initcall_sync(mcheck_init_device); 277121afaf18SBorislav Petkov 277221afaf18SBorislav Petkov /* 277321afaf18SBorislav Petkov * Old style boot options parsing. Only for compatibility. 277421afaf18SBorislav Petkov */ 277521afaf18SBorislav Petkov static int __init mcheck_disable(char *str) 277621afaf18SBorislav Petkov { 277721afaf18SBorislav Petkov mca_cfg.disabled = 1; 277821afaf18SBorislav Petkov return 1; 277921afaf18SBorislav Petkov } 278021afaf18SBorislav Petkov __setup("nomce", mcheck_disable); 278121afaf18SBorislav Petkov 278221afaf18SBorislav Petkov #ifdef CONFIG_DEBUG_FS 278321afaf18SBorislav Petkov struct dentry *mce_get_debugfs_dir(void) 278421afaf18SBorislav Petkov { 278521afaf18SBorislav Petkov static struct dentry *dmce; 278621afaf18SBorislav Petkov 278721afaf18SBorislav Petkov if (!dmce) 278821afaf18SBorislav Petkov dmce = debugfs_create_dir("mce", NULL); 278921afaf18SBorislav Petkov 279021afaf18SBorislav Petkov return dmce; 279121afaf18SBorislav Petkov } 279221afaf18SBorislav Petkov 279321afaf18SBorislav Petkov static void mce_reset(void) 279421afaf18SBorislav Petkov { 279521afaf18SBorislav Petkov atomic_set(&mce_fake_panicked, 0); 279621afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 279721afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 279821afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 27997bb39313SPaul E. McKenney cpumask_setall(&mce_missing_cpus); 280021afaf18SBorislav Petkov } 280121afaf18SBorislav Petkov 280221afaf18SBorislav Petkov static int fake_panic_get(void *data, u64 *val) 280321afaf18SBorislav Petkov { 280421afaf18SBorislav Petkov *val = fake_panic; 280521afaf18SBorislav Petkov return 0; 280621afaf18SBorislav Petkov } 280721afaf18SBorislav Petkov 280821afaf18SBorislav Petkov static int fake_panic_set(void *data, u64 val) 280921afaf18SBorislav Petkov { 281021afaf18SBorislav Petkov mce_reset(); 281121afaf18SBorislav Petkov fake_panic = val; 281221afaf18SBorislav Petkov return 0; 281321afaf18SBorislav Petkov } 281421afaf18SBorislav Petkov 281528156d76SYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set, 281628156d76SYueHaibing "%llu\n"); 281721afaf18SBorislav Petkov 28186e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) 281921afaf18SBorislav Petkov { 28206e4f929eSGreg Kroah-Hartman struct dentry *dmce; 282121afaf18SBorislav Petkov 282221afaf18SBorislav Petkov dmce = mce_get_debugfs_dir(); 28236e4f929eSGreg Kroah-Hartman debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL, 28246e4f929eSGreg Kroah-Hartman &fake_panic_fops); 282521afaf18SBorislav Petkov } 282621afaf18SBorislav Petkov #else 28276e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) { } 282821afaf18SBorislav Petkov #endif 282921afaf18SBorislav Petkov 283021afaf18SBorislav Petkov static int __init mcheck_late_init(void) 283121afaf18SBorislav Petkov { 283221afaf18SBorislav Petkov if (mca_cfg.recovery) 2833ec6347bbSDan Williams enable_copy_mc_fragile(); 283421afaf18SBorislav Petkov 283521afaf18SBorislav Petkov mcheck_debugfs_init(); 283621afaf18SBorislav Petkov 283721afaf18SBorislav Petkov /* 283821afaf18SBorislav Petkov * Flush out everything that has been logged during early boot, now that 283921afaf18SBorislav Petkov * everything has been initialized (workqueues, decoders, ...). 284021afaf18SBorislav Petkov */ 284121afaf18SBorislav Petkov mce_schedule_work(); 284221afaf18SBorislav Petkov 284321afaf18SBorislav Petkov return 0; 284421afaf18SBorislav Petkov } 284521afaf18SBorislav Petkov late_initcall(mcheck_late_init); 2846