1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 221afaf18SBorislav Petkov /* 321afaf18SBorislav Petkov * Machine check handler. 421afaf18SBorislav Petkov * 521afaf18SBorislav Petkov * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. 621afaf18SBorislav Petkov * Rest from unknown author(s). 721afaf18SBorislav Petkov * 2004 Andi Kleen. Rewrote most of it. 821afaf18SBorislav Petkov * Copyright 2008 Intel Corporation 921afaf18SBorislav Petkov * Author: Andi Kleen 1021afaf18SBorislav Petkov */ 1121afaf18SBorislav Petkov 1221afaf18SBorislav Petkov #include <linux/thread_info.h> 1321afaf18SBorislav Petkov #include <linux/capability.h> 1421afaf18SBorislav Petkov #include <linux/miscdevice.h> 1521afaf18SBorislav Petkov #include <linux/ratelimit.h> 1621afaf18SBorislav Petkov #include <linux/rcupdate.h> 1721afaf18SBorislav Petkov #include <linux/kobject.h> 1821afaf18SBorislav Petkov #include <linux/uaccess.h> 1921afaf18SBorislav Petkov #include <linux/kdebug.h> 2021afaf18SBorislav Petkov #include <linux/kernel.h> 2121afaf18SBorislav Petkov #include <linux/percpu.h> 2221afaf18SBorislav Petkov #include <linux/string.h> 2321afaf18SBorislav Petkov #include <linux/device.h> 2421afaf18SBorislav Petkov #include <linux/syscore_ops.h> 2521afaf18SBorislav Petkov #include <linux/delay.h> 2621afaf18SBorislav Petkov #include <linux/ctype.h> 2721afaf18SBorislav Petkov #include <linux/sched.h> 2821afaf18SBorislav Petkov #include <linux/sysfs.h> 2921afaf18SBorislav Petkov #include <linux/types.h> 3021afaf18SBorislav Petkov #include <linux/slab.h> 3121afaf18SBorislav Petkov #include <linux/init.h> 3221afaf18SBorislav Petkov #include <linux/kmod.h> 3321afaf18SBorislav Petkov #include <linux/poll.h> 3421afaf18SBorislav Petkov #include <linux/nmi.h> 3521afaf18SBorislav Petkov #include <linux/cpu.h> 3621afaf18SBorislav Petkov #include <linux/ras.h> 3721afaf18SBorislav Petkov #include <linux/smp.h> 3821afaf18SBorislav Petkov #include <linux/fs.h> 3921afaf18SBorislav Petkov #include <linux/mm.h> 4021afaf18SBorislav Petkov #include <linux/debugfs.h> 4121afaf18SBorislav Petkov #include <linux/irq_work.h> 4221afaf18SBorislav Petkov #include <linux/export.h> 4321afaf18SBorislav Petkov #include <linux/jump_label.h> 4421afaf18SBorislav Petkov #include <linux/set_memory.h> 455567d11cSPeter Zijlstra #include <linux/task_work.h> 460d00449cSPeter Zijlstra #include <linux/hardirq.h> 4721afaf18SBorislav Petkov 4821afaf18SBorislav Petkov #include <asm/intel-family.h> 4921afaf18SBorislav Petkov #include <asm/processor.h> 5021afaf18SBorislav Petkov #include <asm/traps.h> 5121afaf18SBorislav Petkov #include <asm/tlbflush.h> 5221afaf18SBorislav Petkov #include <asm/mce.h> 5321afaf18SBorislav Petkov #include <asm/msr.h> 5421afaf18SBorislav Petkov #include <asm/reboot.h> 5521afaf18SBorislav Petkov 5621afaf18SBorislav Petkov #include "internal.h" 5721afaf18SBorislav Petkov 5821afaf18SBorislav Petkov /* sysfs synchronization */ 5921afaf18SBorislav Petkov static DEFINE_MUTEX(mce_sysfs_mutex); 6021afaf18SBorislav Petkov 6121afaf18SBorislav Petkov #define CREATE_TRACE_POINTS 6221afaf18SBorislav Petkov #include <trace/events/mce.h> 6321afaf18SBorislav Petkov 6421afaf18SBorislav Petkov #define SPINUNIT 100 /* 100ns */ 6521afaf18SBorislav Petkov 6621afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_exception_count); 6721afaf18SBorislav Petkov 68c7d314f3SYazen Ghannam DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks); 69c7d314f3SYazen Ghannam 7095fdce6bSYazen Ghannam struct mce_bank { 7195fdce6bSYazen Ghannam u64 ctl; /* subevents to enable */ 7295fdce6bSYazen Ghannam bool init; /* initialise bank? */ 73b4914508SYazen Ghannam }; 74b4914508SYazen Ghannam static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); 75b4914508SYazen Ghannam 76b4914508SYazen Ghannam #define ATTR_LEN 16 77b4914508SYazen Ghannam /* One object for each MCE bank, shared by all CPUs */ 78b4914508SYazen Ghannam struct mce_bank_dev { 7995fdce6bSYazen Ghannam struct device_attribute attr; /* device attribute */ 8095fdce6bSYazen Ghannam char attrname[ATTR_LEN]; /* attribute name */ 81b4914508SYazen Ghannam u8 bank; /* bank number */ 8295fdce6bSYazen Ghannam }; 83b4914508SYazen Ghannam static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS]; 8495fdce6bSYazen Ghannam 8521afaf18SBorislav Petkov struct mce_vendor_flags mce_flags __read_mostly; 8621afaf18SBorislav Petkov 8721afaf18SBorislav Petkov struct mca_config mca_cfg __read_mostly = { 8821afaf18SBorislav Petkov .bootlog = -1, 8921afaf18SBorislav Petkov /* 9021afaf18SBorislav Petkov * Tolerant levels: 9121afaf18SBorislav Petkov * 0: always panic on uncorrected errors, log corrected errors 9221afaf18SBorislav Petkov * 1: panic or SIGBUS on uncorrected errors, log corrected errors 9321afaf18SBorislav Petkov * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors 9421afaf18SBorislav Petkov * 3: never panic or SIGBUS, log all errors (for testing only) 9521afaf18SBorislav Petkov */ 9621afaf18SBorislav Petkov .tolerant = 1, 9721afaf18SBorislav Petkov .monarch_timeout = -1 9821afaf18SBorislav Petkov }; 9921afaf18SBorislav Petkov 10021afaf18SBorislav Petkov static DEFINE_PER_CPU(struct mce, mces_seen); 10121afaf18SBorislav Petkov static unsigned long mce_need_notify; 10221afaf18SBorislav Petkov static int cpu_missing; 10321afaf18SBorislav Petkov 10421afaf18SBorislav Petkov /* 10521afaf18SBorislav Petkov * MCA banks polled by the period polling timer for corrected events. 10621afaf18SBorislav Petkov * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). 10721afaf18SBorislav Petkov */ 10821afaf18SBorislav Petkov DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { 10921afaf18SBorislav Petkov [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL 11021afaf18SBorislav Petkov }; 11121afaf18SBorislav Petkov 11221afaf18SBorislav Petkov /* 11321afaf18SBorislav Petkov * MCA banks controlled through firmware first for corrected errors. 11421afaf18SBorislav Petkov * This is a global list of banks for which we won't enable CMCI and we 11521afaf18SBorislav Petkov * won't poll. Firmware controls these banks and is responsible for 11621afaf18SBorislav Petkov * reporting corrected errors through GHES. Uncorrected/recoverable 11721afaf18SBorislav Petkov * errors are still notified through a machine check. 11821afaf18SBorislav Petkov */ 11921afaf18SBorislav Petkov mce_banks_t mce_banks_ce_disabled; 12021afaf18SBorislav Petkov 12121afaf18SBorislav Petkov static struct work_struct mce_work; 12221afaf18SBorislav Petkov static struct irq_work mce_irq_work; 12321afaf18SBorislav Petkov 12421afaf18SBorislav Petkov static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); 12521afaf18SBorislav Petkov 12621afaf18SBorislav Petkov /* 12721afaf18SBorislav Petkov * CPU/chipset specific EDAC code can register a notifier call here to print 12821afaf18SBorislav Petkov * MCE errors in a human-readable form. 12921afaf18SBorislav Petkov */ 13021afaf18SBorislav Petkov BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); 13121afaf18SBorislav Petkov 13221afaf18SBorislav Petkov /* Do initial initialization of a struct mce */ 133865d3a9aSThomas Gleixner noinstr void mce_setup(struct mce *m) 13421afaf18SBorislav Petkov { 13521afaf18SBorislav Petkov memset(m, 0, sizeof(struct mce)); 13621afaf18SBorislav Petkov m->cpu = m->extcpu = smp_processor_id(); 13721afaf18SBorislav Petkov /* need the internal __ version to avoid deadlocks */ 13821afaf18SBorislav Petkov m->time = __ktime_get_real_seconds(); 13921afaf18SBorislav Petkov m->cpuvendor = boot_cpu_data.x86_vendor; 14021afaf18SBorislav Petkov m->cpuid = cpuid_eax(1); 14121afaf18SBorislav Petkov m->socketid = cpu_data(m->extcpu).phys_proc_id; 14221afaf18SBorislav Petkov m->apicid = cpu_data(m->extcpu).initial_apicid; 143865d3a9aSThomas Gleixner m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); 14421afaf18SBorislav Petkov 14521afaf18SBorislav Petkov if (this_cpu_has(X86_FEATURE_INTEL_PPIN)) 146865d3a9aSThomas Gleixner m->ppin = __rdmsr(MSR_PPIN); 147077168e2SWei Huang else if (this_cpu_has(X86_FEATURE_AMD_PPIN)) 148865d3a9aSThomas Gleixner m->ppin = __rdmsr(MSR_AMD_PPIN); 14921afaf18SBorislav Petkov 15021afaf18SBorislav Petkov m->microcode = boot_cpu_data.microcode; 15121afaf18SBorislav Petkov } 15221afaf18SBorislav Petkov 15321afaf18SBorislav Petkov DEFINE_PER_CPU(struct mce, injectm); 15421afaf18SBorislav Petkov EXPORT_PER_CPU_SYMBOL_GPL(injectm); 15521afaf18SBorislav Petkov 15621afaf18SBorislav Petkov void mce_log(struct mce *m) 15721afaf18SBorislav Petkov { 15821afaf18SBorislav Petkov if (!mce_gen_pool_add(m)) 15921afaf18SBorislav Petkov irq_work_queue(&mce_irq_work); 16021afaf18SBorislav Petkov } 16181736abdSJan H. Schönherr EXPORT_SYMBOL_GPL(mce_log); 16221afaf18SBorislav Petkov 16321afaf18SBorislav Petkov void mce_register_decode_chain(struct notifier_block *nb) 16421afaf18SBorislav Petkov { 16521afaf18SBorislav Petkov if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC)) 16621afaf18SBorislav Petkov return; 16721afaf18SBorislav Petkov 16821afaf18SBorislav Petkov blocking_notifier_chain_register(&x86_mce_decoder_chain, nb); 16921afaf18SBorislav Petkov } 17021afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_register_decode_chain); 17121afaf18SBorislav Petkov 17221afaf18SBorislav Petkov void mce_unregister_decode_chain(struct notifier_block *nb) 17321afaf18SBorislav Petkov { 17421afaf18SBorislav Petkov blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb); 17521afaf18SBorislav Petkov } 17621afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); 17721afaf18SBorislav Petkov 17821afaf18SBorislav Petkov static inline u32 ctl_reg(int bank) 17921afaf18SBorislav Petkov { 18021afaf18SBorislav Petkov return MSR_IA32_MCx_CTL(bank); 18121afaf18SBorislav Petkov } 18221afaf18SBorislav Petkov 18321afaf18SBorislav Petkov static inline u32 status_reg(int bank) 18421afaf18SBorislav Petkov { 18521afaf18SBorislav Petkov return MSR_IA32_MCx_STATUS(bank); 18621afaf18SBorislav Petkov } 18721afaf18SBorislav Petkov 18821afaf18SBorislav Petkov static inline u32 addr_reg(int bank) 18921afaf18SBorislav Petkov { 19021afaf18SBorislav Petkov return MSR_IA32_MCx_ADDR(bank); 19121afaf18SBorislav Petkov } 19221afaf18SBorislav Petkov 19321afaf18SBorislav Petkov static inline u32 misc_reg(int bank) 19421afaf18SBorislav Petkov { 19521afaf18SBorislav Petkov return MSR_IA32_MCx_MISC(bank); 19621afaf18SBorislav Petkov } 19721afaf18SBorislav Petkov 19821afaf18SBorislav Petkov static inline u32 smca_ctl_reg(int bank) 19921afaf18SBorislav Petkov { 20021afaf18SBorislav Petkov return MSR_AMD64_SMCA_MCx_CTL(bank); 20121afaf18SBorislav Petkov } 20221afaf18SBorislav Petkov 20321afaf18SBorislav Petkov static inline u32 smca_status_reg(int bank) 20421afaf18SBorislav Petkov { 20521afaf18SBorislav Petkov return MSR_AMD64_SMCA_MCx_STATUS(bank); 20621afaf18SBorislav Petkov } 20721afaf18SBorislav Petkov 20821afaf18SBorislav Petkov static inline u32 smca_addr_reg(int bank) 20921afaf18SBorislav Petkov { 21021afaf18SBorislav Petkov return MSR_AMD64_SMCA_MCx_ADDR(bank); 21121afaf18SBorislav Petkov } 21221afaf18SBorislav Petkov 21321afaf18SBorislav Petkov static inline u32 smca_misc_reg(int bank) 21421afaf18SBorislav Petkov { 21521afaf18SBorislav Petkov return MSR_AMD64_SMCA_MCx_MISC(bank); 21621afaf18SBorislav Petkov } 21721afaf18SBorislav Petkov 21821afaf18SBorislav Petkov struct mca_msr_regs msr_ops = { 21921afaf18SBorislav Petkov .ctl = ctl_reg, 22021afaf18SBorislav Petkov .status = status_reg, 22121afaf18SBorislav Petkov .addr = addr_reg, 22221afaf18SBorislav Petkov .misc = misc_reg 22321afaf18SBorislav Petkov }; 22421afaf18SBorislav Petkov 22521afaf18SBorislav Petkov static void __print_mce(struct mce *m) 22621afaf18SBorislav Petkov { 22721afaf18SBorislav Petkov pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", 22821afaf18SBorislav Petkov m->extcpu, 22921afaf18SBorislav Petkov (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""), 23021afaf18SBorislav Petkov m->mcgstatus, m->bank, m->status); 23121afaf18SBorislav Petkov 23221afaf18SBorislav Petkov if (m->ip) { 23321afaf18SBorislav Petkov pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", 23421afaf18SBorislav Petkov !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", 23521afaf18SBorislav Petkov m->cs, m->ip); 23621afaf18SBorislav Petkov 23721afaf18SBorislav Petkov if (m->cs == __KERNEL_CS) 23821afaf18SBorislav Petkov pr_cont("{%pS}", (void *)(unsigned long)m->ip); 23921afaf18SBorislav Petkov pr_cont("\n"); 24021afaf18SBorislav Petkov } 24121afaf18SBorislav Petkov 24221afaf18SBorislav Petkov pr_emerg(HW_ERR "TSC %llx ", m->tsc); 24321afaf18SBorislav Petkov if (m->addr) 24421afaf18SBorislav Petkov pr_cont("ADDR %llx ", m->addr); 24521afaf18SBorislav Petkov if (m->misc) 24621afaf18SBorislav Petkov pr_cont("MISC %llx ", m->misc); 24721afaf18SBorislav Petkov 24821afaf18SBorislav Petkov if (mce_flags.smca) { 24921afaf18SBorislav Petkov if (m->synd) 25021afaf18SBorislav Petkov pr_cont("SYND %llx ", m->synd); 25121afaf18SBorislav Petkov if (m->ipid) 25221afaf18SBorislav Petkov pr_cont("IPID %llx ", m->ipid); 25321afaf18SBorislav Petkov } 25421afaf18SBorislav Petkov 25521afaf18SBorislav Petkov pr_cont("\n"); 256925946cfSTony Luck 25721afaf18SBorislav Petkov /* 25821afaf18SBorislav Petkov * Note this output is parsed by external tools and old fields 25921afaf18SBorislav Petkov * should not be changed. 26021afaf18SBorislav Petkov */ 26121afaf18SBorislav Petkov pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", 26221afaf18SBorislav Petkov m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, 26321afaf18SBorislav Petkov m->microcode); 26421afaf18SBorislav Petkov } 26521afaf18SBorislav Petkov 26621afaf18SBorislav Petkov static void print_mce(struct mce *m) 26721afaf18SBorislav Petkov { 26821afaf18SBorislav Petkov __print_mce(m); 26921afaf18SBorislav Petkov 27021afaf18SBorislav Petkov if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON) 27121afaf18SBorislav Petkov pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); 27221afaf18SBorislav Petkov } 27321afaf18SBorislav Petkov 27421afaf18SBorislav Petkov #define PANIC_TIMEOUT 5 /* 5 seconds */ 27521afaf18SBorislav Petkov 27621afaf18SBorislav Petkov static atomic_t mce_panicked; 27721afaf18SBorislav Petkov 27821afaf18SBorislav Petkov static int fake_panic; 27921afaf18SBorislav Petkov static atomic_t mce_fake_panicked; 28021afaf18SBorislav Petkov 28121afaf18SBorislav Petkov /* Panic in progress. Enable interrupts and wait for final IPI */ 28221afaf18SBorislav Petkov static void wait_for_panic(void) 28321afaf18SBorislav Petkov { 28421afaf18SBorislav Petkov long timeout = PANIC_TIMEOUT*USEC_PER_SEC; 28521afaf18SBorislav Petkov 28621afaf18SBorislav Petkov preempt_disable(); 28721afaf18SBorislav Petkov local_irq_enable(); 28821afaf18SBorislav Petkov while (timeout-- > 0) 28921afaf18SBorislav Petkov udelay(1); 29021afaf18SBorislav Petkov if (panic_timeout == 0) 29121afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 29221afaf18SBorislav Petkov panic("Panicing machine check CPU died"); 29321afaf18SBorislav Petkov } 29421afaf18SBorislav Petkov 29521afaf18SBorislav Petkov static void mce_panic(const char *msg, struct mce *final, char *exp) 29621afaf18SBorislav Petkov { 29721afaf18SBorislav Petkov int apei_err = 0; 29821afaf18SBorislav Petkov struct llist_node *pending; 29921afaf18SBorislav Petkov struct mce_evt_llist *l; 30021afaf18SBorislav Petkov 30121afaf18SBorislav Petkov if (!fake_panic) { 30221afaf18SBorislav Petkov /* 30321afaf18SBorislav Petkov * Make sure only one CPU runs in machine check panic 30421afaf18SBorislav Petkov */ 30521afaf18SBorislav Petkov if (atomic_inc_return(&mce_panicked) > 1) 30621afaf18SBorislav Petkov wait_for_panic(); 30721afaf18SBorislav Petkov barrier(); 30821afaf18SBorislav Petkov 30921afaf18SBorislav Petkov bust_spinlocks(1); 31021afaf18SBorislav Petkov console_verbose(); 31121afaf18SBorislav Petkov } else { 31221afaf18SBorislav Petkov /* Don't log too much for fake panic */ 31321afaf18SBorislav Petkov if (atomic_inc_return(&mce_fake_panicked) > 1) 31421afaf18SBorislav Petkov return; 31521afaf18SBorislav Petkov } 31621afaf18SBorislav Petkov pending = mce_gen_pool_prepare_records(); 31721afaf18SBorislav Petkov /* First print corrected ones that are still unlogged */ 31821afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 31921afaf18SBorislav Petkov struct mce *m = &l->mce; 32021afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) { 32121afaf18SBorislav Petkov print_mce(m); 32221afaf18SBorislav Petkov if (!apei_err) 32321afaf18SBorislav Petkov apei_err = apei_write_mce(m); 32421afaf18SBorislav Petkov } 32521afaf18SBorislav Petkov } 32621afaf18SBorislav Petkov /* Now print uncorrected but with the final one last */ 32721afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 32821afaf18SBorislav Petkov struct mce *m = &l->mce; 32921afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) 33021afaf18SBorislav Petkov continue; 33121afaf18SBorislav Petkov if (!final || mce_cmp(m, final)) { 33221afaf18SBorislav Petkov print_mce(m); 33321afaf18SBorislav Petkov if (!apei_err) 33421afaf18SBorislav Petkov apei_err = apei_write_mce(m); 33521afaf18SBorislav Petkov } 33621afaf18SBorislav Petkov } 33721afaf18SBorislav Petkov if (final) { 33821afaf18SBorislav Petkov print_mce(final); 33921afaf18SBorislav Petkov if (!apei_err) 34021afaf18SBorislav Petkov apei_err = apei_write_mce(final); 34121afaf18SBorislav Petkov } 34221afaf18SBorislav Petkov if (cpu_missing) 34321afaf18SBorislav Petkov pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); 34421afaf18SBorislav Petkov if (exp) 34521afaf18SBorislav Petkov pr_emerg(HW_ERR "Machine check: %s\n", exp); 34621afaf18SBorislav Petkov if (!fake_panic) { 34721afaf18SBorislav Petkov if (panic_timeout == 0) 34821afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 34921afaf18SBorislav Petkov panic(msg); 35021afaf18SBorislav Petkov } else 35121afaf18SBorislav Petkov pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); 35221afaf18SBorislav Petkov } 35321afaf18SBorislav Petkov 35421afaf18SBorislav Petkov /* Support code for software error injection */ 35521afaf18SBorislav Petkov 35621afaf18SBorislav Petkov static int msr_to_offset(u32 msr) 35721afaf18SBorislav Petkov { 35821afaf18SBorislav Petkov unsigned bank = __this_cpu_read(injectm.bank); 35921afaf18SBorislav Petkov 36021afaf18SBorislav Petkov if (msr == mca_cfg.rip_msr) 36121afaf18SBorislav Petkov return offsetof(struct mce, ip); 36221afaf18SBorislav Petkov if (msr == msr_ops.status(bank)) 36321afaf18SBorislav Petkov return offsetof(struct mce, status); 36421afaf18SBorislav Petkov if (msr == msr_ops.addr(bank)) 36521afaf18SBorislav Petkov return offsetof(struct mce, addr); 36621afaf18SBorislav Petkov if (msr == msr_ops.misc(bank)) 36721afaf18SBorislav Petkov return offsetof(struct mce, misc); 36821afaf18SBorislav Petkov if (msr == MSR_IA32_MCG_STATUS) 36921afaf18SBorislav Petkov return offsetof(struct mce, mcgstatus); 37021afaf18SBorislav Petkov return -1; 37121afaf18SBorislav Petkov } 37221afaf18SBorislav Petkov 37321afaf18SBorislav Petkov /* MSR access wrappers used for error injection */ 37421afaf18SBorislav Petkov static u64 mce_rdmsrl(u32 msr) 37521afaf18SBorislav Petkov { 37621afaf18SBorislav Petkov u64 v; 37721afaf18SBorislav Petkov 37821afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 37921afaf18SBorislav Petkov int offset = msr_to_offset(msr); 38021afaf18SBorislav Petkov 38121afaf18SBorislav Petkov if (offset < 0) 38221afaf18SBorislav Petkov return 0; 38321afaf18SBorislav Petkov return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); 38421afaf18SBorislav Petkov } 38521afaf18SBorislav Petkov 38621afaf18SBorislav Petkov if (rdmsrl_safe(msr, &v)) { 38721afaf18SBorislav Petkov WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr); 38821afaf18SBorislav Petkov /* 38921afaf18SBorislav Petkov * Return zero in case the access faulted. This should 39021afaf18SBorislav Petkov * not happen normally but can happen if the CPU does 39121afaf18SBorislav Petkov * something weird, or if the code is buggy. 39221afaf18SBorislav Petkov */ 39321afaf18SBorislav Petkov v = 0; 39421afaf18SBorislav Petkov } 39521afaf18SBorislav Petkov 39621afaf18SBorislav Petkov return v; 39721afaf18SBorislav Petkov } 39821afaf18SBorislav Petkov 39921afaf18SBorislav Petkov static void mce_wrmsrl(u32 msr, u64 v) 40021afaf18SBorislav Petkov { 40121afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 40221afaf18SBorislav Petkov int offset = msr_to_offset(msr); 40321afaf18SBorislav Petkov 40421afaf18SBorislav Petkov if (offset >= 0) 40521afaf18SBorislav Petkov *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; 40621afaf18SBorislav Petkov return; 40721afaf18SBorislav Petkov } 40821afaf18SBorislav Petkov wrmsrl(msr, v); 40921afaf18SBorislav Petkov } 41021afaf18SBorislav Petkov 41121afaf18SBorislav Petkov /* 41221afaf18SBorislav Petkov * Collect all global (w.r.t. this processor) status about this machine 41321afaf18SBorislav Petkov * check into our "mce" struct so that we can use it later to assess 41421afaf18SBorislav Petkov * the severity of the problem as we read per-bank specific details. 41521afaf18SBorislav Petkov */ 41621afaf18SBorislav Petkov static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) 41721afaf18SBorislav Petkov { 41821afaf18SBorislav Petkov mce_setup(m); 41921afaf18SBorislav Petkov 42021afaf18SBorislav Petkov m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 42121afaf18SBorislav Petkov if (regs) { 42221afaf18SBorislav Petkov /* 42321afaf18SBorislav Petkov * Get the address of the instruction at the time of 42421afaf18SBorislav Petkov * the machine check error. 42521afaf18SBorislav Petkov */ 42621afaf18SBorislav Petkov if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { 42721afaf18SBorislav Petkov m->ip = regs->ip; 42821afaf18SBorislav Petkov m->cs = regs->cs; 42921afaf18SBorislav Petkov 43021afaf18SBorislav Petkov /* 43121afaf18SBorislav Petkov * When in VM86 mode make the cs look like ring 3 43221afaf18SBorislav Petkov * always. This is a lie, but it's better than passing 43321afaf18SBorislav Petkov * the additional vm86 bit around everywhere. 43421afaf18SBorislav Petkov */ 43521afaf18SBorislav Petkov if (v8086_mode(regs)) 43621afaf18SBorislav Petkov m->cs |= 3; 43721afaf18SBorislav Petkov } 43821afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 43921afaf18SBorislav Petkov if (mca_cfg.rip_msr) 44021afaf18SBorislav Petkov m->ip = mce_rdmsrl(mca_cfg.rip_msr); 44121afaf18SBorislav Petkov } 44221afaf18SBorislav Petkov } 44321afaf18SBorislav Petkov 44421afaf18SBorislav Petkov int mce_available(struct cpuinfo_x86 *c) 44521afaf18SBorislav Petkov { 44621afaf18SBorislav Petkov if (mca_cfg.disabled) 44721afaf18SBorislav Petkov return 0; 44821afaf18SBorislav Petkov return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); 44921afaf18SBorislav Petkov } 45021afaf18SBorislav Petkov 45121afaf18SBorislav Petkov static void mce_schedule_work(void) 45221afaf18SBorislav Petkov { 45321afaf18SBorislav Petkov if (!mce_gen_pool_empty()) 45421afaf18SBorislav Petkov schedule_work(&mce_work); 45521afaf18SBorislav Petkov } 45621afaf18SBorislav Petkov 45721afaf18SBorislav Petkov static void mce_irq_work_cb(struct irq_work *entry) 45821afaf18SBorislav Petkov { 45921afaf18SBorislav Petkov mce_schedule_work(); 46021afaf18SBorislav Petkov } 46121afaf18SBorislav Petkov 46221afaf18SBorislav Petkov /* 46321afaf18SBorislav Petkov * Check if the address reported by the CPU is in a format we can parse. 46421afaf18SBorislav Petkov * It would be possible to add code for most other cases, but all would 46521afaf18SBorislav Petkov * be somewhat complicated (e.g. segment offset would require an instruction 46621afaf18SBorislav Petkov * parser). So only support physical addresses up to page granuality for now. 46721afaf18SBorislav Petkov */ 46821afaf18SBorislav Petkov int mce_usable_address(struct mce *m) 46921afaf18SBorislav Petkov { 47021afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_ADDRV)) 47121afaf18SBorislav Petkov return 0; 47221afaf18SBorislav Petkov 4736e898d2bSTony W Wang-oc /* Checks after this one are Intel/Zhaoxin-specific: */ 4746e898d2bSTony W Wang-oc if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && 4756e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) 47621afaf18SBorislav Petkov return 1; 47721afaf18SBorislav Petkov 47821afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_MISCV)) 47921afaf18SBorislav Petkov return 0; 48021afaf18SBorislav Petkov 48121afaf18SBorislav Petkov if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) 48221afaf18SBorislav Petkov return 0; 48321afaf18SBorislav Petkov 48421afaf18SBorislav Petkov if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) 48521afaf18SBorislav Petkov return 0; 48621afaf18SBorislav Petkov 48721afaf18SBorislav Petkov return 1; 48821afaf18SBorislav Petkov } 48921afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_usable_address); 49021afaf18SBorislav Petkov 49121afaf18SBorislav Petkov bool mce_is_memory_error(struct mce *m) 49221afaf18SBorislav Petkov { 4936e898d2bSTony W Wang-oc switch (m->cpuvendor) { 4946e898d2bSTony W Wang-oc case X86_VENDOR_AMD: 4956e898d2bSTony W Wang-oc case X86_VENDOR_HYGON: 49621afaf18SBorislav Petkov return amd_mce_is_memory_error(m); 4976e898d2bSTony W Wang-oc 4986e898d2bSTony W Wang-oc case X86_VENDOR_INTEL: 4996e898d2bSTony W Wang-oc case X86_VENDOR_ZHAOXIN: 50021afaf18SBorislav Petkov /* 50121afaf18SBorislav Petkov * Intel SDM Volume 3B - 15.9.2 Compound Error Codes 50221afaf18SBorislav Petkov * 50321afaf18SBorislav Petkov * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for 50421afaf18SBorislav Petkov * indicating a memory error. Bit 8 is used for indicating a 50521afaf18SBorislav Petkov * cache hierarchy error. The combination of bit 2 and bit 3 50621afaf18SBorislav Petkov * is used for indicating a `generic' cache hierarchy error 50721afaf18SBorislav Petkov * But we can't just blindly check the above bits, because if 50821afaf18SBorislav Petkov * bit 11 is set, then it is a bus/interconnect error - and 50921afaf18SBorislav Petkov * either way the above bits just gives more detail on what 51021afaf18SBorislav Petkov * bus/interconnect error happened. Note that bit 12 can be 51121afaf18SBorislav Petkov * ignored, as it's the "filter" bit. 51221afaf18SBorislav Petkov */ 51321afaf18SBorislav Petkov return (m->status & 0xef80) == BIT(7) || 51421afaf18SBorislav Petkov (m->status & 0xef00) == BIT(8) || 51521afaf18SBorislav Petkov (m->status & 0xeffc) == 0xc; 51621afaf18SBorislav Petkov 5176e898d2bSTony W Wang-oc default: 51821afaf18SBorislav Petkov return false; 51921afaf18SBorislav Petkov } 5206e898d2bSTony W Wang-oc } 52121afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_memory_error); 52221afaf18SBorislav Petkov 52317fae129STony Luck static bool whole_page(struct mce *m) 52417fae129STony Luck { 52517fae129STony Luck if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV)) 52617fae129STony Luck return true; 52717fae129STony Luck 52817fae129STony Luck return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT; 52917fae129STony Luck } 53017fae129STony Luck 53121afaf18SBorislav Petkov bool mce_is_correctable(struct mce *m) 53221afaf18SBorislav Petkov { 53321afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED) 53421afaf18SBorislav Petkov return false; 53521afaf18SBorislav Petkov 53621afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED) 53721afaf18SBorislav Petkov return false; 53821afaf18SBorislav Petkov 53921afaf18SBorislav Petkov if (m->status & MCI_STATUS_UC) 54021afaf18SBorislav Petkov return false; 54121afaf18SBorislav Petkov 54221afaf18SBorislav Petkov return true; 54321afaf18SBorislav Petkov } 54421afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_correctable); 54521afaf18SBorislav Petkov 546c9c6d216STony Luck static int mce_early_notifier(struct notifier_block *nb, unsigned long val, 54721afaf18SBorislav Petkov void *data) 54821afaf18SBorislav Petkov { 54921afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 55021afaf18SBorislav Petkov 55121afaf18SBorislav Petkov if (!m) 55221afaf18SBorislav Petkov return NOTIFY_DONE; 55321afaf18SBorislav Petkov 55421afaf18SBorislav Petkov /* Emit the trace record: */ 55521afaf18SBorislav Petkov trace_mce_record(m); 55621afaf18SBorislav Petkov 55721afaf18SBorislav Petkov set_bit(0, &mce_need_notify); 55821afaf18SBorislav Petkov 55921afaf18SBorislav Petkov mce_notify_irq(); 56021afaf18SBorislav Petkov 56121afaf18SBorislav Petkov return NOTIFY_DONE; 56221afaf18SBorislav Petkov } 56321afaf18SBorislav Petkov 564c9c6d216STony Luck static struct notifier_block early_nb = { 565c9c6d216STony Luck .notifier_call = mce_early_notifier, 566c9c6d216STony Luck .priority = MCE_PRIO_EARLY, 56721afaf18SBorislav Petkov }; 56821afaf18SBorislav Petkov 5698438b84aSJan H. Schönherr static int uc_decode_notifier(struct notifier_block *nb, unsigned long val, 57021afaf18SBorislav Petkov void *data) 57121afaf18SBorislav Petkov { 57221afaf18SBorislav Petkov struct mce *mce = (struct mce *)data; 57321afaf18SBorislav Petkov unsigned long pfn; 57421afaf18SBorislav Petkov 5758438b84aSJan H. Schönherr if (!mce || !mce_usable_address(mce)) 57621afaf18SBorislav Petkov return NOTIFY_DONE; 57721afaf18SBorislav Petkov 5788438b84aSJan H. Schönherr if (mce->severity != MCE_AO_SEVERITY && 5798438b84aSJan H. Schönherr mce->severity != MCE_DEFERRED_SEVERITY) 5808438b84aSJan H. Schönherr return NOTIFY_DONE; 5818438b84aSJan H. Schönherr 58221afaf18SBorislav Petkov pfn = mce->addr >> PAGE_SHIFT; 58323ba710aSTony Luck if (!memory_failure(pfn, 0)) { 58417fae129STony Luck set_mce_nospec(pfn, whole_page(mce)); 58523ba710aSTony Luck mce->kflags |= MCE_HANDLED_UC; 58623ba710aSTony Luck } 58721afaf18SBorislav Petkov 58821afaf18SBorislav Petkov return NOTIFY_OK; 58921afaf18SBorislav Petkov } 5908438b84aSJan H. Schönherr 5918438b84aSJan H. Schönherr static struct notifier_block mce_uc_nb = { 5928438b84aSJan H. Schönherr .notifier_call = uc_decode_notifier, 5938438b84aSJan H. Schönherr .priority = MCE_PRIO_UC, 59421afaf18SBorislav Petkov }; 59521afaf18SBorislav Petkov 59621afaf18SBorislav Petkov static int mce_default_notifier(struct notifier_block *nb, unsigned long val, 59721afaf18SBorislav Petkov void *data) 59821afaf18SBorislav Petkov { 59921afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 60021afaf18SBorislav Petkov 60121afaf18SBorislav Petkov if (!m) 60221afaf18SBorislav Petkov return NOTIFY_DONE; 60321afaf18SBorislav Petkov 60443505646STony Luck if (mca_cfg.print_all || !m->kflags) 60521afaf18SBorislav Petkov __print_mce(m); 60621afaf18SBorislav Petkov 60721afaf18SBorislav Petkov return NOTIFY_DONE; 60821afaf18SBorislav Petkov } 60921afaf18SBorislav Petkov 61021afaf18SBorislav Petkov static struct notifier_block mce_default_nb = { 61121afaf18SBorislav Petkov .notifier_call = mce_default_notifier, 61221afaf18SBorislav Petkov /* lowest prio, we want it to run last. */ 61321afaf18SBorislav Petkov .priority = MCE_PRIO_LOWEST, 61421afaf18SBorislav Petkov }; 61521afaf18SBorislav Petkov 61621afaf18SBorislav Petkov /* 61721afaf18SBorislav Petkov * Read ADDR and MISC registers. 61821afaf18SBorislav Petkov */ 61921afaf18SBorislav Petkov static void mce_read_aux(struct mce *m, int i) 62021afaf18SBorislav Petkov { 62121afaf18SBorislav Petkov if (m->status & MCI_STATUS_MISCV) 62221afaf18SBorislav Petkov m->misc = mce_rdmsrl(msr_ops.misc(i)); 62321afaf18SBorislav Petkov 62421afaf18SBorislav Petkov if (m->status & MCI_STATUS_ADDRV) { 62521afaf18SBorislav Petkov m->addr = mce_rdmsrl(msr_ops.addr(i)); 62621afaf18SBorislav Petkov 62721afaf18SBorislav Petkov /* 62821afaf18SBorislav Petkov * Mask the reported address by the reported granularity. 62921afaf18SBorislav Petkov */ 63021afaf18SBorislav Petkov if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { 63121afaf18SBorislav Petkov u8 shift = MCI_MISC_ADDR_LSB(m->misc); 63221afaf18SBorislav Petkov m->addr >>= shift; 63321afaf18SBorislav Petkov m->addr <<= shift; 63421afaf18SBorislav Petkov } 63521afaf18SBorislav Petkov 63621afaf18SBorislav Petkov /* 63721afaf18SBorislav Petkov * Extract [55:<lsb>] where lsb is the least significant 63821afaf18SBorislav Petkov * *valid* bit of the address bits. 63921afaf18SBorislav Petkov */ 64021afaf18SBorislav Petkov if (mce_flags.smca) { 64121afaf18SBorislav Petkov u8 lsb = (m->addr >> 56) & 0x3f; 64221afaf18SBorislav Petkov 64321afaf18SBorislav Petkov m->addr &= GENMASK_ULL(55, lsb); 64421afaf18SBorislav Petkov } 64521afaf18SBorislav Petkov } 64621afaf18SBorislav Petkov 64721afaf18SBorislav Petkov if (mce_flags.smca) { 64821afaf18SBorislav Petkov m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); 64921afaf18SBorislav Petkov 65021afaf18SBorislav Petkov if (m->status & MCI_STATUS_SYNDV) 65121afaf18SBorislav Petkov m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); 65221afaf18SBorislav Petkov } 65321afaf18SBorislav Petkov } 65421afaf18SBorislav Petkov 65521afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_poll_count); 65621afaf18SBorislav Petkov 65721afaf18SBorislav Petkov /* 65821afaf18SBorislav Petkov * Poll for corrected events or events that happened before reset. 65921afaf18SBorislav Petkov * Those are just logged through /dev/mcelog. 66021afaf18SBorislav Petkov * 66121afaf18SBorislav Petkov * This is executed in standard interrupt context. 66221afaf18SBorislav Petkov * 66321afaf18SBorislav Petkov * Note: spec recommends to panic for fatal unsignalled 66421afaf18SBorislav Petkov * errors here. However this would be quite problematic -- 66521afaf18SBorislav Petkov * we would need to reimplement the Monarch handling and 66621afaf18SBorislav Petkov * it would mess up the exclusion between exception handler 667312a4661SLinus Torvalds * and poll handler -- * so we skip this for now. 66821afaf18SBorislav Petkov * These cases should not happen anyways, or only when the CPU 66921afaf18SBorislav Petkov * is already totally * confused. In this case it's likely it will 67021afaf18SBorislav Petkov * not fully execute the machine check handler either. 67121afaf18SBorislav Petkov */ 67221afaf18SBorislav Petkov bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) 67321afaf18SBorislav Petkov { 674b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 67521afaf18SBorislav Petkov bool error_seen = false; 67621afaf18SBorislav Petkov struct mce m; 67721afaf18SBorislav Petkov int i; 67821afaf18SBorislav Petkov 67921afaf18SBorislav Petkov this_cpu_inc(mce_poll_count); 68021afaf18SBorislav Petkov 68121afaf18SBorislav Petkov mce_gather_info(&m, NULL); 68221afaf18SBorislav Petkov 68321afaf18SBorislav Petkov if (flags & MCP_TIMESTAMP) 68421afaf18SBorislav Petkov m.tsc = rdtsc(); 68521afaf18SBorislav Petkov 686c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 68721afaf18SBorislav Petkov if (!mce_banks[i].ctl || !test_bit(i, *b)) 68821afaf18SBorislav Petkov continue; 68921afaf18SBorislav Petkov 69021afaf18SBorislav Petkov m.misc = 0; 69121afaf18SBorislav Petkov m.addr = 0; 69221afaf18SBorislav Petkov m.bank = i; 69321afaf18SBorislav Petkov 69421afaf18SBorislav Petkov barrier(); 69521afaf18SBorislav Petkov m.status = mce_rdmsrl(msr_ops.status(i)); 696f19501aaSTony Luck 697f19501aaSTony Luck /* If this entry is not valid, ignore it */ 69821afaf18SBorislav Petkov if (!(m.status & MCI_STATUS_VAL)) 69921afaf18SBorislav Petkov continue; 70021afaf18SBorislav Petkov 70121afaf18SBorislav Petkov /* 702f19501aaSTony Luck * If we are logging everything (at CPU online) or this 703f19501aaSTony Luck * is a corrected error, then we must log it. 70421afaf18SBorislav Petkov */ 705f19501aaSTony Luck if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC)) 706f19501aaSTony Luck goto log_it; 707f19501aaSTony Luck 708f19501aaSTony Luck /* 709f19501aaSTony Luck * Newer Intel systems that support software error 710f19501aaSTony Luck * recovery need to make additional checks. Other 711f19501aaSTony Luck * CPUs should skip over uncorrected errors, but log 712f19501aaSTony Luck * everything else. 713f19501aaSTony Luck */ 714f19501aaSTony Luck if (!mca_cfg.ser) { 715f19501aaSTony Luck if (m.status & MCI_STATUS_UC) 716f19501aaSTony Luck continue; 717f19501aaSTony Luck goto log_it; 718f19501aaSTony Luck } 719f19501aaSTony Luck 720f19501aaSTony Luck /* Log "not enabled" (speculative) errors */ 721f19501aaSTony Luck if (!(m.status & MCI_STATUS_EN)) 722f19501aaSTony Luck goto log_it; 723f19501aaSTony Luck 724f19501aaSTony Luck /* 725f19501aaSTony Luck * Log UCNA (SDM: 15.6.3 "UCR Error Classification") 726f19501aaSTony Luck * UC == 1 && PCC == 0 && S == 0 727f19501aaSTony Luck */ 728f19501aaSTony Luck if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S)) 729f19501aaSTony Luck goto log_it; 730f19501aaSTony Luck 731f19501aaSTony Luck /* 732f19501aaSTony Luck * Skip anything else. Presumption is that our read of this 733f19501aaSTony Luck * bank is racing with a machine check. Leave the log alone 734f19501aaSTony Luck * for do_machine_check() to deal with it. 735f19501aaSTony Luck */ 73621afaf18SBorislav Petkov continue; 73721afaf18SBorislav Petkov 738f19501aaSTony Luck log_it: 73921afaf18SBorislav Petkov error_seen = true; 74021afaf18SBorislav Petkov 74190454e49SJan H. Schönherr if (flags & MCP_DONTLOG) 74290454e49SJan H. Schönherr goto clear_it; 74390454e49SJan H. Schönherr 74421afaf18SBorislav Petkov mce_read_aux(&m, i); 74521afaf18SBorislav Petkov m.severity = mce_severity(&m, mca_cfg.tolerant, NULL, false); 74621afaf18SBorislav Petkov /* 74721afaf18SBorislav Petkov * Don't get the IP here because it's unlikely to 74821afaf18SBorislav Petkov * have anything to do with the actual error location. 74921afaf18SBorislav Petkov */ 75021afaf18SBorislav Petkov 75190454e49SJan H. Schönherr if (mca_cfg.dont_log_ce && !mce_usable_address(&m)) 75290454e49SJan H. Schönherr goto clear_it; 75390454e49SJan H. Schönherr 75490454e49SJan H. Schönherr mce_log(&m); 75590454e49SJan H. Schönherr 75690454e49SJan H. Schönherr clear_it: 75721afaf18SBorislav Petkov /* 75821afaf18SBorislav Petkov * Clear state for this bank. 75921afaf18SBorislav Petkov */ 76021afaf18SBorislav Petkov mce_wrmsrl(msr_ops.status(i), 0); 76121afaf18SBorislav Petkov } 76221afaf18SBorislav Petkov 76321afaf18SBorislav Petkov /* 76421afaf18SBorislav Petkov * Don't clear MCG_STATUS here because it's only defined for 76521afaf18SBorislav Petkov * exceptions. 76621afaf18SBorislav Petkov */ 76721afaf18SBorislav Petkov 76821afaf18SBorislav Petkov sync_core(); 76921afaf18SBorislav Petkov 77021afaf18SBorislav Petkov return error_seen; 77121afaf18SBorislav Petkov } 77221afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(machine_check_poll); 77321afaf18SBorislav Petkov 77421afaf18SBorislav Petkov /* 77521afaf18SBorislav Petkov * Do a quick check if any of the events requires a panic. 77621afaf18SBorislav Petkov * This decides if we keep the events around or clear them. 77721afaf18SBorislav Petkov */ 77821afaf18SBorislav Petkov static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, 77921afaf18SBorislav Petkov struct pt_regs *regs) 78021afaf18SBorislav Petkov { 7817a8bc2b0SJan H. Schönherr char *tmp = *msg; 78221afaf18SBorislav Petkov int i; 78321afaf18SBorislav Petkov 784c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 78521afaf18SBorislav Petkov m->status = mce_rdmsrl(msr_ops.status(i)); 78621afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 78721afaf18SBorislav Petkov continue; 78821afaf18SBorislav Petkov 78921afaf18SBorislav Petkov __set_bit(i, validp); 79021afaf18SBorislav Petkov if (quirk_no_way_out) 79121afaf18SBorislav Petkov quirk_no_way_out(i, m, regs); 79221afaf18SBorislav Petkov 793d28af26fSTony Luck m->bank = i; 794a3a57ddaSJan H. Schönherr if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) { 79521afaf18SBorislav Petkov mce_read_aux(m, i); 79621afaf18SBorislav Petkov *msg = tmp; 79721afaf18SBorislav Petkov return 1; 79821afaf18SBorislav Petkov } 79921afaf18SBorislav Petkov } 80021afaf18SBorislav Petkov return 0; 80121afaf18SBorislav Petkov } 80221afaf18SBorislav Petkov 80321afaf18SBorislav Petkov /* 80421afaf18SBorislav Petkov * Variable to establish order between CPUs while scanning. 80521afaf18SBorislav Petkov * Each CPU spins initially until executing is equal its number. 80621afaf18SBorislav Petkov */ 80721afaf18SBorislav Petkov static atomic_t mce_executing; 80821afaf18SBorislav Petkov 80921afaf18SBorislav Petkov /* 81021afaf18SBorislav Petkov * Defines order of CPUs on entry. First CPU becomes Monarch. 81121afaf18SBorislav Petkov */ 81221afaf18SBorislav Petkov static atomic_t mce_callin; 81321afaf18SBorislav Petkov 81421afaf18SBorislav Petkov /* 81521afaf18SBorislav Petkov * Check if a timeout waiting for other CPUs happened. 81621afaf18SBorislav Petkov */ 81721afaf18SBorislav Petkov static int mce_timed_out(u64 *t, const char *msg) 81821afaf18SBorislav Petkov { 81921afaf18SBorislav Petkov /* 82021afaf18SBorislav Petkov * The others already did panic for some reason. 82121afaf18SBorislav Petkov * Bail out like in a timeout. 82221afaf18SBorislav Petkov * rmb() to tell the compiler that system_state 82321afaf18SBorislav Petkov * might have been modified by someone else. 82421afaf18SBorislav Petkov */ 82521afaf18SBorislav Petkov rmb(); 82621afaf18SBorislav Petkov if (atomic_read(&mce_panicked)) 82721afaf18SBorislav Petkov wait_for_panic(); 82821afaf18SBorislav Petkov if (!mca_cfg.monarch_timeout) 82921afaf18SBorislav Petkov goto out; 83021afaf18SBorislav Petkov if ((s64)*t < SPINUNIT) { 83121afaf18SBorislav Petkov if (mca_cfg.tolerant <= 1) 83221afaf18SBorislav Petkov mce_panic(msg, NULL, NULL); 83321afaf18SBorislav Petkov cpu_missing = 1; 83421afaf18SBorislav Petkov return 1; 83521afaf18SBorislav Petkov } 83621afaf18SBorislav Petkov *t -= SPINUNIT; 83721afaf18SBorislav Petkov out: 83821afaf18SBorislav Petkov touch_nmi_watchdog(); 83921afaf18SBorislav Petkov return 0; 84021afaf18SBorislav Petkov } 84121afaf18SBorislav Petkov 84221afaf18SBorislav Petkov /* 84321afaf18SBorislav Petkov * The Monarch's reign. The Monarch is the CPU who entered 84421afaf18SBorislav Petkov * the machine check handler first. It waits for the others to 84521afaf18SBorislav Petkov * raise the exception too and then grades them. When any 84621afaf18SBorislav Petkov * error is fatal panic. Only then let the others continue. 84721afaf18SBorislav Petkov * 84821afaf18SBorislav Petkov * The other CPUs entering the MCE handler will be controlled by the 84921afaf18SBorislav Petkov * Monarch. They are called Subjects. 85021afaf18SBorislav Petkov * 85121afaf18SBorislav Petkov * This way we prevent any potential data corruption in a unrecoverable case 85221afaf18SBorislav Petkov * and also makes sure always all CPU's errors are examined. 85321afaf18SBorislav Petkov * 85421afaf18SBorislav Petkov * Also this detects the case of a machine check event coming from outer 85521afaf18SBorislav Petkov * space (not detected by any CPUs) In this case some external agent wants 85621afaf18SBorislav Petkov * us to shut down, so panic too. 85721afaf18SBorislav Petkov * 85821afaf18SBorislav Petkov * The other CPUs might still decide to panic if the handler happens 85921afaf18SBorislav Petkov * in a unrecoverable place, but in this case the system is in a semi-stable 86021afaf18SBorislav Petkov * state and won't corrupt anything by itself. It's ok to let the others 86121afaf18SBorislav Petkov * continue for a bit first. 86221afaf18SBorislav Petkov * 86321afaf18SBorislav Petkov * All the spin loops have timeouts; when a timeout happens a CPU 86421afaf18SBorislav Petkov * typically elects itself to be Monarch. 86521afaf18SBorislav Petkov */ 86621afaf18SBorislav Petkov static void mce_reign(void) 86721afaf18SBorislav Petkov { 86821afaf18SBorislav Petkov int cpu; 86921afaf18SBorislav Petkov struct mce *m = NULL; 87021afaf18SBorislav Petkov int global_worst = 0; 87121afaf18SBorislav Petkov char *msg = NULL; 87221afaf18SBorislav Petkov char *nmsg = NULL; 87321afaf18SBorislav Petkov 87421afaf18SBorislav Petkov /* 87521afaf18SBorislav Petkov * This CPU is the Monarch and the other CPUs have run 87621afaf18SBorislav Petkov * through their handlers. 87721afaf18SBorislav Petkov * Grade the severity of the errors of all the CPUs. 87821afaf18SBorislav Petkov */ 87921afaf18SBorislav Petkov for_each_possible_cpu(cpu) { 88021afaf18SBorislav Petkov int severity = mce_severity(&per_cpu(mces_seen, cpu), 88121afaf18SBorislav Petkov mca_cfg.tolerant, 88221afaf18SBorislav Petkov &nmsg, true); 88321afaf18SBorislav Petkov if (severity > global_worst) { 88421afaf18SBorislav Petkov msg = nmsg; 88521afaf18SBorislav Petkov global_worst = severity; 88621afaf18SBorislav Petkov m = &per_cpu(mces_seen, cpu); 88721afaf18SBorislav Petkov } 88821afaf18SBorislav Petkov } 88921afaf18SBorislav Petkov 89021afaf18SBorislav Petkov /* 89121afaf18SBorislav Petkov * Cannot recover? Panic here then. 89221afaf18SBorislav Petkov * This dumps all the mces in the log buffer and stops the 89321afaf18SBorislav Petkov * other CPUs. 89421afaf18SBorislav Petkov */ 89521afaf18SBorislav Petkov if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) 89621afaf18SBorislav Petkov mce_panic("Fatal machine check", m, msg); 89721afaf18SBorislav Petkov 89821afaf18SBorislav Petkov /* 89921afaf18SBorislav Petkov * For UC somewhere we let the CPU who detects it handle it. 90021afaf18SBorislav Petkov * Also must let continue the others, otherwise the handling 90121afaf18SBorislav Petkov * CPU could deadlock on a lock. 90221afaf18SBorislav Petkov */ 90321afaf18SBorislav Petkov 90421afaf18SBorislav Petkov /* 90521afaf18SBorislav Petkov * No machine check event found. Must be some external 90621afaf18SBorislav Petkov * source or one CPU is hung. Panic. 90721afaf18SBorislav Petkov */ 90821afaf18SBorislav Petkov if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) 90921afaf18SBorislav Petkov mce_panic("Fatal machine check from unknown source", NULL, NULL); 91021afaf18SBorislav Petkov 91121afaf18SBorislav Petkov /* 91221afaf18SBorislav Petkov * Now clear all the mces_seen so that they don't reappear on 91321afaf18SBorislav Petkov * the next mce. 91421afaf18SBorislav Petkov */ 91521afaf18SBorislav Petkov for_each_possible_cpu(cpu) 91621afaf18SBorislav Petkov memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); 91721afaf18SBorislav Petkov } 91821afaf18SBorislav Petkov 91921afaf18SBorislav Petkov static atomic_t global_nwo; 92021afaf18SBorislav Petkov 92121afaf18SBorislav Petkov /* 92221afaf18SBorislav Petkov * Start of Monarch synchronization. This waits until all CPUs have 92321afaf18SBorislav Petkov * entered the exception handler and then determines if any of them 92421afaf18SBorislav Petkov * saw a fatal event that requires panic. Then it executes them 92521afaf18SBorislav Petkov * in the entry order. 92621afaf18SBorislav Petkov * TBD double check parallel CPU hotunplug 92721afaf18SBorislav Petkov */ 92821afaf18SBorislav Petkov static int mce_start(int *no_way_out) 92921afaf18SBorislav Petkov { 93021afaf18SBorislav Petkov int order; 93121afaf18SBorislav Petkov int cpus = num_online_cpus(); 93221afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 93321afaf18SBorislav Petkov 93421afaf18SBorislav Petkov if (!timeout) 93521afaf18SBorislav Petkov return -1; 93621afaf18SBorislav Petkov 93721afaf18SBorislav Petkov atomic_add(*no_way_out, &global_nwo); 93821afaf18SBorislav Petkov /* 93921afaf18SBorislav Petkov * Rely on the implied barrier below, such that global_nwo 94021afaf18SBorislav Petkov * is updated before mce_callin. 94121afaf18SBorislav Petkov */ 94221afaf18SBorislav Petkov order = atomic_inc_return(&mce_callin); 94321afaf18SBorislav Petkov 94421afaf18SBorislav Petkov /* 94521afaf18SBorislav Petkov * Wait for everyone. 94621afaf18SBorislav Petkov */ 94721afaf18SBorislav Petkov while (atomic_read(&mce_callin) != cpus) { 94821afaf18SBorislav Petkov if (mce_timed_out(&timeout, 94921afaf18SBorislav Petkov "Timeout: Not all CPUs entered broadcast exception handler")) { 95021afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 95121afaf18SBorislav Petkov return -1; 95221afaf18SBorislav Petkov } 95321afaf18SBorislav Petkov ndelay(SPINUNIT); 95421afaf18SBorislav Petkov } 95521afaf18SBorislav Petkov 95621afaf18SBorislav Petkov /* 95721afaf18SBorislav Petkov * mce_callin should be read before global_nwo 95821afaf18SBorislav Petkov */ 95921afaf18SBorislav Petkov smp_rmb(); 96021afaf18SBorislav Petkov 96121afaf18SBorislav Petkov if (order == 1) { 96221afaf18SBorislav Petkov /* 96321afaf18SBorislav Petkov * Monarch: Starts executing now, the others wait. 96421afaf18SBorislav Petkov */ 96521afaf18SBorislav Petkov atomic_set(&mce_executing, 1); 96621afaf18SBorislav Petkov } else { 96721afaf18SBorislav Petkov /* 96821afaf18SBorislav Petkov * Subject: Now start the scanning loop one by one in 96921afaf18SBorislav Petkov * the original callin order. 97021afaf18SBorislav Petkov * This way when there are any shared banks it will be 97121afaf18SBorislav Petkov * only seen by one CPU before cleared, avoiding duplicates. 97221afaf18SBorislav Petkov */ 97321afaf18SBorislav Petkov while (atomic_read(&mce_executing) < order) { 97421afaf18SBorislav Petkov if (mce_timed_out(&timeout, 97521afaf18SBorislav Petkov "Timeout: Subject CPUs unable to finish machine check processing")) { 97621afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 97721afaf18SBorislav Petkov return -1; 97821afaf18SBorislav Petkov } 97921afaf18SBorislav Petkov ndelay(SPINUNIT); 98021afaf18SBorislav Petkov } 98121afaf18SBorislav Petkov } 98221afaf18SBorislav Petkov 98321afaf18SBorislav Petkov /* 98421afaf18SBorislav Petkov * Cache the global no_way_out state. 98521afaf18SBorislav Petkov */ 98621afaf18SBorislav Petkov *no_way_out = atomic_read(&global_nwo); 98721afaf18SBorislav Petkov 98821afaf18SBorislav Petkov return order; 98921afaf18SBorislav Petkov } 99021afaf18SBorislav Petkov 99121afaf18SBorislav Petkov /* 99221afaf18SBorislav Petkov * Synchronize between CPUs after main scanning loop. 99321afaf18SBorislav Petkov * This invokes the bulk of the Monarch processing. 99421afaf18SBorislav Petkov */ 99521afaf18SBorislav Petkov static int mce_end(int order) 99621afaf18SBorislav Petkov { 99721afaf18SBorislav Petkov int ret = -1; 99821afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 99921afaf18SBorislav Petkov 100021afaf18SBorislav Petkov if (!timeout) 100121afaf18SBorislav Petkov goto reset; 100221afaf18SBorislav Petkov if (order < 0) 100321afaf18SBorislav Petkov goto reset; 100421afaf18SBorislav Petkov 100521afaf18SBorislav Petkov /* 100621afaf18SBorislav Petkov * Allow others to run. 100721afaf18SBorislav Petkov */ 100821afaf18SBorislav Petkov atomic_inc(&mce_executing); 100921afaf18SBorislav Petkov 101021afaf18SBorislav Petkov if (order == 1) { 101121afaf18SBorislav Petkov /* CHECKME: Can this race with a parallel hotplug? */ 101221afaf18SBorislav Petkov int cpus = num_online_cpus(); 101321afaf18SBorislav Petkov 101421afaf18SBorislav Petkov /* 101521afaf18SBorislav Petkov * Monarch: Wait for everyone to go through their scanning 101621afaf18SBorislav Petkov * loops. 101721afaf18SBorislav Petkov */ 101821afaf18SBorislav Petkov while (atomic_read(&mce_executing) <= cpus) { 101921afaf18SBorislav Petkov if (mce_timed_out(&timeout, 102021afaf18SBorislav Petkov "Timeout: Monarch CPU unable to finish machine check processing")) 102121afaf18SBorislav Petkov goto reset; 102221afaf18SBorislav Petkov ndelay(SPINUNIT); 102321afaf18SBorislav Petkov } 102421afaf18SBorislav Petkov 102521afaf18SBorislav Petkov mce_reign(); 102621afaf18SBorislav Petkov barrier(); 102721afaf18SBorislav Petkov ret = 0; 102821afaf18SBorislav Petkov } else { 102921afaf18SBorislav Petkov /* 103021afaf18SBorislav Petkov * Subject: Wait for Monarch to finish. 103121afaf18SBorislav Petkov */ 103221afaf18SBorislav Petkov while (atomic_read(&mce_executing) != 0) { 103321afaf18SBorislav Petkov if (mce_timed_out(&timeout, 103421afaf18SBorislav Petkov "Timeout: Monarch CPU did not finish machine check processing")) 103521afaf18SBorislav Petkov goto reset; 103621afaf18SBorislav Petkov ndelay(SPINUNIT); 103721afaf18SBorislav Petkov } 103821afaf18SBorislav Petkov 103921afaf18SBorislav Petkov /* 104021afaf18SBorislav Petkov * Don't reset anything. That's done by the Monarch. 104121afaf18SBorislav Petkov */ 104221afaf18SBorislav Petkov return 0; 104321afaf18SBorislav Petkov } 104421afaf18SBorislav Petkov 104521afaf18SBorislav Petkov /* 104621afaf18SBorislav Petkov * Reset all global state. 104721afaf18SBorislav Petkov */ 104821afaf18SBorislav Petkov reset: 104921afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 105021afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 105121afaf18SBorislav Petkov barrier(); 105221afaf18SBorislav Petkov 105321afaf18SBorislav Petkov /* 105421afaf18SBorislav Petkov * Let others run again. 105521afaf18SBorislav Petkov */ 105621afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 105721afaf18SBorislav Petkov return ret; 105821afaf18SBorislav Petkov } 105921afaf18SBorislav Petkov 106021afaf18SBorislav Petkov static void mce_clear_state(unsigned long *toclear) 106121afaf18SBorislav Petkov { 106221afaf18SBorislav Petkov int i; 106321afaf18SBorislav Petkov 1064c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 106521afaf18SBorislav Petkov if (test_bit(i, toclear)) 106621afaf18SBorislav Petkov mce_wrmsrl(msr_ops.status(i), 0); 106721afaf18SBorislav Petkov } 106821afaf18SBorislav Petkov } 106921afaf18SBorislav Petkov 107021afaf18SBorislav Petkov /* 107121afaf18SBorislav Petkov * Cases where we avoid rendezvous handler timeout: 107221afaf18SBorislav Petkov * 1) If this CPU is offline. 107321afaf18SBorislav Petkov * 107421afaf18SBorislav Petkov * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to 107521afaf18SBorislav Petkov * skip those CPUs which remain looping in the 1st kernel - see 107621afaf18SBorislav Petkov * crash_nmi_callback(). 107721afaf18SBorislav Petkov * 107821afaf18SBorislav Petkov * Note: there still is a small window between kexec-ing and the new, 107921afaf18SBorislav Petkov * kdump kernel establishing a new #MC handler where a broadcasted MCE 108021afaf18SBorislav Petkov * might not get handled properly. 108121afaf18SBorislav Petkov */ 108294a46d31SThomas Gleixner static noinstr bool mce_check_crashing_cpu(void) 108321afaf18SBorislav Petkov { 108494a46d31SThomas Gleixner unsigned int cpu = smp_processor_id(); 108594a46d31SThomas Gleixner 108614d3b376SPeter Zijlstra if (arch_cpu_is_offline(cpu) || 108721afaf18SBorislav Petkov (crashing_cpu != -1 && crashing_cpu != cpu)) { 108821afaf18SBorislav Petkov u64 mcgstatus; 108921afaf18SBorislav Petkov 1090aedbdeabSThomas Gleixner mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS); 109170f0c230STony W Wang-oc 109270f0c230STony W Wang-oc if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { 109370f0c230STony W Wang-oc if (mcgstatus & MCG_STATUS_LMCES) 109470f0c230STony W Wang-oc return false; 109570f0c230STony W Wang-oc } 109670f0c230STony W Wang-oc 109721afaf18SBorislav Petkov if (mcgstatus & MCG_STATUS_RIPV) { 1098aedbdeabSThomas Gleixner __wrmsr(MSR_IA32_MCG_STATUS, 0, 0); 109921afaf18SBorislav Petkov return true; 110021afaf18SBorislav Petkov } 110121afaf18SBorislav Petkov } 110221afaf18SBorislav Petkov return false; 110321afaf18SBorislav Petkov } 110421afaf18SBorislav Petkov 110521afaf18SBorislav Petkov static void __mc_scan_banks(struct mce *m, struct mce *final, 110621afaf18SBorislav Petkov unsigned long *toclear, unsigned long *valid_banks, 110721afaf18SBorislav Petkov int no_way_out, int *worst) 110821afaf18SBorislav Petkov { 1109b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 111021afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 111121afaf18SBorislav Petkov int severity, i; 111221afaf18SBorislav Petkov 1113c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 111421afaf18SBorislav Petkov __clear_bit(i, toclear); 111521afaf18SBorislav Petkov if (!test_bit(i, valid_banks)) 111621afaf18SBorislav Petkov continue; 111721afaf18SBorislav Petkov 111821afaf18SBorislav Petkov if (!mce_banks[i].ctl) 111921afaf18SBorislav Petkov continue; 112021afaf18SBorislav Petkov 112121afaf18SBorislav Petkov m->misc = 0; 112221afaf18SBorislav Petkov m->addr = 0; 112321afaf18SBorislav Petkov m->bank = i; 112421afaf18SBorislav Petkov 112521afaf18SBorislav Petkov m->status = mce_rdmsrl(msr_ops.status(i)); 112621afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 112721afaf18SBorislav Petkov continue; 112821afaf18SBorislav Petkov 112921afaf18SBorislav Petkov /* 113021afaf18SBorislav Petkov * Corrected or non-signaled errors are handled by 113121afaf18SBorislav Petkov * machine_check_poll(). Leave them alone, unless this panics. 113221afaf18SBorislav Petkov */ 113321afaf18SBorislav Petkov if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && 113421afaf18SBorislav Petkov !no_way_out) 113521afaf18SBorislav Petkov continue; 113621afaf18SBorislav Petkov 113721afaf18SBorislav Petkov /* Set taint even when machine check was not enabled. */ 113821afaf18SBorislav Petkov add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 113921afaf18SBorislav Petkov 114021afaf18SBorislav Petkov severity = mce_severity(m, cfg->tolerant, NULL, true); 114121afaf18SBorislav Petkov 114221afaf18SBorislav Petkov /* 114321afaf18SBorislav Petkov * When machine check was for corrected/deferred handler don't 114421afaf18SBorislav Petkov * touch, unless we're panicking. 114521afaf18SBorislav Petkov */ 114621afaf18SBorislav Petkov if ((severity == MCE_KEEP_SEVERITY || 114721afaf18SBorislav Petkov severity == MCE_UCNA_SEVERITY) && !no_way_out) 114821afaf18SBorislav Petkov continue; 114921afaf18SBorislav Petkov 115021afaf18SBorislav Petkov __set_bit(i, toclear); 115121afaf18SBorislav Petkov 115221afaf18SBorislav Petkov /* Machine check event was not enabled. Clear, but ignore. */ 115321afaf18SBorislav Petkov if (severity == MCE_NO_SEVERITY) 115421afaf18SBorislav Petkov continue; 115521afaf18SBorislav Petkov 115621afaf18SBorislav Petkov mce_read_aux(m, i); 115721afaf18SBorislav Petkov 115821afaf18SBorislav Petkov /* assuming valid severity level != 0 */ 115921afaf18SBorislav Petkov m->severity = severity; 116021afaf18SBorislav Petkov 116121afaf18SBorislav Petkov mce_log(m); 116221afaf18SBorislav Petkov 116321afaf18SBorislav Petkov if (severity > *worst) { 116421afaf18SBorislav Petkov *final = *m; 116521afaf18SBorislav Petkov *worst = severity; 116621afaf18SBorislav Petkov } 116721afaf18SBorislav Petkov } 116821afaf18SBorislav Petkov 116921afaf18SBorislav Petkov /* mce_clear_state will clear *final, save locally for use later */ 117021afaf18SBorislav Petkov *m = *final; 117121afaf18SBorislav Petkov } 117221afaf18SBorislav Petkov 11735567d11cSPeter Zijlstra static void kill_me_now(struct callback_head *ch) 11745567d11cSPeter Zijlstra { 11755567d11cSPeter Zijlstra force_sig(SIGBUS); 11765567d11cSPeter Zijlstra } 11775567d11cSPeter Zijlstra 11785567d11cSPeter Zijlstra static void kill_me_maybe(struct callback_head *cb) 11795567d11cSPeter Zijlstra { 11805567d11cSPeter Zijlstra struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me); 11815567d11cSPeter Zijlstra int flags = MF_ACTION_REQUIRED; 11825567d11cSPeter Zijlstra 11835567d11cSPeter Zijlstra pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr); 118417fae129STony Luck 118517fae129STony Luck if (!p->mce_ripv) 11865567d11cSPeter Zijlstra flags |= MF_MUST_KILL; 11875567d11cSPeter Zijlstra 11885567d11cSPeter Zijlstra if (!memory_failure(p->mce_addr >> PAGE_SHIFT, flags)) { 118917fae129STony Luck set_mce_nospec(p->mce_addr >> PAGE_SHIFT, p->mce_whole_page); 11905567d11cSPeter Zijlstra return; 11915567d11cSPeter Zijlstra } 11925567d11cSPeter Zijlstra 11935567d11cSPeter Zijlstra pr_err("Memory error not recovered"); 11945567d11cSPeter Zijlstra kill_me_now(cb); 11955567d11cSPeter Zijlstra } 11965567d11cSPeter Zijlstra 119721afaf18SBorislav Petkov /* 119821afaf18SBorislav Petkov * The actual machine check handler. This only handles real 119921afaf18SBorislav Petkov * exceptions when something got corrupted coming in through int 18. 120021afaf18SBorislav Petkov * 120121afaf18SBorislav Petkov * This is executed in NMI context not subject to normal locking rules. This 120221afaf18SBorislav Petkov * implies that most kernel services cannot be safely used. Don't even 120321afaf18SBorislav Petkov * think about putting a printk in there! 120421afaf18SBorislav Petkov * 120521afaf18SBorislav Petkov * On Intel systems this is entered on all CPUs in parallel through 120621afaf18SBorislav Petkov * MCE broadcast. However some CPUs might be broken beyond repair, 120721afaf18SBorislav Petkov * so be always careful when synchronizing with others. 120855ba18d6SAndy Lutomirski * 120955ba18d6SAndy Lutomirski * Tracing and kprobes are disabled: if we interrupted a kernel context 121055ba18d6SAndy Lutomirski * with IF=1, we need to minimize stack usage. There are also recursion 121155ba18d6SAndy Lutomirski * issues: if the machine check was due to a failure of the memory 121255ba18d6SAndy Lutomirski * backing the user stack, tracing that reads the user stack will cause 121355ba18d6SAndy Lutomirski * potentially infinite recursion. 121421afaf18SBorislav Petkov */ 12157f6fa101SIra Weiny noinstr void do_machine_check(struct pt_regs *regs) 121621afaf18SBorislav Petkov { 121721afaf18SBorislav Petkov DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); 121821afaf18SBorislav Petkov DECLARE_BITMAP(toclear, MAX_NR_BANKS); 121921afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 122021afaf18SBorislav Petkov struct mce m, *final; 12217a8bc2b0SJan H. Schönherr char *msg = NULL; 122221afaf18SBorislav Petkov int worst = 0; 122321afaf18SBorislav Petkov 122421afaf18SBorislav Petkov /* 122521afaf18SBorislav Petkov * Establish sequential order between the CPUs entering the machine 122621afaf18SBorislav Petkov * check handler. 122721afaf18SBorislav Petkov */ 122821afaf18SBorislav Petkov int order = -1; 122921afaf18SBorislav Petkov 123021afaf18SBorislav Petkov /* 123121afaf18SBorislav Petkov * If no_way_out gets set, there is no safe way to recover from this 123221afaf18SBorislav Petkov * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. 123321afaf18SBorislav Petkov */ 123421afaf18SBorislav Petkov int no_way_out = 0; 123521afaf18SBorislav Petkov 123621afaf18SBorislav Petkov /* 123721afaf18SBorislav Petkov * If kill_it gets set, there might be a way to recover from this 123821afaf18SBorislav Petkov * error. 123921afaf18SBorislav Petkov */ 124021afaf18SBorislav Petkov int kill_it = 0; 124121afaf18SBorislav Petkov 124221afaf18SBorislav Petkov /* 124321afaf18SBorislav Petkov * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES 124421afaf18SBorislav Petkov * on Intel. 124521afaf18SBorislav Petkov */ 124621afaf18SBorislav Petkov int lmce = 1; 124721afaf18SBorislav Petkov 124821afaf18SBorislav Petkov this_cpu_inc(mce_exception_count); 124921afaf18SBorislav Petkov 125021afaf18SBorislav Petkov mce_gather_info(&m, regs); 125121afaf18SBorislav Petkov m.tsc = rdtsc(); 125221afaf18SBorislav Petkov 125321afaf18SBorislav Petkov final = this_cpu_ptr(&mces_seen); 125421afaf18SBorislav Petkov *final = m; 125521afaf18SBorislav Petkov 125621afaf18SBorislav Petkov memset(valid_banks, 0, sizeof(valid_banks)); 125721afaf18SBorislav Petkov no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); 125821afaf18SBorislav Petkov 125921afaf18SBorislav Petkov barrier(); 126021afaf18SBorislav Petkov 126121afaf18SBorislav Petkov /* 126221afaf18SBorislav Petkov * When no restart IP might need to kill or panic. 126321afaf18SBorislav Petkov * Assume the worst for now, but if we find the 126421afaf18SBorislav Petkov * severity is MCE_AR_SEVERITY we have other options. 126521afaf18SBorislav Petkov */ 126621afaf18SBorislav Petkov if (!(m.mcgstatus & MCG_STATUS_RIPV)) 126721afaf18SBorislav Petkov kill_it = 1; 126821afaf18SBorislav Petkov 126921afaf18SBorislav Petkov /* 127021afaf18SBorislav Petkov * Check if this MCE is signaled to only this logical processor, 127170f0c230STony W Wang-oc * on Intel, Zhaoxin only. 127221afaf18SBorislav Petkov */ 127370f0c230STony W Wang-oc if (m.cpuvendor == X86_VENDOR_INTEL || 127470f0c230STony W Wang-oc m.cpuvendor == X86_VENDOR_ZHAOXIN) 127521afaf18SBorislav Petkov lmce = m.mcgstatus & MCG_STATUS_LMCES; 127621afaf18SBorislav Petkov 127721afaf18SBorislav Petkov /* 127821afaf18SBorislav Petkov * Local machine check may already know that we have to panic. 127921afaf18SBorislav Petkov * Broadcast machine check begins rendezvous in mce_start() 128021afaf18SBorislav Petkov * Go through all banks in exclusion of the other CPUs. This way we 128121afaf18SBorislav Petkov * don't report duplicated events on shared banks because the first one 128221afaf18SBorislav Petkov * to see it will clear it. 128321afaf18SBorislav Petkov */ 128421afaf18SBorislav Petkov if (lmce) { 128521afaf18SBorislav Petkov if (no_way_out) 128621afaf18SBorislav Petkov mce_panic("Fatal local machine check", &m, msg); 128721afaf18SBorislav Petkov } else { 128821afaf18SBorislav Petkov order = mce_start(&no_way_out); 128921afaf18SBorislav Petkov } 129021afaf18SBorislav Petkov 129121afaf18SBorislav Petkov __mc_scan_banks(&m, final, toclear, valid_banks, no_way_out, &worst); 129221afaf18SBorislav Petkov 129321afaf18SBorislav Petkov if (!no_way_out) 129421afaf18SBorislav Petkov mce_clear_state(toclear); 129521afaf18SBorislav Petkov 129621afaf18SBorislav Petkov /* 129721afaf18SBorislav Petkov * Do most of the synchronization with other CPUs. 129821afaf18SBorislav Petkov * When there's any problem use only local no_way_out state. 129921afaf18SBorislav Petkov */ 130021afaf18SBorislav Petkov if (!lmce) { 130121afaf18SBorislav Petkov if (mce_end(order) < 0) 130221afaf18SBorislav Petkov no_way_out = worst >= MCE_PANIC_SEVERITY; 130321afaf18SBorislav Petkov } else { 130421afaf18SBorislav Petkov /* 130521afaf18SBorislav Petkov * If there was a fatal machine check we should have 130621afaf18SBorislav Petkov * already called mce_panic earlier in this function. 130721afaf18SBorislav Petkov * Since we re-read the banks, we might have found 130821afaf18SBorislav Petkov * something new. Check again to see if we found a 130921afaf18SBorislav Petkov * fatal error. We call "mce_severity()" again to 131021afaf18SBorislav Petkov * make sure we have the right "msg". 131121afaf18SBorislav Petkov */ 131221afaf18SBorislav Petkov if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) { 131321afaf18SBorislav Petkov mce_severity(&m, cfg->tolerant, &msg, true); 131421afaf18SBorislav Petkov mce_panic("Local fatal machine check!", &m, msg); 131521afaf18SBorislav Petkov } 131621afaf18SBorislav Petkov } 131721afaf18SBorislav Petkov 131821afaf18SBorislav Petkov /* 131921afaf18SBorislav Petkov * If tolerant is at an insane level we drop requests to kill 132021afaf18SBorislav Petkov * processes and continue even when there is no way out. 132121afaf18SBorislav Petkov */ 132221afaf18SBorislav Petkov if (cfg->tolerant == 3) 132321afaf18SBorislav Petkov kill_it = 0; 132421afaf18SBorislav Petkov else if (no_way_out) 132521afaf18SBorislav Petkov mce_panic("Fatal machine check on current CPU", &m, msg); 132621afaf18SBorislav Petkov 132721afaf18SBorislav Petkov if (worst > 0) 132839f0584eSBorislav Petkov irq_work_queue(&mce_irq_work); 132939f0584eSBorislav Petkov 133021afaf18SBorislav Petkov mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); 133121afaf18SBorislav Petkov 133221afaf18SBorislav Petkov sync_core(); 133321afaf18SBorislav Petkov 133421afaf18SBorislav Petkov if (worst != MCE_AR_SEVERITY && !kill_it) 133594a46d31SThomas Gleixner return; 133621afaf18SBorislav Petkov 133721afaf18SBorislav Petkov /* Fault was in user mode and we need to take some action */ 133821afaf18SBorislav Petkov if ((m.cs & 3) == 3) { 1339b052df3dSThomas Gleixner /* If this triggers there is no way to recover. Die hard. */ 1340b052df3dSThomas Gleixner BUG_ON(!on_thread_stack() || !user_mode(regs)); 134121afaf18SBorislav Petkov 13425567d11cSPeter Zijlstra current->mce_addr = m.addr; 134317fae129STony Luck current->mce_ripv = !!(m.mcgstatus & MCG_STATUS_RIPV); 134417fae129STony Luck current->mce_whole_page = whole_page(&m); 13455567d11cSPeter Zijlstra current->mce_kill_me.func = kill_me_maybe; 13465567d11cSPeter Zijlstra if (kill_it) 13475567d11cSPeter Zijlstra current->mce_kill_me.func = kill_me_now; 13485567d11cSPeter Zijlstra task_work_add(current, ¤t->mce_kill_me, true); 134921afaf18SBorislav Petkov } else { 13501df73b21SBorislav Petkov /* 13511df73b21SBorislav Petkov * Handle an MCE which has happened in kernel space but from 13521df73b21SBorislav Petkov * which the kernel can recover: ex_has_fault_handler() has 13531df73b21SBorislav Petkov * already verified that the rIP at which the error happened is 13541df73b21SBorislav Petkov * a rIP from which the kernel can recover (by jumping to 13551df73b21SBorislav Petkov * recovery code specified in _ASM_EXTABLE_FAULT()) and the 13561df73b21SBorislav Petkov * corresponding exception handler which would do that is the 13571df73b21SBorislav Petkov * proper one. 13581df73b21SBorislav Petkov */ 13591df73b21SBorislav Petkov if (m.kflags & MCE_IN_KERNEL_RECOV) { 13608cd501c1SThomas Gleixner if (!fixup_exception(regs, X86_TRAP_MC, 0, 0)) 13612d806d07SJan H. Schönherr mce_panic("Failed kernel mode recovery", &m, msg); 136221afaf18SBorislav Petkov } 13631df73b21SBorislav Petkov } 136421afaf18SBorislav Petkov } 136521afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(do_machine_check); 136621afaf18SBorislav Petkov 136721afaf18SBorislav Petkov #ifndef CONFIG_MEMORY_FAILURE 136821afaf18SBorislav Petkov int memory_failure(unsigned long pfn, int flags) 136921afaf18SBorislav Petkov { 137021afaf18SBorislav Petkov /* mce_severity() should not hand us an ACTION_REQUIRED error */ 137121afaf18SBorislav Petkov BUG_ON(flags & MF_ACTION_REQUIRED); 137221afaf18SBorislav Petkov pr_err("Uncorrected memory error in page 0x%lx ignored\n" 137321afaf18SBorislav Petkov "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", 137421afaf18SBorislav Petkov pfn); 137521afaf18SBorislav Petkov 137621afaf18SBorislav Petkov return 0; 137721afaf18SBorislav Petkov } 137821afaf18SBorislav Petkov #endif 137921afaf18SBorislav Petkov 138021afaf18SBorislav Petkov /* 138121afaf18SBorislav Petkov * Periodic polling timer for "silent" machine check errors. If the 138221afaf18SBorislav Petkov * poller finds an MCE, poll 2x faster. When the poller finds no more 138321afaf18SBorislav Petkov * errors, poll 2x slower (up to check_interval seconds). 138421afaf18SBorislav Petkov */ 138521afaf18SBorislav Petkov static unsigned long check_interval = INITIAL_CHECK_INTERVAL; 138621afaf18SBorislav Petkov 138721afaf18SBorislav Petkov static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ 138821afaf18SBorislav Petkov static DEFINE_PER_CPU(struct timer_list, mce_timer); 138921afaf18SBorislav Petkov 139021afaf18SBorislav Petkov static unsigned long mce_adjust_timer_default(unsigned long interval) 139121afaf18SBorislav Petkov { 139221afaf18SBorislav Petkov return interval; 139321afaf18SBorislav Petkov } 139421afaf18SBorislav Petkov 139521afaf18SBorislav Petkov static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; 139621afaf18SBorislav Petkov 139721afaf18SBorislav Petkov static void __start_timer(struct timer_list *t, unsigned long interval) 139821afaf18SBorislav Petkov { 139921afaf18SBorislav Petkov unsigned long when = jiffies + interval; 140021afaf18SBorislav Petkov unsigned long flags; 140121afaf18SBorislav Petkov 140221afaf18SBorislav Petkov local_irq_save(flags); 140321afaf18SBorislav Petkov 140421afaf18SBorislav Petkov if (!timer_pending(t) || time_before(when, t->expires)) 140521afaf18SBorislav Petkov mod_timer(t, round_jiffies(when)); 140621afaf18SBorislav Petkov 140721afaf18SBorislav Petkov local_irq_restore(flags); 140821afaf18SBorislav Petkov } 140921afaf18SBorislav Petkov 141021afaf18SBorislav Petkov static void mce_timer_fn(struct timer_list *t) 141121afaf18SBorislav Petkov { 141221afaf18SBorislav Petkov struct timer_list *cpu_t = this_cpu_ptr(&mce_timer); 141321afaf18SBorislav Petkov unsigned long iv; 141421afaf18SBorislav Petkov 141521afaf18SBorislav Petkov WARN_ON(cpu_t != t); 141621afaf18SBorislav Petkov 141721afaf18SBorislav Petkov iv = __this_cpu_read(mce_next_interval); 141821afaf18SBorislav Petkov 141921afaf18SBorislav Petkov if (mce_available(this_cpu_ptr(&cpu_info))) { 142021afaf18SBorislav Petkov machine_check_poll(0, this_cpu_ptr(&mce_poll_banks)); 142121afaf18SBorislav Petkov 142221afaf18SBorislav Petkov if (mce_intel_cmci_poll()) { 142321afaf18SBorislav Petkov iv = mce_adjust_timer(iv); 142421afaf18SBorislav Petkov goto done; 142521afaf18SBorislav Petkov } 142621afaf18SBorislav Petkov } 142721afaf18SBorislav Petkov 142821afaf18SBorislav Petkov /* 142921afaf18SBorislav Petkov * Alert userspace if needed. If we logged an MCE, reduce the polling 143021afaf18SBorislav Petkov * interval, otherwise increase the polling interval. 143121afaf18SBorislav Petkov */ 143221afaf18SBorislav Petkov if (mce_notify_irq()) 143321afaf18SBorislav Petkov iv = max(iv / 2, (unsigned long) HZ/100); 143421afaf18SBorislav Petkov else 143521afaf18SBorislav Petkov iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); 143621afaf18SBorislav Petkov 143721afaf18SBorislav Petkov done: 143821afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, iv); 143921afaf18SBorislav Petkov __start_timer(t, iv); 144021afaf18SBorislav Petkov } 144121afaf18SBorislav Petkov 144221afaf18SBorislav Petkov /* 144321afaf18SBorislav Petkov * Ensure that the timer is firing in @interval from now. 144421afaf18SBorislav Petkov */ 144521afaf18SBorislav Petkov void mce_timer_kick(unsigned long interval) 144621afaf18SBorislav Petkov { 144721afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 144821afaf18SBorislav Petkov unsigned long iv = __this_cpu_read(mce_next_interval); 144921afaf18SBorislav Petkov 145021afaf18SBorislav Petkov __start_timer(t, interval); 145121afaf18SBorislav Petkov 145221afaf18SBorislav Petkov if (interval < iv) 145321afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, interval); 145421afaf18SBorislav Petkov } 145521afaf18SBorislav Petkov 145621afaf18SBorislav Petkov /* Must not be called in IRQ context where del_timer_sync() can deadlock */ 145721afaf18SBorislav Petkov static void mce_timer_delete_all(void) 145821afaf18SBorislav Petkov { 145921afaf18SBorislav Petkov int cpu; 146021afaf18SBorislav Petkov 146121afaf18SBorislav Petkov for_each_online_cpu(cpu) 146221afaf18SBorislav Petkov del_timer_sync(&per_cpu(mce_timer, cpu)); 146321afaf18SBorislav Petkov } 146421afaf18SBorislav Petkov 146521afaf18SBorislav Petkov /* 146621afaf18SBorislav Petkov * Notify the user(s) about new machine check events. 146721afaf18SBorislav Petkov * Can be called from interrupt context, but not from machine check/NMI 146821afaf18SBorislav Petkov * context. 146921afaf18SBorislav Petkov */ 147021afaf18SBorislav Petkov int mce_notify_irq(void) 147121afaf18SBorislav Petkov { 147221afaf18SBorislav Petkov /* Not more than two messages every minute */ 147321afaf18SBorislav Petkov static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); 147421afaf18SBorislav Petkov 147521afaf18SBorislav Petkov if (test_and_clear_bit(0, &mce_need_notify)) { 147621afaf18SBorislav Petkov mce_work_trigger(); 147721afaf18SBorislav Petkov 147821afaf18SBorislav Petkov if (__ratelimit(&ratelimit)) 147921afaf18SBorislav Petkov pr_info(HW_ERR "Machine check events logged\n"); 148021afaf18SBorislav Petkov 148121afaf18SBorislav Petkov return 1; 148221afaf18SBorislav Petkov } 148321afaf18SBorislav Petkov return 0; 148421afaf18SBorislav Petkov } 148521afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_notify_irq); 148621afaf18SBorislav Petkov 1487b4914508SYazen Ghannam static void __mcheck_cpu_mce_banks_init(void) 148821afaf18SBorislav Petkov { 1489b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1490c7d314f3SYazen Ghannam u8 n_banks = this_cpu_read(mce_num_banks); 149121afaf18SBorislav Petkov int i; 149221afaf18SBorislav Petkov 1493c7d314f3SYazen Ghannam for (i = 0; i < n_banks; i++) { 149421afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 149521afaf18SBorislav Petkov 1496068b053dSYazen Ghannam /* 1497068b053dSYazen Ghannam * Init them all, __mcheck_cpu_apply_quirks() is going to apply 1498068b053dSYazen Ghannam * the required vendor quirks before 1499068b053dSYazen Ghannam * __mcheck_cpu_init_clear_banks() does the final bank setup. 1500068b053dSYazen Ghannam */ 150121afaf18SBorislav Petkov b->ctl = -1ULL; 150221afaf18SBorislav Petkov b->init = 1; 150321afaf18SBorislav Petkov } 150421afaf18SBorislav Petkov } 150521afaf18SBorislav Petkov 150621afaf18SBorislav Petkov /* 150721afaf18SBorislav Petkov * Initialize Machine Checks for a CPU. 150821afaf18SBorislav Petkov */ 1509b4914508SYazen Ghannam static void __mcheck_cpu_cap_init(void) 151021afaf18SBorislav Petkov { 151121afaf18SBorislav Petkov u64 cap; 1512006c0770SYazen Ghannam u8 b; 151321afaf18SBorislav Petkov 151421afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 151521afaf18SBorislav Petkov 151621afaf18SBorislav Petkov b = cap & MCG_BANKCNT_MASK; 151721afaf18SBorislav Petkov 1518c7d314f3SYazen Ghannam if (b > MAX_NR_BANKS) { 1519c7d314f3SYazen Ghannam pr_warn("CPU%d: Using only %u machine check banks out of %u\n", 1520c7d314f3SYazen Ghannam smp_processor_id(), MAX_NR_BANKS, b); 1521c7d314f3SYazen Ghannam b = MAX_NR_BANKS; 1522c7d314f3SYazen Ghannam } 1523c7d314f3SYazen Ghannam 1524c7d314f3SYazen Ghannam this_cpu_write(mce_num_banks, b); 152521afaf18SBorislav Petkov 1526b4914508SYazen Ghannam __mcheck_cpu_mce_banks_init(); 152721afaf18SBorislav Petkov 152821afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 152921afaf18SBorislav Petkov if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) 153021afaf18SBorislav Petkov mca_cfg.rip_msr = MSR_IA32_MCG_EIP; 153121afaf18SBorislav Petkov 153221afaf18SBorislav Petkov if (cap & MCG_SER_P) 153321afaf18SBorislav Petkov mca_cfg.ser = 1; 153421afaf18SBorislav Petkov } 153521afaf18SBorislav Petkov 153621afaf18SBorislav Petkov static void __mcheck_cpu_init_generic(void) 153721afaf18SBorislav Petkov { 153821afaf18SBorislav Petkov enum mcp_flags m_fl = 0; 153921afaf18SBorislav Petkov mce_banks_t all_banks; 154021afaf18SBorislav Petkov u64 cap; 154121afaf18SBorislav Petkov 154221afaf18SBorislav Petkov if (!mca_cfg.bootlog) 154321afaf18SBorislav Petkov m_fl = MCP_DONTLOG; 154421afaf18SBorislav Petkov 154521afaf18SBorislav Petkov /* 154621afaf18SBorislav Petkov * Log the machine checks left over from the previous reset. 154721afaf18SBorislav Petkov */ 154821afaf18SBorislav Petkov bitmap_fill(all_banks, MAX_NR_BANKS); 154921afaf18SBorislav Petkov machine_check_poll(MCP_UC | m_fl, &all_banks); 155021afaf18SBorislav Petkov 155121afaf18SBorislav Petkov cr4_set_bits(X86_CR4_MCE); 155221afaf18SBorislav Petkov 155321afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 155421afaf18SBorislav Petkov if (cap & MCG_CTL_P) 155521afaf18SBorislav Petkov wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); 155621afaf18SBorislav Petkov } 155721afaf18SBorislav Petkov 155821afaf18SBorislav Petkov static void __mcheck_cpu_init_clear_banks(void) 155921afaf18SBorislav Petkov { 1560b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 156121afaf18SBorislav Petkov int i; 156221afaf18SBorislav Petkov 1563c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 156421afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 156521afaf18SBorislav Petkov 156621afaf18SBorislav Petkov if (!b->init) 156721afaf18SBorislav Petkov continue; 156821afaf18SBorislav Petkov wrmsrl(msr_ops.ctl(i), b->ctl); 156921afaf18SBorislav Petkov wrmsrl(msr_ops.status(i), 0); 157021afaf18SBorislav Petkov } 157121afaf18SBorislav Petkov } 157221afaf18SBorislav Petkov 157321afaf18SBorislav Petkov /* 1574068b053dSYazen Ghannam * Do a final check to see if there are any unused/RAZ banks. 1575068b053dSYazen Ghannam * 1576068b053dSYazen Ghannam * This must be done after the banks have been initialized and any quirks have 1577068b053dSYazen Ghannam * been applied. 1578068b053dSYazen Ghannam * 1579068b053dSYazen Ghannam * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs. 1580068b053dSYazen Ghannam * Otherwise, a user who disables a bank will not be able to re-enable it 1581068b053dSYazen Ghannam * without a system reboot. 1582068b053dSYazen Ghannam */ 1583068b053dSYazen Ghannam static void __mcheck_cpu_check_banks(void) 1584068b053dSYazen Ghannam { 1585068b053dSYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1586068b053dSYazen Ghannam u64 msrval; 1587068b053dSYazen Ghannam int i; 1588068b053dSYazen Ghannam 1589068b053dSYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1590068b053dSYazen Ghannam struct mce_bank *b = &mce_banks[i]; 1591068b053dSYazen Ghannam 1592068b053dSYazen Ghannam if (!b->init) 1593068b053dSYazen Ghannam continue; 1594068b053dSYazen Ghannam 1595068b053dSYazen Ghannam rdmsrl(msr_ops.ctl(i), msrval); 1596068b053dSYazen Ghannam b->init = !!msrval; 1597068b053dSYazen Ghannam } 1598068b053dSYazen Ghannam } 1599068b053dSYazen Ghannam 1600068b053dSYazen Ghannam /* 160121afaf18SBorislav Petkov * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and 160221afaf18SBorislav Petkov * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM 160321afaf18SBorislav Petkov * Vol 3B Table 15-20). But this confuses both the code that determines 160421afaf18SBorislav Petkov * whether the machine check occurred in kernel or user mode, and also 160521afaf18SBorislav Petkov * the severity assessment code. Pretend that EIPV was set, and take the 160621afaf18SBorislav Petkov * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. 160721afaf18SBorislav Petkov */ 160821afaf18SBorislav Petkov static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) 160921afaf18SBorislav Petkov { 161021afaf18SBorislav Petkov if (bank != 0) 161121afaf18SBorislav Petkov return; 161221afaf18SBorislav Petkov if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) 161321afaf18SBorislav Petkov return; 161421afaf18SBorislav Petkov if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| 161521afaf18SBorislav Petkov MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| 161621afaf18SBorislav Petkov MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| 161721afaf18SBorislav Petkov MCACOD)) != 161821afaf18SBorislav Petkov (MCI_STATUS_UC|MCI_STATUS_EN| 161921afaf18SBorislav Petkov MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| 162021afaf18SBorislav Petkov MCI_STATUS_AR|MCACOD_INSTR)) 162121afaf18SBorislav Petkov return; 162221afaf18SBorislav Petkov 162321afaf18SBorislav Petkov m->mcgstatus |= MCG_STATUS_EIPV; 162421afaf18SBorislav Petkov m->ip = regs->ip; 162521afaf18SBorislav Petkov m->cs = regs->cs; 162621afaf18SBorislav Petkov } 162721afaf18SBorislav Petkov 162821afaf18SBorislav Petkov /* Add per CPU specific workarounds here */ 162921afaf18SBorislav Petkov static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) 163021afaf18SBorislav Petkov { 1631b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 163221afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 163321afaf18SBorislav Petkov 163421afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_UNKNOWN) { 163521afaf18SBorislav Petkov pr_info("unknown CPU type - not enabling MCE support\n"); 163621afaf18SBorislav Petkov return -EOPNOTSUPP; 163721afaf18SBorislav Petkov } 163821afaf18SBorislav Petkov 163921afaf18SBorislav Petkov /* This should be disabled by the BIOS, but isn't always */ 164021afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD) { 1641c7d314f3SYazen Ghannam if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { 164221afaf18SBorislav Petkov /* 164321afaf18SBorislav Petkov * disable GART TBL walk error reporting, which 164421afaf18SBorislav Petkov * trips off incorrectly with the IOMMU & 3ware 164521afaf18SBorislav Petkov * & Cerberus: 164621afaf18SBorislav Petkov */ 164721afaf18SBorislav Petkov clear_bit(10, (unsigned long *)&mce_banks[4].ctl); 164821afaf18SBorislav Petkov } 164921afaf18SBorislav Petkov if (c->x86 < 0x11 && cfg->bootlog < 0) { 165021afaf18SBorislav Petkov /* 165121afaf18SBorislav Petkov * Lots of broken BIOS around that don't clear them 165221afaf18SBorislav Petkov * by default and leave crap in there. Don't log: 165321afaf18SBorislav Petkov */ 165421afaf18SBorislav Petkov cfg->bootlog = 0; 165521afaf18SBorislav Petkov } 165621afaf18SBorislav Petkov /* 165721afaf18SBorislav Petkov * Various K7s with broken bank 0 around. Always disable 165821afaf18SBorislav Petkov * by default. 165921afaf18SBorislav Petkov */ 1660c7d314f3SYazen Ghannam if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0) 166121afaf18SBorislav Petkov mce_banks[0].ctl = 0; 166221afaf18SBorislav Petkov 166321afaf18SBorislav Petkov /* 166421afaf18SBorislav Petkov * overflow_recov is supported for F15h Models 00h-0fh 166521afaf18SBorislav Petkov * even though we don't have a CPUID bit for it. 166621afaf18SBorislav Petkov */ 166721afaf18SBorislav Petkov if (c->x86 == 0x15 && c->x86_model <= 0xf) 166821afaf18SBorislav Petkov mce_flags.overflow_recov = 1; 166921afaf18SBorislav Petkov 167021afaf18SBorislav Petkov } 167121afaf18SBorislav Petkov 167221afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_INTEL) { 167321afaf18SBorislav Petkov /* 167421afaf18SBorislav Petkov * SDM documents that on family 6 bank 0 should not be written 167521afaf18SBorislav Petkov * because it aliases to another special BIOS controlled 167621afaf18SBorislav Petkov * register. 167721afaf18SBorislav Petkov * But it's not aliased anymore on model 0x1a+ 167821afaf18SBorislav Petkov * Don't ignore bank 0 completely because there could be a 167921afaf18SBorislav Petkov * valid event later, merely don't write CTL0. 168021afaf18SBorislav Petkov */ 168121afaf18SBorislav Petkov 1682c7d314f3SYazen Ghannam if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) 168321afaf18SBorislav Petkov mce_banks[0].init = 0; 168421afaf18SBorislav Petkov 168521afaf18SBorislav Petkov /* 168621afaf18SBorislav Petkov * All newer Intel systems support MCE broadcasting. Enable 168721afaf18SBorislav Petkov * synchronization with a one second timeout. 168821afaf18SBorislav Petkov */ 168921afaf18SBorislav Petkov if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && 169021afaf18SBorislav Petkov cfg->monarch_timeout < 0) 169121afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 169221afaf18SBorislav Petkov 169321afaf18SBorislav Petkov /* 169421afaf18SBorislav Petkov * There are also broken BIOSes on some Pentium M and 169521afaf18SBorislav Petkov * earlier systems: 169621afaf18SBorislav Petkov */ 169721afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) 169821afaf18SBorislav Petkov cfg->bootlog = 0; 169921afaf18SBorislav Petkov 170021afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model == 45) 170121afaf18SBorislav Petkov quirk_no_way_out = quirk_sandybridge_ifu; 170221afaf18SBorislav Petkov } 17036e898d2bSTony W Wang-oc 17046e898d2bSTony W Wang-oc if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { 17056e898d2bSTony W Wang-oc /* 17066e898d2bSTony W Wang-oc * All newer Zhaoxin CPUs support MCE broadcasting. Enable 17076e898d2bSTony W Wang-oc * synchronization with a one second timeout. 17086e898d2bSTony W Wang-oc */ 17096e898d2bSTony W Wang-oc if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 17106e898d2bSTony W Wang-oc if (cfg->monarch_timeout < 0) 17116e898d2bSTony W Wang-oc cfg->monarch_timeout = USEC_PER_SEC; 17126e898d2bSTony W Wang-oc } 17136e898d2bSTony W Wang-oc } 17146e898d2bSTony W Wang-oc 171521afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 171621afaf18SBorislav Petkov cfg->monarch_timeout = 0; 171721afaf18SBorislav Petkov if (cfg->bootlog != 0) 171821afaf18SBorislav Petkov cfg->panic_timeout = 30; 171921afaf18SBorislav Petkov 172021afaf18SBorislav Petkov return 0; 172121afaf18SBorislav Petkov } 172221afaf18SBorislav Petkov 172321afaf18SBorislav Petkov static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) 172421afaf18SBorislav Petkov { 172521afaf18SBorislav Petkov if (c->x86 != 5) 172621afaf18SBorislav Petkov return 0; 172721afaf18SBorislav Petkov 172821afaf18SBorislav Petkov switch (c->x86_vendor) { 172921afaf18SBorislav Petkov case X86_VENDOR_INTEL: 173021afaf18SBorislav Petkov intel_p5_mcheck_init(c); 173121afaf18SBorislav Petkov return 1; 173221afaf18SBorislav Petkov break; 173321afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 173421afaf18SBorislav Petkov winchip_mcheck_init(c); 173521afaf18SBorislav Petkov return 1; 173621afaf18SBorislav Petkov break; 173721afaf18SBorislav Petkov default: 173821afaf18SBorislav Petkov return 0; 173921afaf18SBorislav Petkov } 174021afaf18SBorislav Petkov 174121afaf18SBorislav Petkov return 0; 174221afaf18SBorislav Petkov } 174321afaf18SBorislav Petkov 174421afaf18SBorislav Petkov /* 174521afaf18SBorislav Petkov * Init basic CPU features needed for early decoding of MCEs. 174621afaf18SBorislav Petkov */ 174721afaf18SBorislav Petkov static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) 174821afaf18SBorislav Petkov { 174921afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) { 175021afaf18SBorislav Petkov mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); 175121afaf18SBorislav Petkov mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); 175221afaf18SBorislav Petkov mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); 1753c9bf318fSThomas Gleixner mce_flags.amd_threshold = 1; 175421afaf18SBorislav Petkov 175521afaf18SBorislav Petkov if (mce_flags.smca) { 175621afaf18SBorislav Petkov msr_ops.ctl = smca_ctl_reg; 175721afaf18SBorislav Petkov msr_ops.status = smca_status_reg; 175821afaf18SBorislav Petkov msr_ops.addr = smca_addr_reg; 175921afaf18SBorislav Petkov msr_ops.misc = smca_misc_reg; 176021afaf18SBorislav Petkov } 176121afaf18SBorislav Petkov } 176221afaf18SBorislav Petkov } 176321afaf18SBorislav Petkov 176421afaf18SBorislav Petkov static void mce_centaur_feature_init(struct cpuinfo_x86 *c) 176521afaf18SBorislav Petkov { 176621afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 176721afaf18SBorislav Petkov 176821afaf18SBorislav Petkov /* 176921afaf18SBorislav Petkov * All newer Centaur CPUs support MCE broadcasting. Enable 177021afaf18SBorislav Petkov * synchronization with a one second timeout. 177121afaf18SBorislav Petkov */ 177221afaf18SBorislav Petkov if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) || 177321afaf18SBorislav Petkov c->x86 > 6) { 177421afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 177521afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 177621afaf18SBorislav Petkov } 177721afaf18SBorislav Petkov } 177821afaf18SBorislav Petkov 17795a3d56a0STony W Wang-oc static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) 17805a3d56a0STony W Wang-oc { 17815a3d56a0STony W Wang-oc struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 17825a3d56a0STony W Wang-oc 17835a3d56a0STony W Wang-oc /* 17845a3d56a0STony W Wang-oc * These CPUs have MCA bank 8 which reports only one error type called 17855a3d56a0STony W Wang-oc * SVAD (System View Address Decoder). The reporting of that error is 17865a3d56a0STony W Wang-oc * controlled by IA32_MC8.CTL.0. 17875a3d56a0STony W Wang-oc * 17885a3d56a0STony W Wang-oc * If enabled, prefetching on these CPUs will cause SVAD MCE when 17895a3d56a0STony W Wang-oc * virtual machines start and result in a system panic. Always disable 17905a3d56a0STony W Wang-oc * bank 8 SVAD error by default. 17915a3d56a0STony W Wang-oc */ 17925a3d56a0STony W Wang-oc if ((c->x86 == 7 && c->x86_model == 0x1b) || 17935a3d56a0STony W Wang-oc (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 17945a3d56a0STony W Wang-oc if (this_cpu_read(mce_num_banks) > 8) 17955a3d56a0STony W Wang-oc mce_banks[8].ctl = 0; 17965a3d56a0STony W Wang-oc } 17975a3d56a0STony W Wang-oc 17985a3d56a0STony W Wang-oc intel_init_cmci(); 179970f0c230STony W Wang-oc intel_init_lmce(); 18005a3d56a0STony W Wang-oc mce_adjust_timer = cmci_intel_adjust_timer; 18015a3d56a0STony W Wang-oc } 18025a3d56a0STony W Wang-oc 180370f0c230STony W Wang-oc static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) 180470f0c230STony W Wang-oc { 180570f0c230STony W Wang-oc intel_clear_lmce(); 180670f0c230STony W Wang-oc } 180770f0c230STony W Wang-oc 180821afaf18SBorislav Petkov static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) 180921afaf18SBorislav Petkov { 181021afaf18SBorislav Petkov switch (c->x86_vendor) { 181121afaf18SBorislav Petkov case X86_VENDOR_INTEL: 181221afaf18SBorislav Petkov mce_intel_feature_init(c); 181321afaf18SBorislav Petkov mce_adjust_timer = cmci_intel_adjust_timer; 181421afaf18SBorislav Petkov break; 181521afaf18SBorislav Petkov 181621afaf18SBorislav Petkov case X86_VENDOR_AMD: { 181721afaf18SBorislav Petkov mce_amd_feature_init(c); 181821afaf18SBorislav Petkov break; 181921afaf18SBorislav Petkov } 182021afaf18SBorislav Petkov 182121afaf18SBorislav Petkov case X86_VENDOR_HYGON: 182221afaf18SBorislav Petkov mce_hygon_feature_init(c); 182321afaf18SBorislav Petkov break; 182421afaf18SBorislav Petkov 182521afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 182621afaf18SBorislav Petkov mce_centaur_feature_init(c); 182721afaf18SBorislav Petkov break; 182821afaf18SBorislav Petkov 18295a3d56a0STony W Wang-oc case X86_VENDOR_ZHAOXIN: 18305a3d56a0STony W Wang-oc mce_zhaoxin_feature_init(c); 18315a3d56a0STony W Wang-oc break; 18325a3d56a0STony W Wang-oc 183321afaf18SBorislav Petkov default: 183421afaf18SBorislav Petkov break; 183521afaf18SBorislav Petkov } 183621afaf18SBorislav Petkov } 183721afaf18SBorislav Petkov 183821afaf18SBorislav Petkov static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) 183921afaf18SBorislav Petkov { 184021afaf18SBorislav Petkov switch (c->x86_vendor) { 184121afaf18SBorislav Petkov case X86_VENDOR_INTEL: 184221afaf18SBorislav Petkov mce_intel_feature_clear(c); 184321afaf18SBorislav Petkov break; 184470f0c230STony W Wang-oc 184570f0c230STony W Wang-oc case X86_VENDOR_ZHAOXIN: 184670f0c230STony W Wang-oc mce_zhaoxin_feature_clear(c); 184770f0c230STony W Wang-oc break; 184870f0c230STony W Wang-oc 184921afaf18SBorislav Petkov default: 185021afaf18SBorislav Petkov break; 185121afaf18SBorislav Petkov } 185221afaf18SBorislav Petkov } 185321afaf18SBorislav Petkov 185421afaf18SBorislav Petkov static void mce_start_timer(struct timer_list *t) 185521afaf18SBorislav Petkov { 185621afaf18SBorislav Petkov unsigned long iv = check_interval * HZ; 185721afaf18SBorislav Petkov 185821afaf18SBorislav Petkov if (mca_cfg.ignore_ce || !iv) 185921afaf18SBorislav Petkov return; 186021afaf18SBorislav Petkov 186121afaf18SBorislav Petkov this_cpu_write(mce_next_interval, iv); 186221afaf18SBorislav Petkov __start_timer(t, iv); 186321afaf18SBorislav Petkov } 186421afaf18SBorislav Petkov 186521afaf18SBorislav Petkov static void __mcheck_cpu_setup_timer(void) 186621afaf18SBorislav Petkov { 186721afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 186821afaf18SBorislav Petkov 186921afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 187021afaf18SBorislav Petkov } 187121afaf18SBorislav Petkov 187221afaf18SBorislav Petkov static void __mcheck_cpu_init_timer(void) 187321afaf18SBorislav Petkov { 187421afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 187521afaf18SBorislav Petkov 187621afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 187721afaf18SBorislav Petkov mce_start_timer(t); 187821afaf18SBorislav Petkov } 187921afaf18SBorislav Petkov 188045d4b7b9SYazen Ghannam bool filter_mce(struct mce *m) 188145d4b7b9SYazen Ghannam { 188271a84402SYazen Ghannam if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 188371a84402SYazen Ghannam return amd_filter_mce(m); 18842976908eSPrarit Bhargava if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 18852976908eSPrarit Bhargava return intel_filter_mce(m); 188671a84402SYazen Ghannam 188745d4b7b9SYazen Ghannam return false; 188845d4b7b9SYazen Ghannam } 188945d4b7b9SYazen Ghannam 189021afaf18SBorislav Petkov /* Handle unconfigured int18 (should never happen) */ 1891865d3a9aSThomas Gleixner static noinstr void unexpected_machine_check(struct pt_regs *regs) 189221afaf18SBorislav Petkov { 1893865d3a9aSThomas Gleixner instrumentation_begin(); 189421afaf18SBorislav Petkov pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", 189521afaf18SBorislav Petkov smp_processor_id()); 1896865d3a9aSThomas Gleixner instrumentation_end(); 189721afaf18SBorislav Petkov } 189821afaf18SBorislav Petkov 189921afaf18SBorislav Petkov /* Call the installed machine check handler for this CPU setup. */ 19008cd501c1SThomas Gleixner void (*machine_check_vector)(struct pt_regs *) = unexpected_machine_check; 190121afaf18SBorislav Petkov 19024c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_kernel(struct pt_regs *regs) 190321afaf18SBorislav Petkov { 190413cbc0cdSAndy Lutomirski WARN_ON_ONCE(user_mode(regs)); 190513cbc0cdSAndy Lutomirski 19064c0dcd83SThomas Gleixner /* 19074c0dcd83SThomas Gleixner * Only required when from kernel mode. See 19084c0dcd83SThomas Gleixner * mce_check_crashing_cpu() for details. 19094c0dcd83SThomas Gleixner */ 191094a46d31SThomas Gleixner if (machine_check_vector == do_machine_check && 191194a46d31SThomas Gleixner mce_check_crashing_cpu()) 191294a46d31SThomas Gleixner return; 191394a46d31SThomas Gleixner 191494a46d31SThomas Gleixner nmi_enter(); 1915865d3a9aSThomas Gleixner /* 1916865d3a9aSThomas Gleixner * The call targets are marked noinstr, but objtool can't figure 1917865d3a9aSThomas Gleixner * that out because it's an indirect call. Annotate it. 1918865d3a9aSThomas Gleixner */ 1919865d3a9aSThomas Gleixner instrumentation_begin(); 1920bf2b3008SPeter Zijlstra trace_hardirqs_off_finish(); 19218cd501c1SThomas Gleixner machine_check_vector(regs); 19223ffdfdceSThomas Gleixner if (regs->flags & X86_EFLAGS_IF) 19233ffdfdceSThomas Gleixner trace_hardirqs_on_prepare(); 1924865d3a9aSThomas Gleixner instrumentation_end(); 192594a46d31SThomas Gleixner nmi_exit(); 192621afaf18SBorislav Petkov } 192721afaf18SBorislav Petkov 19284c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_user(struct pt_regs *regs) 19294c0dcd83SThomas Gleixner { 1930517e4992SThomas Gleixner irqentry_enter_from_user_mode(regs); 1931865d3a9aSThomas Gleixner instrumentation_begin(); 19324c0dcd83SThomas Gleixner machine_check_vector(regs); 1933865d3a9aSThomas Gleixner instrumentation_end(); 1934517e4992SThomas Gleixner irqentry_exit_to_user_mode(regs); 19354c0dcd83SThomas Gleixner } 19364c0dcd83SThomas Gleixner 19374c0dcd83SThomas Gleixner #ifdef CONFIG_X86_64 19384c0dcd83SThomas Gleixner /* MCE hit kernel mode */ 19394c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE(exc_machine_check) 19404c0dcd83SThomas Gleixner { 1941cd840e42SPeter Zijlstra unsigned long dr7; 1942cd840e42SPeter Zijlstra 1943cd840e42SPeter Zijlstra dr7 = local_db_save(); 19444c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 1945cd840e42SPeter Zijlstra local_db_restore(dr7); 19464c0dcd83SThomas Gleixner } 19474c0dcd83SThomas Gleixner 19484c0dcd83SThomas Gleixner /* The user mode variant. */ 19494c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE_USER(exc_machine_check) 19504c0dcd83SThomas Gleixner { 1951cd840e42SPeter Zijlstra unsigned long dr7; 1952cd840e42SPeter Zijlstra 1953cd840e42SPeter Zijlstra dr7 = local_db_save(); 19544c0dcd83SThomas Gleixner exc_machine_check_user(regs); 1955cd840e42SPeter Zijlstra local_db_restore(dr7); 19564c0dcd83SThomas Gleixner } 19574c0dcd83SThomas Gleixner #else 19584c0dcd83SThomas Gleixner /* 32bit unified entry point */ 195913cbc0cdSAndy Lutomirski DEFINE_IDTENTRY_RAW(exc_machine_check) 19604c0dcd83SThomas Gleixner { 1961cd840e42SPeter Zijlstra unsigned long dr7; 1962cd840e42SPeter Zijlstra 1963cd840e42SPeter Zijlstra dr7 = local_db_save(); 19644c0dcd83SThomas Gleixner if (user_mode(regs)) 19654c0dcd83SThomas Gleixner exc_machine_check_user(regs); 19664c0dcd83SThomas Gleixner else 19674c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 1968cd840e42SPeter Zijlstra local_db_restore(dr7); 19694c0dcd83SThomas Gleixner } 19704c0dcd83SThomas Gleixner #endif 197121afaf18SBorislav Petkov 197221afaf18SBorislav Petkov /* 197321afaf18SBorislav Petkov * Called for each booted CPU to set up machine checks. 197421afaf18SBorislav Petkov * Must be called with preempt off: 197521afaf18SBorislav Petkov */ 197621afaf18SBorislav Petkov void mcheck_cpu_init(struct cpuinfo_x86 *c) 197721afaf18SBorislav Petkov { 197821afaf18SBorislav Petkov if (mca_cfg.disabled) 197921afaf18SBorislav Petkov return; 198021afaf18SBorislav Petkov 198121afaf18SBorislav Petkov if (__mcheck_cpu_ancient_init(c)) 198221afaf18SBorislav Petkov return; 198321afaf18SBorislav Petkov 198421afaf18SBorislav Petkov if (!mce_available(c)) 198521afaf18SBorislav Petkov return; 198621afaf18SBorislav Petkov 1987b4914508SYazen Ghannam __mcheck_cpu_cap_init(); 1988b4914508SYazen Ghannam 1989b4914508SYazen Ghannam if (__mcheck_cpu_apply_quirks(c) < 0) { 199021afaf18SBorislav Petkov mca_cfg.disabled = 1; 199121afaf18SBorislav Petkov return; 199221afaf18SBorislav Petkov } 199321afaf18SBorislav Petkov 199421afaf18SBorislav Petkov if (mce_gen_pool_init()) { 199521afaf18SBorislav Petkov mca_cfg.disabled = 1; 199621afaf18SBorislav Petkov pr_emerg("Couldn't allocate MCE records pool!\n"); 199721afaf18SBorislav Petkov return; 199821afaf18SBorislav Petkov } 199921afaf18SBorislav Petkov 200021afaf18SBorislav Petkov machine_check_vector = do_machine_check; 200121afaf18SBorislav Petkov 200221afaf18SBorislav Petkov __mcheck_cpu_init_early(c); 200321afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 200421afaf18SBorislav Petkov __mcheck_cpu_init_vendor(c); 200521afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 2006068b053dSYazen Ghannam __mcheck_cpu_check_banks(); 200721afaf18SBorislav Petkov __mcheck_cpu_setup_timer(); 200821afaf18SBorislav Petkov } 200921afaf18SBorislav Petkov 201021afaf18SBorislav Petkov /* 201121afaf18SBorislav Petkov * Called for each booted CPU to clear some machine checks opt-ins 201221afaf18SBorislav Petkov */ 201321afaf18SBorislav Petkov void mcheck_cpu_clear(struct cpuinfo_x86 *c) 201421afaf18SBorislav Petkov { 201521afaf18SBorislav Petkov if (mca_cfg.disabled) 201621afaf18SBorislav Petkov return; 201721afaf18SBorislav Petkov 201821afaf18SBorislav Petkov if (!mce_available(c)) 201921afaf18SBorislav Petkov return; 202021afaf18SBorislav Petkov 202121afaf18SBorislav Petkov /* 202221afaf18SBorislav Petkov * Possibly to clear general settings generic to x86 202321afaf18SBorislav Petkov * __mcheck_cpu_clear_generic(c); 202421afaf18SBorislav Petkov */ 202521afaf18SBorislav Petkov __mcheck_cpu_clear_vendor(c); 202621afaf18SBorislav Petkov 202721afaf18SBorislav Petkov } 202821afaf18SBorislav Petkov 202921afaf18SBorislav Petkov static void __mce_disable_bank(void *arg) 203021afaf18SBorislav Petkov { 203121afaf18SBorislav Petkov int bank = *((int *)arg); 203221afaf18SBorislav Petkov __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); 203321afaf18SBorislav Petkov cmci_disable_bank(bank); 203421afaf18SBorislav Petkov } 203521afaf18SBorislav Petkov 203621afaf18SBorislav Petkov void mce_disable_bank(int bank) 203721afaf18SBorislav Petkov { 2038c7d314f3SYazen Ghannam if (bank >= this_cpu_read(mce_num_banks)) { 203921afaf18SBorislav Petkov pr_warn(FW_BUG 204021afaf18SBorislav Petkov "Ignoring request to disable invalid MCA bank %d.\n", 204121afaf18SBorislav Petkov bank); 204221afaf18SBorislav Petkov return; 204321afaf18SBorislav Petkov } 204421afaf18SBorislav Petkov set_bit(bank, mce_banks_ce_disabled); 204521afaf18SBorislav Petkov on_each_cpu(__mce_disable_bank, &bank, 1); 204621afaf18SBorislav Petkov } 204721afaf18SBorislav Petkov 204821afaf18SBorislav Petkov /* 204921afaf18SBorislav Petkov * mce=off Disables machine check 205021afaf18SBorislav Petkov * mce=no_cmci Disables CMCI 205121afaf18SBorislav Petkov * mce=no_lmce Disables LMCE 205221afaf18SBorislav Petkov * mce=dont_log_ce Clears corrected events silently, no log created for CEs. 205343505646STony Luck * mce=print_all Print all machine check logs to console 205421afaf18SBorislav Petkov * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. 205521afaf18SBorislav Petkov * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) 205621afaf18SBorislav Petkov * monarchtimeout is how long to wait for other CPUs on machine 205721afaf18SBorislav Petkov * check, or 0 to not wait 205821afaf18SBorislav Petkov * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h 205921afaf18SBorislav Petkov and older. 206021afaf18SBorislav Petkov * mce=nobootlog Don't log MCEs from before booting. 206121afaf18SBorislav Petkov * mce=bios_cmci_threshold Don't program the CMCI threshold 206221afaf18SBorislav Petkov * mce=recovery force enable memcpy_mcsafe() 206321afaf18SBorislav Petkov */ 206421afaf18SBorislav Petkov static int __init mcheck_enable(char *str) 206521afaf18SBorislav Petkov { 206621afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 206721afaf18SBorislav Petkov 206821afaf18SBorislav Petkov if (*str == 0) { 206921afaf18SBorislav Petkov enable_p5_mce(); 207021afaf18SBorislav Petkov return 1; 207121afaf18SBorislav Petkov } 207221afaf18SBorislav Petkov if (*str == '=') 207321afaf18SBorislav Petkov str++; 207421afaf18SBorislav Petkov if (!strcmp(str, "off")) 207521afaf18SBorislav Petkov cfg->disabled = 1; 207621afaf18SBorislav Petkov else if (!strcmp(str, "no_cmci")) 207721afaf18SBorislav Petkov cfg->cmci_disabled = true; 207821afaf18SBorislav Petkov else if (!strcmp(str, "no_lmce")) 207921afaf18SBorislav Petkov cfg->lmce_disabled = 1; 208021afaf18SBorislav Petkov else if (!strcmp(str, "dont_log_ce")) 208121afaf18SBorislav Petkov cfg->dont_log_ce = true; 208243505646STony Luck else if (!strcmp(str, "print_all")) 208343505646STony Luck cfg->print_all = true; 208421afaf18SBorislav Petkov else if (!strcmp(str, "ignore_ce")) 208521afaf18SBorislav Petkov cfg->ignore_ce = true; 208621afaf18SBorislav Petkov else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) 208721afaf18SBorislav Petkov cfg->bootlog = (str[0] == 'b'); 208821afaf18SBorislav Petkov else if (!strcmp(str, "bios_cmci_threshold")) 208921afaf18SBorislav Petkov cfg->bios_cmci_threshold = 1; 209021afaf18SBorislav Petkov else if (!strcmp(str, "recovery")) 209121afaf18SBorislav Petkov cfg->recovery = 1; 209221afaf18SBorislav Petkov else if (isdigit(str[0])) { 209321afaf18SBorislav Petkov if (get_option(&str, &cfg->tolerant) == 2) 209421afaf18SBorislav Petkov get_option(&str, &(cfg->monarch_timeout)); 209521afaf18SBorislav Petkov } else { 209621afaf18SBorislav Petkov pr_info("mce argument %s ignored. Please use /sys\n", str); 209721afaf18SBorislav Petkov return 0; 209821afaf18SBorislav Petkov } 209921afaf18SBorislav Petkov return 1; 210021afaf18SBorislav Petkov } 210121afaf18SBorislav Petkov __setup("mce", mcheck_enable); 210221afaf18SBorislav Petkov 210321afaf18SBorislav Petkov int __init mcheck_init(void) 210421afaf18SBorislav Petkov { 210521afaf18SBorislav Petkov mcheck_intel_therm_init(); 2106c9c6d216STony Luck mce_register_decode_chain(&early_nb); 21078438b84aSJan H. Schönherr mce_register_decode_chain(&mce_uc_nb); 210821afaf18SBorislav Petkov mce_register_decode_chain(&mce_default_nb); 210921afaf18SBorislav Petkov mcheck_vendor_init_severity(); 211021afaf18SBorislav Petkov 211121afaf18SBorislav Petkov INIT_WORK(&mce_work, mce_gen_pool_process); 211221afaf18SBorislav Petkov init_irq_work(&mce_irq_work, mce_irq_work_cb); 211321afaf18SBorislav Petkov 211421afaf18SBorislav Petkov return 0; 211521afaf18SBorislav Petkov } 211621afaf18SBorislav Petkov 211721afaf18SBorislav Petkov /* 211821afaf18SBorislav Petkov * mce_syscore: PM support 211921afaf18SBorislav Petkov */ 212021afaf18SBorislav Petkov 212121afaf18SBorislav Petkov /* 212221afaf18SBorislav Petkov * Disable machine checks on suspend and shutdown. We can't really handle 212321afaf18SBorislav Petkov * them later. 212421afaf18SBorislav Petkov */ 212521afaf18SBorislav Petkov static void mce_disable_error_reporting(void) 212621afaf18SBorislav Petkov { 2127b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 212821afaf18SBorislav Petkov int i; 212921afaf18SBorislav Petkov 2130c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 213121afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 213221afaf18SBorislav Petkov 213321afaf18SBorislav Petkov if (b->init) 213421afaf18SBorislav Petkov wrmsrl(msr_ops.ctl(i), 0); 213521afaf18SBorislav Petkov } 213621afaf18SBorislav Petkov return; 213721afaf18SBorislav Petkov } 213821afaf18SBorislav Petkov 213921afaf18SBorislav Petkov static void vendor_disable_error_reporting(void) 214021afaf18SBorislav Petkov { 214121afaf18SBorislav Petkov /* 21426e898d2bSTony W Wang-oc * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these 21436e898d2bSTony W Wang-oc * MSRs are socket-wide. Disabling them for just a single offlined CPU 21446e898d2bSTony W Wang-oc * is bad, since it will inhibit reporting for all shared resources on 21456e898d2bSTony W Wang-oc * the socket like the last level cache (LLC), the integrated memory 21466e898d2bSTony W Wang-oc * controller (iMC), etc. 214721afaf18SBorislav Petkov */ 214821afaf18SBorislav Petkov if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || 214921afaf18SBorislav Petkov boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || 21506e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 21516e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) 215221afaf18SBorislav Petkov return; 215321afaf18SBorislav Petkov 215421afaf18SBorislav Petkov mce_disable_error_reporting(); 215521afaf18SBorislav Petkov } 215621afaf18SBorislav Petkov 215721afaf18SBorislav Petkov static int mce_syscore_suspend(void) 215821afaf18SBorislav Petkov { 215921afaf18SBorislav Petkov vendor_disable_error_reporting(); 216021afaf18SBorislav Petkov return 0; 216121afaf18SBorislav Petkov } 216221afaf18SBorislav Petkov 216321afaf18SBorislav Petkov static void mce_syscore_shutdown(void) 216421afaf18SBorislav Petkov { 216521afaf18SBorislav Petkov vendor_disable_error_reporting(); 216621afaf18SBorislav Petkov } 216721afaf18SBorislav Petkov 216821afaf18SBorislav Petkov /* 216921afaf18SBorislav Petkov * On resume clear all MCE state. Don't want to see leftovers from the BIOS. 217021afaf18SBorislav Petkov * Only one CPU is active at this time, the others get re-added later using 217121afaf18SBorislav Petkov * CPU hotplug: 217221afaf18SBorislav Petkov */ 217321afaf18SBorislav Petkov static void mce_syscore_resume(void) 217421afaf18SBorislav Petkov { 217521afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 217621afaf18SBorislav Petkov __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); 217721afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 217821afaf18SBorislav Petkov } 217921afaf18SBorislav Petkov 218021afaf18SBorislav Petkov static struct syscore_ops mce_syscore_ops = { 218121afaf18SBorislav Petkov .suspend = mce_syscore_suspend, 218221afaf18SBorislav Petkov .shutdown = mce_syscore_shutdown, 218321afaf18SBorislav Petkov .resume = mce_syscore_resume, 218421afaf18SBorislav Petkov }; 218521afaf18SBorislav Petkov 218621afaf18SBorislav Petkov /* 218721afaf18SBorislav Petkov * mce_device: Sysfs support 218821afaf18SBorislav Petkov */ 218921afaf18SBorislav Petkov 219021afaf18SBorislav Petkov static void mce_cpu_restart(void *data) 219121afaf18SBorislav Petkov { 219221afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 219321afaf18SBorislav Petkov return; 219421afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 219521afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 219621afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 219721afaf18SBorislav Petkov } 219821afaf18SBorislav Petkov 219921afaf18SBorislav Petkov /* Reinit MCEs after user configuration changes */ 220021afaf18SBorislav Petkov static void mce_restart(void) 220121afaf18SBorislav Petkov { 220221afaf18SBorislav Petkov mce_timer_delete_all(); 220321afaf18SBorislav Petkov on_each_cpu(mce_cpu_restart, NULL, 1); 220421afaf18SBorislav Petkov } 220521afaf18SBorislav Petkov 220621afaf18SBorislav Petkov /* Toggle features for corrected errors */ 220721afaf18SBorislav Petkov static void mce_disable_cmci(void *data) 220821afaf18SBorislav Petkov { 220921afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 221021afaf18SBorislav Petkov return; 221121afaf18SBorislav Petkov cmci_clear(); 221221afaf18SBorislav Petkov } 221321afaf18SBorislav Petkov 221421afaf18SBorislav Petkov static void mce_enable_ce(void *all) 221521afaf18SBorislav Petkov { 221621afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 221721afaf18SBorislav Petkov return; 221821afaf18SBorislav Petkov cmci_reenable(); 221921afaf18SBorislav Petkov cmci_recheck(); 222021afaf18SBorislav Petkov if (all) 222121afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 222221afaf18SBorislav Petkov } 222321afaf18SBorislav Petkov 222421afaf18SBorislav Petkov static struct bus_type mce_subsys = { 222521afaf18SBorislav Petkov .name = "machinecheck", 222621afaf18SBorislav Petkov .dev_name = "machinecheck", 222721afaf18SBorislav Petkov }; 222821afaf18SBorislav Petkov 222921afaf18SBorislav Petkov DEFINE_PER_CPU(struct device *, mce_device); 223021afaf18SBorislav Petkov 2231b4914508SYazen Ghannam static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr) 223221afaf18SBorislav Petkov { 2233b4914508SYazen Ghannam return container_of(attr, struct mce_bank_dev, attr); 223421afaf18SBorislav Petkov } 223521afaf18SBorislav Petkov 223621afaf18SBorislav Petkov static ssize_t show_bank(struct device *s, struct device_attribute *attr, 223721afaf18SBorislav Petkov char *buf) 223821afaf18SBorislav Petkov { 2239b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2240b4914508SYazen Ghannam struct mce_bank *b; 2241b4914508SYazen Ghannam 2242c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2243b4914508SYazen Ghannam return -EINVAL; 2244b4914508SYazen Ghannam 2245b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2246b4914508SYazen Ghannam 2247068b053dSYazen Ghannam if (!b->init) 2248068b053dSYazen Ghannam return -ENODEV; 2249068b053dSYazen Ghannam 2250b4914508SYazen Ghannam return sprintf(buf, "%llx\n", b->ctl); 225121afaf18SBorislav Petkov } 225221afaf18SBorislav Petkov 225321afaf18SBorislav Petkov static ssize_t set_bank(struct device *s, struct device_attribute *attr, 225421afaf18SBorislav Petkov const char *buf, size_t size) 225521afaf18SBorislav Petkov { 2256b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2257b4914508SYazen Ghannam struct mce_bank *b; 225821afaf18SBorislav Petkov u64 new; 225921afaf18SBorislav Petkov 226021afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 226121afaf18SBorislav Petkov return -EINVAL; 226221afaf18SBorislav Petkov 2263c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2264b4914508SYazen Ghannam return -EINVAL; 2265b4914508SYazen Ghannam 2266b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2267b4914508SYazen Ghannam 2268068b053dSYazen Ghannam if (!b->init) 2269068b053dSYazen Ghannam return -ENODEV; 2270068b053dSYazen Ghannam 2271b4914508SYazen Ghannam b->ctl = new; 227221afaf18SBorislav Petkov mce_restart(); 227321afaf18SBorislav Petkov 227421afaf18SBorislav Petkov return size; 227521afaf18SBorislav Petkov } 227621afaf18SBorislav Petkov 227721afaf18SBorislav Petkov static ssize_t set_ignore_ce(struct device *s, 227821afaf18SBorislav Petkov struct device_attribute *attr, 227921afaf18SBorislav Petkov const char *buf, size_t size) 228021afaf18SBorislav Petkov { 228121afaf18SBorislav Petkov u64 new; 228221afaf18SBorislav Petkov 228321afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 228421afaf18SBorislav Petkov return -EINVAL; 228521afaf18SBorislav Petkov 228621afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 228721afaf18SBorislav Petkov if (mca_cfg.ignore_ce ^ !!new) { 228821afaf18SBorislav Petkov if (new) { 228921afaf18SBorislav Petkov /* disable ce features */ 229021afaf18SBorislav Petkov mce_timer_delete_all(); 229121afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 229221afaf18SBorislav Petkov mca_cfg.ignore_ce = true; 229321afaf18SBorislav Petkov } else { 229421afaf18SBorislav Petkov /* enable ce features */ 229521afaf18SBorislav Petkov mca_cfg.ignore_ce = false; 229621afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, (void *)1, 1); 229721afaf18SBorislav Petkov } 229821afaf18SBorislav Petkov } 229921afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 230021afaf18SBorislav Petkov 230121afaf18SBorislav Petkov return size; 230221afaf18SBorislav Petkov } 230321afaf18SBorislav Petkov 230421afaf18SBorislav Petkov static ssize_t set_cmci_disabled(struct device *s, 230521afaf18SBorislav Petkov struct device_attribute *attr, 230621afaf18SBorislav Petkov const char *buf, size_t size) 230721afaf18SBorislav Petkov { 230821afaf18SBorislav Petkov u64 new; 230921afaf18SBorislav Petkov 231021afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 231121afaf18SBorislav Petkov return -EINVAL; 231221afaf18SBorislav Petkov 231321afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 231421afaf18SBorislav Petkov if (mca_cfg.cmci_disabled ^ !!new) { 231521afaf18SBorislav Petkov if (new) { 231621afaf18SBorislav Petkov /* disable cmci */ 231721afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 231821afaf18SBorislav Petkov mca_cfg.cmci_disabled = true; 231921afaf18SBorislav Petkov } else { 232021afaf18SBorislav Petkov /* enable cmci */ 232121afaf18SBorislav Petkov mca_cfg.cmci_disabled = false; 232221afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, NULL, 1); 232321afaf18SBorislav Petkov } 232421afaf18SBorislav Petkov } 232521afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 232621afaf18SBorislav Petkov 232721afaf18SBorislav Petkov return size; 232821afaf18SBorislav Petkov } 232921afaf18SBorislav Petkov 233021afaf18SBorislav Petkov static ssize_t store_int_with_restart(struct device *s, 233121afaf18SBorislav Petkov struct device_attribute *attr, 233221afaf18SBorislav Petkov const char *buf, size_t size) 233321afaf18SBorislav Petkov { 233421afaf18SBorislav Petkov unsigned long old_check_interval = check_interval; 233521afaf18SBorislav Petkov ssize_t ret = device_store_ulong(s, attr, buf, size); 233621afaf18SBorislav Petkov 233721afaf18SBorislav Petkov if (check_interval == old_check_interval) 233821afaf18SBorislav Petkov return ret; 233921afaf18SBorislav Petkov 234021afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 234121afaf18SBorislav Petkov mce_restart(); 234221afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 234321afaf18SBorislav Petkov 234421afaf18SBorislav Petkov return ret; 234521afaf18SBorislav Petkov } 234621afaf18SBorislav Petkov 234721afaf18SBorislav Petkov static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); 234821afaf18SBorislav Petkov static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); 234921afaf18SBorislav Petkov static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); 235043505646STony Luck static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all); 235121afaf18SBorislav Petkov 235221afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_check_interval = { 235321afaf18SBorislav Petkov __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), 235421afaf18SBorislav Petkov &check_interval 235521afaf18SBorislav Petkov }; 235621afaf18SBorislav Petkov 235721afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_ignore_ce = { 235821afaf18SBorislav Petkov __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), 235921afaf18SBorislav Petkov &mca_cfg.ignore_ce 236021afaf18SBorislav Petkov }; 236121afaf18SBorislav Petkov 236221afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_cmci_disabled = { 236321afaf18SBorislav Petkov __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), 236421afaf18SBorislav Petkov &mca_cfg.cmci_disabled 236521afaf18SBorislav Petkov }; 236621afaf18SBorislav Petkov 236721afaf18SBorislav Petkov static struct device_attribute *mce_device_attrs[] = { 236821afaf18SBorislav Petkov &dev_attr_tolerant.attr, 236921afaf18SBorislav Petkov &dev_attr_check_interval.attr, 237021afaf18SBorislav Petkov #ifdef CONFIG_X86_MCELOG_LEGACY 237121afaf18SBorislav Petkov &dev_attr_trigger, 237221afaf18SBorislav Petkov #endif 237321afaf18SBorislav Petkov &dev_attr_monarch_timeout.attr, 237421afaf18SBorislav Petkov &dev_attr_dont_log_ce.attr, 237543505646STony Luck &dev_attr_print_all.attr, 237621afaf18SBorislav Petkov &dev_attr_ignore_ce.attr, 237721afaf18SBorislav Petkov &dev_attr_cmci_disabled.attr, 237821afaf18SBorislav Petkov NULL 237921afaf18SBorislav Petkov }; 238021afaf18SBorislav Petkov 238121afaf18SBorislav Petkov static cpumask_var_t mce_device_initialized; 238221afaf18SBorislav Petkov 238321afaf18SBorislav Petkov static void mce_device_release(struct device *dev) 238421afaf18SBorislav Petkov { 238521afaf18SBorislav Petkov kfree(dev); 238621afaf18SBorislav Petkov } 238721afaf18SBorislav Petkov 2388b4914508SYazen Ghannam /* Per CPU device init. All of the CPUs still share the same bank device: */ 238921afaf18SBorislav Petkov static int mce_device_create(unsigned int cpu) 239021afaf18SBorislav Petkov { 239121afaf18SBorislav Petkov struct device *dev; 239221afaf18SBorislav Petkov int err; 239321afaf18SBorislav Petkov int i, j; 239421afaf18SBorislav Petkov 239521afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) 239621afaf18SBorislav Petkov return -EIO; 239721afaf18SBorislav Petkov 239821afaf18SBorislav Petkov dev = per_cpu(mce_device, cpu); 239921afaf18SBorislav Petkov if (dev) 240021afaf18SBorislav Petkov return 0; 240121afaf18SBorislav Petkov 240221afaf18SBorislav Petkov dev = kzalloc(sizeof(*dev), GFP_KERNEL); 240321afaf18SBorislav Petkov if (!dev) 240421afaf18SBorislav Petkov return -ENOMEM; 240521afaf18SBorislav Petkov dev->id = cpu; 240621afaf18SBorislav Petkov dev->bus = &mce_subsys; 240721afaf18SBorislav Petkov dev->release = &mce_device_release; 240821afaf18SBorislav Petkov 240921afaf18SBorislav Petkov err = device_register(dev); 241021afaf18SBorislav Petkov if (err) { 241121afaf18SBorislav Petkov put_device(dev); 241221afaf18SBorislav Petkov return err; 241321afaf18SBorislav Petkov } 241421afaf18SBorislav Petkov 241521afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) { 241621afaf18SBorislav Petkov err = device_create_file(dev, mce_device_attrs[i]); 241721afaf18SBorislav Petkov if (err) 241821afaf18SBorislav Petkov goto error; 241921afaf18SBorislav Petkov } 2420c7d314f3SYazen Ghannam for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) { 2421b4914508SYazen Ghannam err = device_create_file(dev, &mce_bank_devs[j].attr); 242221afaf18SBorislav Petkov if (err) 242321afaf18SBorislav Petkov goto error2; 242421afaf18SBorislav Petkov } 242521afaf18SBorislav Petkov cpumask_set_cpu(cpu, mce_device_initialized); 242621afaf18SBorislav Petkov per_cpu(mce_device, cpu) = dev; 242721afaf18SBorislav Petkov 242821afaf18SBorislav Petkov return 0; 242921afaf18SBorislav Petkov error2: 243021afaf18SBorislav Petkov while (--j >= 0) 2431b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[j].attr); 243221afaf18SBorislav Petkov error: 243321afaf18SBorislav Petkov while (--i >= 0) 243421afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 243521afaf18SBorislav Petkov 243621afaf18SBorislav Petkov device_unregister(dev); 243721afaf18SBorislav Petkov 243821afaf18SBorislav Petkov return err; 243921afaf18SBorislav Petkov } 244021afaf18SBorislav Petkov 244121afaf18SBorislav Petkov static void mce_device_remove(unsigned int cpu) 244221afaf18SBorislav Petkov { 244321afaf18SBorislav Petkov struct device *dev = per_cpu(mce_device, cpu); 244421afaf18SBorislav Petkov int i; 244521afaf18SBorislav Petkov 244621afaf18SBorislav Petkov if (!cpumask_test_cpu(cpu, mce_device_initialized)) 244721afaf18SBorislav Petkov return; 244821afaf18SBorislav Petkov 244921afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) 245021afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 245121afaf18SBorislav Petkov 2452c7d314f3SYazen Ghannam for (i = 0; i < per_cpu(mce_num_banks, cpu); i++) 2453b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[i].attr); 245421afaf18SBorislav Petkov 245521afaf18SBorislav Petkov device_unregister(dev); 245621afaf18SBorislav Petkov cpumask_clear_cpu(cpu, mce_device_initialized); 245721afaf18SBorislav Petkov per_cpu(mce_device, cpu) = NULL; 245821afaf18SBorislav Petkov } 245921afaf18SBorislav Petkov 246021afaf18SBorislav Petkov /* Make sure there are no machine checks on offlined CPUs. */ 246121afaf18SBorislav Petkov static void mce_disable_cpu(void) 246221afaf18SBorislav Petkov { 246321afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 246421afaf18SBorislav Petkov return; 246521afaf18SBorislav Petkov 246621afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 246721afaf18SBorislav Petkov cmci_clear(); 246821afaf18SBorislav Petkov 246921afaf18SBorislav Petkov vendor_disable_error_reporting(); 247021afaf18SBorislav Petkov } 247121afaf18SBorislav Petkov 247221afaf18SBorislav Petkov static void mce_reenable_cpu(void) 247321afaf18SBorislav Petkov { 2474b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 247521afaf18SBorislav Petkov int i; 247621afaf18SBorislav Petkov 247721afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 247821afaf18SBorislav Petkov return; 247921afaf18SBorislav Petkov 248021afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 248121afaf18SBorislav Petkov cmci_reenable(); 2482c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 248321afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 248421afaf18SBorislav Petkov 248521afaf18SBorislav Petkov if (b->init) 248621afaf18SBorislav Petkov wrmsrl(msr_ops.ctl(i), b->ctl); 248721afaf18SBorislav Petkov } 248821afaf18SBorislav Petkov } 248921afaf18SBorislav Petkov 249021afaf18SBorislav Petkov static int mce_cpu_dead(unsigned int cpu) 249121afaf18SBorislav Petkov { 249221afaf18SBorislav Petkov mce_intel_hcpu_update(cpu); 249321afaf18SBorislav Petkov 249421afaf18SBorislav Petkov /* intentionally ignoring frozen here */ 249521afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 249621afaf18SBorislav Petkov cmci_rediscover(); 249721afaf18SBorislav Petkov return 0; 249821afaf18SBorislav Petkov } 249921afaf18SBorislav Petkov 250021afaf18SBorislav Petkov static int mce_cpu_online(unsigned int cpu) 250121afaf18SBorislav Petkov { 250221afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 250321afaf18SBorislav Petkov int ret; 250421afaf18SBorislav Petkov 250521afaf18SBorislav Petkov mce_device_create(cpu); 250621afaf18SBorislav Petkov 250721afaf18SBorislav Petkov ret = mce_threshold_create_device(cpu); 250821afaf18SBorislav Petkov if (ret) { 250921afaf18SBorislav Petkov mce_device_remove(cpu); 251021afaf18SBorislav Petkov return ret; 251121afaf18SBorislav Petkov } 251221afaf18SBorislav Petkov mce_reenable_cpu(); 251321afaf18SBorislav Petkov mce_start_timer(t); 251421afaf18SBorislav Petkov return 0; 251521afaf18SBorislav Petkov } 251621afaf18SBorislav Petkov 251721afaf18SBorislav Petkov static int mce_cpu_pre_down(unsigned int cpu) 251821afaf18SBorislav Petkov { 251921afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 252021afaf18SBorislav Petkov 252121afaf18SBorislav Petkov mce_disable_cpu(); 252221afaf18SBorislav Petkov del_timer_sync(t); 252321afaf18SBorislav Petkov mce_threshold_remove_device(cpu); 252421afaf18SBorislav Petkov mce_device_remove(cpu); 252521afaf18SBorislav Petkov return 0; 252621afaf18SBorislav Petkov } 252721afaf18SBorislav Petkov 252821afaf18SBorislav Petkov static __init void mce_init_banks(void) 252921afaf18SBorislav Petkov { 253021afaf18SBorislav Petkov int i; 253121afaf18SBorislav Petkov 2532b4914508SYazen Ghannam for (i = 0; i < MAX_NR_BANKS; i++) { 2533b4914508SYazen Ghannam struct mce_bank_dev *b = &mce_bank_devs[i]; 253421afaf18SBorislav Petkov struct device_attribute *a = &b->attr; 253521afaf18SBorislav Petkov 2536b4914508SYazen Ghannam b->bank = i; 2537b4914508SYazen Ghannam 253821afaf18SBorislav Petkov sysfs_attr_init(&a->attr); 253921afaf18SBorislav Petkov a->attr.name = b->attrname; 254021afaf18SBorislav Petkov snprintf(b->attrname, ATTR_LEN, "bank%d", i); 254121afaf18SBorislav Petkov 254221afaf18SBorislav Petkov a->attr.mode = 0644; 254321afaf18SBorislav Petkov a->show = show_bank; 254421afaf18SBorislav Petkov a->store = set_bank; 254521afaf18SBorislav Petkov } 254621afaf18SBorislav Petkov } 254721afaf18SBorislav Petkov 25486e7a41c6SThomas Gleixner /* 25496e7a41c6SThomas Gleixner * When running on XEN, this initcall is ordered against the XEN mcelog 25506e7a41c6SThomas Gleixner * initcall: 25516e7a41c6SThomas Gleixner * 25526e7a41c6SThomas Gleixner * device_initcall(xen_late_init_mcelog); 25536e7a41c6SThomas Gleixner * device_initcall_sync(mcheck_init_device); 25546e7a41c6SThomas Gleixner */ 255521afaf18SBorislav Petkov static __init int mcheck_init_device(void) 255621afaf18SBorislav Petkov { 255721afaf18SBorislav Petkov int err; 255821afaf18SBorislav Petkov 255921afaf18SBorislav Petkov /* 256021afaf18SBorislav Petkov * Check if we have a spare virtual bit. This will only become 256121afaf18SBorislav Petkov * a problem if/when we move beyond 5-level page tables. 256221afaf18SBorislav Petkov */ 256321afaf18SBorislav Petkov MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63); 256421afaf18SBorislav Petkov 256521afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) { 256621afaf18SBorislav Petkov err = -EIO; 256721afaf18SBorislav Petkov goto err_out; 256821afaf18SBorislav Petkov } 256921afaf18SBorislav Petkov 257021afaf18SBorislav Petkov if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { 257121afaf18SBorislav Petkov err = -ENOMEM; 257221afaf18SBorislav Petkov goto err_out; 257321afaf18SBorislav Petkov } 257421afaf18SBorislav Petkov 257521afaf18SBorislav Petkov mce_init_banks(); 257621afaf18SBorislav Petkov 257721afaf18SBorislav Petkov err = subsys_system_register(&mce_subsys, NULL); 257821afaf18SBorislav Petkov if (err) 257921afaf18SBorislav Petkov goto err_out_mem; 258021afaf18SBorislav Petkov 258121afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL, 258221afaf18SBorislav Petkov mce_cpu_dead); 258321afaf18SBorislav Petkov if (err) 258421afaf18SBorislav Petkov goto err_out_mem; 258521afaf18SBorislav Petkov 25866e7a41c6SThomas Gleixner /* 25876e7a41c6SThomas Gleixner * Invokes mce_cpu_online() on all CPUs which are online when 25886e7a41c6SThomas Gleixner * the state is installed. 25896e7a41c6SThomas Gleixner */ 259021afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online", 259121afaf18SBorislav Petkov mce_cpu_online, mce_cpu_pre_down); 259221afaf18SBorislav Petkov if (err < 0) 259321afaf18SBorislav Petkov goto err_out_online; 259421afaf18SBorislav Petkov 259521afaf18SBorislav Petkov register_syscore_ops(&mce_syscore_ops); 259621afaf18SBorislav Petkov 259721afaf18SBorislav Petkov return 0; 259821afaf18SBorislav Petkov 259921afaf18SBorislav Petkov err_out_online: 260021afaf18SBorislav Petkov cpuhp_remove_state(CPUHP_X86_MCE_DEAD); 260121afaf18SBorislav Petkov 260221afaf18SBorislav Petkov err_out_mem: 260321afaf18SBorislav Petkov free_cpumask_var(mce_device_initialized); 260421afaf18SBorislav Petkov 260521afaf18SBorislav Petkov err_out: 260621afaf18SBorislav Petkov pr_err("Unable to init MCE device (rc: %d)\n", err); 260721afaf18SBorislav Petkov 260821afaf18SBorislav Petkov return err; 260921afaf18SBorislav Petkov } 261021afaf18SBorislav Petkov device_initcall_sync(mcheck_init_device); 261121afaf18SBorislav Petkov 261221afaf18SBorislav Petkov /* 261321afaf18SBorislav Petkov * Old style boot options parsing. Only for compatibility. 261421afaf18SBorislav Petkov */ 261521afaf18SBorislav Petkov static int __init mcheck_disable(char *str) 261621afaf18SBorislav Petkov { 261721afaf18SBorislav Petkov mca_cfg.disabled = 1; 261821afaf18SBorislav Petkov return 1; 261921afaf18SBorislav Petkov } 262021afaf18SBorislav Petkov __setup("nomce", mcheck_disable); 262121afaf18SBorislav Petkov 262221afaf18SBorislav Petkov #ifdef CONFIG_DEBUG_FS 262321afaf18SBorislav Petkov struct dentry *mce_get_debugfs_dir(void) 262421afaf18SBorislav Petkov { 262521afaf18SBorislav Petkov static struct dentry *dmce; 262621afaf18SBorislav Petkov 262721afaf18SBorislav Petkov if (!dmce) 262821afaf18SBorislav Petkov dmce = debugfs_create_dir("mce", NULL); 262921afaf18SBorislav Petkov 263021afaf18SBorislav Petkov return dmce; 263121afaf18SBorislav Petkov } 263221afaf18SBorislav Petkov 263321afaf18SBorislav Petkov static void mce_reset(void) 263421afaf18SBorislav Petkov { 263521afaf18SBorislav Petkov cpu_missing = 0; 263621afaf18SBorislav Petkov atomic_set(&mce_fake_panicked, 0); 263721afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 263821afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 263921afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 264021afaf18SBorislav Petkov } 264121afaf18SBorislav Petkov 264221afaf18SBorislav Petkov static int fake_panic_get(void *data, u64 *val) 264321afaf18SBorislav Petkov { 264421afaf18SBorislav Petkov *val = fake_panic; 264521afaf18SBorislav Petkov return 0; 264621afaf18SBorislav Petkov } 264721afaf18SBorislav Petkov 264821afaf18SBorislav Petkov static int fake_panic_set(void *data, u64 val) 264921afaf18SBorislav Petkov { 265021afaf18SBorislav Petkov mce_reset(); 265121afaf18SBorislav Petkov fake_panic = val; 265221afaf18SBorislav Petkov return 0; 265321afaf18SBorislav Petkov } 265421afaf18SBorislav Petkov 265528156d76SYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set, 265628156d76SYueHaibing "%llu\n"); 265721afaf18SBorislav Petkov 26586e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) 265921afaf18SBorislav Petkov { 26606e4f929eSGreg Kroah-Hartman struct dentry *dmce; 266121afaf18SBorislav Petkov 266221afaf18SBorislav Petkov dmce = mce_get_debugfs_dir(); 26636e4f929eSGreg Kroah-Hartman debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL, 26646e4f929eSGreg Kroah-Hartman &fake_panic_fops); 266521afaf18SBorislav Petkov } 266621afaf18SBorislav Petkov #else 26676e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) { } 266821afaf18SBorislav Petkov #endif 266921afaf18SBorislav Petkov 267021afaf18SBorislav Petkov DEFINE_STATIC_KEY_FALSE(mcsafe_key); 267121afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mcsafe_key); 267221afaf18SBorislav Petkov 267321afaf18SBorislav Petkov static int __init mcheck_late_init(void) 267421afaf18SBorislav Petkov { 267521afaf18SBorislav Petkov if (mca_cfg.recovery) 267621afaf18SBorislav Petkov static_branch_inc(&mcsafe_key); 267721afaf18SBorislav Petkov 267821afaf18SBorislav Petkov mcheck_debugfs_init(); 267921afaf18SBorislav Petkov 268021afaf18SBorislav Petkov /* 268121afaf18SBorislav Petkov * Flush out everything that has been logged during early boot, now that 268221afaf18SBorislav Petkov * everything has been initialized (workqueues, decoders, ...). 268321afaf18SBorislav Petkov */ 268421afaf18SBorislav Petkov mce_schedule_work(); 268521afaf18SBorislav Petkov 268621afaf18SBorislav Petkov return 0; 268721afaf18SBorislav Petkov } 268821afaf18SBorislav Petkov late_initcall(mcheck_late_init); 2689