1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 221afaf18SBorislav Petkov /* 321afaf18SBorislav Petkov * Machine check handler. 421afaf18SBorislav Petkov * 521afaf18SBorislav Petkov * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. 621afaf18SBorislav Petkov * Rest from unknown author(s). 721afaf18SBorislav Petkov * 2004 Andi Kleen. Rewrote most of it. 821afaf18SBorislav Petkov * Copyright 2008 Intel Corporation 921afaf18SBorislav Petkov * Author: Andi Kleen 1021afaf18SBorislav Petkov */ 1121afaf18SBorislav Petkov 1221afaf18SBorislav Petkov #include <linux/thread_info.h> 1321afaf18SBorislav Petkov #include <linux/capability.h> 1421afaf18SBorislav Petkov #include <linux/miscdevice.h> 1521afaf18SBorislav Petkov #include <linux/ratelimit.h> 1621afaf18SBorislav Petkov #include <linux/rcupdate.h> 1721afaf18SBorislav Petkov #include <linux/kobject.h> 1821afaf18SBorislav Petkov #include <linux/uaccess.h> 1921afaf18SBorislav Petkov #include <linux/kdebug.h> 2021afaf18SBorislav Petkov #include <linux/kernel.h> 2121afaf18SBorislav Petkov #include <linux/percpu.h> 2221afaf18SBorislav Petkov #include <linux/string.h> 2321afaf18SBorislav Petkov #include <linux/device.h> 2421afaf18SBorislav Petkov #include <linux/syscore_ops.h> 2521afaf18SBorislav Petkov #include <linux/delay.h> 2621afaf18SBorislav Petkov #include <linux/ctype.h> 2721afaf18SBorislav Petkov #include <linux/sched.h> 2821afaf18SBorislav Petkov #include <linux/sysfs.h> 2921afaf18SBorislav Petkov #include <linux/types.h> 3021afaf18SBorislav Petkov #include <linux/slab.h> 3121afaf18SBorislav Petkov #include <linux/init.h> 3221afaf18SBorislav Petkov #include <linux/kmod.h> 3321afaf18SBorislav Petkov #include <linux/poll.h> 3421afaf18SBorislav Petkov #include <linux/nmi.h> 3521afaf18SBorislav Petkov #include <linux/cpu.h> 3621afaf18SBorislav Petkov #include <linux/ras.h> 3721afaf18SBorislav Petkov #include <linux/smp.h> 3821afaf18SBorislav Petkov #include <linux/fs.h> 3921afaf18SBorislav Petkov #include <linux/mm.h> 4021afaf18SBorislav Petkov #include <linux/debugfs.h> 4121afaf18SBorislav Petkov #include <linux/irq_work.h> 4221afaf18SBorislav Petkov #include <linux/export.h> 4321afaf18SBorislav Petkov #include <linux/set_memory.h> 449998a983SRicardo Neri #include <linux/sync_core.h> 455567d11cSPeter Zijlstra #include <linux/task_work.h> 460d00449cSPeter Zijlstra #include <linux/hardirq.h> 4721afaf18SBorislav Petkov 4821afaf18SBorislav Petkov #include <asm/intel-family.h> 4921afaf18SBorislav Petkov #include <asm/processor.h> 5021afaf18SBorislav Petkov #include <asm/traps.h> 5121afaf18SBorislav Petkov #include <asm/tlbflush.h> 5221afaf18SBorislav Petkov #include <asm/mce.h> 5321afaf18SBorislav Petkov #include <asm/msr.h> 5421afaf18SBorislav Petkov #include <asm/reboot.h> 5521afaf18SBorislav Petkov 5621afaf18SBorislav Petkov #include "internal.h" 5721afaf18SBorislav Petkov 5821afaf18SBorislav Petkov /* sysfs synchronization */ 5921afaf18SBorislav Petkov static DEFINE_MUTEX(mce_sysfs_mutex); 6021afaf18SBorislav Petkov 6121afaf18SBorislav Petkov #define CREATE_TRACE_POINTS 6221afaf18SBorislav Petkov #include <trace/events/mce.h> 6321afaf18SBorislav Petkov 6421afaf18SBorislav Petkov #define SPINUNIT 100 /* 100ns */ 6521afaf18SBorislav Petkov 6621afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_exception_count); 6721afaf18SBorislav Petkov 68c7d314f3SYazen Ghannam DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks); 69c7d314f3SYazen Ghannam 70fcd343a2SSmita Koralahalli DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array); 71b4914508SYazen Ghannam 72b4914508SYazen Ghannam #define ATTR_LEN 16 73b4914508SYazen Ghannam /* One object for each MCE bank, shared by all CPUs */ 74b4914508SYazen Ghannam struct mce_bank_dev { 7595fdce6bSYazen Ghannam struct device_attribute attr; /* device attribute */ 7695fdce6bSYazen Ghannam char attrname[ATTR_LEN]; /* attribute name */ 77b4914508SYazen Ghannam u8 bank; /* bank number */ 7895fdce6bSYazen Ghannam }; 79b4914508SYazen Ghannam static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS]; 8095fdce6bSYazen Ghannam 8121afaf18SBorislav Petkov struct mce_vendor_flags mce_flags __read_mostly; 8221afaf18SBorislav Petkov 8321afaf18SBorislav Petkov struct mca_config mca_cfg __read_mostly = { 8421afaf18SBorislav Petkov .bootlog = -1, 8521afaf18SBorislav Petkov .monarch_timeout = -1 8621afaf18SBorislav Petkov }; 8721afaf18SBorislav Petkov 8821afaf18SBorislav Petkov static DEFINE_PER_CPU(struct mce, mces_seen); 8921afaf18SBorislav Petkov static unsigned long mce_need_notify; 9021afaf18SBorislav Petkov 9121afaf18SBorislav Petkov /* 9221afaf18SBorislav Petkov * MCA banks polled by the period polling timer for corrected events. 9321afaf18SBorislav Petkov * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). 9421afaf18SBorislav Petkov */ 9521afaf18SBorislav Petkov DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { 9621afaf18SBorislav Petkov [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL 9721afaf18SBorislav Petkov }; 9821afaf18SBorislav Petkov 9921afaf18SBorislav Petkov /* 10021afaf18SBorislav Petkov * MCA banks controlled through firmware first for corrected errors. 10121afaf18SBorislav Petkov * This is a global list of banks for which we won't enable CMCI and we 10221afaf18SBorislav Petkov * won't poll. Firmware controls these banks and is responsible for 10321afaf18SBorislav Petkov * reporting corrected errors through GHES. Uncorrected/recoverable 10421afaf18SBorislav Petkov * errors are still notified through a machine check. 10521afaf18SBorislav Petkov */ 10621afaf18SBorislav Petkov mce_banks_t mce_banks_ce_disabled; 10721afaf18SBorislav Petkov 10821afaf18SBorislav Petkov static struct work_struct mce_work; 10921afaf18SBorislav Petkov static struct irq_work mce_irq_work; 11021afaf18SBorislav Petkov 11121afaf18SBorislav Petkov /* 11221afaf18SBorislav Petkov * CPU/chipset specific EDAC code can register a notifier call here to print 11321afaf18SBorislav Petkov * MCE errors in a human-readable form. 11421afaf18SBorislav Petkov */ 11521afaf18SBorislav Petkov BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); 11621afaf18SBorislav Petkov 11721afaf18SBorislav Petkov /* Do initial initialization of a struct mce */ 118487d654dSBorislav Petkov void mce_setup(struct mce *m) 11921afaf18SBorislav Petkov { 12021afaf18SBorislav Petkov memset(m, 0, sizeof(struct mce)); 12121afaf18SBorislav Petkov m->cpu = m->extcpu = smp_processor_id(); 12221afaf18SBorislav Petkov /* need the internal __ version to avoid deadlocks */ 12321afaf18SBorislav Petkov m->time = __ktime_get_real_seconds(); 12421afaf18SBorislav Petkov m->cpuvendor = boot_cpu_data.x86_vendor; 12521afaf18SBorislav Petkov m->cpuid = cpuid_eax(1); 12621afaf18SBorislav Petkov m->socketid = cpu_data(m->extcpu).phys_proc_id; 12721afaf18SBorislav Petkov m->apicid = cpu_data(m->extcpu).initial_apicid; 128865d3a9aSThomas Gleixner m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); 129822ccfadSTony Luck m->ppin = cpu_data(m->extcpu).ppin; 13021afaf18SBorislav Petkov m->microcode = boot_cpu_data.microcode; 13121afaf18SBorislav Petkov } 13221afaf18SBorislav Petkov 13321afaf18SBorislav Petkov DEFINE_PER_CPU(struct mce, injectm); 13421afaf18SBorislav Petkov EXPORT_PER_CPU_SYMBOL_GPL(injectm); 13521afaf18SBorislav Petkov 13621afaf18SBorislav Petkov void mce_log(struct mce *m) 13721afaf18SBorislav Petkov { 13821afaf18SBorislav Petkov if (!mce_gen_pool_add(m)) 13921afaf18SBorislav Petkov irq_work_queue(&mce_irq_work); 14021afaf18SBorislav Petkov } 14181736abdSJan H. Schönherr EXPORT_SYMBOL_GPL(mce_log); 14221afaf18SBorislav Petkov 14321afaf18SBorislav Petkov void mce_register_decode_chain(struct notifier_block *nb) 14421afaf18SBorislav Petkov { 14515af3659SZhen Lei if (WARN_ON(nb->priority < MCE_PRIO_LOWEST || 14615af3659SZhen Lei nb->priority > MCE_PRIO_HIGHEST)) 14721afaf18SBorislav Petkov return; 14821afaf18SBorislav Petkov 14921afaf18SBorislav Petkov blocking_notifier_chain_register(&x86_mce_decoder_chain, nb); 15021afaf18SBorislav Petkov } 15121afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_register_decode_chain); 15221afaf18SBorislav Petkov 15321afaf18SBorislav Petkov void mce_unregister_decode_chain(struct notifier_block *nb) 15421afaf18SBorislav Petkov { 15521afaf18SBorislav Petkov blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb); 15621afaf18SBorislav Petkov } 15721afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); 15821afaf18SBorislav Petkov 15921afaf18SBorislav Petkov static void __print_mce(struct mce *m) 16021afaf18SBorislav Petkov { 16121afaf18SBorislav Petkov pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", 16221afaf18SBorislav Petkov m->extcpu, 16321afaf18SBorislav Petkov (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""), 16421afaf18SBorislav Petkov m->mcgstatus, m->bank, m->status); 16521afaf18SBorislav Petkov 16621afaf18SBorislav Petkov if (m->ip) { 16721afaf18SBorislav Petkov pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", 16821afaf18SBorislav Petkov !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", 16921afaf18SBorislav Petkov m->cs, m->ip); 17021afaf18SBorislav Petkov 17121afaf18SBorislav Petkov if (m->cs == __KERNEL_CS) 17221afaf18SBorislav Petkov pr_cont("{%pS}", (void *)(unsigned long)m->ip); 17321afaf18SBorislav Petkov pr_cont("\n"); 17421afaf18SBorislav Petkov } 17521afaf18SBorislav Petkov 17621afaf18SBorislav Petkov pr_emerg(HW_ERR "TSC %llx ", m->tsc); 17721afaf18SBorislav Petkov if (m->addr) 17821afaf18SBorislav Petkov pr_cont("ADDR %llx ", m->addr); 17921afaf18SBorislav Petkov if (m->misc) 18021afaf18SBorislav Petkov pr_cont("MISC %llx ", m->misc); 181bb2de0adSSmita Koralahalli if (m->ppin) 182bb2de0adSSmita Koralahalli pr_cont("PPIN %llx ", m->ppin); 18321afaf18SBorislav Petkov 18421afaf18SBorislav Petkov if (mce_flags.smca) { 18521afaf18SBorislav Petkov if (m->synd) 18621afaf18SBorislav Petkov pr_cont("SYND %llx ", m->synd); 18721afaf18SBorislav Petkov if (m->ipid) 18821afaf18SBorislav Petkov pr_cont("IPID %llx ", m->ipid); 18921afaf18SBorislav Petkov } 19021afaf18SBorislav Petkov 19121afaf18SBorislav Petkov pr_cont("\n"); 192925946cfSTony Luck 19321afaf18SBorislav Petkov /* 19421afaf18SBorislav Petkov * Note this output is parsed by external tools and old fields 19521afaf18SBorislav Petkov * should not be changed. 19621afaf18SBorislav Petkov */ 19721afaf18SBorislav Petkov pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", 19821afaf18SBorislav Petkov m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, 19921afaf18SBorislav Petkov m->microcode); 20021afaf18SBorislav Petkov } 20121afaf18SBorislav Petkov 20221afaf18SBorislav Petkov static void print_mce(struct mce *m) 20321afaf18SBorislav Petkov { 20421afaf18SBorislav Petkov __print_mce(m); 20521afaf18SBorislav Petkov 20621afaf18SBorislav Petkov if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON) 20721afaf18SBorislav Petkov pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); 20821afaf18SBorislav Petkov } 20921afaf18SBorislav Petkov 21021afaf18SBorislav Petkov #define PANIC_TIMEOUT 5 /* 5 seconds */ 21121afaf18SBorislav Petkov 21221afaf18SBorislav Petkov static atomic_t mce_panicked; 21321afaf18SBorislav Petkov 21421afaf18SBorislav Petkov static int fake_panic; 21521afaf18SBorislav Petkov static atomic_t mce_fake_panicked; 21621afaf18SBorislav Petkov 21721afaf18SBorislav Petkov /* Panic in progress. Enable interrupts and wait for final IPI */ 21821afaf18SBorislav Petkov static void wait_for_panic(void) 21921afaf18SBorislav Petkov { 22021afaf18SBorislav Petkov long timeout = PANIC_TIMEOUT*USEC_PER_SEC; 22121afaf18SBorislav Petkov 22221afaf18SBorislav Petkov preempt_disable(); 22321afaf18SBorislav Petkov local_irq_enable(); 22421afaf18SBorislav Petkov while (timeout-- > 0) 22521afaf18SBorislav Petkov udelay(1); 22621afaf18SBorislav Petkov if (panic_timeout == 0) 22721afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 22821afaf18SBorislav Petkov panic("Panicing machine check CPU died"); 22921afaf18SBorislav Petkov } 23021afaf18SBorislav Petkov 2313c7ce80aSBorislav Petkov static noinstr void mce_panic(const char *msg, struct mce *final, char *exp) 23221afaf18SBorislav Petkov { 23321afaf18SBorislav Petkov struct llist_node *pending; 23421afaf18SBorislav Petkov struct mce_evt_llist *l; 2353c7ce80aSBorislav Petkov int apei_err = 0; 2363c7ce80aSBorislav Petkov 2373c7ce80aSBorislav Petkov /* 2383c7ce80aSBorislav Petkov * Allow instrumentation around external facilities usage. Not that it 2393c7ce80aSBorislav Petkov * matters a whole lot since the machine is going to panic anyway. 2403c7ce80aSBorislav Petkov */ 2413c7ce80aSBorislav Petkov instrumentation_begin(); 24221afaf18SBorislav Petkov 24321afaf18SBorislav Petkov if (!fake_panic) { 24421afaf18SBorislav Petkov /* 24521afaf18SBorislav Petkov * Make sure only one CPU runs in machine check panic 24621afaf18SBorislav Petkov */ 24721afaf18SBorislav Petkov if (atomic_inc_return(&mce_panicked) > 1) 24821afaf18SBorislav Petkov wait_for_panic(); 24921afaf18SBorislav Petkov barrier(); 25021afaf18SBorislav Petkov 25121afaf18SBorislav Petkov bust_spinlocks(1); 25221afaf18SBorislav Petkov console_verbose(); 25321afaf18SBorislav Petkov } else { 25421afaf18SBorislav Petkov /* Don't log too much for fake panic */ 25521afaf18SBorislav Petkov if (atomic_inc_return(&mce_fake_panicked) > 1) 2563c7ce80aSBorislav Petkov goto out; 25721afaf18SBorislav Petkov } 25821afaf18SBorislav Petkov pending = mce_gen_pool_prepare_records(); 25921afaf18SBorislav Petkov /* First print corrected ones that are still unlogged */ 26021afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 26121afaf18SBorislav Petkov struct mce *m = &l->mce; 26221afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) { 26321afaf18SBorislav Petkov print_mce(m); 26421afaf18SBorislav Petkov if (!apei_err) 26521afaf18SBorislav Petkov apei_err = apei_write_mce(m); 26621afaf18SBorislav Petkov } 26721afaf18SBorislav Petkov } 26821afaf18SBorislav Petkov /* Now print uncorrected but with the final one last */ 26921afaf18SBorislav Petkov llist_for_each_entry(l, pending, llnode) { 27021afaf18SBorislav Petkov struct mce *m = &l->mce; 27121afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_UC)) 27221afaf18SBorislav Petkov continue; 27321afaf18SBorislav Petkov if (!final || mce_cmp(m, final)) { 27421afaf18SBorislav Petkov print_mce(m); 27521afaf18SBorislav Petkov if (!apei_err) 27621afaf18SBorislav Petkov apei_err = apei_write_mce(m); 27721afaf18SBorislav Petkov } 27821afaf18SBorislav Petkov } 27921afaf18SBorislav Petkov if (final) { 28021afaf18SBorislav Petkov print_mce(final); 28121afaf18SBorislav Petkov if (!apei_err) 28221afaf18SBorislav Petkov apei_err = apei_write_mce(final); 28321afaf18SBorislav Petkov } 28421afaf18SBorislav Petkov if (exp) 28521afaf18SBorislav Petkov pr_emerg(HW_ERR "Machine check: %s\n", exp); 28621afaf18SBorislav Petkov if (!fake_panic) { 28721afaf18SBorislav Petkov if (panic_timeout == 0) 28821afaf18SBorislav Petkov panic_timeout = mca_cfg.panic_timeout; 28921afaf18SBorislav Petkov panic(msg); 29021afaf18SBorislav Petkov } else 29121afaf18SBorislav Petkov pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); 2923c7ce80aSBorislav Petkov 2933c7ce80aSBorislav Petkov out: 2943c7ce80aSBorislav Petkov instrumentation_end(); 29521afaf18SBorislav Petkov } 29621afaf18SBorislav Petkov 29721afaf18SBorislav Petkov /* Support code for software error injection */ 29821afaf18SBorislav Petkov 29921afaf18SBorislav Petkov static int msr_to_offset(u32 msr) 30021afaf18SBorislav Petkov { 30121afaf18SBorislav Petkov unsigned bank = __this_cpu_read(injectm.bank); 30221afaf18SBorislav Petkov 30321afaf18SBorislav Petkov if (msr == mca_cfg.rip_msr) 30421afaf18SBorislav Petkov return offsetof(struct mce, ip); 3058121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_STATUS)) 30621afaf18SBorislav Petkov return offsetof(struct mce, status); 3078121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_ADDR)) 30821afaf18SBorislav Petkov return offsetof(struct mce, addr); 3098121b8f9SBorislav Petkov if (msr == mca_msr_reg(bank, MCA_MISC)) 31021afaf18SBorislav Petkov return offsetof(struct mce, misc); 31121afaf18SBorislav Petkov if (msr == MSR_IA32_MCG_STATUS) 31221afaf18SBorislav Petkov return offsetof(struct mce, mcgstatus); 31321afaf18SBorislav Petkov return -1; 31421afaf18SBorislav Petkov } 31521afaf18SBorislav Petkov 31646d28947SThomas Gleixner void ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr) 317e2def7d4SBorislav Petkov { 318e42404afSThomas Gleixner if (wrmsr) { 319e42404afSThomas Gleixner pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n", 320e42404afSThomas Gleixner (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax, 321e42404afSThomas Gleixner regs->ip, (void *)regs->ip); 322e42404afSThomas Gleixner } else { 323e2def7d4SBorislav Petkov pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n", 324e2def7d4SBorislav Petkov (unsigned int)regs->cx, regs->ip, (void *)regs->ip); 325e42404afSThomas Gleixner } 326e2def7d4SBorislav Petkov 327e2def7d4SBorislav Petkov show_stack_regs(regs); 328e2def7d4SBorislav Petkov 329e2def7d4SBorislav Petkov panic("MCA architectural violation!\n"); 330e2def7d4SBorislav Petkov 331e2def7d4SBorislav Petkov while (true) 332e2def7d4SBorislav Petkov cpu_relax(); 333e42404afSThomas Gleixner } 334e2def7d4SBorislav Petkov 33521afaf18SBorislav Petkov /* MSR access wrappers used for error injection */ 33688f66a42SBorislav Petkov noinstr u64 mce_rdmsrl(u32 msr) 33721afaf18SBorislav Petkov { 338e2def7d4SBorislav Petkov DECLARE_ARGS(val, low, high); 33921afaf18SBorislav Petkov 34021afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 341e1007770SBorislav Petkov int offset; 342e1007770SBorislav Petkov u64 ret; 34321afaf18SBorislav Petkov 344e1007770SBorislav Petkov instrumentation_begin(); 345e1007770SBorislav Petkov 346e1007770SBorislav Petkov offset = msr_to_offset(msr); 34721afaf18SBorislav Petkov if (offset < 0) 348e1007770SBorislav Petkov ret = 0; 349e1007770SBorislav Petkov else 350e1007770SBorislav Petkov ret = *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); 351e1007770SBorislav Petkov 352e1007770SBorislav Petkov instrumentation_end(); 353e1007770SBorislav Petkov 354e1007770SBorislav Petkov return ret; 35521afaf18SBorislav Petkov } 35621afaf18SBorislav Petkov 35721afaf18SBorislav Petkov /* 358e2def7d4SBorislav Petkov * RDMSR on MCA MSRs should not fault. If they do, this is very much an 359e2def7d4SBorislav Petkov * architectural violation and needs to be reported to hw vendor. Panic 360e2def7d4SBorislav Petkov * the box to not allow any further progress. 36121afaf18SBorislav Petkov */ 362e2def7d4SBorislav Petkov asm volatile("1: rdmsr\n" 363e2def7d4SBorislav Petkov "2:\n" 36446d28947SThomas Gleixner _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR_IN_MCE) 365e2def7d4SBorislav Petkov : EAX_EDX_RET(val, low, high) : "c" (msr)); 366e2def7d4SBorislav Petkov 367e2def7d4SBorislav Petkov 368e2def7d4SBorislav Petkov return EAX_EDX_VAL(val, low, high); 36921afaf18SBorislav Petkov } 37021afaf18SBorislav Petkov 371e1007770SBorislav Petkov static noinstr void mce_wrmsrl(u32 msr, u64 v) 37221afaf18SBorislav Petkov { 373e2def7d4SBorislav Petkov u32 low, high; 374e2def7d4SBorislav Petkov 37521afaf18SBorislav Petkov if (__this_cpu_read(injectm.finished)) { 376e1007770SBorislav Petkov int offset; 37721afaf18SBorislav Petkov 378e1007770SBorislav Petkov instrumentation_begin(); 379e1007770SBorislav Petkov 380e1007770SBorislav Petkov offset = msr_to_offset(msr); 38121afaf18SBorislav Petkov if (offset >= 0) 38221afaf18SBorislav Petkov *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; 383e1007770SBorislav Petkov 384e1007770SBorislav Petkov instrumentation_end(); 385e1007770SBorislav Petkov 38621afaf18SBorislav Petkov return; 38721afaf18SBorislav Petkov } 388e2def7d4SBorislav Petkov 389e2def7d4SBorislav Petkov low = (u32)v; 390e2def7d4SBorislav Petkov high = (u32)(v >> 32); 391e2def7d4SBorislav Petkov 392e2def7d4SBorislav Petkov /* See comment in mce_rdmsrl() */ 393e2def7d4SBorislav Petkov asm volatile("1: wrmsr\n" 394e2def7d4SBorislav Petkov "2:\n" 39546d28947SThomas Gleixner _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR_IN_MCE) 396e2def7d4SBorislav Petkov : : "c" (msr), "a"(low), "d" (high) : "memory"); 39721afaf18SBorislav Petkov } 39821afaf18SBorislav Petkov 39921afaf18SBorislav Petkov /* 40021afaf18SBorislav Petkov * Collect all global (w.r.t. this processor) status about this machine 40121afaf18SBorislav Petkov * check into our "mce" struct so that we can use it later to assess 40221afaf18SBorislav Petkov * the severity of the problem as we read per-bank specific details. 40321afaf18SBorislav Petkov */ 404487d654dSBorislav Petkov static noinstr void mce_gather_info(struct mce *m, struct pt_regs *regs) 40521afaf18SBorislav Petkov { 406487d654dSBorislav Petkov /* 407487d654dSBorislav Petkov * Enable instrumentation around mce_setup() which calls external 408487d654dSBorislav Petkov * facilities. 409487d654dSBorislav Petkov */ 410487d654dSBorislav Petkov instrumentation_begin(); 41121afaf18SBorislav Petkov mce_setup(m); 412487d654dSBorislav Petkov instrumentation_end(); 41321afaf18SBorislav Petkov 41421afaf18SBorislav Petkov m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 41521afaf18SBorislav Petkov if (regs) { 41621afaf18SBorislav Petkov /* 41721afaf18SBorislav Petkov * Get the address of the instruction at the time of 41821afaf18SBorislav Petkov * the machine check error. 41921afaf18SBorislav Petkov */ 42021afaf18SBorislav Petkov if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { 42121afaf18SBorislav Petkov m->ip = regs->ip; 42221afaf18SBorislav Petkov m->cs = regs->cs; 42321afaf18SBorislav Petkov 42421afaf18SBorislav Petkov /* 42521afaf18SBorislav Petkov * When in VM86 mode make the cs look like ring 3 42621afaf18SBorislav Petkov * always. This is a lie, but it's better than passing 42721afaf18SBorislav Petkov * the additional vm86 bit around everywhere. 42821afaf18SBorislav Petkov */ 42921afaf18SBorislav Petkov if (v8086_mode(regs)) 43021afaf18SBorislav Petkov m->cs |= 3; 43121afaf18SBorislav Petkov } 43221afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 43321afaf18SBorislav Petkov if (mca_cfg.rip_msr) 43421afaf18SBorislav Petkov m->ip = mce_rdmsrl(mca_cfg.rip_msr); 43521afaf18SBorislav Petkov } 43621afaf18SBorislav Petkov } 43721afaf18SBorislav Petkov 43821afaf18SBorislav Petkov int mce_available(struct cpuinfo_x86 *c) 43921afaf18SBorislav Petkov { 44021afaf18SBorislav Petkov if (mca_cfg.disabled) 44121afaf18SBorislav Petkov return 0; 44221afaf18SBorislav Petkov return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); 44321afaf18SBorislav Petkov } 44421afaf18SBorislav Petkov 44521afaf18SBorislav Petkov static void mce_schedule_work(void) 44621afaf18SBorislav Petkov { 44721afaf18SBorislav Petkov if (!mce_gen_pool_empty()) 44821afaf18SBorislav Petkov schedule_work(&mce_work); 44921afaf18SBorislav Petkov } 45021afaf18SBorislav Petkov 45121afaf18SBorislav Petkov static void mce_irq_work_cb(struct irq_work *entry) 45221afaf18SBorislav Petkov { 45321afaf18SBorislav Petkov mce_schedule_work(); 45421afaf18SBorislav Petkov } 45521afaf18SBorislav Petkov 45621afaf18SBorislav Petkov /* 45721afaf18SBorislav Petkov * Check if the address reported by the CPU is in a format we can parse. 45821afaf18SBorislav Petkov * It would be possible to add code for most other cases, but all would 45921afaf18SBorislav Petkov * be somewhat complicated (e.g. segment offset would require an instruction 460d9f6e12fSIngo Molnar * parser). So only support physical addresses up to page granularity for now. 46121afaf18SBorislav Petkov */ 46221afaf18SBorislav Petkov int mce_usable_address(struct mce *m) 46321afaf18SBorislav Petkov { 46421afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_ADDRV)) 46521afaf18SBorislav Petkov return 0; 46621afaf18SBorislav Petkov 4676e898d2bSTony W Wang-oc /* Checks after this one are Intel/Zhaoxin-specific: */ 4686e898d2bSTony W Wang-oc if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && 4696e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) 47021afaf18SBorislav Petkov return 1; 47121afaf18SBorislav Petkov 47221afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_MISCV)) 47321afaf18SBorislav Petkov return 0; 47421afaf18SBorislav Petkov 47521afaf18SBorislav Petkov if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) 47621afaf18SBorislav Petkov return 0; 47721afaf18SBorislav Petkov 47821afaf18SBorislav Petkov if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) 47921afaf18SBorislav Petkov return 0; 48021afaf18SBorislav Petkov 48121afaf18SBorislav Petkov return 1; 48221afaf18SBorislav Petkov } 48321afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_usable_address); 48421afaf18SBorislav Petkov 48521afaf18SBorislav Petkov bool mce_is_memory_error(struct mce *m) 48621afaf18SBorislav Petkov { 4876e898d2bSTony W Wang-oc switch (m->cpuvendor) { 4886e898d2bSTony W Wang-oc case X86_VENDOR_AMD: 4896e898d2bSTony W Wang-oc case X86_VENDOR_HYGON: 49021afaf18SBorislav Petkov return amd_mce_is_memory_error(m); 4916e898d2bSTony W Wang-oc 4926e898d2bSTony W Wang-oc case X86_VENDOR_INTEL: 4936e898d2bSTony W Wang-oc case X86_VENDOR_ZHAOXIN: 49421afaf18SBorislav Petkov /* 49521afaf18SBorislav Petkov * Intel SDM Volume 3B - 15.9.2 Compound Error Codes 49621afaf18SBorislav Petkov * 49721afaf18SBorislav Petkov * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for 49821afaf18SBorislav Petkov * indicating a memory error. Bit 8 is used for indicating a 49921afaf18SBorislav Petkov * cache hierarchy error. The combination of bit 2 and bit 3 50021afaf18SBorislav Petkov * is used for indicating a `generic' cache hierarchy error 50121afaf18SBorislav Petkov * But we can't just blindly check the above bits, because if 50221afaf18SBorislav Petkov * bit 11 is set, then it is a bus/interconnect error - and 50321afaf18SBorislav Petkov * either way the above bits just gives more detail on what 50421afaf18SBorislav Petkov * bus/interconnect error happened. Note that bit 12 can be 50521afaf18SBorislav Petkov * ignored, as it's the "filter" bit. 50621afaf18SBorislav Petkov */ 50721afaf18SBorislav Petkov return (m->status & 0xef80) == BIT(7) || 50821afaf18SBorislav Petkov (m->status & 0xef00) == BIT(8) || 50921afaf18SBorislav Petkov (m->status & 0xeffc) == 0xc; 51021afaf18SBorislav Petkov 5116e898d2bSTony W Wang-oc default: 51221afaf18SBorislav Petkov return false; 51321afaf18SBorislav Petkov } 5146e898d2bSTony W Wang-oc } 51521afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_memory_error); 51621afaf18SBorislav Petkov 51717fae129STony Luck static bool whole_page(struct mce *m) 51817fae129STony Luck { 51917fae129STony Luck if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV)) 52017fae129STony Luck return true; 52117fae129STony Luck 52217fae129STony Luck return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT; 52317fae129STony Luck } 52417fae129STony Luck 52521afaf18SBorislav Petkov bool mce_is_correctable(struct mce *m) 52621afaf18SBorislav Petkov { 52721afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED) 52821afaf18SBorislav Petkov return false; 52921afaf18SBorislav Petkov 53021afaf18SBorislav Petkov if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED) 53121afaf18SBorislav Petkov return false; 53221afaf18SBorislav Petkov 53321afaf18SBorislav Petkov if (m->status & MCI_STATUS_UC) 53421afaf18SBorislav Petkov return false; 53521afaf18SBorislav Petkov 53621afaf18SBorislav Petkov return true; 53721afaf18SBorislav Petkov } 53821afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_is_correctable); 53921afaf18SBorislav Petkov 540c9c6d216STony Luck static int mce_early_notifier(struct notifier_block *nb, unsigned long val, 54121afaf18SBorislav Petkov void *data) 54221afaf18SBorislav Petkov { 54321afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 54421afaf18SBorislav Petkov 54521afaf18SBorislav Petkov if (!m) 54621afaf18SBorislav Petkov return NOTIFY_DONE; 54721afaf18SBorislav Petkov 54821afaf18SBorislav Petkov /* Emit the trace record: */ 54921afaf18SBorislav Petkov trace_mce_record(m); 55021afaf18SBorislav Petkov 55121afaf18SBorislav Petkov set_bit(0, &mce_need_notify); 55221afaf18SBorislav Petkov 55321afaf18SBorislav Petkov mce_notify_irq(); 55421afaf18SBorislav Petkov 55521afaf18SBorislav Petkov return NOTIFY_DONE; 55621afaf18SBorislav Petkov } 55721afaf18SBorislav Petkov 558c9c6d216STony Luck static struct notifier_block early_nb = { 559c9c6d216STony Luck .notifier_call = mce_early_notifier, 560c9c6d216STony Luck .priority = MCE_PRIO_EARLY, 56121afaf18SBorislav Petkov }; 56221afaf18SBorislav Petkov 5638438b84aSJan H. Schönherr static int uc_decode_notifier(struct notifier_block *nb, unsigned long val, 56421afaf18SBorislav Petkov void *data) 56521afaf18SBorislav Petkov { 56621afaf18SBorislav Petkov struct mce *mce = (struct mce *)data; 56721afaf18SBorislav Petkov unsigned long pfn; 56821afaf18SBorislav Petkov 5698438b84aSJan H. Schönherr if (!mce || !mce_usable_address(mce)) 57021afaf18SBorislav Petkov return NOTIFY_DONE; 57121afaf18SBorislav Petkov 5728438b84aSJan H. Schönherr if (mce->severity != MCE_AO_SEVERITY && 5738438b84aSJan H. Schönherr mce->severity != MCE_DEFERRED_SEVERITY) 5748438b84aSJan H. Schönherr return NOTIFY_DONE; 5758438b84aSJan H. Schönherr 5768a01ec97STony Luck pfn = (mce->addr & MCI_ADDR_PHYSADDR) >> PAGE_SHIFT; 57723ba710aSTony Luck if (!memory_failure(pfn, 0)) { 5785898b43aSJane Chu set_mce_nospec(pfn); 57923ba710aSTony Luck mce->kflags |= MCE_HANDLED_UC; 58023ba710aSTony Luck } 58121afaf18SBorislav Petkov 58221afaf18SBorislav Petkov return NOTIFY_OK; 58321afaf18SBorislav Petkov } 5848438b84aSJan H. Schönherr 5858438b84aSJan H. Schönherr static struct notifier_block mce_uc_nb = { 5868438b84aSJan H. Schönherr .notifier_call = uc_decode_notifier, 5878438b84aSJan H. Schönherr .priority = MCE_PRIO_UC, 58821afaf18SBorislav Petkov }; 58921afaf18SBorislav Petkov 59021afaf18SBorislav Petkov static int mce_default_notifier(struct notifier_block *nb, unsigned long val, 59121afaf18SBorislav Petkov void *data) 59221afaf18SBorislav Petkov { 59321afaf18SBorislav Petkov struct mce *m = (struct mce *)data; 59421afaf18SBorislav Petkov 59521afaf18SBorislav Petkov if (!m) 59621afaf18SBorislav Petkov return NOTIFY_DONE; 59721afaf18SBorislav Petkov 59843505646STony Luck if (mca_cfg.print_all || !m->kflags) 59921afaf18SBorislav Petkov __print_mce(m); 60021afaf18SBorislav Petkov 60121afaf18SBorislav Petkov return NOTIFY_DONE; 60221afaf18SBorislav Petkov } 60321afaf18SBorislav Petkov 60421afaf18SBorislav Petkov static struct notifier_block mce_default_nb = { 60521afaf18SBorislav Petkov .notifier_call = mce_default_notifier, 60621afaf18SBorislav Petkov /* lowest prio, we want it to run last. */ 60721afaf18SBorislav Petkov .priority = MCE_PRIO_LOWEST, 60821afaf18SBorislav Petkov }; 60921afaf18SBorislav Petkov 61021afaf18SBorislav Petkov /* 61121afaf18SBorislav Petkov * Read ADDR and MISC registers. 61221afaf18SBorislav Petkov */ 613db6c996dSBorislav Petkov static noinstr void mce_read_aux(struct mce *m, int i) 61421afaf18SBorislav Petkov { 61521afaf18SBorislav Petkov if (m->status & MCI_STATUS_MISCV) 6168121b8f9SBorislav Petkov m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC)); 61721afaf18SBorislav Petkov 61821afaf18SBorislav Petkov if (m->status & MCI_STATUS_ADDRV) { 6198121b8f9SBorislav Petkov m->addr = mce_rdmsrl(mca_msr_reg(i, MCA_ADDR)); 62021afaf18SBorislav Petkov 62121afaf18SBorislav Petkov /* 62221afaf18SBorislav Petkov * Mask the reported address by the reported granularity. 62321afaf18SBorislav Petkov */ 62421afaf18SBorislav Petkov if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { 62521afaf18SBorislav Petkov u8 shift = MCI_MISC_ADDR_LSB(m->misc); 62621afaf18SBorislav Petkov m->addr >>= shift; 62721afaf18SBorislav Petkov m->addr <<= shift; 62821afaf18SBorislav Petkov } 62921afaf18SBorislav Petkov 6302117654eSSmita Koralahalli smca_extract_err_addr(m); 63121afaf18SBorislav Petkov } 63221afaf18SBorislav Petkov 63321afaf18SBorislav Petkov if (mce_flags.smca) { 63421afaf18SBorislav Petkov m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); 63521afaf18SBorislav Petkov 63621afaf18SBorislav Petkov if (m->status & MCI_STATUS_SYNDV) 63721afaf18SBorislav Petkov m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); 63821afaf18SBorislav Petkov } 63921afaf18SBorislav Petkov } 64021afaf18SBorislav Petkov 64121afaf18SBorislav Petkov DEFINE_PER_CPU(unsigned, mce_poll_count); 64221afaf18SBorislav Petkov 64321afaf18SBorislav Petkov /* 64421afaf18SBorislav Petkov * Poll for corrected events or events that happened before reset. 64521afaf18SBorislav Petkov * Those are just logged through /dev/mcelog. 64621afaf18SBorislav Petkov * 64721afaf18SBorislav Petkov * This is executed in standard interrupt context. 64821afaf18SBorislav Petkov * 64921afaf18SBorislav Petkov * Note: spec recommends to panic for fatal unsignalled 65021afaf18SBorislav Petkov * errors here. However this would be quite problematic -- 65121afaf18SBorislav Petkov * we would need to reimplement the Monarch handling and 65221afaf18SBorislav Petkov * it would mess up the exclusion between exception handler 653312a4661SLinus Torvalds * and poll handler -- * so we skip this for now. 65421afaf18SBorislav Petkov * These cases should not happen anyways, or only when the CPU 65521afaf18SBorislav Petkov * is already totally * confused. In this case it's likely it will 65621afaf18SBorislav Petkov * not fully execute the machine check handler either. 65721afaf18SBorislav Petkov */ 65821afaf18SBorislav Petkov bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) 65921afaf18SBorislav Petkov { 660b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 66121afaf18SBorislav Petkov bool error_seen = false; 66221afaf18SBorislav Petkov struct mce m; 66321afaf18SBorislav Petkov int i; 66421afaf18SBorislav Petkov 66521afaf18SBorislav Petkov this_cpu_inc(mce_poll_count); 66621afaf18SBorislav Petkov 66721afaf18SBorislav Petkov mce_gather_info(&m, NULL); 66821afaf18SBorislav Petkov 66921afaf18SBorislav Petkov if (flags & MCP_TIMESTAMP) 67021afaf18SBorislav Petkov m.tsc = rdtsc(); 67121afaf18SBorislav Petkov 672c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 67321afaf18SBorislav Petkov if (!mce_banks[i].ctl || !test_bit(i, *b)) 67421afaf18SBorislav Petkov continue; 67521afaf18SBorislav Petkov 67621afaf18SBorislav Petkov m.misc = 0; 67721afaf18SBorislav Petkov m.addr = 0; 67821afaf18SBorislav Petkov m.bank = i; 67921afaf18SBorislav Petkov 68021afaf18SBorislav Petkov barrier(); 6818121b8f9SBorislav Petkov m.status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 682f19501aaSTony Luck 683f19501aaSTony Luck /* If this entry is not valid, ignore it */ 68421afaf18SBorislav Petkov if (!(m.status & MCI_STATUS_VAL)) 68521afaf18SBorislav Petkov continue; 68621afaf18SBorislav Petkov 68721afaf18SBorislav Petkov /* 688f19501aaSTony Luck * If we are logging everything (at CPU online) or this 689f19501aaSTony Luck * is a corrected error, then we must log it. 69021afaf18SBorislav Petkov */ 691f19501aaSTony Luck if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC)) 692f19501aaSTony Luck goto log_it; 693f19501aaSTony Luck 694f19501aaSTony Luck /* 695f19501aaSTony Luck * Newer Intel systems that support software error 696f19501aaSTony Luck * recovery need to make additional checks. Other 697f19501aaSTony Luck * CPUs should skip over uncorrected errors, but log 698f19501aaSTony Luck * everything else. 699f19501aaSTony Luck */ 700f19501aaSTony Luck if (!mca_cfg.ser) { 701f19501aaSTony Luck if (m.status & MCI_STATUS_UC) 702f19501aaSTony Luck continue; 703f19501aaSTony Luck goto log_it; 704f19501aaSTony Luck } 705f19501aaSTony Luck 706f19501aaSTony Luck /* Log "not enabled" (speculative) errors */ 707f19501aaSTony Luck if (!(m.status & MCI_STATUS_EN)) 708f19501aaSTony Luck goto log_it; 709f19501aaSTony Luck 710f19501aaSTony Luck /* 711f19501aaSTony Luck * Log UCNA (SDM: 15.6.3 "UCR Error Classification") 712f19501aaSTony Luck * UC == 1 && PCC == 0 && S == 0 713f19501aaSTony Luck */ 714f19501aaSTony Luck if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S)) 715f19501aaSTony Luck goto log_it; 716f19501aaSTony Luck 717f19501aaSTony Luck /* 718f19501aaSTony Luck * Skip anything else. Presumption is that our read of this 719f19501aaSTony Luck * bank is racing with a machine check. Leave the log alone 720f19501aaSTony Luck * for do_machine_check() to deal with it. 721f19501aaSTony Luck */ 72221afaf18SBorislav Petkov continue; 72321afaf18SBorislav Petkov 724f19501aaSTony Luck log_it: 72521afaf18SBorislav Petkov error_seen = true; 72621afaf18SBorislav Petkov 72790454e49SJan H. Schönherr if (flags & MCP_DONTLOG) 72890454e49SJan H. Schönherr goto clear_it; 72990454e49SJan H. Schönherr 73021afaf18SBorislav Petkov mce_read_aux(&m, i); 7317f1b8e0dSBorislav Petkov m.severity = mce_severity(&m, NULL, NULL, false); 73221afaf18SBorislav Petkov /* 73321afaf18SBorislav Petkov * Don't get the IP here because it's unlikely to 73421afaf18SBorislav Petkov * have anything to do with the actual error location. 73521afaf18SBorislav Petkov */ 73621afaf18SBorislav Petkov 73790454e49SJan H. Schönherr if (mca_cfg.dont_log_ce && !mce_usable_address(&m)) 73890454e49SJan H. Schönherr goto clear_it; 73990454e49SJan H. Schönherr 7403bff147bSBorislav Petkov if (flags & MCP_QUEUE_LOG) 7413bff147bSBorislav Petkov mce_gen_pool_add(&m); 7423bff147bSBorislav Petkov else 74390454e49SJan H. Schönherr mce_log(&m); 74490454e49SJan H. Schönherr 74590454e49SJan H. Schönherr clear_it: 74621afaf18SBorislav Petkov /* 74721afaf18SBorislav Petkov * Clear state for this bank. 74821afaf18SBorislav Petkov */ 7498121b8f9SBorislav Petkov mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 75021afaf18SBorislav Petkov } 75121afaf18SBorislav Petkov 75221afaf18SBorislav Petkov /* 75321afaf18SBorislav Petkov * Don't clear MCG_STATUS here because it's only defined for 75421afaf18SBorislav Petkov * exceptions. 75521afaf18SBorislav Petkov */ 75621afaf18SBorislav Petkov 75721afaf18SBorislav Petkov sync_core(); 75821afaf18SBorislav Petkov 75921afaf18SBorislav Petkov return error_seen; 76021afaf18SBorislav Petkov } 76121afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(machine_check_poll); 76221afaf18SBorislav Petkov 76321afaf18SBorislav Petkov /* 764cc466666SBorislav Petkov * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and 765cc466666SBorislav Petkov * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM 766cc466666SBorislav Petkov * Vol 3B Table 15-20). But this confuses both the code that determines 767cc466666SBorislav Petkov * whether the machine check occurred in kernel or user mode, and also 768cc466666SBorislav Petkov * the severity assessment code. Pretend that EIPV was set, and take the 769cc466666SBorislav Petkov * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. 770cc466666SBorislav Petkov */ 771f11445baSBorislav Petkov static __always_inline void 772f11445baSBorislav Petkov quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) 773cc466666SBorislav Petkov { 774cc466666SBorislav Petkov if (bank != 0) 775cc466666SBorislav Petkov return; 776cc466666SBorislav Petkov if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) 777cc466666SBorislav Petkov return; 778cc466666SBorislav Petkov if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| 779cc466666SBorislav Petkov MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| 780cc466666SBorislav Petkov MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| 781cc466666SBorislav Petkov MCACOD)) != 782cc466666SBorislav Petkov (MCI_STATUS_UC|MCI_STATUS_EN| 783cc466666SBorislav Petkov MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| 784cc466666SBorislav Petkov MCI_STATUS_AR|MCACOD_INSTR)) 785cc466666SBorislav Petkov return; 786cc466666SBorislav Petkov 787cc466666SBorislav Petkov m->mcgstatus |= MCG_STATUS_EIPV; 788cc466666SBorislav Petkov m->ip = regs->ip; 789cc466666SBorislav Petkov m->cs = regs->cs; 790cc466666SBorislav Petkov } 791cc466666SBorislav Petkov 792cc466666SBorislav Petkov /* 7938ca97812SJue Wang * Disable fast string copy and return from the MCE handler upon the first SRAR 7948ca97812SJue Wang * MCE on bank 1 due to a CPU erratum on Intel Skylake/Cascade Lake/Cooper Lake 7958ca97812SJue Wang * CPUs. 7968ca97812SJue Wang * The fast string copy instructions ("REP; MOVS*") could consume an 7978ca97812SJue Wang * uncorrectable memory error in the cache line _right after_ the desired region 7988ca97812SJue Wang * to copy and raise an MCE with RIP pointing to the instruction _after_ the 7998ca97812SJue Wang * "REP; MOVS*". 8008ca97812SJue Wang * This mitigation addresses the issue completely with the caveat of performance 8018ca97812SJue Wang * degradation on the CPU affected. This is still better than the OS crashing on 8028ca97812SJue Wang * MCEs raised on an irrelevant process due to "REP; MOVS*" accesses from a 8038ca97812SJue Wang * kernel context (e.g., copy_page). 8048ca97812SJue Wang * 8058ca97812SJue Wang * Returns true when fast string copy on CPU has been disabled. 8068ca97812SJue Wang */ 8078ca97812SJue Wang static noinstr bool quirk_skylake_repmov(void) 8088ca97812SJue Wang { 8098ca97812SJue Wang u64 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 8108ca97812SJue Wang u64 misc_enable = mce_rdmsrl(MSR_IA32_MISC_ENABLE); 8118ca97812SJue Wang u64 mc1_status; 8128ca97812SJue Wang 8138ca97812SJue Wang /* 8148ca97812SJue Wang * Apply the quirk only to local machine checks, i.e., no broadcast 8158ca97812SJue Wang * sync is needed. 8168ca97812SJue Wang */ 8178ca97812SJue Wang if (!(mcgstatus & MCG_STATUS_LMCES) || 8188ca97812SJue Wang !(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) 8198ca97812SJue Wang return false; 8208ca97812SJue Wang 8218ca97812SJue Wang mc1_status = mce_rdmsrl(MSR_IA32_MCx_STATUS(1)); 8228ca97812SJue Wang 8238ca97812SJue Wang /* Check for a software-recoverable data fetch error. */ 8248ca97812SJue Wang if ((mc1_status & 8258ca97812SJue Wang (MCI_STATUS_VAL | MCI_STATUS_OVER | MCI_STATUS_UC | MCI_STATUS_EN | 8268ca97812SJue Wang MCI_STATUS_ADDRV | MCI_STATUS_MISCV | MCI_STATUS_PCC | 8278ca97812SJue Wang MCI_STATUS_AR | MCI_STATUS_S)) == 8288ca97812SJue Wang (MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | 8298ca97812SJue Wang MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 8308ca97812SJue Wang MCI_STATUS_AR | MCI_STATUS_S)) { 8318ca97812SJue Wang misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING; 8328ca97812SJue Wang mce_wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 8338ca97812SJue Wang mce_wrmsrl(MSR_IA32_MCx_STATUS(1), 0); 8348ca97812SJue Wang 8358ca97812SJue Wang instrumentation_begin(); 8368ca97812SJue Wang pr_err_once("Erratum detected, disable fast string copy instructions.\n"); 8378ca97812SJue Wang instrumentation_end(); 8388ca97812SJue Wang 8398ca97812SJue Wang return true; 8408ca97812SJue Wang } 8418ca97812SJue Wang 8428ca97812SJue Wang return false; 8438ca97812SJue Wang } 8448ca97812SJue Wang 8458ca97812SJue Wang /* 84621afaf18SBorislav Petkov * Do a quick check if any of the events requires a panic. 84721afaf18SBorislav Petkov * This decides if we keep the events around or clear them. 84821afaf18SBorislav Petkov */ 849f11445baSBorislav Petkov static __always_inline int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, 85021afaf18SBorislav Petkov struct pt_regs *regs) 85121afaf18SBorislav Petkov { 8527a8bc2b0SJan H. Schönherr char *tmp = *msg; 85321afaf18SBorislav Petkov int i; 85421afaf18SBorislav Petkov 855c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 8568121b8f9SBorislav Petkov m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 85721afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 85821afaf18SBorislav Petkov continue; 85921afaf18SBorislav Petkov 860f11445baSBorislav Petkov arch___set_bit(i, validp); 861cc466666SBorislav Petkov if (mce_flags.snb_ifu_quirk) 862cc466666SBorislav Petkov quirk_sandybridge_ifu(i, m, regs); 86321afaf18SBorislav Petkov 864d28af26fSTony Luck m->bank = i; 8657f1b8e0dSBorislav Petkov if (mce_severity(m, regs, &tmp, true) >= MCE_PANIC_SEVERITY) { 86621afaf18SBorislav Petkov mce_read_aux(m, i); 86721afaf18SBorislav Petkov *msg = tmp; 86821afaf18SBorislav Petkov return 1; 86921afaf18SBorislav Petkov } 87021afaf18SBorislav Petkov } 87121afaf18SBorislav Petkov return 0; 87221afaf18SBorislav Petkov } 87321afaf18SBorislav Petkov 87421afaf18SBorislav Petkov /* 87521afaf18SBorislav Petkov * Variable to establish order between CPUs while scanning. 87621afaf18SBorislav Petkov * Each CPU spins initially until executing is equal its number. 87721afaf18SBorislav Petkov */ 87821afaf18SBorislav Petkov static atomic_t mce_executing; 87921afaf18SBorislav Petkov 88021afaf18SBorislav Petkov /* 88121afaf18SBorislav Petkov * Defines order of CPUs on entry. First CPU becomes Monarch. 88221afaf18SBorislav Petkov */ 88321afaf18SBorislav Petkov static atomic_t mce_callin; 88421afaf18SBorislav Petkov 88521afaf18SBorislav Petkov /* 8867bb39313SPaul E. McKenney * Track which CPUs entered the MCA broadcast synchronization and which not in 8877bb39313SPaul E. McKenney * order to print holdouts. 8887bb39313SPaul E. McKenney */ 8897bb39313SPaul E. McKenney static cpumask_t mce_missing_cpus = CPU_MASK_ALL; 8907bb39313SPaul E. McKenney 8917bb39313SPaul E. McKenney /* 89221afaf18SBorislav Petkov * Check if a timeout waiting for other CPUs happened. 89321afaf18SBorislav Petkov */ 894edb3d07eSBorislav Petkov static noinstr int mce_timed_out(u64 *t, const char *msg) 89521afaf18SBorislav Petkov { 896edb3d07eSBorislav Petkov int ret = 0; 897edb3d07eSBorislav Petkov 898edb3d07eSBorislav Petkov /* Enable instrumentation around calls to external facilities */ 899edb3d07eSBorislav Petkov instrumentation_begin(); 900edb3d07eSBorislav Petkov 90121afaf18SBorislav Petkov /* 90221afaf18SBorislav Petkov * The others already did panic for some reason. 90321afaf18SBorislav Petkov * Bail out like in a timeout. 90421afaf18SBorislav Petkov * rmb() to tell the compiler that system_state 90521afaf18SBorislav Petkov * might have been modified by someone else. 90621afaf18SBorislav Petkov */ 90721afaf18SBorislav Petkov rmb(); 90821afaf18SBorislav Petkov if (atomic_read(&mce_panicked)) 90921afaf18SBorislav Petkov wait_for_panic(); 91021afaf18SBorislav Petkov if (!mca_cfg.monarch_timeout) 91121afaf18SBorislav Petkov goto out; 91221afaf18SBorislav Petkov if ((s64)*t < SPINUNIT) { 9137bb39313SPaul E. McKenney if (cpumask_and(&mce_missing_cpus, cpu_online_mask, &mce_missing_cpus)) 9147bb39313SPaul E. McKenney pr_emerg("CPUs not responding to MCE broadcast (may include false positives): %*pbl\n", 9157bb39313SPaul E. McKenney cpumask_pr_args(&mce_missing_cpus)); 91621afaf18SBorislav Petkov mce_panic(msg, NULL, NULL); 9177f1b8e0dSBorislav Petkov 918edb3d07eSBorislav Petkov ret = 1; 919edb3d07eSBorislav Petkov goto out; 92021afaf18SBorislav Petkov } 92121afaf18SBorislav Petkov *t -= SPINUNIT; 922edb3d07eSBorislav Petkov 92321afaf18SBorislav Petkov out: 92421afaf18SBorislav Petkov touch_nmi_watchdog(); 925edb3d07eSBorislav Petkov 926edb3d07eSBorislav Petkov instrumentation_end(); 927edb3d07eSBorislav Petkov 928edb3d07eSBorislav Petkov return ret; 92921afaf18SBorislav Petkov } 93021afaf18SBorislav Petkov 93121afaf18SBorislav Petkov /* 93221afaf18SBorislav Petkov * The Monarch's reign. The Monarch is the CPU who entered 93321afaf18SBorislav Petkov * the machine check handler first. It waits for the others to 93421afaf18SBorislav Petkov * raise the exception too and then grades them. When any 93521afaf18SBorislav Petkov * error is fatal panic. Only then let the others continue. 93621afaf18SBorislav Petkov * 93721afaf18SBorislav Petkov * The other CPUs entering the MCE handler will be controlled by the 93821afaf18SBorislav Petkov * Monarch. They are called Subjects. 93921afaf18SBorislav Petkov * 94021afaf18SBorislav Petkov * This way we prevent any potential data corruption in a unrecoverable case 94121afaf18SBorislav Petkov * and also makes sure always all CPU's errors are examined. 94221afaf18SBorislav Petkov * 94321afaf18SBorislav Petkov * Also this detects the case of a machine check event coming from outer 94421afaf18SBorislav Petkov * space (not detected by any CPUs) In this case some external agent wants 94521afaf18SBorislav Petkov * us to shut down, so panic too. 94621afaf18SBorislav Petkov * 94721afaf18SBorislav Petkov * The other CPUs might still decide to panic if the handler happens 94821afaf18SBorislav Petkov * in a unrecoverable place, but in this case the system is in a semi-stable 94921afaf18SBorislav Petkov * state and won't corrupt anything by itself. It's ok to let the others 95021afaf18SBorislav Petkov * continue for a bit first. 95121afaf18SBorislav Petkov * 95221afaf18SBorislav Petkov * All the spin loops have timeouts; when a timeout happens a CPU 95321afaf18SBorislav Petkov * typically elects itself to be Monarch. 95421afaf18SBorislav Petkov */ 95521afaf18SBorislav Petkov static void mce_reign(void) 95621afaf18SBorislav Petkov { 95721afaf18SBorislav Petkov int cpu; 95821afaf18SBorislav Petkov struct mce *m = NULL; 95921afaf18SBorislav Petkov int global_worst = 0; 96021afaf18SBorislav Petkov char *msg = NULL; 96121afaf18SBorislav Petkov 96221afaf18SBorislav Petkov /* 96321afaf18SBorislav Petkov * This CPU is the Monarch and the other CPUs have run 96421afaf18SBorislav Petkov * through their handlers. 96521afaf18SBorislav Petkov * Grade the severity of the errors of all the CPUs. 96621afaf18SBorislav Petkov */ 96721afaf18SBorislav Petkov for_each_possible_cpu(cpu) { 96813c877f4STony Luck struct mce *mtmp = &per_cpu(mces_seen, cpu); 96913c877f4STony Luck 97013c877f4STony Luck if (mtmp->severity > global_worst) { 97113c877f4STony Luck global_worst = mtmp->severity; 97221afaf18SBorislav Petkov m = &per_cpu(mces_seen, cpu); 97321afaf18SBorislav Petkov } 97421afaf18SBorislav Petkov } 97521afaf18SBorislav Petkov 97621afaf18SBorislav Petkov /* 97721afaf18SBorislav Petkov * Cannot recover? Panic here then. 97821afaf18SBorislav Petkov * This dumps all the mces in the log buffer and stops the 97921afaf18SBorislav Petkov * other CPUs. 98021afaf18SBorislav Petkov */ 9817f1b8e0dSBorislav Petkov if (m && global_worst >= MCE_PANIC_SEVERITY) { 98213c877f4STony Luck /* call mce_severity() to get "msg" for panic */ 9837f1b8e0dSBorislav Petkov mce_severity(m, NULL, &msg, true); 98421afaf18SBorislav Petkov mce_panic("Fatal machine check", m, msg); 98513c877f4STony Luck } 98621afaf18SBorislav Petkov 98721afaf18SBorislav Petkov /* 98821afaf18SBorislav Petkov * For UC somewhere we let the CPU who detects it handle it. 98921afaf18SBorislav Petkov * Also must let continue the others, otherwise the handling 99021afaf18SBorislav Petkov * CPU could deadlock on a lock. 99121afaf18SBorislav Petkov */ 99221afaf18SBorislav Petkov 99321afaf18SBorislav Petkov /* 99421afaf18SBorislav Petkov * No machine check event found. Must be some external 99521afaf18SBorislav Petkov * source or one CPU is hung. Panic. 99621afaf18SBorislav Petkov */ 9977f1b8e0dSBorislav Petkov if (global_worst <= MCE_KEEP_SEVERITY) 99821afaf18SBorislav Petkov mce_panic("Fatal machine check from unknown source", NULL, NULL); 99921afaf18SBorislav Petkov 100021afaf18SBorislav Petkov /* 100121afaf18SBorislav Petkov * Now clear all the mces_seen so that they don't reappear on 100221afaf18SBorislav Petkov * the next mce. 100321afaf18SBorislav Petkov */ 100421afaf18SBorislav Petkov for_each_possible_cpu(cpu) 100521afaf18SBorislav Petkov memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); 100621afaf18SBorislav Petkov } 100721afaf18SBorislav Petkov 100821afaf18SBorislav Petkov static atomic_t global_nwo; 100921afaf18SBorislav Petkov 101021afaf18SBorislav Petkov /* 101121afaf18SBorislav Petkov * Start of Monarch synchronization. This waits until all CPUs have 101221afaf18SBorislav Petkov * entered the exception handler and then determines if any of them 101321afaf18SBorislav Petkov * saw a fatal event that requires panic. Then it executes them 101421afaf18SBorislav Petkov * in the entry order. 101521afaf18SBorislav Petkov * TBD double check parallel CPU hotunplug 101621afaf18SBorislav Petkov */ 1017e3d72e8eSBorislav Petkov static noinstr int mce_start(int *no_way_out) 101821afaf18SBorislav Petkov { 101921afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 1020e3d72e8eSBorislav Petkov int order, ret = -1; 102121afaf18SBorislav Petkov 102221afaf18SBorislav Petkov if (!timeout) 1023e3d72e8eSBorislav Petkov return ret; 102421afaf18SBorislav Petkov 1025f11445baSBorislav Petkov arch_atomic_add(*no_way_out, &global_nwo); 102621afaf18SBorislav Petkov /* 102721afaf18SBorislav Petkov * Rely on the implied barrier below, such that global_nwo 102821afaf18SBorislav Petkov * is updated before mce_callin. 102921afaf18SBorislav Petkov */ 1030f11445baSBorislav Petkov order = arch_atomic_inc_return(&mce_callin); 1031f11445baSBorislav Petkov arch_cpumask_clear_cpu(smp_processor_id(), &mce_missing_cpus); 103221afaf18SBorislav Petkov 1033e3d72e8eSBorislav Petkov /* Enable instrumentation around calls to external facilities */ 1034e3d72e8eSBorislav Petkov instrumentation_begin(); 1035e3d72e8eSBorislav Petkov 103621afaf18SBorislav Petkov /* 103721afaf18SBorislav Petkov * Wait for everyone. 103821afaf18SBorislav Petkov */ 1039f11445baSBorislav Petkov while (arch_atomic_read(&mce_callin) != num_online_cpus()) { 104021afaf18SBorislav Petkov if (mce_timed_out(&timeout, 104121afaf18SBorislav Petkov "Timeout: Not all CPUs entered broadcast exception handler")) { 1042f11445baSBorislav Petkov arch_atomic_set(&global_nwo, 0); 1043e3d72e8eSBorislav Petkov goto out; 104421afaf18SBorislav Petkov } 104521afaf18SBorislav Petkov ndelay(SPINUNIT); 104621afaf18SBorislav Petkov } 104721afaf18SBorislav Petkov 104821afaf18SBorislav Petkov /* 104921afaf18SBorislav Petkov * mce_callin should be read before global_nwo 105021afaf18SBorislav Petkov */ 105121afaf18SBorislav Petkov smp_rmb(); 105221afaf18SBorislav Petkov 105321afaf18SBorislav Petkov if (order == 1) { 105421afaf18SBorislav Petkov /* 105521afaf18SBorislav Petkov * Monarch: Starts executing now, the others wait. 105621afaf18SBorislav Petkov */ 1057f11445baSBorislav Petkov arch_atomic_set(&mce_executing, 1); 105821afaf18SBorislav Petkov } else { 105921afaf18SBorislav Petkov /* 106021afaf18SBorislav Petkov * Subject: Now start the scanning loop one by one in 106121afaf18SBorislav Petkov * the original callin order. 106221afaf18SBorislav Petkov * This way when there are any shared banks it will be 106321afaf18SBorislav Petkov * only seen by one CPU before cleared, avoiding duplicates. 106421afaf18SBorislav Petkov */ 1065f11445baSBorislav Petkov while (arch_atomic_read(&mce_executing) < order) { 106621afaf18SBorislav Petkov if (mce_timed_out(&timeout, 106721afaf18SBorislav Petkov "Timeout: Subject CPUs unable to finish machine check processing")) { 1068f11445baSBorislav Petkov arch_atomic_set(&global_nwo, 0); 1069e3d72e8eSBorislav Petkov goto out; 107021afaf18SBorislav Petkov } 107121afaf18SBorislav Petkov ndelay(SPINUNIT); 107221afaf18SBorislav Petkov } 107321afaf18SBorislav Petkov } 107421afaf18SBorislav Petkov 107521afaf18SBorislav Petkov /* 107621afaf18SBorislav Petkov * Cache the global no_way_out state. 107721afaf18SBorislav Petkov */ 1078f11445baSBorislav Petkov *no_way_out = arch_atomic_read(&global_nwo); 107921afaf18SBorislav Petkov 1080e3d72e8eSBorislav Petkov ret = order; 1081e3d72e8eSBorislav Petkov 1082e3d72e8eSBorislav Petkov out: 1083e3d72e8eSBorislav Petkov instrumentation_end(); 1084e3d72e8eSBorislav Petkov 1085e3d72e8eSBorislav Petkov return ret; 108621afaf18SBorislav Petkov } 108721afaf18SBorislav Petkov 108821afaf18SBorislav Petkov /* 108921afaf18SBorislav Petkov * Synchronize between CPUs after main scanning loop. 109021afaf18SBorislav Petkov * This invokes the bulk of the Monarch processing. 109121afaf18SBorislav Petkov */ 1092b4813539SBorislav Petkov static noinstr int mce_end(int order) 109321afaf18SBorislav Petkov { 109421afaf18SBorislav Petkov u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; 1095b4813539SBorislav Petkov int ret = -1; 1096b4813539SBorislav Petkov 1097b4813539SBorislav Petkov /* Allow instrumentation around external facilities. */ 1098b4813539SBorislav Petkov instrumentation_begin(); 109921afaf18SBorislav Petkov 110021afaf18SBorislav Petkov if (!timeout) 110121afaf18SBorislav Petkov goto reset; 110221afaf18SBorislav Petkov if (order < 0) 110321afaf18SBorislav Petkov goto reset; 110421afaf18SBorislav Petkov 110521afaf18SBorislav Petkov /* 110621afaf18SBorislav Petkov * Allow others to run. 110721afaf18SBorislav Petkov */ 110821afaf18SBorislav Petkov atomic_inc(&mce_executing); 110921afaf18SBorislav Petkov 111021afaf18SBorislav Petkov if (order == 1) { 111121afaf18SBorislav Petkov /* 111221afaf18SBorislav Petkov * Monarch: Wait for everyone to go through their scanning 111321afaf18SBorislav Petkov * loops. 111421afaf18SBorislav Petkov */ 1115ad669ec1SBorislav Petkov while (atomic_read(&mce_executing) <= num_online_cpus()) { 111621afaf18SBorislav Petkov if (mce_timed_out(&timeout, 111721afaf18SBorislav Petkov "Timeout: Monarch CPU unable to finish machine check processing")) 111821afaf18SBorislav Petkov goto reset; 111921afaf18SBorislav Petkov ndelay(SPINUNIT); 112021afaf18SBorislav Petkov } 112121afaf18SBorislav Petkov 112221afaf18SBorislav Petkov mce_reign(); 112321afaf18SBorislav Petkov barrier(); 112421afaf18SBorislav Petkov ret = 0; 112521afaf18SBorislav Petkov } else { 112621afaf18SBorislav Petkov /* 112721afaf18SBorislav Petkov * Subject: Wait for Monarch to finish. 112821afaf18SBorislav Petkov */ 112921afaf18SBorislav Petkov while (atomic_read(&mce_executing) != 0) { 113021afaf18SBorislav Petkov if (mce_timed_out(&timeout, 113121afaf18SBorislav Petkov "Timeout: Monarch CPU did not finish machine check processing")) 113221afaf18SBorislav Petkov goto reset; 113321afaf18SBorislav Petkov ndelay(SPINUNIT); 113421afaf18SBorislav Petkov } 113521afaf18SBorislav Petkov 113621afaf18SBorislav Petkov /* 113721afaf18SBorislav Petkov * Don't reset anything. That's done by the Monarch. 113821afaf18SBorislav Petkov */ 1139b4813539SBorislav Petkov ret = 0; 1140b4813539SBorislav Petkov goto out; 114121afaf18SBorislav Petkov } 114221afaf18SBorislav Petkov 114321afaf18SBorislav Petkov /* 114421afaf18SBorislav Petkov * Reset all global state. 114521afaf18SBorislav Petkov */ 114621afaf18SBorislav Petkov reset: 114721afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 114821afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 11497bb39313SPaul E. McKenney cpumask_setall(&mce_missing_cpus); 115021afaf18SBorislav Petkov barrier(); 115121afaf18SBorislav Petkov 115221afaf18SBorislav Petkov /* 115321afaf18SBorislav Petkov * Let others run again. 115421afaf18SBorislav Petkov */ 115521afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 1156b4813539SBorislav Petkov 1157b4813539SBorislav Petkov out: 1158b4813539SBorislav Petkov instrumentation_end(); 1159b4813539SBorislav Petkov 116021afaf18SBorislav Petkov return ret; 116121afaf18SBorislav Petkov } 116221afaf18SBorislav Petkov 1163f11445baSBorislav Petkov static __always_inline void mce_clear_state(unsigned long *toclear) 116421afaf18SBorislav Petkov { 116521afaf18SBorislav Petkov int i; 116621afaf18SBorislav Petkov 1167c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1168f11445baSBorislav Petkov if (arch_test_bit(i, toclear)) 11698121b8f9SBorislav Petkov mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 117021afaf18SBorislav Petkov } 117121afaf18SBorislav Petkov } 117221afaf18SBorislav Petkov 117321afaf18SBorislav Petkov /* 117421afaf18SBorislav Petkov * Cases where we avoid rendezvous handler timeout: 117521afaf18SBorislav Petkov * 1) If this CPU is offline. 117621afaf18SBorislav Petkov * 117721afaf18SBorislav Petkov * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to 117821afaf18SBorislav Petkov * skip those CPUs which remain looping in the 1st kernel - see 117921afaf18SBorislav Petkov * crash_nmi_callback(). 118021afaf18SBorislav Petkov * 118121afaf18SBorislav Petkov * Note: there still is a small window between kexec-ing and the new, 118221afaf18SBorislav Petkov * kdump kernel establishing a new #MC handler where a broadcasted MCE 118321afaf18SBorislav Petkov * might not get handled properly. 118421afaf18SBorislav Petkov */ 118594a46d31SThomas Gleixner static noinstr bool mce_check_crashing_cpu(void) 118621afaf18SBorislav Petkov { 118794a46d31SThomas Gleixner unsigned int cpu = smp_processor_id(); 118894a46d31SThomas Gleixner 118914d3b376SPeter Zijlstra if (arch_cpu_is_offline(cpu) || 119021afaf18SBorislav Petkov (crashing_cpu != -1 && crashing_cpu != cpu)) { 119121afaf18SBorislav Petkov u64 mcgstatus; 119221afaf18SBorislav Petkov 1193aedbdeabSThomas Gleixner mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS); 119470f0c230STony W Wang-oc 119570f0c230STony W Wang-oc if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { 119670f0c230STony W Wang-oc if (mcgstatus & MCG_STATUS_LMCES) 119770f0c230STony W Wang-oc return false; 119870f0c230STony W Wang-oc } 119970f0c230STony W Wang-oc 120021afaf18SBorislav Petkov if (mcgstatus & MCG_STATUS_RIPV) { 1201aedbdeabSThomas Gleixner __wrmsr(MSR_IA32_MCG_STATUS, 0, 0); 120221afaf18SBorislav Petkov return true; 120321afaf18SBorislav Petkov } 120421afaf18SBorislav Petkov } 120521afaf18SBorislav Petkov return false; 120621afaf18SBorislav Petkov } 120721afaf18SBorislav Petkov 120875581a20SBorislav Petkov static __always_inline int 120975581a20SBorislav Petkov __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final, 121075581a20SBorislav Petkov unsigned long *toclear, unsigned long *valid_banks, int no_way_out, 121175581a20SBorislav Petkov int *worst) 121221afaf18SBorislav Petkov { 1213b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 121421afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 121575581a20SBorislav Petkov int severity, i, taint = 0; 121621afaf18SBorislav Petkov 1217c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1218f11445baSBorislav Petkov arch___clear_bit(i, toclear); 1219f11445baSBorislav Petkov if (!arch_test_bit(i, valid_banks)) 122021afaf18SBorislav Petkov continue; 122121afaf18SBorislav Petkov 122221afaf18SBorislav Petkov if (!mce_banks[i].ctl) 122321afaf18SBorislav Petkov continue; 122421afaf18SBorislav Petkov 122521afaf18SBorislav Petkov m->misc = 0; 122621afaf18SBorislav Petkov m->addr = 0; 122721afaf18SBorislav Petkov m->bank = i; 122821afaf18SBorislav Petkov 12298121b8f9SBorislav Petkov m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 123021afaf18SBorislav Petkov if (!(m->status & MCI_STATUS_VAL)) 123121afaf18SBorislav Petkov continue; 123221afaf18SBorislav Petkov 123321afaf18SBorislav Petkov /* 123421afaf18SBorislav Petkov * Corrected or non-signaled errors are handled by 123521afaf18SBorislav Petkov * machine_check_poll(). Leave them alone, unless this panics. 123621afaf18SBorislav Petkov */ 123721afaf18SBorislav Petkov if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && 123821afaf18SBorislav Petkov !no_way_out) 123921afaf18SBorislav Petkov continue; 124021afaf18SBorislav Petkov 124121afaf18SBorislav Petkov /* Set taint even when machine check was not enabled. */ 124275581a20SBorislav Petkov taint++; 124321afaf18SBorislav Petkov 12447f1b8e0dSBorislav Petkov severity = mce_severity(m, regs, NULL, true); 124521afaf18SBorislav Petkov 124621afaf18SBorislav Petkov /* 124721afaf18SBorislav Petkov * When machine check was for corrected/deferred handler don't 124821afaf18SBorislav Petkov * touch, unless we're panicking. 124921afaf18SBorislav Petkov */ 125021afaf18SBorislav Petkov if ((severity == MCE_KEEP_SEVERITY || 125121afaf18SBorislav Petkov severity == MCE_UCNA_SEVERITY) && !no_way_out) 125221afaf18SBorislav Petkov continue; 125321afaf18SBorislav Petkov 1254f11445baSBorislav Petkov arch___set_bit(i, toclear); 125521afaf18SBorislav Petkov 125621afaf18SBorislav Petkov /* Machine check event was not enabled. Clear, but ignore. */ 125721afaf18SBorislav Petkov if (severity == MCE_NO_SEVERITY) 125821afaf18SBorislav Petkov continue; 125921afaf18SBorislav Petkov 126021afaf18SBorislav Petkov mce_read_aux(m, i); 126121afaf18SBorislav Petkov 126221afaf18SBorislav Petkov /* assuming valid severity level != 0 */ 126321afaf18SBorislav Petkov m->severity = severity; 126421afaf18SBorislav Petkov 126575581a20SBorislav Petkov /* 126675581a20SBorislav Petkov * Enable instrumentation around the mce_log() call which is 126775581a20SBorislav Petkov * done in #MC context, where instrumentation is disabled. 126875581a20SBorislav Petkov */ 126975581a20SBorislav Petkov instrumentation_begin(); 127021afaf18SBorislav Petkov mce_log(m); 127175581a20SBorislav Petkov instrumentation_end(); 127221afaf18SBorislav Petkov 127321afaf18SBorislav Petkov if (severity > *worst) { 127421afaf18SBorislav Petkov *final = *m; 127521afaf18SBorislav Petkov *worst = severity; 127621afaf18SBorislav Petkov } 127721afaf18SBorislav Petkov } 127821afaf18SBorislav Petkov 127921afaf18SBorislav Petkov /* mce_clear_state will clear *final, save locally for use later */ 128021afaf18SBorislav Petkov *m = *final; 128175581a20SBorislav Petkov 128275581a20SBorislav Petkov return taint; 128321afaf18SBorislav Petkov } 128421afaf18SBorislav Petkov 12855567d11cSPeter Zijlstra static void kill_me_now(struct callback_head *ch) 12865567d11cSPeter Zijlstra { 128781065b35STony Luck struct task_struct *p = container_of(ch, struct task_struct, mce_kill_me); 128881065b35STony Luck 128981065b35STony Luck p->mce_count = 0; 12905567d11cSPeter Zijlstra force_sig(SIGBUS); 12915567d11cSPeter Zijlstra } 12925567d11cSPeter Zijlstra 12935567d11cSPeter Zijlstra static void kill_me_maybe(struct callback_head *cb) 12945567d11cSPeter Zijlstra { 12955567d11cSPeter Zijlstra struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me); 12965567d11cSPeter Zijlstra int flags = MF_ACTION_REQUIRED; 12978a01ec97STony Luck unsigned long pfn; 1298a3f5d80eSNaoya Horiguchi int ret; 12995567d11cSPeter Zijlstra 130081065b35STony Luck p->mce_count = 0; 13015567d11cSPeter Zijlstra pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr); 130217fae129STony Luck 130317fae129STony Luck if (!p->mce_ripv) 13045567d11cSPeter Zijlstra flags |= MF_MUST_KILL; 13055567d11cSPeter Zijlstra 13068a01ec97STony Luck pfn = (p->mce_addr & MCI_ADDR_PHYSADDR) >> PAGE_SHIFT; 13078a01ec97STony Luck ret = memory_failure(pfn, flags); 1308a6e3cf70STony Luck if (!ret) { 13098a01ec97STony Luck set_mce_nospec(pfn); 13101e36d9c6STony Luck sync_core(); 13115567d11cSPeter Zijlstra return; 13125567d11cSPeter Zijlstra } 13135567d11cSPeter Zijlstra 1314a3f5d80eSNaoya Horiguchi /* 1315a3f5d80eSNaoya Horiguchi * -EHWPOISON from memory_failure() means that it already sent SIGBUS 1316d1fe111fSluofei * to the current process with the proper error info, 1317d1fe111fSluofei * -EOPNOTSUPP means hwpoison_filter() filtered the error event, 1318d1fe111fSluofei * 1319d1fe111fSluofei * In both cases, no further processing is required. 1320a3f5d80eSNaoya Horiguchi */ 1321d1fe111fSluofei if (ret == -EHWPOISON || ret == -EOPNOTSUPP) 1322a3f5d80eSNaoya Horiguchi return; 1323a3f5d80eSNaoya Horiguchi 13245567d11cSPeter Zijlstra pr_err("Memory error not recovered"); 13255567d11cSPeter Zijlstra kill_me_now(cb); 13265567d11cSPeter Zijlstra } 1327a6e3cf70STony Luck 1328a6e3cf70STony Luck static void kill_me_never(struct callback_head *cb) 1329a6e3cf70STony Luck { 1330a6e3cf70STony Luck struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me); 13318a01ec97STony Luck unsigned long pfn; 1332a6e3cf70STony Luck 1333a6e3cf70STony Luck p->mce_count = 0; 1334a6e3cf70STony Luck pr_err("Kernel accessed poison in user space at %llx\n", p->mce_addr); 13358a01ec97STony Luck pfn = (p->mce_addr & MCI_ADDR_PHYSADDR) >> PAGE_SHIFT; 13368a01ec97STony Luck if (!memory_failure(pfn, 0)) 13378a01ec97STony Luck set_mce_nospec(pfn); 133830063810STony Luck } 13395567d11cSPeter Zijlstra 1340a6e3cf70STony Luck static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callback_head *)) 1341c0ab7ffcSTony Luck { 134281065b35STony Luck int count = ++current->mce_count; 134381065b35STony Luck 134481065b35STony Luck /* First call, save all the details */ 134581065b35STony Luck if (count == 1) { 1346c0ab7ffcSTony Luck current->mce_addr = m->addr; 1347c0ab7ffcSTony Luck current->mce_kflags = m->kflags; 1348c0ab7ffcSTony Luck current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV); 1349c0ab7ffcSTony Luck current->mce_whole_page = whole_page(m); 1350a6e3cf70STony Luck current->mce_kill_me.func = func; 135181065b35STony Luck } 135281065b35STony Luck 135381065b35STony Luck /* Ten is likely overkill. Don't expect more than two faults before task_work() */ 135481065b35STony Luck if (count > 10) 135581065b35STony Luck mce_panic("Too many consecutive machine checks while accessing user data", m, msg); 135681065b35STony Luck 135781065b35STony Luck /* Second or later call, make sure page address matches the one from first call */ 135881065b35STony Luck if (count > 1 && (current->mce_addr >> PAGE_SHIFT) != (m->addr >> PAGE_SHIFT)) 135981065b35STony Luck mce_panic("Consecutive machine checks to different user pages", m, msg); 136081065b35STony Luck 136181065b35STony Luck /* Do not call task_work_add() more than once */ 136281065b35STony Luck if (count > 1) 136381065b35STony Luck return; 1364c0ab7ffcSTony Luck 136591989c70SJens Axboe task_work_add(current, ¤t->mce_kill_me, TWA_RESUME); 1366c0ab7ffcSTony Luck } 136721afaf18SBorislav Petkov 1368cbe1de16SBorislav Petkov /* Handle unconfigured int18 (should never happen) */ 1369cbe1de16SBorislav Petkov static noinstr void unexpected_machine_check(struct pt_regs *regs) 1370cbe1de16SBorislav Petkov { 1371cbe1de16SBorislav Petkov instrumentation_begin(); 1372cbe1de16SBorislav Petkov pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", 1373cbe1de16SBorislav Petkov smp_processor_id()); 1374cbe1de16SBorislav Petkov instrumentation_end(); 1375cbe1de16SBorislav Petkov } 1376cbe1de16SBorislav Petkov 137721afaf18SBorislav Petkov /* 1378487d654dSBorislav Petkov * The actual machine check handler. This only handles real exceptions when 1379487d654dSBorislav Petkov * something got corrupted coming in through int 18. 138021afaf18SBorislav Petkov * 1381487d654dSBorislav Petkov * This is executed in #MC context not subject to normal locking rules. 1382487d654dSBorislav Petkov * This implies that most kernel services cannot be safely used. Don't even 138321afaf18SBorislav Petkov * think about putting a printk in there! 138421afaf18SBorislav Petkov * 138521afaf18SBorislav Petkov * On Intel systems this is entered on all CPUs in parallel through 138621afaf18SBorislav Petkov * MCE broadcast. However some CPUs might be broken beyond repair, 138721afaf18SBorislav Petkov * so be always careful when synchronizing with others. 138855ba18d6SAndy Lutomirski * 138955ba18d6SAndy Lutomirski * Tracing and kprobes are disabled: if we interrupted a kernel context 139055ba18d6SAndy Lutomirski * with IF=1, we need to minimize stack usage. There are also recursion 139155ba18d6SAndy Lutomirski * issues: if the machine check was due to a failure of the memory 139255ba18d6SAndy Lutomirski * backing the user stack, tracing that reads the user stack will cause 139355ba18d6SAndy Lutomirski * potentially infinite recursion. 1394487d654dSBorislav Petkov * 1395487d654dSBorislav Petkov * Currently, the #MC handler calls out to a number of external facilities 1396487d654dSBorislav Petkov * and, therefore, allows instrumentation around them. The optimal thing to 1397487d654dSBorislav Petkov * have would be to do the absolutely minimal work required in #MC context 1398487d654dSBorislav Petkov * and have instrumentation disabled only around that. Further processing can 1399487d654dSBorislav Petkov * then happen in process context where instrumentation is allowed. Achieving 1400487d654dSBorislav Petkov * that requires careful auditing and modifications. Until then, the code 1401487d654dSBorislav Petkov * allows instrumentation temporarily, where required. * 140221afaf18SBorislav Petkov */ 14037f6fa101SIra Weiny noinstr void do_machine_check(struct pt_regs *regs) 140421afaf18SBorislav Petkov { 140575581a20SBorislav Petkov int worst = 0, order, no_way_out, kill_current_task, lmce, taint = 0; 1406cd5e0d1fSBorislav Petkov DECLARE_BITMAP(valid_banks, MAX_NR_BANKS) = { 0 }; 1407cd5e0d1fSBorislav Petkov DECLARE_BITMAP(toclear, MAX_NR_BANKS) = { 0 }; 140821afaf18SBorislav Petkov struct mce m, *final; 14097a8bc2b0SJan H. Schönherr char *msg = NULL; 1410cbe1de16SBorislav Petkov 1411cbe1de16SBorislav Petkov if (unlikely(mce_flags.p5)) 1412cbe1de16SBorislav Petkov return pentium_machine_check(regs); 1413cbe1de16SBorislav Petkov else if (unlikely(mce_flags.winchip)) 1414cbe1de16SBorislav Petkov return winchip_machine_check(regs); 1415cbe1de16SBorislav Petkov else if (unlikely(!mca_cfg.initialized)) 1416cbe1de16SBorislav Petkov return unexpected_machine_check(regs); 141721afaf18SBorislav Petkov 14188ca97812SJue Wang if (mce_flags.skx_repmov_quirk && quirk_skylake_repmov()) 14198ca97812SJue Wang goto clear; 14208ca97812SJue Wang 142121afaf18SBorislav Petkov /* 142221afaf18SBorislav Petkov * Establish sequential order between the CPUs entering the machine 142321afaf18SBorislav Petkov * check handler. 142421afaf18SBorislav Petkov */ 1425cbe1de16SBorislav Petkov order = -1; 142621afaf18SBorislav Petkov 142721afaf18SBorislav Petkov /* 142821afaf18SBorislav Petkov * If no_way_out gets set, there is no safe way to recover from this 14297f1b8e0dSBorislav Petkov * MCE. 143021afaf18SBorislav Petkov */ 1431cbe1de16SBorislav Petkov no_way_out = 0; 143221afaf18SBorislav Petkov 143321afaf18SBorislav Petkov /* 1434e1c06d23SGabriele Paoloni * If kill_current_task is not set, there might be a way to recover from this 143521afaf18SBorislav Petkov * error. 143621afaf18SBorislav Petkov */ 1437cbe1de16SBorislav Petkov kill_current_task = 0; 143821afaf18SBorislav Petkov 143921afaf18SBorislav Petkov /* 144021afaf18SBorislav Petkov * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES 144121afaf18SBorislav Petkov * on Intel. 144221afaf18SBorislav Petkov */ 1443cbe1de16SBorislav Petkov lmce = 1; 144421afaf18SBorislav Petkov 144521afaf18SBorislav Petkov this_cpu_inc(mce_exception_count); 144621afaf18SBorislav Petkov 144721afaf18SBorislav Petkov mce_gather_info(&m, regs); 144821afaf18SBorislav Petkov m.tsc = rdtsc(); 144921afaf18SBorislav Petkov 145021afaf18SBorislav Petkov final = this_cpu_ptr(&mces_seen); 145121afaf18SBorislav Petkov *final = m; 145221afaf18SBorislav Petkov 145321afaf18SBorislav Petkov no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); 145421afaf18SBorislav Petkov 145521afaf18SBorislav Petkov barrier(); 145621afaf18SBorislav Petkov 145721afaf18SBorislav Petkov /* 145821afaf18SBorislav Petkov * When no restart IP might need to kill or panic. 145921afaf18SBorislav Petkov * Assume the worst for now, but if we find the 146021afaf18SBorislav Petkov * severity is MCE_AR_SEVERITY we have other options. 146121afaf18SBorislav Petkov */ 146221afaf18SBorislav Petkov if (!(m.mcgstatus & MCG_STATUS_RIPV)) 14637f1b8e0dSBorislav Petkov kill_current_task = 1; 146421afaf18SBorislav Petkov /* 146521afaf18SBorislav Petkov * Check if this MCE is signaled to only this logical processor, 146670f0c230STony W Wang-oc * on Intel, Zhaoxin only. 146721afaf18SBorislav Petkov */ 146870f0c230STony W Wang-oc if (m.cpuvendor == X86_VENDOR_INTEL || 146970f0c230STony W Wang-oc m.cpuvendor == X86_VENDOR_ZHAOXIN) 147021afaf18SBorislav Petkov lmce = m.mcgstatus & MCG_STATUS_LMCES; 147121afaf18SBorislav Petkov 147221afaf18SBorislav Petkov /* 147321afaf18SBorislav Petkov * Local machine check may already know that we have to panic. 147421afaf18SBorislav Petkov * Broadcast machine check begins rendezvous in mce_start() 147521afaf18SBorislav Petkov * Go through all banks in exclusion of the other CPUs. This way we 147621afaf18SBorislav Petkov * don't report duplicated events on shared banks because the first one 147721afaf18SBorislav Petkov * to see it will clear it. 147821afaf18SBorislav Petkov */ 147921afaf18SBorislav Petkov if (lmce) { 14807f1b8e0dSBorislav Petkov if (no_way_out) 148121afaf18SBorislav Petkov mce_panic("Fatal local machine check", &m, msg); 148221afaf18SBorislav Petkov } else { 148321afaf18SBorislav Petkov order = mce_start(&no_way_out); 148421afaf18SBorislav Petkov } 148521afaf18SBorislav Petkov 148675581a20SBorislav Petkov taint = __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst); 148721afaf18SBorislav Petkov 148821afaf18SBorislav Petkov if (!no_way_out) 148921afaf18SBorislav Petkov mce_clear_state(toclear); 149021afaf18SBorislav Petkov 149121afaf18SBorislav Petkov /* 149221afaf18SBorislav Petkov * Do most of the synchronization with other CPUs. 149321afaf18SBorislav Petkov * When there's any problem use only local no_way_out state. 149421afaf18SBorislav Petkov */ 149521afaf18SBorislav Petkov if (!lmce) { 149625bc65d8SGabriele Paoloni if (mce_end(order) < 0) { 149725bc65d8SGabriele Paoloni if (!no_way_out) 149821afaf18SBorislav Petkov no_way_out = worst >= MCE_PANIC_SEVERITY; 1499e273e6e1SGabriele Paoloni 15007f1b8e0dSBorislav Petkov if (no_way_out) 1501e273e6e1SGabriele Paoloni mce_panic("Fatal machine check on current CPU", &m, msg); 150225bc65d8SGabriele Paoloni } 150321afaf18SBorislav Petkov } else { 150421afaf18SBorislav Petkov /* 150521afaf18SBorislav Petkov * If there was a fatal machine check we should have 150621afaf18SBorislav Petkov * already called mce_panic earlier in this function. 150721afaf18SBorislav Petkov * Since we re-read the banks, we might have found 150821afaf18SBorislav Petkov * something new. Check again to see if we found a 150921afaf18SBorislav Petkov * fatal error. We call "mce_severity()" again to 151021afaf18SBorislav Petkov * make sure we have the right "msg". 151121afaf18SBorislav Petkov */ 15127f1b8e0dSBorislav Petkov if (worst >= MCE_PANIC_SEVERITY) { 15137f1b8e0dSBorislav Petkov mce_severity(&m, regs, &msg, true); 151421afaf18SBorislav Petkov mce_panic("Local fatal machine check!", &m, msg); 151521afaf18SBorislav Petkov } 151621afaf18SBorislav Petkov } 151721afaf18SBorislav Petkov 15184fbce464SBorislav Petkov /* 151975581a20SBorislav Petkov * Enable instrumentation around the external facilities like task_work_add() 152075581a20SBorislav Petkov * (via queue_task_work()), fixup_exception() etc. For now, that is. Fixing this 152175581a20SBorislav Petkov * properly would need a lot more involved reorganization. 15224fbce464SBorislav Petkov */ 15234fbce464SBorislav Petkov instrumentation_begin(); 15244fbce464SBorislav Petkov 152575581a20SBorislav Petkov if (taint) 152675581a20SBorislav Petkov add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); 152775581a20SBorislav Petkov 152875581a20SBorislav Petkov if (worst != MCE_AR_SEVERITY && !kill_current_task) 152975581a20SBorislav Petkov goto out; 153075581a20SBorislav Petkov 153121afaf18SBorislav Petkov /* Fault was in user mode and we need to take some action */ 153221afaf18SBorislav Petkov if ((m.cs & 3) == 3) { 1533b052df3dSThomas Gleixner /* If this triggers there is no way to recover. Die hard. */ 1534b052df3dSThomas Gleixner BUG_ON(!on_thread_stack() || !user_mode(regs)); 153521afaf18SBorislav Petkov 1536a6e3cf70STony Luck if (kill_current_task) 1537a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_now); 1538a6e3cf70STony Luck else 1539a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_maybe); 1540c0ab7ffcSTony Luck 154121afaf18SBorislav Petkov } else { 15421df73b21SBorislav Petkov /* 15431df73b21SBorislav Petkov * Handle an MCE which has happened in kernel space but from 15441df73b21SBorislav Petkov * which the kernel can recover: ex_has_fault_handler() has 15451df73b21SBorislav Petkov * already verified that the rIP at which the error happened is 15461df73b21SBorislav Petkov * a rIP from which the kernel can recover (by jumping to 15471df73b21SBorislav Petkov * recovery code specified in _ASM_EXTABLE_FAULT()) and the 15481df73b21SBorislav Petkov * corresponding exception handler which would do that is the 15491df73b21SBorislav Petkov * proper one. 15501df73b21SBorislav Petkov */ 15511df73b21SBorislav Petkov if (m.kflags & MCE_IN_KERNEL_RECOV) { 15528cd501c1SThomas Gleixner if (!fixup_exception(regs, X86_TRAP_MC, 0, 0)) 15532d806d07SJan H. Schönherr mce_panic("Failed kernel mode recovery", &m, msg); 155421afaf18SBorislav Petkov } 1555c0ab7ffcSTony Luck 1556c0ab7ffcSTony Luck if (m.kflags & MCE_IN_KERNEL_COPYIN) 1557a6e3cf70STony Luck queue_task_work(&m, msg, kill_me_never); 15581df73b21SBorislav Petkov } 15594fbce464SBorislav Petkov 156075581a20SBorislav Petkov out: 15614fbce464SBorislav Petkov instrumentation_end(); 15624fbce464SBorislav Petkov 15638ca97812SJue Wang clear: 15641e36d9c6STony Luck mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); 156521afaf18SBorislav Petkov } 156621afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(do_machine_check); 156721afaf18SBorislav Petkov 156821afaf18SBorislav Petkov #ifndef CONFIG_MEMORY_FAILURE 156921afaf18SBorislav Petkov int memory_failure(unsigned long pfn, int flags) 157021afaf18SBorislav Petkov { 157121afaf18SBorislav Petkov /* mce_severity() should not hand us an ACTION_REQUIRED error */ 157221afaf18SBorislav Petkov BUG_ON(flags & MF_ACTION_REQUIRED); 157321afaf18SBorislav Petkov pr_err("Uncorrected memory error in page 0x%lx ignored\n" 157421afaf18SBorislav Petkov "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", 157521afaf18SBorislav Petkov pfn); 157621afaf18SBorislav Petkov 157721afaf18SBorislav Petkov return 0; 157821afaf18SBorislav Petkov } 157921afaf18SBorislav Petkov #endif 158021afaf18SBorislav Petkov 158121afaf18SBorislav Petkov /* 158221afaf18SBorislav Petkov * Periodic polling timer for "silent" machine check errors. If the 158321afaf18SBorislav Petkov * poller finds an MCE, poll 2x faster. When the poller finds no more 158421afaf18SBorislav Petkov * errors, poll 2x slower (up to check_interval seconds). 158521afaf18SBorislav Petkov */ 158621afaf18SBorislav Petkov static unsigned long check_interval = INITIAL_CHECK_INTERVAL; 158721afaf18SBorislav Petkov 158821afaf18SBorislav Petkov static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ 158921afaf18SBorislav Petkov static DEFINE_PER_CPU(struct timer_list, mce_timer); 159021afaf18SBorislav Petkov 159121afaf18SBorislav Petkov static unsigned long mce_adjust_timer_default(unsigned long interval) 159221afaf18SBorislav Petkov { 159321afaf18SBorislav Petkov return interval; 159421afaf18SBorislav Petkov } 159521afaf18SBorislav Petkov 159621afaf18SBorislav Petkov static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; 159721afaf18SBorislav Petkov 159821afaf18SBorislav Petkov static void __start_timer(struct timer_list *t, unsigned long interval) 159921afaf18SBorislav Petkov { 160021afaf18SBorislav Petkov unsigned long when = jiffies + interval; 160121afaf18SBorislav Petkov unsigned long flags; 160221afaf18SBorislav Petkov 160321afaf18SBorislav Petkov local_irq_save(flags); 160421afaf18SBorislav Petkov 160521afaf18SBorislav Petkov if (!timer_pending(t) || time_before(when, t->expires)) 160621afaf18SBorislav Petkov mod_timer(t, round_jiffies(when)); 160721afaf18SBorislav Petkov 160821afaf18SBorislav Petkov local_irq_restore(flags); 160921afaf18SBorislav Petkov } 161021afaf18SBorislav Petkov 161121afaf18SBorislav Petkov static void mce_timer_fn(struct timer_list *t) 161221afaf18SBorislav Petkov { 161321afaf18SBorislav Petkov struct timer_list *cpu_t = this_cpu_ptr(&mce_timer); 161421afaf18SBorislav Petkov unsigned long iv; 161521afaf18SBorislav Petkov 161621afaf18SBorislav Petkov WARN_ON(cpu_t != t); 161721afaf18SBorislav Petkov 161821afaf18SBorislav Petkov iv = __this_cpu_read(mce_next_interval); 161921afaf18SBorislav Petkov 162021afaf18SBorislav Petkov if (mce_available(this_cpu_ptr(&cpu_info))) { 162121afaf18SBorislav Petkov machine_check_poll(0, this_cpu_ptr(&mce_poll_banks)); 162221afaf18SBorislav Petkov 162321afaf18SBorislav Petkov if (mce_intel_cmci_poll()) { 162421afaf18SBorislav Petkov iv = mce_adjust_timer(iv); 162521afaf18SBorislav Petkov goto done; 162621afaf18SBorislav Petkov } 162721afaf18SBorislav Petkov } 162821afaf18SBorislav Petkov 162921afaf18SBorislav Petkov /* 163021afaf18SBorislav Petkov * Alert userspace if needed. If we logged an MCE, reduce the polling 163121afaf18SBorislav Petkov * interval, otherwise increase the polling interval. 163221afaf18SBorislav Petkov */ 163321afaf18SBorislav Petkov if (mce_notify_irq()) 163421afaf18SBorislav Petkov iv = max(iv / 2, (unsigned long) HZ/100); 163521afaf18SBorislav Petkov else 163621afaf18SBorislav Petkov iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); 163721afaf18SBorislav Petkov 163821afaf18SBorislav Petkov done: 163921afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, iv); 164021afaf18SBorislav Petkov __start_timer(t, iv); 164121afaf18SBorislav Petkov } 164221afaf18SBorislav Petkov 164321afaf18SBorislav Petkov /* 164421afaf18SBorislav Petkov * Ensure that the timer is firing in @interval from now. 164521afaf18SBorislav Petkov */ 164621afaf18SBorislav Petkov void mce_timer_kick(unsigned long interval) 164721afaf18SBorislav Petkov { 164821afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 164921afaf18SBorislav Petkov unsigned long iv = __this_cpu_read(mce_next_interval); 165021afaf18SBorislav Petkov 165121afaf18SBorislav Petkov __start_timer(t, interval); 165221afaf18SBorislav Petkov 165321afaf18SBorislav Petkov if (interval < iv) 165421afaf18SBorislav Petkov __this_cpu_write(mce_next_interval, interval); 165521afaf18SBorislav Petkov } 165621afaf18SBorislav Petkov 165721afaf18SBorislav Petkov /* Must not be called in IRQ context where del_timer_sync() can deadlock */ 165821afaf18SBorislav Petkov static void mce_timer_delete_all(void) 165921afaf18SBorislav Petkov { 166021afaf18SBorislav Petkov int cpu; 166121afaf18SBorislav Petkov 166221afaf18SBorislav Petkov for_each_online_cpu(cpu) 166321afaf18SBorislav Petkov del_timer_sync(&per_cpu(mce_timer, cpu)); 166421afaf18SBorislav Petkov } 166521afaf18SBorislav Petkov 166621afaf18SBorislav Petkov /* 166721afaf18SBorislav Petkov * Notify the user(s) about new machine check events. 166821afaf18SBorislav Petkov * Can be called from interrupt context, but not from machine check/NMI 166921afaf18SBorislav Petkov * context. 167021afaf18SBorislav Petkov */ 167121afaf18SBorislav Petkov int mce_notify_irq(void) 167221afaf18SBorislav Petkov { 167321afaf18SBorislav Petkov /* Not more than two messages every minute */ 167421afaf18SBorislav Petkov static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); 167521afaf18SBorislav Petkov 167621afaf18SBorislav Petkov if (test_and_clear_bit(0, &mce_need_notify)) { 167721afaf18SBorislav Petkov mce_work_trigger(); 167821afaf18SBorislav Petkov 167921afaf18SBorislav Petkov if (__ratelimit(&ratelimit)) 168021afaf18SBorislav Petkov pr_info(HW_ERR "Machine check events logged\n"); 168121afaf18SBorislav Petkov 168221afaf18SBorislav Petkov return 1; 168321afaf18SBorislav Petkov } 168421afaf18SBorislav Petkov return 0; 168521afaf18SBorislav Petkov } 168621afaf18SBorislav Petkov EXPORT_SYMBOL_GPL(mce_notify_irq); 168721afaf18SBorislav Petkov 1688b4914508SYazen Ghannam static void __mcheck_cpu_mce_banks_init(void) 168921afaf18SBorislav Petkov { 1690b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1691c7d314f3SYazen Ghannam u8 n_banks = this_cpu_read(mce_num_banks); 169221afaf18SBorislav Petkov int i; 169321afaf18SBorislav Petkov 1694c7d314f3SYazen Ghannam for (i = 0; i < n_banks; i++) { 169521afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 169621afaf18SBorislav Petkov 1697068b053dSYazen Ghannam /* 1698068b053dSYazen Ghannam * Init them all, __mcheck_cpu_apply_quirks() is going to apply 1699068b053dSYazen Ghannam * the required vendor quirks before 1700068b053dSYazen Ghannam * __mcheck_cpu_init_clear_banks() does the final bank setup. 1701068b053dSYazen Ghannam */ 170221afaf18SBorislav Petkov b->ctl = -1ULL; 170377080929SKaixu Xia b->init = true; 170421afaf18SBorislav Petkov } 170521afaf18SBorislav Petkov } 170621afaf18SBorislav Petkov 170721afaf18SBorislav Petkov /* 170821afaf18SBorislav Petkov * Initialize Machine Checks for a CPU. 170921afaf18SBorislav Petkov */ 1710b4914508SYazen Ghannam static void __mcheck_cpu_cap_init(void) 171121afaf18SBorislav Petkov { 171221afaf18SBorislav Petkov u64 cap; 1713006c0770SYazen Ghannam u8 b; 171421afaf18SBorislav Petkov 171521afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 171621afaf18SBorislav Petkov 171721afaf18SBorislav Petkov b = cap & MCG_BANKCNT_MASK; 171821afaf18SBorislav Petkov 1719c7d314f3SYazen Ghannam if (b > MAX_NR_BANKS) { 1720c7d314f3SYazen Ghannam pr_warn("CPU%d: Using only %u machine check banks out of %u\n", 1721c7d314f3SYazen Ghannam smp_processor_id(), MAX_NR_BANKS, b); 1722c7d314f3SYazen Ghannam b = MAX_NR_BANKS; 1723c7d314f3SYazen Ghannam } 1724c7d314f3SYazen Ghannam 1725c7d314f3SYazen Ghannam this_cpu_write(mce_num_banks, b); 172621afaf18SBorislav Petkov 1727b4914508SYazen Ghannam __mcheck_cpu_mce_banks_init(); 172821afaf18SBorislav Petkov 172921afaf18SBorislav Petkov /* Use accurate RIP reporting if available. */ 173021afaf18SBorislav Petkov if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) 173121afaf18SBorislav Petkov mca_cfg.rip_msr = MSR_IA32_MCG_EIP; 173221afaf18SBorislav Petkov 173321afaf18SBorislav Petkov if (cap & MCG_SER_P) 173421afaf18SBorislav Petkov mca_cfg.ser = 1; 173521afaf18SBorislav Petkov } 173621afaf18SBorislav Petkov 173721afaf18SBorislav Petkov static void __mcheck_cpu_init_generic(void) 173821afaf18SBorislav Petkov { 173921afaf18SBorislav Petkov enum mcp_flags m_fl = 0; 174021afaf18SBorislav Petkov mce_banks_t all_banks; 174121afaf18SBorislav Petkov u64 cap; 174221afaf18SBorislav Petkov 174321afaf18SBorislav Petkov if (!mca_cfg.bootlog) 174421afaf18SBorislav Petkov m_fl = MCP_DONTLOG; 174521afaf18SBorislav Petkov 174621afaf18SBorislav Petkov /* 17473bff147bSBorislav Petkov * Log the machine checks left over from the previous reset. Log them 17483bff147bSBorislav Petkov * only, do not start processing them. That will happen in mcheck_late_init() 17493bff147bSBorislav Petkov * when all consumers have been registered on the notifier chain. 175021afaf18SBorislav Petkov */ 175121afaf18SBorislav Petkov bitmap_fill(all_banks, MAX_NR_BANKS); 17523bff147bSBorislav Petkov machine_check_poll(MCP_UC | MCP_QUEUE_LOG | m_fl, &all_banks); 175321afaf18SBorislav Petkov 175421afaf18SBorislav Petkov cr4_set_bits(X86_CR4_MCE); 175521afaf18SBorislav Petkov 175621afaf18SBorislav Petkov rdmsrl(MSR_IA32_MCG_CAP, cap); 175721afaf18SBorislav Petkov if (cap & MCG_CTL_P) 175821afaf18SBorislav Petkov wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); 175921afaf18SBorislav Petkov } 176021afaf18SBorislav Petkov 176121afaf18SBorislav Petkov static void __mcheck_cpu_init_clear_banks(void) 176221afaf18SBorislav Petkov { 1763b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 176421afaf18SBorislav Petkov int i; 176521afaf18SBorislav Petkov 1766c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 176721afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 176821afaf18SBorislav Petkov 176921afaf18SBorislav Petkov if (!b->init) 177021afaf18SBorislav Petkov continue; 17718121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); 17728121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 177321afaf18SBorislav Petkov } 177421afaf18SBorislav Petkov } 177521afaf18SBorislav Petkov 177621afaf18SBorislav Petkov /* 1777068b053dSYazen Ghannam * Do a final check to see if there are any unused/RAZ banks. 1778068b053dSYazen Ghannam * 1779068b053dSYazen Ghannam * This must be done after the banks have been initialized and any quirks have 1780068b053dSYazen Ghannam * been applied. 1781068b053dSYazen Ghannam * 1782068b053dSYazen Ghannam * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs. 1783068b053dSYazen Ghannam * Otherwise, a user who disables a bank will not be able to re-enable it 1784068b053dSYazen Ghannam * without a system reboot. 1785068b053dSYazen Ghannam */ 1786068b053dSYazen Ghannam static void __mcheck_cpu_check_banks(void) 1787068b053dSYazen Ghannam { 1788068b053dSYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 1789068b053dSYazen Ghannam u64 msrval; 1790068b053dSYazen Ghannam int i; 1791068b053dSYazen Ghannam 1792068b053dSYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1793068b053dSYazen Ghannam struct mce_bank *b = &mce_banks[i]; 1794068b053dSYazen Ghannam 1795068b053dSYazen Ghannam if (!b->init) 1796068b053dSYazen Ghannam continue; 1797068b053dSYazen Ghannam 17988121b8f9SBorislav Petkov rdmsrl(mca_msr_reg(i, MCA_CTL), msrval); 1799068b053dSYazen Ghannam b->init = !!msrval; 1800068b053dSYazen Ghannam } 1801068b053dSYazen Ghannam } 1802068b053dSYazen Ghannam 180321afaf18SBorislav Petkov /* Add per CPU specific workarounds here */ 180421afaf18SBorislav Petkov static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) 180521afaf18SBorislav Petkov { 1806b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 180721afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 180821afaf18SBorislav Petkov 180921afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_UNKNOWN) { 181021afaf18SBorislav Petkov pr_info("unknown CPU type - not enabling MCE support\n"); 181121afaf18SBorislav Petkov return -EOPNOTSUPP; 181221afaf18SBorislav Petkov } 181321afaf18SBorislav Petkov 181421afaf18SBorislav Petkov /* This should be disabled by the BIOS, but isn't always */ 181521afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD) { 1816c7d314f3SYazen Ghannam if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { 181721afaf18SBorislav Petkov /* 181821afaf18SBorislav Petkov * disable GART TBL walk error reporting, which 181921afaf18SBorislav Petkov * trips off incorrectly with the IOMMU & 3ware 182021afaf18SBorislav Petkov * & Cerberus: 182121afaf18SBorislav Petkov */ 182221afaf18SBorislav Petkov clear_bit(10, (unsigned long *)&mce_banks[4].ctl); 182321afaf18SBorislav Petkov } 182421afaf18SBorislav Petkov if (c->x86 < 0x11 && cfg->bootlog < 0) { 182521afaf18SBorislav Petkov /* 182621afaf18SBorislav Petkov * Lots of broken BIOS around that don't clear them 182721afaf18SBorislav Petkov * by default and leave crap in there. Don't log: 182821afaf18SBorislav Petkov */ 182921afaf18SBorislav Petkov cfg->bootlog = 0; 183021afaf18SBorislav Petkov } 183121afaf18SBorislav Petkov /* 183221afaf18SBorislav Petkov * Various K7s with broken bank 0 around. Always disable 183321afaf18SBorislav Petkov * by default. 183421afaf18SBorislav Petkov */ 1835c7d314f3SYazen Ghannam if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0) 183621afaf18SBorislav Petkov mce_banks[0].ctl = 0; 183721afaf18SBorislav Petkov 183821afaf18SBorislav Petkov /* 183921afaf18SBorislav Petkov * overflow_recov is supported for F15h Models 00h-0fh 184021afaf18SBorislav Petkov * even though we don't have a CPUID bit for it. 184121afaf18SBorislav Petkov */ 184221afaf18SBorislav Petkov if (c->x86 == 0x15 && c->x86_model <= 0xf) 184321afaf18SBorislav Petkov mce_flags.overflow_recov = 1; 184421afaf18SBorislav Petkov 184521afaf18SBorislav Petkov } 184621afaf18SBorislav Petkov 184721afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_INTEL) { 184821afaf18SBorislav Petkov /* 184921afaf18SBorislav Petkov * SDM documents that on family 6 bank 0 should not be written 185021afaf18SBorislav Petkov * because it aliases to another special BIOS controlled 185121afaf18SBorislav Petkov * register. 185221afaf18SBorislav Petkov * But it's not aliased anymore on model 0x1a+ 185321afaf18SBorislav Petkov * Don't ignore bank 0 completely because there could be a 185421afaf18SBorislav Petkov * valid event later, merely don't write CTL0. 185521afaf18SBorislav Petkov */ 185621afaf18SBorislav Petkov 1857c7d314f3SYazen Ghannam if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) 185877080929SKaixu Xia mce_banks[0].init = false; 185921afaf18SBorislav Petkov 186021afaf18SBorislav Petkov /* 186121afaf18SBorislav Petkov * All newer Intel systems support MCE broadcasting. Enable 186221afaf18SBorislav Petkov * synchronization with a one second timeout. 186321afaf18SBorislav Petkov */ 186421afaf18SBorislav Petkov if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && 186521afaf18SBorislav Petkov cfg->monarch_timeout < 0) 186621afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 186721afaf18SBorislav Petkov 186821afaf18SBorislav Petkov /* 186921afaf18SBorislav Petkov * There are also broken BIOSes on some Pentium M and 187021afaf18SBorislav Petkov * earlier systems: 187121afaf18SBorislav Petkov */ 187221afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) 187321afaf18SBorislav Petkov cfg->bootlog = 0; 187421afaf18SBorislav Petkov 187521afaf18SBorislav Petkov if (c->x86 == 6 && c->x86_model == 45) 1876cc466666SBorislav Petkov mce_flags.snb_ifu_quirk = 1; 18778ca97812SJue Wang 18788ca97812SJue Wang /* 18798ca97812SJue Wang * Skylake, Cascacde Lake and Cooper Lake require a quirk on 18808ca97812SJue Wang * rep movs. 18818ca97812SJue Wang */ 18828ca97812SJue Wang if (c->x86 == 6 && c->x86_model == INTEL_FAM6_SKYLAKE_X) 18838ca97812SJue Wang mce_flags.skx_repmov_quirk = 1; 188421afaf18SBorislav Petkov } 18856e898d2bSTony W Wang-oc 18866e898d2bSTony W Wang-oc if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { 18876e898d2bSTony W Wang-oc /* 18886e898d2bSTony W Wang-oc * All newer Zhaoxin CPUs support MCE broadcasting. Enable 18896e898d2bSTony W Wang-oc * synchronization with a one second timeout. 18906e898d2bSTony W Wang-oc */ 18916e898d2bSTony W Wang-oc if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 18926e898d2bSTony W Wang-oc if (cfg->monarch_timeout < 0) 18936e898d2bSTony W Wang-oc cfg->monarch_timeout = USEC_PER_SEC; 18946e898d2bSTony W Wang-oc } 18956e898d2bSTony W Wang-oc } 18966e898d2bSTony W Wang-oc 189721afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 189821afaf18SBorislav Petkov cfg->monarch_timeout = 0; 189921afaf18SBorislav Petkov if (cfg->bootlog != 0) 190021afaf18SBorislav Petkov cfg->panic_timeout = 30; 190121afaf18SBorislav Petkov 190221afaf18SBorislav Petkov return 0; 190321afaf18SBorislav Petkov } 190421afaf18SBorislav Petkov 190521afaf18SBorislav Petkov static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) 190621afaf18SBorislav Petkov { 190721afaf18SBorislav Petkov if (c->x86 != 5) 190821afaf18SBorislav Petkov return 0; 190921afaf18SBorislav Petkov 191021afaf18SBorislav Petkov switch (c->x86_vendor) { 191121afaf18SBorislav Petkov case X86_VENDOR_INTEL: 191221afaf18SBorislav Petkov intel_p5_mcheck_init(c); 1913cbe1de16SBorislav Petkov mce_flags.p5 = 1; 191421afaf18SBorislav Petkov return 1; 191521afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 191621afaf18SBorislav Petkov winchip_mcheck_init(c); 1917cbe1de16SBorislav Petkov mce_flags.winchip = 1; 191821afaf18SBorislav Petkov return 1; 191921afaf18SBorislav Petkov default: 192021afaf18SBorislav Petkov return 0; 192121afaf18SBorislav Petkov } 192221afaf18SBorislav Petkov 192321afaf18SBorislav Petkov return 0; 192421afaf18SBorislav Petkov } 192521afaf18SBorislav Petkov 192621afaf18SBorislav Petkov /* 192721afaf18SBorislav Petkov * Init basic CPU features needed for early decoding of MCEs. 192821afaf18SBorislav Petkov */ 192921afaf18SBorislav Petkov static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) 193021afaf18SBorislav Petkov { 193121afaf18SBorislav Petkov if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) { 193221afaf18SBorislav Petkov mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); 193321afaf18SBorislav Petkov mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); 193421afaf18SBorislav Petkov mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); 1935c9bf318fSThomas Gleixner mce_flags.amd_threshold = 1; 193621afaf18SBorislav Petkov } 193721afaf18SBorislav Petkov } 193821afaf18SBorislav Petkov 193921afaf18SBorislav Petkov static void mce_centaur_feature_init(struct cpuinfo_x86 *c) 194021afaf18SBorislav Petkov { 194121afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 194221afaf18SBorislav Petkov 194321afaf18SBorislav Petkov /* 194421afaf18SBorislav Petkov * All newer Centaur CPUs support MCE broadcasting. Enable 194521afaf18SBorislav Petkov * synchronization with a one second timeout. 194621afaf18SBorislav Petkov */ 194721afaf18SBorislav Petkov if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) || 194821afaf18SBorislav Petkov c->x86 > 6) { 194921afaf18SBorislav Petkov if (cfg->monarch_timeout < 0) 195021afaf18SBorislav Petkov cfg->monarch_timeout = USEC_PER_SEC; 195121afaf18SBorislav Petkov } 195221afaf18SBorislav Petkov } 195321afaf18SBorislav Petkov 19545a3d56a0STony W Wang-oc static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) 19555a3d56a0STony W Wang-oc { 19565a3d56a0STony W Wang-oc struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 19575a3d56a0STony W Wang-oc 19585a3d56a0STony W Wang-oc /* 19595a3d56a0STony W Wang-oc * These CPUs have MCA bank 8 which reports only one error type called 19605a3d56a0STony W Wang-oc * SVAD (System View Address Decoder). The reporting of that error is 19615a3d56a0STony W Wang-oc * controlled by IA32_MC8.CTL.0. 19625a3d56a0STony W Wang-oc * 19635a3d56a0STony W Wang-oc * If enabled, prefetching on these CPUs will cause SVAD MCE when 19645a3d56a0STony W Wang-oc * virtual machines start and result in a system panic. Always disable 19655a3d56a0STony W Wang-oc * bank 8 SVAD error by default. 19665a3d56a0STony W Wang-oc */ 19675a3d56a0STony W Wang-oc if ((c->x86 == 7 && c->x86_model == 0x1b) || 19685a3d56a0STony W Wang-oc (c->x86_model == 0x19 || c->x86_model == 0x1f)) { 19695a3d56a0STony W Wang-oc if (this_cpu_read(mce_num_banks) > 8) 19705a3d56a0STony W Wang-oc mce_banks[8].ctl = 0; 19715a3d56a0STony W Wang-oc } 19725a3d56a0STony W Wang-oc 19735a3d56a0STony W Wang-oc intel_init_cmci(); 197470f0c230STony W Wang-oc intel_init_lmce(); 19755a3d56a0STony W Wang-oc mce_adjust_timer = cmci_intel_adjust_timer; 19765a3d56a0STony W Wang-oc } 19775a3d56a0STony W Wang-oc 197870f0c230STony W Wang-oc static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) 197970f0c230STony W Wang-oc { 198070f0c230STony W Wang-oc intel_clear_lmce(); 198170f0c230STony W Wang-oc } 198270f0c230STony W Wang-oc 198321afaf18SBorislav Petkov static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) 198421afaf18SBorislav Petkov { 198521afaf18SBorislav Petkov switch (c->x86_vendor) { 198621afaf18SBorislav Petkov case X86_VENDOR_INTEL: 198721afaf18SBorislav Petkov mce_intel_feature_init(c); 198821afaf18SBorislav Petkov mce_adjust_timer = cmci_intel_adjust_timer; 198921afaf18SBorislav Petkov break; 199021afaf18SBorislav Petkov 199121afaf18SBorislav Petkov case X86_VENDOR_AMD: { 199221afaf18SBorislav Petkov mce_amd_feature_init(c); 199321afaf18SBorislav Petkov break; 199421afaf18SBorislav Petkov } 199521afaf18SBorislav Petkov 199621afaf18SBorislav Petkov case X86_VENDOR_HYGON: 199721afaf18SBorislav Petkov mce_hygon_feature_init(c); 199821afaf18SBorislav Petkov break; 199921afaf18SBorislav Petkov 200021afaf18SBorislav Petkov case X86_VENDOR_CENTAUR: 200121afaf18SBorislav Petkov mce_centaur_feature_init(c); 200221afaf18SBorislav Petkov break; 200321afaf18SBorislav Petkov 20045a3d56a0STony W Wang-oc case X86_VENDOR_ZHAOXIN: 20055a3d56a0STony W Wang-oc mce_zhaoxin_feature_init(c); 20065a3d56a0STony W Wang-oc break; 20075a3d56a0STony W Wang-oc 200821afaf18SBorislav Petkov default: 200921afaf18SBorislav Petkov break; 201021afaf18SBorislav Petkov } 201121afaf18SBorislav Petkov } 201221afaf18SBorislav Petkov 201321afaf18SBorislav Petkov static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) 201421afaf18SBorislav Petkov { 201521afaf18SBorislav Petkov switch (c->x86_vendor) { 201621afaf18SBorislav Petkov case X86_VENDOR_INTEL: 201721afaf18SBorislav Petkov mce_intel_feature_clear(c); 201821afaf18SBorislav Petkov break; 201970f0c230STony W Wang-oc 202070f0c230STony W Wang-oc case X86_VENDOR_ZHAOXIN: 202170f0c230STony W Wang-oc mce_zhaoxin_feature_clear(c); 202270f0c230STony W Wang-oc break; 202370f0c230STony W Wang-oc 202421afaf18SBorislav Petkov default: 202521afaf18SBorislav Petkov break; 202621afaf18SBorislav Petkov } 202721afaf18SBorislav Petkov } 202821afaf18SBorislav Petkov 202921afaf18SBorislav Petkov static void mce_start_timer(struct timer_list *t) 203021afaf18SBorislav Petkov { 203121afaf18SBorislav Petkov unsigned long iv = check_interval * HZ; 203221afaf18SBorislav Petkov 203321afaf18SBorislav Petkov if (mca_cfg.ignore_ce || !iv) 203421afaf18SBorislav Petkov return; 203521afaf18SBorislav Petkov 203621afaf18SBorislav Petkov this_cpu_write(mce_next_interval, iv); 203721afaf18SBorislav Petkov __start_timer(t, iv); 203821afaf18SBorislav Petkov } 203921afaf18SBorislav Petkov 204021afaf18SBorislav Petkov static void __mcheck_cpu_setup_timer(void) 204121afaf18SBorislav Petkov { 204221afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 204321afaf18SBorislav Petkov 204421afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 204521afaf18SBorislav Petkov } 204621afaf18SBorislav Petkov 204721afaf18SBorislav Petkov static void __mcheck_cpu_init_timer(void) 204821afaf18SBorislav Petkov { 204921afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 205021afaf18SBorislav Petkov 205121afaf18SBorislav Petkov timer_setup(t, mce_timer_fn, TIMER_PINNED); 205221afaf18SBorislav Petkov mce_start_timer(t); 205321afaf18SBorislav Petkov } 205421afaf18SBorislav Petkov 205545d4b7b9SYazen Ghannam bool filter_mce(struct mce *m) 205645d4b7b9SYazen Ghannam { 205771a84402SYazen Ghannam if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 205871a84402SYazen Ghannam return amd_filter_mce(m); 20592976908eSPrarit Bhargava if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 20602976908eSPrarit Bhargava return intel_filter_mce(m); 206171a84402SYazen Ghannam 206245d4b7b9SYazen Ghannam return false; 206345d4b7b9SYazen Ghannam } 206445d4b7b9SYazen Ghannam 20654c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_kernel(struct pt_regs *regs) 206621afaf18SBorislav Petkov { 2067b6be002bSThomas Gleixner irqentry_state_t irq_state; 2068bc21a291SThomas Gleixner 206913cbc0cdSAndy Lutomirski WARN_ON_ONCE(user_mode(regs)); 207013cbc0cdSAndy Lutomirski 20714c0dcd83SThomas Gleixner /* 20724c0dcd83SThomas Gleixner * Only required when from kernel mode. See 20734c0dcd83SThomas Gleixner * mce_check_crashing_cpu() for details. 20744c0dcd83SThomas Gleixner */ 2075cbe1de16SBorislav Petkov if (mca_cfg.initialized && mce_check_crashing_cpu()) 207694a46d31SThomas Gleixner return; 207794a46d31SThomas Gleixner 2078b6be002bSThomas Gleixner irq_state = irqentry_nmi_enter(regs); 207973749536SPeter Zijlstra 2080cbe1de16SBorislav Petkov do_machine_check(regs); 208173749536SPeter Zijlstra 2082b6be002bSThomas Gleixner irqentry_nmi_exit(regs, irq_state); 208321afaf18SBorislav Petkov } 208421afaf18SBorislav Petkov 20854c0dcd83SThomas Gleixner static __always_inline void exc_machine_check_user(struct pt_regs *regs) 20864c0dcd83SThomas Gleixner { 2087517e4992SThomas Gleixner irqentry_enter_from_user_mode(regs); 208873749536SPeter Zijlstra 2089cbe1de16SBorislav Petkov do_machine_check(regs); 209073749536SPeter Zijlstra 2091517e4992SThomas Gleixner irqentry_exit_to_user_mode(regs); 20924c0dcd83SThomas Gleixner } 20934c0dcd83SThomas Gleixner 20944c0dcd83SThomas Gleixner #ifdef CONFIG_X86_64 20954c0dcd83SThomas Gleixner /* MCE hit kernel mode */ 20964c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE(exc_machine_check) 20974c0dcd83SThomas Gleixner { 2098cd840e42SPeter Zijlstra unsigned long dr7; 2099cd840e42SPeter Zijlstra 2100cd840e42SPeter Zijlstra dr7 = local_db_save(); 21014c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 2102cd840e42SPeter Zijlstra local_db_restore(dr7); 21034c0dcd83SThomas Gleixner } 21044c0dcd83SThomas Gleixner 21054c0dcd83SThomas Gleixner /* The user mode variant. */ 21064c0dcd83SThomas Gleixner DEFINE_IDTENTRY_MCE_USER(exc_machine_check) 21074c0dcd83SThomas Gleixner { 2108cd840e42SPeter Zijlstra unsigned long dr7; 2109cd840e42SPeter Zijlstra 2110cd840e42SPeter Zijlstra dr7 = local_db_save(); 21114c0dcd83SThomas Gleixner exc_machine_check_user(regs); 2112cd840e42SPeter Zijlstra local_db_restore(dr7); 21134c0dcd83SThomas Gleixner } 21144c0dcd83SThomas Gleixner #else 21154c0dcd83SThomas Gleixner /* 32bit unified entry point */ 211613cbc0cdSAndy Lutomirski DEFINE_IDTENTRY_RAW(exc_machine_check) 21174c0dcd83SThomas Gleixner { 2118cd840e42SPeter Zijlstra unsigned long dr7; 2119cd840e42SPeter Zijlstra 2120cd840e42SPeter Zijlstra dr7 = local_db_save(); 21214c0dcd83SThomas Gleixner if (user_mode(regs)) 21224c0dcd83SThomas Gleixner exc_machine_check_user(regs); 21234c0dcd83SThomas Gleixner else 21244c0dcd83SThomas Gleixner exc_machine_check_kernel(regs); 2125cd840e42SPeter Zijlstra local_db_restore(dr7); 21264c0dcd83SThomas Gleixner } 21274c0dcd83SThomas Gleixner #endif 212821afaf18SBorislav Petkov 212921afaf18SBorislav Petkov /* 213021afaf18SBorislav Petkov * Called for each booted CPU to set up machine checks. 213121afaf18SBorislav Petkov * Must be called with preempt off: 213221afaf18SBorislav Petkov */ 213321afaf18SBorislav Petkov void mcheck_cpu_init(struct cpuinfo_x86 *c) 213421afaf18SBorislav Petkov { 213521afaf18SBorislav Petkov if (mca_cfg.disabled) 213621afaf18SBorislav Petkov return; 213721afaf18SBorislav Petkov 213821afaf18SBorislav Petkov if (__mcheck_cpu_ancient_init(c)) 213921afaf18SBorislav Petkov return; 214021afaf18SBorislav Petkov 214121afaf18SBorislav Petkov if (!mce_available(c)) 214221afaf18SBorislav Petkov return; 214321afaf18SBorislav Petkov 2144b4914508SYazen Ghannam __mcheck_cpu_cap_init(); 2145b4914508SYazen Ghannam 2146b4914508SYazen Ghannam if (__mcheck_cpu_apply_quirks(c) < 0) { 214721afaf18SBorislav Petkov mca_cfg.disabled = 1; 214821afaf18SBorislav Petkov return; 214921afaf18SBorislav Petkov } 215021afaf18SBorislav Petkov 215121afaf18SBorislav Petkov if (mce_gen_pool_init()) { 215221afaf18SBorislav Petkov mca_cfg.disabled = 1; 215321afaf18SBorislav Petkov pr_emerg("Couldn't allocate MCE records pool!\n"); 215421afaf18SBorislav Petkov return; 215521afaf18SBorislav Petkov } 215621afaf18SBorislav Petkov 2157cbe1de16SBorislav Petkov mca_cfg.initialized = 1; 215821afaf18SBorislav Petkov 215921afaf18SBorislav Petkov __mcheck_cpu_init_early(c); 216021afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 216121afaf18SBorislav Petkov __mcheck_cpu_init_vendor(c); 216221afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 2163068b053dSYazen Ghannam __mcheck_cpu_check_banks(); 216421afaf18SBorislav Petkov __mcheck_cpu_setup_timer(); 216521afaf18SBorislav Petkov } 216621afaf18SBorislav Petkov 216721afaf18SBorislav Petkov /* 216821afaf18SBorislav Petkov * Called for each booted CPU to clear some machine checks opt-ins 216921afaf18SBorislav Petkov */ 217021afaf18SBorislav Petkov void mcheck_cpu_clear(struct cpuinfo_x86 *c) 217121afaf18SBorislav Petkov { 217221afaf18SBorislav Petkov if (mca_cfg.disabled) 217321afaf18SBorislav Petkov return; 217421afaf18SBorislav Petkov 217521afaf18SBorislav Petkov if (!mce_available(c)) 217621afaf18SBorislav Petkov return; 217721afaf18SBorislav Petkov 217821afaf18SBorislav Petkov /* 217921afaf18SBorislav Petkov * Possibly to clear general settings generic to x86 218021afaf18SBorislav Petkov * __mcheck_cpu_clear_generic(c); 218121afaf18SBorislav Petkov */ 218221afaf18SBorislav Petkov __mcheck_cpu_clear_vendor(c); 218321afaf18SBorislav Petkov 218421afaf18SBorislav Petkov } 218521afaf18SBorislav Petkov 218621afaf18SBorislav Petkov static void __mce_disable_bank(void *arg) 218721afaf18SBorislav Petkov { 218821afaf18SBorislav Petkov int bank = *((int *)arg); 218921afaf18SBorislav Petkov __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); 219021afaf18SBorislav Petkov cmci_disable_bank(bank); 219121afaf18SBorislav Petkov } 219221afaf18SBorislav Petkov 219321afaf18SBorislav Petkov void mce_disable_bank(int bank) 219421afaf18SBorislav Petkov { 2195c7d314f3SYazen Ghannam if (bank >= this_cpu_read(mce_num_banks)) { 219621afaf18SBorislav Petkov pr_warn(FW_BUG 219721afaf18SBorislav Petkov "Ignoring request to disable invalid MCA bank %d.\n", 219821afaf18SBorislav Petkov bank); 219921afaf18SBorislav Petkov return; 220021afaf18SBorislav Petkov } 220121afaf18SBorislav Petkov set_bit(bank, mce_banks_ce_disabled); 220221afaf18SBorislav Petkov on_each_cpu(__mce_disable_bank, &bank, 1); 220321afaf18SBorislav Petkov } 220421afaf18SBorislav Petkov 220521afaf18SBorislav Petkov /* 220621afaf18SBorislav Petkov * mce=off Disables machine check 220721afaf18SBorislav Petkov * mce=no_cmci Disables CMCI 220821afaf18SBorislav Petkov * mce=no_lmce Disables LMCE 220921afaf18SBorislav Petkov * mce=dont_log_ce Clears corrected events silently, no log created for CEs. 221043505646STony Luck * mce=print_all Print all machine check logs to console 221121afaf18SBorislav Petkov * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. 221221afaf18SBorislav Petkov * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) 221321afaf18SBorislav Petkov * monarchtimeout is how long to wait for other CPUs on machine 221421afaf18SBorislav Petkov * check, or 0 to not wait 221521afaf18SBorislav Petkov * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h 221621afaf18SBorislav Petkov and older. 221721afaf18SBorislav Petkov * mce=nobootlog Don't log MCEs from before booting. 221821afaf18SBorislav Petkov * mce=bios_cmci_threshold Don't program the CMCI threshold 2219ec6347bbSDan Williams * mce=recovery force enable copy_mc_fragile() 222021afaf18SBorislav Petkov */ 222121afaf18SBorislav Petkov static int __init mcheck_enable(char *str) 222221afaf18SBorislav Petkov { 222321afaf18SBorislav Petkov struct mca_config *cfg = &mca_cfg; 222421afaf18SBorislav Petkov 222521afaf18SBorislav Petkov if (*str == 0) { 222621afaf18SBorislav Petkov enable_p5_mce(); 222721afaf18SBorislav Petkov return 1; 222821afaf18SBorislav Petkov } 222921afaf18SBorislav Petkov if (*str == '=') 223021afaf18SBorislav Petkov str++; 223121afaf18SBorislav Petkov if (!strcmp(str, "off")) 223221afaf18SBorislav Petkov cfg->disabled = 1; 223321afaf18SBorislav Petkov else if (!strcmp(str, "no_cmci")) 223421afaf18SBorislav Petkov cfg->cmci_disabled = true; 223521afaf18SBorislav Petkov else if (!strcmp(str, "no_lmce")) 223621afaf18SBorislav Petkov cfg->lmce_disabled = 1; 223721afaf18SBorislav Petkov else if (!strcmp(str, "dont_log_ce")) 223821afaf18SBorislav Petkov cfg->dont_log_ce = true; 223943505646STony Luck else if (!strcmp(str, "print_all")) 224043505646STony Luck cfg->print_all = true; 224121afaf18SBorislav Petkov else if (!strcmp(str, "ignore_ce")) 224221afaf18SBorislav Petkov cfg->ignore_ce = true; 224321afaf18SBorislav Petkov else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) 224421afaf18SBorislav Petkov cfg->bootlog = (str[0] == 'b'); 224521afaf18SBorislav Petkov else if (!strcmp(str, "bios_cmci_threshold")) 224621afaf18SBorislav Petkov cfg->bios_cmci_threshold = 1; 224721afaf18SBorislav Petkov else if (!strcmp(str, "recovery")) 224821afaf18SBorislav Petkov cfg->recovery = 1; 22497f1b8e0dSBorislav Petkov else if (isdigit(str[0])) 225021afaf18SBorislav Petkov get_option(&str, &(cfg->monarch_timeout)); 22517f1b8e0dSBorislav Petkov else { 225221afaf18SBorislav Petkov pr_info("mce argument %s ignored. Please use /sys\n", str); 225321afaf18SBorislav Petkov return 0; 225421afaf18SBorislav Petkov } 225521afaf18SBorislav Petkov return 1; 225621afaf18SBorislav Petkov } 225721afaf18SBorislav Petkov __setup("mce", mcheck_enable); 225821afaf18SBorislav Petkov 225921afaf18SBorislav Petkov int __init mcheck_init(void) 226021afaf18SBorislav Petkov { 2261c9c6d216STony Luck mce_register_decode_chain(&early_nb); 22628438b84aSJan H. Schönherr mce_register_decode_chain(&mce_uc_nb); 226321afaf18SBorislav Petkov mce_register_decode_chain(&mce_default_nb); 226421afaf18SBorislav Petkov 226521afaf18SBorislav Petkov INIT_WORK(&mce_work, mce_gen_pool_process); 226621afaf18SBorislav Petkov init_irq_work(&mce_irq_work, mce_irq_work_cb); 226721afaf18SBorislav Petkov 226821afaf18SBorislav Petkov return 0; 226921afaf18SBorislav Petkov } 227021afaf18SBorislav Petkov 227121afaf18SBorislav Petkov /* 227221afaf18SBorislav Petkov * mce_syscore: PM support 227321afaf18SBorislav Petkov */ 227421afaf18SBorislav Petkov 227521afaf18SBorislav Petkov /* 227621afaf18SBorislav Petkov * Disable machine checks on suspend and shutdown. We can't really handle 227721afaf18SBorislav Petkov * them later. 227821afaf18SBorislav Petkov */ 227921afaf18SBorislav Petkov static void mce_disable_error_reporting(void) 228021afaf18SBorislav Petkov { 2281b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 228221afaf18SBorislav Petkov int i; 228321afaf18SBorislav Petkov 2284c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 228521afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 228621afaf18SBorislav Petkov 228721afaf18SBorislav Petkov if (b->init) 22888121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), 0); 228921afaf18SBorislav Petkov } 229021afaf18SBorislav Petkov return; 229121afaf18SBorislav Petkov } 229221afaf18SBorislav Petkov 229321afaf18SBorislav Petkov static void vendor_disable_error_reporting(void) 229421afaf18SBorislav Petkov { 229521afaf18SBorislav Petkov /* 22966e898d2bSTony W Wang-oc * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these 22976e898d2bSTony W Wang-oc * MSRs are socket-wide. Disabling them for just a single offlined CPU 22986e898d2bSTony W Wang-oc * is bad, since it will inhibit reporting for all shared resources on 22996e898d2bSTony W Wang-oc * the socket like the last level cache (LLC), the integrated memory 23006e898d2bSTony W Wang-oc * controller (iMC), etc. 230121afaf18SBorislav Petkov */ 230221afaf18SBorislav Petkov if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || 230321afaf18SBorislav Petkov boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || 23046e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 23056e898d2bSTony W Wang-oc boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) 230621afaf18SBorislav Petkov return; 230721afaf18SBorislav Petkov 230821afaf18SBorislav Petkov mce_disable_error_reporting(); 230921afaf18SBorislav Petkov } 231021afaf18SBorislav Petkov 231121afaf18SBorislav Petkov static int mce_syscore_suspend(void) 231221afaf18SBorislav Petkov { 231321afaf18SBorislav Petkov vendor_disable_error_reporting(); 231421afaf18SBorislav Petkov return 0; 231521afaf18SBorislav Petkov } 231621afaf18SBorislav Petkov 231721afaf18SBorislav Petkov static void mce_syscore_shutdown(void) 231821afaf18SBorislav Petkov { 231921afaf18SBorislav Petkov vendor_disable_error_reporting(); 232021afaf18SBorislav Petkov } 232121afaf18SBorislav Petkov 232221afaf18SBorislav Petkov /* 232321afaf18SBorislav Petkov * On resume clear all MCE state. Don't want to see leftovers from the BIOS. 232421afaf18SBorislav Petkov * Only one CPU is active at this time, the others get re-added later using 232521afaf18SBorislav Petkov * CPU hotplug: 232621afaf18SBorislav Petkov */ 232721afaf18SBorislav Petkov static void mce_syscore_resume(void) 232821afaf18SBorislav Petkov { 232921afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 233021afaf18SBorislav Petkov __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); 233121afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 233221afaf18SBorislav Petkov } 233321afaf18SBorislav Petkov 233421afaf18SBorislav Petkov static struct syscore_ops mce_syscore_ops = { 233521afaf18SBorislav Petkov .suspend = mce_syscore_suspend, 233621afaf18SBorislav Petkov .shutdown = mce_syscore_shutdown, 233721afaf18SBorislav Petkov .resume = mce_syscore_resume, 233821afaf18SBorislav Petkov }; 233921afaf18SBorislav Petkov 234021afaf18SBorislav Petkov /* 234121afaf18SBorislav Petkov * mce_device: Sysfs support 234221afaf18SBorislav Petkov */ 234321afaf18SBorislav Petkov 234421afaf18SBorislav Petkov static void mce_cpu_restart(void *data) 234521afaf18SBorislav Petkov { 234621afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 234721afaf18SBorislav Petkov return; 234821afaf18SBorislav Petkov __mcheck_cpu_init_generic(); 234921afaf18SBorislav Petkov __mcheck_cpu_init_clear_banks(); 235021afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 235121afaf18SBorislav Petkov } 235221afaf18SBorislav Petkov 235321afaf18SBorislav Petkov /* Reinit MCEs after user configuration changes */ 235421afaf18SBorislav Petkov static void mce_restart(void) 235521afaf18SBorislav Petkov { 235621afaf18SBorislav Petkov mce_timer_delete_all(); 235721afaf18SBorislav Petkov on_each_cpu(mce_cpu_restart, NULL, 1); 2358*4783b9cbSYazen Ghannam mce_schedule_work(); 235921afaf18SBorislav Petkov } 236021afaf18SBorislav Petkov 236121afaf18SBorislav Petkov /* Toggle features for corrected errors */ 236221afaf18SBorislav Petkov static void mce_disable_cmci(void *data) 236321afaf18SBorislav Petkov { 236421afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 236521afaf18SBorislav Petkov return; 236621afaf18SBorislav Petkov cmci_clear(); 236721afaf18SBorislav Petkov } 236821afaf18SBorislav Petkov 236921afaf18SBorislav Petkov static void mce_enable_ce(void *all) 237021afaf18SBorislav Petkov { 237121afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 237221afaf18SBorislav Petkov return; 237321afaf18SBorislav Petkov cmci_reenable(); 237421afaf18SBorislav Petkov cmci_recheck(); 237521afaf18SBorislav Petkov if (all) 237621afaf18SBorislav Petkov __mcheck_cpu_init_timer(); 237721afaf18SBorislav Petkov } 237821afaf18SBorislav Petkov 237921afaf18SBorislav Petkov static struct bus_type mce_subsys = { 238021afaf18SBorislav Petkov .name = "machinecheck", 238121afaf18SBorislav Petkov .dev_name = "machinecheck", 238221afaf18SBorislav Petkov }; 238321afaf18SBorislav Petkov 238421afaf18SBorislav Petkov DEFINE_PER_CPU(struct device *, mce_device); 238521afaf18SBorislav Petkov 2386b4914508SYazen Ghannam static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr) 238721afaf18SBorislav Petkov { 2388b4914508SYazen Ghannam return container_of(attr, struct mce_bank_dev, attr); 238921afaf18SBorislav Petkov } 239021afaf18SBorislav Petkov 239121afaf18SBorislav Petkov static ssize_t show_bank(struct device *s, struct device_attribute *attr, 239221afaf18SBorislav Petkov char *buf) 239321afaf18SBorislav Petkov { 2394b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2395b4914508SYazen Ghannam struct mce_bank *b; 2396b4914508SYazen Ghannam 2397c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2398b4914508SYazen Ghannam return -EINVAL; 2399b4914508SYazen Ghannam 2400b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2401b4914508SYazen Ghannam 2402068b053dSYazen Ghannam if (!b->init) 2403068b053dSYazen Ghannam return -ENODEV; 2404068b053dSYazen Ghannam 2405b4914508SYazen Ghannam return sprintf(buf, "%llx\n", b->ctl); 240621afaf18SBorislav Petkov } 240721afaf18SBorislav Petkov 240821afaf18SBorislav Petkov static ssize_t set_bank(struct device *s, struct device_attribute *attr, 240921afaf18SBorislav Petkov const char *buf, size_t size) 241021afaf18SBorislav Petkov { 2411b4914508SYazen Ghannam u8 bank = attr_to_bank(attr)->bank; 2412b4914508SYazen Ghannam struct mce_bank *b; 241321afaf18SBorislav Petkov u64 new; 241421afaf18SBorislav Petkov 241521afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 241621afaf18SBorislav Petkov return -EINVAL; 241721afaf18SBorislav Petkov 2418c7d314f3SYazen Ghannam if (bank >= per_cpu(mce_num_banks, s->id)) 2419b4914508SYazen Ghannam return -EINVAL; 2420b4914508SYazen Ghannam 2421b4914508SYazen Ghannam b = &per_cpu(mce_banks_array, s->id)[bank]; 2422b4914508SYazen Ghannam 2423068b053dSYazen Ghannam if (!b->init) 2424068b053dSYazen Ghannam return -ENODEV; 2425068b053dSYazen Ghannam 2426b4914508SYazen Ghannam b->ctl = new; 242721afaf18SBorislav Petkov mce_restart(); 242821afaf18SBorislav Petkov 242921afaf18SBorislav Petkov return size; 243021afaf18SBorislav Petkov } 243121afaf18SBorislav Petkov 243221afaf18SBorislav Petkov static ssize_t set_ignore_ce(struct device *s, 243321afaf18SBorislav Petkov struct device_attribute *attr, 243421afaf18SBorislav Petkov const char *buf, size_t size) 243521afaf18SBorislav Petkov { 243621afaf18SBorislav Petkov u64 new; 243721afaf18SBorislav Petkov 243821afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 243921afaf18SBorislav Petkov return -EINVAL; 244021afaf18SBorislav Petkov 244121afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 244221afaf18SBorislav Petkov if (mca_cfg.ignore_ce ^ !!new) { 244321afaf18SBorislav Petkov if (new) { 244421afaf18SBorislav Petkov /* disable ce features */ 244521afaf18SBorislav Petkov mce_timer_delete_all(); 244621afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 244721afaf18SBorislav Petkov mca_cfg.ignore_ce = true; 244821afaf18SBorislav Petkov } else { 244921afaf18SBorislav Petkov /* enable ce features */ 245021afaf18SBorislav Petkov mca_cfg.ignore_ce = false; 245121afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, (void *)1, 1); 245221afaf18SBorislav Petkov } 245321afaf18SBorislav Petkov } 245421afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 245521afaf18SBorislav Petkov 245621afaf18SBorislav Petkov return size; 245721afaf18SBorislav Petkov } 245821afaf18SBorislav Petkov 245921afaf18SBorislav Petkov static ssize_t set_cmci_disabled(struct device *s, 246021afaf18SBorislav Petkov struct device_attribute *attr, 246121afaf18SBorislav Petkov const char *buf, size_t size) 246221afaf18SBorislav Petkov { 246321afaf18SBorislav Petkov u64 new; 246421afaf18SBorislav Petkov 246521afaf18SBorislav Petkov if (kstrtou64(buf, 0, &new) < 0) 246621afaf18SBorislav Petkov return -EINVAL; 246721afaf18SBorislav Petkov 246821afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 246921afaf18SBorislav Petkov if (mca_cfg.cmci_disabled ^ !!new) { 247021afaf18SBorislav Petkov if (new) { 247121afaf18SBorislav Petkov /* disable cmci */ 247221afaf18SBorislav Petkov on_each_cpu(mce_disable_cmci, NULL, 1); 247321afaf18SBorislav Petkov mca_cfg.cmci_disabled = true; 247421afaf18SBorislav Petkov } else { 247521afaf18SBorislav Petkov /* enable cmci */ 247621afaf18SBorislav Petkov mca_cfg.cmci_disabled = false; 247721afaf18SBorislav Petkov on_each_cpu(mce_enable_ce, NULL, 1); 247821afaf18SBorislav Petkov } 247921afaf18SBorislav Petkov } 248021afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 248121afaf18SBorislav Petkov 248221afaf18SBorislav Petkov return size; 248321afaf18SBorislav Petkov } 248421afaf18SBorislav Petkov 248521afaf18SBorislav Petkov static ssize_t store_int_with_restart(struct device *s, 248621afaf18SBorislav Petkov struct device_attribute *attr, 248721afaf18SBorislav Petkov const char *buf, size_t size) 248821afaf18SBorislav Petkov { 248921afaf18SBorislav Petkov unsigned long old_check_interval = check_interval; 249021afaf18SBorislav Petkov ssize_t ret = device_store_ulong(s, attr, buf, size); 249121afaf18SBorislav Petkov 249221afaf18SBorislav Petkov if (check_interval == old_check_interval) 249321afaf18SBorislav Petkov return ret; 249421afaf18SBorislav Petkov 249521afaf18SBorislav Petkov mutex_lock(&mce_sysfs_mutex); 249621afaf18SBorislav Petkov mce_restart(); 249721afaf18SBorislav Petkov mutex_unlock(&mce_sysfs_mutex); 249821afaf18SBorislav Petkov 249921afaf18SBorislav Petkov return ret; 250021afaf18SBorislav Petkov } 250121afaf18SBorislav Petkov 250221afaf18SBorislav Petkov static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); 250321afaf18SBorislav Petkov static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); 250443505646STony Luck static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all); 250521afaf18SBorislav Petkov 250621afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_check_interval = { 250721afaf18SBorislav Petkov __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), 250821afaf18SBorislav Petkov &check_interval 250921afaf18SBorislav Petkov }; 251021afaf18SBorislav Petkov 251121afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_ignore_ce = { 251221afaf18SBorislav Petkov __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), 251321afaf18SBorislav Petkov &mca_cfg.ignore_ce 251421afaf18SBorislav Petkov }; 251521afaf18SBorislav Petkov 251621afaf18SBorislav Petkov static struct dev_ext_attribute dev_attr_cmci_disabled = { 251721afaf18SBorislav Petkov __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), 251821afaf18SBorislav Petkov &mca_cfg.cmci_disabled 251921afaf18SBorislav Petkov }; 252021afaf18SBorislav Petkov 252121afaf18SBorislav Petkov static struct device_attribute *mce_device_attrs[] = { 252221afaf18SBorislav Petkov &dev_attr_check_interval.attr, 252321afaf18SBorislav Petkov #ifdef CONFIG_X86_MCELOG_LEGACY 252421afaf18SBorislav Petkov &dev_attr_trigger, 252521afaf18SBorislav Petkov #endif 252621afaf18SBorislav Petkov &dev_attr_monarch_timeout.attr, 252721afaf18SBorislav Petkov &dev_attr_dont_log_ce.attr, 252843505646STony Luck &dev_attr_print_all.attr, 252921afaf18SBorislav Petkov &dev_attr_ignore_ce.attr, 253021afaf18SBorislav Petkov &dev_attr_cmci_disabled.attr, 253121afaf18SBorislav Petkov NULL 253221afaf18SBorislav Petkov }; 253321afaf18SBorislav Petkov 253421afaf18SBorislav Petkov static cpumask_var_t mce_device_initialized; 253521afaf18SBorislav Petkov 253621afaf18SBorislav Petkov static void mce_device_release(struct device *dev) 253721afaf18SBorislav Petkov { 253821afaf18SBorislav Petkov kfree(dev); 253921afaf18SBorislav Petkov } 254021afaf18SBorislav Petkov 2541b4914508SYazen Ghannam /* Per CPU device init. All of the CPUs still share the same bank device: */ 254221afaf18SBorislav Petkov static int mce_device_create(unsigned int cpu) 254321afaf18SBorislav Petkov { 254421afaf18SBorislav Petkov struct device *dev; 254521afaf18SBorislav Petkov int err; 254621afaf18SBorislav Petkov int i, j; 254721afaf18SBorislav Petkov 254821afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) 254921afaf18SBorislav Petkov return -EIO; 255021afaf18SBorislav Petkov 255121afaf18SBorislav Petkov dev = per_cpu(mce_device, cpu); 255221afaf18SBorislav Petkov if (dev) 255321afaf18SBorislav Petkov return 0; 255421afaf18SBorislav Petkov 255521afaf18SBorislav Petkov dev = kzalloc(sizeof(*dev), GFP_KERNEL); 255621afaf18SBorislav Petkov if (!dev) 255721afaf18SBorislav Petkov return -ENOMEM; 255821afaf18SBorislav Petkov dev->id = cpu; 255921afaf18SBorislav Petkov dev->bus = &mce_subsys; 256021afaf18SBorislav Petkov dev->release = &mce_device_release; 256121afaf18SBorislav Petkov 256221afaf18SBorislav Petkov err = device_register(dev); 256321afaf18SBorislav Petkov if (err) { 256421afaf18SBorislav Petkov put_device(dev); 256521afaf18SBorislav Petkov return err; 256621afaf18SBorislav Petkov } 256721afaf18SBorislav Petkov 256821afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) { 256921afaf18SBorislav Petkov err = device_create_file(dev, mce_device_attrs[i]); 257021afaf18SBorislav Petkov if (err) 257121afaf18SBorislav Petkov goto error; 257221afaf18SBorislav Petkov } 2573c7d314f3SYazen Ghannam for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) { 2574b4914508SYazen Ghannam err = device_create_file(dev, &mce_bank_devs[j].attr); 257521afaf18SBorislav Petkov if (err) 257621afaf18SBorislav Petkov goto error2; 257721afaf18SBorislav Petkov } 257821afaf18SBorislav Petkov cpumask_set_cpu(cpu, mce_device_initialized); 257921afaf18SBorislav Petkov per_cpu(mce_device, cpu) = dev; 258021afaf18SBorislav Petkov 258121afaf18SBorislav Petkov return 0; 258221afaf18SBorislav Petkov error2: 258321afaf18SBorislav Petkov while (--j >= 0) 2584b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[j].attr); 258521afaf18SBorislav Petkov error: 258621afaf18SBorislav Petkov while (--i >= 0) 258721afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 258821afaf18SBorislav Petkov 258921afaf18SBorislav Petkov device_unregister(dev); 259021afaf18SBorislav Petkov 259121afaf18SBorislav Petkov return err; 259221afaf18SBorislav Petkov } 259321afaf18SBorislav Petkov 259421afaf18SBorislav Petkov static void mce_device_remove(unsigned int cpu) 259521afaf18SBorislav Petkov { 259621afaf18SBorislav Petkov struct device *dev = per_cpu(mce_device, cpu); 259721afaf18SBorislav Petkov int i; 259821afaf18SBorislav Petkov 259921afaf18SBorislav Petkov if (!cpumask_test_cpu(cpu, mce_device_initialized)) 260021afaf18SBorislav Petkov return; 260121afaf18SBorislav Petkov 260221afaf18SBorislav Petkov for (i = 0; mce_device_attrs[i]; i++) 260321afaf18SBorislav Petkov device_remove_file(dev, mce_device_attrs[i]); 260421afaf18SBorislav Petkov 2605c7d314f3SYazen Ghannam for (i = 0; i < per_cpu(mce_num_banks, cpu); i++) 2606b4914508SYazen Ghannam device_remove_file(dev, &mce_bank_devs[i].attr); 260721afaf18SBorislav Petkov 260821afaf18SBorislav Petkov device_unregister(dev); 260921afaf18SBorislav Petkov cpumask_clear_cpu(cpu, mce_device_initialized); 261021afaf18SBorislav Petkov per_cpu(mce_device, cpu) = NULL; 261121afaf18SBorislav Petkov } 261221afaf18SBorislav Petkov 261321afaf18SBorislav Petkov /* Make sure there are no machine checks on offlined CPUs. */ 261421afaf18SBorislav Petkov static void mce_disable_cpu(void) 261521afaf18SBorislav Petkov { 261621afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 261721afaf18SBorislav Petkov return; 261821afaf18SBorislav Petkov 261921afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 262021afaf18SBorislav Petkov cmci_clear(); 262121afaf18SBorislav Petkov 262221afaf18SBorislav Petkov vendor_disable_error_reporting(); 262321afaf18SBorislav Petkov } 262421afaf18SBorislav Petkov 262521afaf18SBorislav Petkov static void mce_reenable_cpu(void) 262621afaf18SBorislav Petkov { 2627b4914508SYazen Ghannam struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); 262821afaf18SBorislav Petkov int i; 262921afaf18SBorislav Petkov 263021afaf18SBorislav Petkov if (!mce_available(raw_cpu_ptr(&cpu_info))) 263121afaf18SBorislav Petkov return; 263221afaf18SBorislav Petkov 263321afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 263421afaf18SBorislav Petkov cmci_reenable(); 2635c7d314f3SYazen Ghannam for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 263621afaf18SBorislav Petkov struct mce_bank *b = &mce_banks[i]; 263721afaf18SBorislav Petkov 263821afaf18SBorislav Petkov if (b->init) 26398121b8f9SBorislav Petkov wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); 264021afaf18SBorislav Petkov } 264121afaf18SBorislav Petkov } 264221afaf18SBorislav Petkov 264321afaf18SBorislav Petkov static int mce_cpu_dead(unsigned int cpu) 264421afaf18SBorislav Petkov { 264521afaf18SBorislav Petkov mce_intel_hcpu_update(cpu); 264621afaf18SBorislav Petkov 264721afaf18SBorislav Petkov /* intentionally ignoring frozen here */ 264821afaf18SBorislav Petkov if (!cpuhp_tasks_frozen) 264921afaf18SBorislav Petkov cmci_rediscover(); 265021afaf18SBorislav Petkov return 0; 265121afaf18SBorislav Petkov } 265221afaf18SBorislav Petkov 265321afaf18SBorislav Petkov static int mce_cpu_online(unsigned int cpu) 265421afaf18SBorislav Petkov { 265521afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 265621afaf18SBorislav Petkov int ret; 265721afaf18SBorislav Petkov 265821afaf18SBorislav Petkov mce_device_create(cpu); 265921afaf18SBorislav Petkov 266021afaf18SBorislav Petkov ret = mce_threshold_create_device(cpu); 266121afaf18SBorislav Petkov if (ret) { 266221afaf18SBorislav Petkov mce_device_remove(cpu); 266321afaf18SBorislav Petkov return ret; 266421afaf18SBorislav Petkov } 266521afaf18SBorislav Petkov mce_reenable_cpu(); 266621afaf18SBorislav Petkov mce_start_timer(t); 266721afaf18SBorislav Petkov return 0; 266821afaf18SBorislav Petkov } 266921afaf18SBorislav Petkov 267021afaf18SBorislav Petkov static int mce_cpu_pre_down(unsigned int cpu) 267121afaf18SBorislav Petkov { 267221afaf18SBorislav Petkov struct timer_list *t = this_cpu_ptr(&mce_timer); 267321afaf18SBorislav Petkov 267421afaf18SBorislav Petkov mce_disable_cpu(); 267521afaf18SBorislav Petkov del_timer_sync(t); 267621afaf18SBorislav Petkov mce_threshold_remove_device(cpu); 267721afaf18SBorislav Petkov mce_device_remove(cpu); 267821afaf18SBorislav Petkov return 0; 267921afaf18SBorislav Petkov } 268021afaf18SBorislav Petkov 268121afaf18SBorislav Petkov static __init void mce_init_banks(void) 268221afaf18SBorislav Petkov { 268321afaf18SBorislav Petkov int i; 268421afaf18SBorislav Petkov 2685b4914508SYazen Ghannam for (i = 0; i < MAX_NR_BANKS; i++) { 2686b4914508SYazen Ghannam struct mce_bank_dev *b = &mce_bank_devs[i]; 268721afaf18SBorislav Petkov struct device_attribute *a = &b->attr; 268821afaf18SBorislav Petkov 2689b4914508SYazen Ghannam b->bank = i; 2690b4914508SYazen Ghannam 269121afaf18SBorislav Petkov sysfs_attr_init(&a->attr); 269221afaf18SBorislav Petkov a->attr.name = b->attrname; 269321afaf18SBorislav Petkov snprintf(b->attrname, ATTR_LEN, "bank%d", i); 269421afaf18SBorislav Petkov 269521afaf18SBorislav Petkov a->attr.mode = 0644; 269621afaf18SBorislav Petkov a->show = show_bank; 269721afaf18SBorislav Petkov a->store = set_bank; 269821afaf18SBorislav Petkov } 269921afaf18SBorislav Petkov } 270021afaf18SBorislav Petkov 27016e7a41c6SThomas Gleixner /* 27026e7a41c6SThomas Gleixner * When running on XEN, this initcall is ordered against the XEN mcelog 27036e7a41c6SThomas Gleixner * initcall: 27046e7a41c6SThomas Gleixner * 27056e7a41c6SThomas Gleixner * device_initcall(xen_late_init_mcelog); 27066e7a41c6SThomas Gleixner * device_initcall_sync(mcheck_init_device); 27076e7a41c6SThomas Gleixner */ 270821afaf18SBorislav Petkov static __init int mcheck_init_device(void) 270921afaf18SBorislav Petkov { 271021afaf18SBorislav Petkov int err; 271121afaf18SBorislav Petkov 271221afaf18SBorislav Petkov /* 271321afaf18SBorislav Petkov * Check if we have a spare virtual bit. This will only become 271421afaf18SBorislav Petkov * a problem if/when we move beyond 5-level page tables. 271521afaf18SBorislav Petkov */ 271621afaf18SBorislav Petkov MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63); 271721afaf18SBorislav Petkov 271821afaf18SBorislav Petkov if (!mce_available(&boot_cpu_data)) { 271921afaf18SBorislav Petkov err = -EIO; 272021afaf18SBorislav Petkov goto err_out; 272121afaf18SBorislav Petkov } 272221afaf18SBorislav Petkov 272321afaf18SBorislav Petkov if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { 272421afaf18SBorislav Petkov err = -ENOMEM; 272521afaf18SBorislav Petkov goto err_out; 272621afaf18SBorislav Petkov } 272721afaf18SBorislav Petkov 272821afaf18SBorislav Petkov mce_init_banks(); 272921afaf18SBorislav Petkov 273021afaf18SBorislav Petkov err = subsys_system_register(&mce_subsys, NULL); 273121afaf18SBorislav Petkov if (err) 273221afaf18SBorislav Petkov goto err_out_mem; 273321afaf18SBorislav Petkov 273421afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL, 273521afaf18SBorislav Petkov mce_cpu_dead); 273621afaf18SBorislav Petkov if (err) 273721afaf18SBorislav Petkov goto err_out_mem; 273821afaf18SBorislav Petkov 27396e7a41c6SThomas Gleixner /* 27406e7a41c6SThomas Gleixner * Invokes mce_cpu_online() on all CPUs which are online when 27416e7a41c6SThomas Gleixner * the state is installed. 27426e7a41c6SThomas Gleixner */ 274321afaf18SBorislav Petkov err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online", 274421afaf18SBorislav Petkov mce_cpu_online, mce_cpu_pre_down); 274521afaf18SBorislav Petkov if (err < 0) 274621afaf18SBorislav Petkov goto err_out_online; 274721afaf18SBorislav Petkov 274821afaf18SBorislav Petkov register_syscore_ops(&mce_syscore_ops); 274921afaf18SBorislav Petkov 275021afaf18SBorislav Petkov return 0; 275121afaf18SBorislav Petkov 275221afaf18SBorislav Petkov err_out_online: 275321afaf18SBorislav Petkov cpuhp_remove_state(CPUHP_X86_MCE_DEAD); 275421afaf18SBorislav Petkov 275521afaf18SBorislav Petkov err_out_mem: 275621afaf18SBorislav Petkov free_cpumask_var(mce_device_initialized); 275721afaf18SBorislav Petkov 275821afaf18SBorislav Petkov err_out: 275921afaf18SBorislav Petkov pr_err("Unable to init MCE device (rc: %d)\n", err); 276021afaf18SBorislav Petkov 276121afaf18SBorislav Petkov return err; 276221afaf18SBorislav Petkov } 276321afaf18SBorislav Petkov device_initcall_sync(mcheck_init_device); 276421afaf18SBorislav Petkov 276521afaf18SBorislav Petkov /* 276621afaf18SBorislav Petkov * Old style boot options parsing. Only for compatibility. 276721afaf18SBorislav Petkov */ 276821afaf18SBorislav Petkov static int __init mcheck_disable(char *str) 276921afaf18SBorislav Petkov { 277021afaf18SBorislav Petkov mca_cfg.disabled = 1; 277121afaf18SBorislav Petkov return 1; 277221afaf18SBorislav Petkov } 277321afaf18SBorislav Petkov __setup("nomce", mcheck_disable); 277421afaf18SBorislav Petkov 277521afaf18SBorislav Petkov #ifdef CONFIG_DEBUG_FS 277621afaf18SBorislav Petkov struct dentry *mce_get_debugfs_dir(void) 277721afaf18SBorislav Petkov { 277821afaf18SBorislav Petkov static struct dentry *dmce; 277921afaf18SBorislav Petkov 278021afaf18SBorislav Petkov if (!dmce) 278121afaf18SBorislav Petkov dmce = debugfs_create_dir("mce", NULL); 278221afaf18SBorislav Petkov 278321afaf18SBorislav Petkov return dmce; 278421afaf18SBorislav Petkov } 278521afaf18SBorislav Petkov 278621afaf18SBorislav Petkov static void mce_reset(void) 278721afaf18SBorislav Petkov { 278821afaf18SBorislav Petkov atomic_set(&mce_fake_panicked, 0); 278921afaf18SBorislav Petkov atomic_set(&mce_executing, 0); 279021afaf18SBorislav Petkov atomic_set(&mce_callin, 0); 279121afaf18SBorislav Petkov atomic_set(&global_nwo, 0); 27927bb39313SPaul E. McKenney cpumask_setall(&mce_missing_cpus); 279321afaf18SBorislav Petkov } 279421afaf18SBorislav Petkov 279521afaf18SBorislav Petkov static int fake_panic_get(void *data, u64 *val) 279621afaf18SBorislav Petkov { 279721afaf18SBorislav Petkov *val = fake_panic; 279821afaf18SBorislav Petkov return 0; 279921afaf18SBorislav Petkov } 280021afaf18SBorislav Petkov 280121afaf18SBorislav Petkov static int fake_panic_set(void *data, u64 val) 280221afaf18SBorislav Petkov { 280321afaf18SBorislav Petkov mce_reset(); 280421afaf18SBorislav Petkov fake_panic = val; 280521afaf18SBorislav Petkov return 0; 280621afaf18SBorislav Petkov } 280721afaf18SBorislav Petkov 280828156d76SYueHaibing DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set, 280928156d76SYueHaibing "%llu\n"); 281021afaf18SBorislav Petkov 28116e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) 281221afaf18SBorislav Petkov { 28136e4f929eSGreg Kroah-Hartman struct dentry *dmce; 281421afaf18SBorislav Petkov 281521afaf18SBorislav Petkov dmce = mce_get_debugfs_dir(); 28166e4f929eSGreg Kroah-Hartman debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL, 28176e4f929eSGreg Kroah-Hartman &fake_panic_fops); 281821afaf18SBorislav Petkov } 281921afaf18SBorislav Petkov #else 28206e4f929eSGreg Kroah-Hartman static void __init mcheck_debugfs_init(void) { } 282121afaf18SBorislav Petkov #endif 282221afaf18SBorislav Petkov 282321afaf18SBorislav Petkov static int __init mcheck_late_init(void) 282421afaf18SBorislav Petkov { 282521afaf18SBorislav Petkov if (mca_cfg.recovery) 2826ec6347bbSDan Williams enable_copy_mc_fragile(); 282721afaf18SBorislav Petkov 282821afaf18SBorislav Petkov mcheck_debugfs_init(); 282921afaf18SBorislav Petkov 283021afaf18SBorislav Petkov /* 283121afaf18SBorislav Petkov * Flush out everything that has been logged during early boot, now that 283221afaf18SBorislav Petkov * everything has been initialized (workqueues, decoders, ...). 283321afaf18SBorislav Petkov */ 283421afaf18SBorislav Petkov mce_schedule_work(); 283521afaf18SBorislav Petkov 283621afaf18SBorislav Petkov return 0; 283721afaf18SBorislav Petkov } 283821afaf18SBorislav Petkov late_initcall(mcheck_late_init); 2839