1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Bridge between MCE and APEI 4 * 5 * On some machine, corrected memory errors are reported via APEI 6 * generic hardware error source (GHES) instead of corrected Machine 7 * Check. These corrected memory errors can be reported to user space 8 * through /dev/mcelog via faking a corrected Machine Check, so that 9 * the error memory page can be offlined by /sbin/mcelog if the error 10 * count for one page is beyond the threshold. 11 * 12 * For fatal MCE, save MCE record into persistent storage via ERST, so 13 * that the MCE record can be logged after reboot via ERST. 14 * 15 * Copyright 2010 Intel Corp. 16 * Author: Huang Ying <ying.huang@intel.com> 17 */ 18 19 #include <linux/export.h> 20 #include <linux/kernel.h> 21 #include <linux/acpi.h> 22 #include <linux/cper.h> 23 #include <acpi/apei.h> 24 #include <acpi/ghes.h> 25 #include <asm/mce.h> 26 27 #include "internal.h" 28 29 void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err) 30 { 31 struct mce m; 32 33 if (!(mem_err->validation_bits & CPER_MEM_VALID_PA)) 34 return; 35 36 mce_setup(&m); 37 m.bank = -1; 38 /* Fake a memory read error with unknown channel */ 39 m.status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | 0x9f; 40 41 if (severity >= GHES_SEV_RECOVERABLE) 42 m.status |= MCI_STATUS_UC; 43 44 if (severity >= GHES_SEV_PANIC) { 45 m.status |= MCI_STATUS_PCC; 46 m.tsc = rdtsc(); 47 } 48 49 m.addr = mem_err->physical_addr; 50 mce_log(&m); 51 } 52 EXPORT_SYMBOL_GPL(apei_mce_report_mem_error); 53 54 int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) 55 { 56 const u64 *i_mce = ((const u64 *) (ctx_info + 1)); 57 unsigned int cpu; 58 struct mce m; 59 60 if (!boot_cpu_has(X86_FEATURE_SMCA)) 61 return -EINVAL; 62 63 /* 64 * The starting address of the register array extracted from BERT must 65 * match with the first expected register in the register layout of 66 * SMCA address space. This address corresponds to banks's MCA_STATUS 67 * register. 68 * 69 * Match any MCi_STATUS register by turning off bank numbers. 70 */ 71 if ((ctx_info->msr_addr & MSR_AMD64_SMCA_MC0_STATUS) != 72 MSR_AMD64_SMCA_MC0_STATUS) 73 return -EINVAL; 74 75 /* 76 * The register array size must be large enough to include all the 77 * SMCA registers which need to be extracted. 78 * 79 * The number of registers in the register array is determined by 80 * Register Array Size/8 as defined in UEFI spec v2.8, sec N.2.4.2.2. 81 * The register layout is fixed and currently the raw data in the 82 * register array includes 6 SMCA registers which the kernel can 83 * extract. 84 */ 85 if (ctx_info->reg_arr_size < 48) 86 return -EINVAL; 87 88 mce_setup(&m); 89 90 m.extcpu = -1; 91 m.socketid = -1; 92 93 for_each_possible_cpu(cpu) { 94 if (cpu_data(cpu).initial_apicid == lapic_id) { 95 m.extcpu = cpu; 96 m.socketid = cpu_data(m.extcpu).phys_proc_id; 97 break; 98 } 99 } 100 101 m.apicid = lapic_id; 102 m.bank = (ctx_info->msr_addr >> 4) & 0xFF; 103 m.status = *i_mce; 104 m.addr = *(i_mce + 1); 105 m.misc = *(i_mce + 2); 106 /* Skipping MCA_CONFIG */ 107 m.ipid = *(i_mce + 4); 108 m.synd = *(i_mce + 5); 109 110 mce_log(&m); 111 112 return 0; 113 } 114 115 #define CPER_CREATOR_MCE \ 116 GUID_INIT(0x75a574e3, 0x5052, 0x4b29, 0x8a, 0x8e, 0xbe, 0x2c, \ 117 0x64, 0x90, 0xb8, 0x9d) 118 #define CPER_SECTION_TYPE_MCE \ 119 GUID_INIT(0xfe08ffbe, 0x95e4, 0x4be7, 0xbc, 0x73, 0x40, 0x96, \ 120 0x04, 0x4a, 0x38, 0xfc) 121 122 /* 123 * CPER specification (in UEFI specification 2.3 appendix N) requires 124 * byte-packed. 125 */ 126 struct cper_mce_record { 127 struct cper_record_header hdr; 128 struct cper_section_descriptor sec_hdr; 129 struct mce mce; 130 } __packed; 131 132 int apei_write_mce(struct mce *m) 133 { 134 struct cper_mce_record rcd; 135 136 memset(&rcd, 0, sizeof(rcd)); 137 memcpy(rcd.hdr.signature, CPER_SIG_RECORD, CPER_SIG_SIZE); 138 rcd.hdr.revision = CPER_RECORD_REV; 139 rcd.hdr.signature_end = CPER_SIG_END; 140 rcd.hdr.section_count = 1; 141 rcd.hdr.error_severity = CPER_SEV_FATAL; 142 /* timestamp, platform_id, partition_id are all invalid */ 143 rcd.hdr.validation_bits = 0; 144 rcd.hdr.record_length = sizeof(rcd); 145 rcd.hdr.creator_id = CPER_CREATOR_MCE; 146 rcd.hdr.notification_type = CPER_NOTIFY_MCE; 147 rcd.hdr.record_id = cper_next_record_id(); 148 rcd.hdr.flags = CPER_HW_ERROR_FLAGS_PREVERR; 149 150 rcd.sec_hdr.section_offset = (void *)&rcd.mce - (void *)&rcd; 151 rcd.sec_hdr.section_length = sizeof(rcd.mce); 152 rcd.sec_hdr.revision = CPER_SEC_REV; 153 /* fru_id and fru_text is invalid */ 154 rcd.sec_hdr.validation_bits = 0; 155 rcd.sec_hdr.flags = CPER_SEC_PRIMARY; 156 rcd.sec_hdr.section_type = CPER_SECTION_TYPE_MCE; 157 rcd.sec_hdr.section_severity = CPER_SEV_FATAL; 158 159 memcpy(&rcd.mce, m, sizeof(*m)); 160 161 return erst_write(&rcd.hdr); 162 } 163 164 ssize_t apei_read_mce(struct mce *m, u64 *record_id) 165 { 166 struct cper_mce_record rcd; 167 int rc, pos; 168 169 rc = erst_get_record_id_begin(&pos); 170 if (rc) 171 return rc; 172 retry: 173 rc = erst_get_record_id_next(&pos, record_id); 174 if (rc) 175 goto out; 176 /* no more record */ 177 if (*record_id == APEI_ERST_INVALID_RECORD_ID) 178 goto out; 179 rc = erst_read(*record_id, &rcd.hdr, sizeof(rcd)); 180 /* someone else has cleared the record, try next one */ 181 if (rc == -ENOENT) 182 goto retry; 183 else if (rc < 0) 184 goto out; 185 /* try to skip other type records in storage */ 186 else if (rc != sizeof(rcd) || 187 !guid_equal(&rcd.hdr.creator_id, &CPER_CREATOR_MCE)) 188 goto retry; 189 memcpy(m, &rcd.mce, sizeof(*m)); 190 rc = sizeof(*m); 191 out: 192 erst_get_record_id_end(); 193 194 return rc; 195 } 196 197 /* Check whether there is record in ERST */ 198 int apei_check_mce(void) 199 { 200 return erst_get_record_count(); 201 } 202 203 int apei_clear_mce(u64 record_id) 204 { 205 return erst_clear(record_id); 206 } 207