1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Bridge between MCE and APEI 4 * 5 * On some machine, corrected memory errors are reported via APEI 6 * generic hardware error source (GHES) instead of corrected Machine 7 * Check. These corrected memory errors can be reported to user space 8 * through /dev/mcelog via faking a corrected Machine Check, so that 9 * the error memory page can be offlined by /sbin/mcelog if the error 10 * count for one page is beyond the threshold. 11 * 12 * For fatal MCE, save MCE record into persistent storage via ERST, so 13 * that the MCE record can be logged after reboot via ERST. 14 * 15 * Copyright 2010 Intel Corp. 16 * Author: Huang Ying <ying.huang@intel.com> 17 */ 18 19 #include <linux/export.h> 20 #include <linux/kernel.h> 21 #include <linux/acpi.h> 22 #include <linux/cper.h> 23 #include <acpi/apei.h> 24 #include <acpi/ghes.h> 25 #include <asm/mce.h> 26 27 #include "internal.h" 28 29 void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err) 30 { 31 struct mce m; 32 int lsb; 33 34 if (!(mem_err->validation_bits & CPER_MEM_VALID_PA)) 35 return; 36 37 /* 38 * Even if the ->validation_bits are set for address mask, 39 * to be extra safe, check and reject an error radius '0', 40 * and fall back to the default page size. 41 */ 42 if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK) 43 lsb = find_first_bit((void *)&mem_err->physical_addr_mask, PAGE_SHIFT); 44 else 45 lsb = PAGE_SHIFT; 46 47 mce_setup(&m); 48 m.bank = -1; 49 /* Fake a memory read error with unknown channel */ 50 m.status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 0x9f; 51 m.misc = (MCI_MISC_ADDR_PHYS << 6) | lsb; 52 53 if (severity >= GHES_SEV_RECOVERABLE) 54 m.status |= MCI_STATUS_UC; 55 56 if (severity >= GHES_SEV_PANIC) { 57 m.status |= MCI_STATUS_PCC; 58 m.tsc = rdtsc(); 59 } 60 61 m.addr = mem_err->physical_addr; 62 mce_log(&m); 63 } 64 EXPORT_SYMBOL_GPL(apei_mce_report_mem_error); 65 66 int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) 67 { 68 const u64 *i_mce = ((const u64 *) (ctx_info + 1)); 69 unsigned int cpu; 70 struct mce m; 71 72 if (!boot_cpu_has(X86_FEATURE_SMCA)) 73 return -EINVAL; 74 75 /* 76 * The starting address of the register array extracted from BERT must 77 * match with the first expected register in the register layout of 78 * SMCA address space. This address corresponds to banks's MCA_STATUS 79 * register. 80 * 81 * Match any MCi_STATUS register by turning off bank numbers. 82 */ 83 if ((ctx_info->msr_addr & MSR_AMD64_SMCA_MC0_STATUS) != 84 MSR_AMD64_SMCA_MC0_STATUS) 85 return -EINVAL; 86 87 /* 88 * The register array size must be large enough to include all the 89 * SMCA registers which need to be extracted. 90 * 91 * The number of registers in the register array is determined by 92 * Register Array Size/8 as defined in UEFI spec v2.8, sec N.2.4.2.2. 93 * The register layout is fixed and currently the raw data in the 94 * register array includes 6 SMCA registers which the kernel can 95 * extract. 96 */ 97 if (ctx_info->reg_arr_size < 48) 98 return -EINVAL; 99 100 mce_setup(&m); 101 102 m.extcpu = -1; 103 m.socketid = -1; 104 105 for_each_possible_cpu(cpu) { 106 if (cpu_data(cpu).initial_apicid == lapic_id) { 107 m.extcpu = cpu; 108 m.socketid = cpu_data(m.extcpu).phys_proc_id; 109 break; 110 } 111 } 112 113 m.apicid = lapic_id; 114 m.bank = (ctx_info->msr_addr >> 4) & 0xFF; 115 m.status = *i_mce; 116 m.addr = *(i_mce + 1); 117 m.misc = *(i_mce + 2); 118 /* Skipping MCA_CONFIG */ 119 m.ipid = *(i_mce + 4); 120 m.synd = *(i_mce + 5); 121 122 mce_log(&m); 123 124 return 0; 125 } 126 127 #define CPER_CREATOR_MCE \ 128 GUID_INIT(0x75a574e3, 0x5052, 0x4b29, 0x8a, 0x8e, 0xbe, 0x2c, \ 129 0x64, 0x90, 0xb8, 0x9d) 130 #define CPER_SECTION_TYPE_MCE \ 131 GUID_INIT(0xfe08ffbe, 0x95e4, 0x4be7, 0xbc, 0x73, 0x40, 0x96, \ 132 0x04, 0x4a, 0x38, 0xfc) 133 134 /* 135 * CPER specification (in UEFI specification 2.3 appendix N) requires 136 * byte-packed. 137 */ 138 struct cper_mce_record { 139 struct cper_record_header hdr; 140 struct cper_section_descriptor sec_hdr; 141 struct mce mce; 142 } __packed; 143 144 int apei_write_mce(struct mce *m) 145 { 146 struct cper_mce_record rcd; 147 148 memset(&rcd, 0, sizeof(rcd)); 149 memcpy(rcd.hdr.signature, CPER_SIG_RECORD, CPER_SIG_SIZE); 150 rcd.hdr.revision = CPER_RECORD_REV; 151 rcd.hdr.signature_end = CPER_SIG_END; 152 rcd.hdr.section_count = 1; 153 rcd.hdr.error_severity = CPER_SEV_FATAL; 154 /* timestamp, platform_id, partition_id are all invalid */ 155 rcd.hdr.validation_bits = 0; 156 rcd.hdr.record_length = sizeof(rcd); 157 rcd.hdr.creator_id = CPER_CREATOR_MCE; 158 rcd.hdr.notification_type = CPER_NOTIFY_MCE; 159 rcd.hdr.record_id = cper_next_record_id(); 160 rcd.hdr.flags = CPER_HW_ERROR_FLAGS_PREVERR; 161 162 rcd.sec_hdr.section_offset = (void *)&rcd.mce - (void *)&rcd; 163 rcd.sec_hdr.section_length = sizeof(rcd.mce); 164 rcd.sec_hdr.revision = CPER_SEC_REV; 165 /* fru_id and fru_text is invalid */ 166 rcd.sec_hdr.validation_bits = 0; 167 rcd.sec_hdr.flags = CPER_SEC_PRIMARY; 168 rcd.sec_hdr.section_type = CPER_SECTION_TYPE_MCE; 169 rcd.sec_hdr.section_severity = CPER_SEV_FATAL; 170 171 memcpy(&rcd.mce, m, sizeof(*m)); 172 173 return erst_write(&rcd.hdr); 174 } 175 176 ssize_t apei_read_mce(struct mce *m, u64 *record_id) 177 { 178 struct cper_mce_record rcd; 179 int rc, pos; 180 181 rc = erst_get_record_id_begin(&pos); 182 if (rc) 183 return rc; 184 retry: 185 rc = erst_get_record_id_next(&pos, record_id); 186 if (rc) 187 goto out; 188 /* no more record */ 189 if (*record_id == APEI_ERST_INVALID_RECORD_ID) 190 goto out; 191 rc = erst_read_record(*record_id, &rcd.hdr, sizeof(rcd), sizeof(rcd), 192 &CPER_CREATOR_MCE); 193 /* someone else has cleared the record, try next one */ 194 if (rc == -ENOENT) 195 goto retry; 196 else if (rc < 0) 197 goto out; 198 199 memcpy(m, &rcd.mce, sizeof(*m)); 200 rc = sizeof(*m); 201 out: 202 erst_get_record_id_end(); 203 204 return rc; 205 } 206 207 /* Check whether there is record in ERST */ 208 int apei_check_mce(void) 209 { 210 return erst_get_record_count(); 211 } 212 213 int apei_clear_mce(u64 record_id) 214 { 215 return erst_clear(record_id); 216 } 217