1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Bridge between MCE and APEI 4 * 5 * On some machine, corrected memory errors are reported via APEI 6 * generic hardware error source (GHES) instead of corrected Machine 7 * Check. These corrected memory errors can be reported to user space 8 * through /dev/mcelog via faking a corrected Machine Check, so that 9 * the error memory page can be offlined by /sbin/mcelog if the error 10 * count for one page is beyond the threshold. 11 * 12 * For fatal MCE, save MCE record into persistent storage via ERST, so 13 * that the MCE record can be logged after reboot via ERST. 14 * 15 * Copyright 2010 Intel Corp. 16 * Author: Huang Ying <ying.huang@intel.com> 17 */ 18 19 #include <linux/export.h> 20 #include <linux/kernel.h> 21 #include <linux/acpi.h> 22 #include <linux/cper.h> 23 #include <acpi/apei.h> 24 #include <acpi/ghes.h> 25 #include <asm/mce.h> 26 27 #include "internal.h" 28 29 void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err) 30 { 31 struct mce m; 32 33 if (!(mem_err->validation_bits & CPER_MEM_VALID_PA)) 34 return; 35 36 mce_setup(&m); 37 m.bank = -1; 38 /* Fake a memory read error with unknown channel */ 39 m.status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 0x9f; 40 m.misc = (MCI_MISC_ADDR_PHYS << 6) | PAGE_SHIFT; 41 42 if (severity >= GHES_SEV_RECOVERABLE) 43 m.status |= MCI_STATUS_UC; 44 45 if (severity >= GHES_SEV_PANIC) { 46 m.status |= MCI_STATUS_PCC; 47 m.tsc = rdtsc(); 48 } 49 50 m.addr = mem_err->physical_addr; 51 mce_log(&m); 52 } 53 EXPORT_SYMBOL_GPL(apei_mce_report_mem_error); 54 55 int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) 56 { 57 const u64 *i_mce = ((const u64 *) (ctx_info + 1)); 58 unsigned int cpu; 59 struct mce m; 60 61 if (!boot_cpu_has(X86_FEATURE_SMCA)) 62 return -EINVAL; 63 64 /* 65 * The starting address of the register array extracted from BERT must 66 * match with the first expected register in the register layout of 67 * SMCA address space. This address corresponds to banks's MCA_STATUS 68 * register. 69 * 70 * Match any MCi_STATUS register by turning off bank numbers. 71 */ 72 if ((ctx_info->msr_addr & MSR_AMD64_SMCA_MC0_STATUS) != 73 MSR_AMD64_SMCA_MC0_STATUS) 74 return -EINVAL; 75 76 /* 77 * The register array size must be large enough to include all the 78 * SMCA registers which need to be extracted. 79 * 80 * The number of registers in the register array is determined by 81 * Register Array Size/8 as defined in UEFI spec v2.8, sec N.2.4.2.2. 82 * The register layout is fixed and currently the raw data in the 83 * register array includes 6 SMCA registers which the kernel can 84 * extract. 85 */ 86 if (ctx_info->reg_arr_size < 48) 87 return -EINVAL; 88 89 mce_setup(&m); 90 91 m.extcpu = -1; 92 m.socketid = -1; 93 94 for_each_possible_cpu(cpu) { 95 if (cpu_data(cpu).initial_apicid == lapic_id) { 96 m.extcpu = cpu; 97 m.socketid = cpu_data(m.extcpu).phys_proc_id; 98 break; 99 } 100 } 101 102 m.apicid = lapic_id; 103 m.bank = (ctx_info->msr_addr >> 4) & 0xFF; 104 m.status = *i_mce; 105 m.addr = *(i_mce + 1); 106 m.misc = *(i_mce + 2); 107 /* Skipping MCA_CONFIG */ 108 m.ipid = *(i_mce + 4); 109 m.synd = *(i_mce + 5); 110 111 mce_log(&m); 112 113 return 0; 114 } 115 116 #define CPER_CREATOR_MCE \ 117 GUID_INIT(0x75a574e3, 0x5052, 0x4b29, 0x8a, 0x8e, 0xbe, 0x2c, \ 118 0x64, 0x90, 0xb8, 0x9d) 119 #define CPER_SECTION_TYPE_MCE \ 120 GUID_INIT(0xfe08ffbe, 0x95e4, 0x4be7, 0xbc, 0x73, 0x40, 0x96, \ 121 0x04, 0x4a, 0x38, 0xfc) 122 123 /* 124 * CPER specification (in UEFI specification 2.3 appendix N) requires 125 * byte-packed. 126 */ 127 struct cper_mce_record { 128 struct cper_record_header hdr; 129 struct cper_section_descriptor sec_hdr; 130 struct mce mce; 131 } __packed; 132 133 int apei_write_mce(struct mce *m) 134 { 135 struct cper_mce_record rcd; 136 137 memset(&rcd, 0, sizeof(rcd)); 138 memcpy(rcd.hdr.signature, CPER_SIG_RECORD, CPER_SIG_SIZE); 139 rcd.hdr.revision = CPER_RECORD_REV; 140 rcd.hdr.signature_end = CPER_SIG_END; 141 rcd.hdr.section_count = 1; 142 rcd.hdr.error_severity = CPER_SEV_FATAL; 143 /* timestamp, platform_id, partition_id are all invalid */ 144 rcd.hdr.validation_bits = 0; 145 rcd.hdr.record_length = sizeof(rcd); 146 rcd.hdr.creator_id = CPER_CREATOR_MCE; 147 rcd.hdr.notification_type = CPER_NOTIFY_MCE; 148 rcd.hdr.record_id = cper_next_record_id(); 149 rcd.hdr.flags = CPER_HW_ERROR_FLAGS_PREVERR; 150 151 rcd.sec_hdr.section_offset = (void *)&rcd.mce - (void *)&rcd; 152 rcd.sec_hdr.section_length = sizeof(rcd.mce); 153 rcd.sec_hdr.revision = CPER_SEC_REV; 154 /* fru_id and fru_text is invalid */ 155 rcd.sec_hdr.validation_bits = 0; 156 rcd.sec_hdr.flags = CPER_SEC_PRIMARY; 157 rcd.sec_hdr.section_type = CPER_SECTION_TYPE_MCE; 158 rcd.sec_hdr.section_severity = CPER_SEV_FATAL; 159 160 memcpy(&rcd.mce, m, sizeof(*m)); 161 162 return erst_write(&rcd.hdr); 163 } 164 165 ssize_t apei_read_mce(struct mce *m, u64 *record_id) 166 { 167 struct cper_mce_record rcd; 168 int rc, pos; 169 170 rc = erst_get_record_id_begin(&pos); 171 if (rc) 172 return rc; 173 retry: 174 rc = erst_get_record_id_next(&pos, record_id); 175 if (rc) 176 goto out; 177 /* no more record */ 178 if (*record_id == APEI_ERST_INVALID_RECORD_ID) 179 goto out; 180 rc = erst_read_record(*record_id, &rcd.hdr, sizeof(rcd), sizeof(rcd), 181 &CPER_CREATOR_MCE); 182 /* someone else has cleared the record, try next one */ 183 if (rc == -ENOENT) 184 goto retry; 185 else if (rc < 0) 186 goto out; 187 188 memcpy(m, &rcd.mce, sizeof(*m)); 189 rc = sizeof(*m); 190 out: 191 erst_get_record_id_end(); 192 193 return rc; 194 } 195 196 /* Check whether there is record in ERST */ 197 int apei_check_mce(void) 198 { 199 return erst_get_record_count(); 200 } 201 202 int apei_clear_mce(u64 record_id) 203 { 204 return erst_clear(record_id); 205 } 206