1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (c) 2005-2016 Advanced Micro Devices, Inc. 4 * 5 * Written by Jacob Shin - AMD, Inc. 6 * Maintained by: Borislav Petkov <bp@alien8.de> 7 * 8 * All MC4_MISCi registers are shared between cores on a node. 9 */ 10 #include <linux/interrupt.h> 11 #include <linux/notifier.h> 12 #include <linux/kobject.h> 13 #include <linux/percpu.h> 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/sysfs.h> 17 #include <linux/slab.h> 18 #include <linux/init.h> 19 #include <linux/cpu.h> 20 #include <linux/smp.h> 21 #include <linux/string.h> 22 23 #include <asm/amd_nb.h> 24 #include <asm/traps.h> 25 #include <asm/apic.h> 26 #include <asm/mce.h> 27 #include <asm/msr.h> 28 #include <asm/trace/irq_vectors.h> 29 30 #include "internal.h" 31 32 #define NR_BLOCKS 5 33 #define THRESHOLD_MAX 0xFFF 34 #define INT_TYPE_APIC 0x00020000 35 #define MASK_VALID_HI 0x80000000 36 #define MASK_CNTP_HI 0x40000000 37 #define MASK_LOCKED_HI 0x20000000 38 #define MASK_LVTOFF_HI 0x00F00000 39 #define MASK_COUNT_EN_HI 0x00080000 40 #define MASK_INT_TYPE_HI 0x00060000 41 #define MASK_OVERFLOW_HI 0x00010000 42 #define MASK_ERR_COUNT_HI 0x00000FFF 43 #define MASK_BLKPTR_LO 0xFF000000 44 #define MCG_XBLK_ADDR 0xC0000400 45 46 /* Deferred error settings */ 47 #define MSR_CU_DEF_ERR 0xC0000410 48 #define MASK_DEF_LVTOFF 0x000000F0 49 #define MASK_DEF_INT_TYPE 0x00000006 50 #define DEF_LVT_OFF 0x2 51 #define DEF_INT_TYPE_APIC 0x2 52 53 /* Scalable MCA: */ 54 55 /* Threshold LVT offset is at MSR0xC0000410[15:12] */ 56 #define SMCA_THR_LVT_OFF 0xF000 57 58 static bool thresholding_irq_en; 59 60 static const char * const th_names[] = { 61 "load_store", 62 "insn_fetch", 63 "combined_unit", 64 "decode_unit", 65 "northbridge", 66 "execution_unit", 67 }; 68 69 static const char * const smca_umc_block_names[] = { 70 "dram_ecc", 71 "misc_umc" 72 }; 73 74 #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype)) 75 76 struct smca_hwid { 77 unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */ 78 u32 hwid_mcatype; /* (hwid,mcatype) tuple */ 79 }; 80 81 struct smca_bank { 82 const struct smca_hwid *hwid; 83 u32 id; /* Value of MCA_IPID[InstanceId]. */ 84 u8 sysfs_id; /* Value used for sysfs name. */ 85 }; 86 87 static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks); 88 static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts); 89 90 struct smca_bank_name { 91 const char *name; /* Short name for sysfs */ 92 const char *long_name; /* Long name for pretty-printing */ 93 }; 94 95 static struct smca_bank_name smca_names[] = { 96 [SMCA_LS ... SMCA_LS_V2] = { "load_store", "Load Store Unit" }, 97 [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, 98 [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, 99 [SMCA_DE] = { "decode_unit", "Decode Unit" }, 100 [SMCA_RESERVED] = { "reserved", "Reserved" }, 101 [SMCA_EX] = { "execution_unit", "Execution Unit" }, 102 [SMCA_FP] = { "floating_point", "Floating Point Unit" }, 103 [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, 104 [SMCA_CS ... SMCA_CS_V2] = { "coherent_slave", "Coherent Slave" }, 105 [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, 106 107 /* UMC v2 is separate because both of them can exist in a single system. */ 108 [SMCA_UMC] = { "umc", "Unified Memory Controller" }, 109 [SMCA_UMC_V2] = { "umc_v2", "Unified Memory Controller v2" }, 110 [SMCA_PB] = { "param_block", "Parameter Block" }, 111 [SMCA_PSP ... SMCA_PSP_V2] = { "psp", "Platform Security Processor" }, 112 [SMCA_SMU ... SMCA_SMU_V2] = { "smu", "System Management Unit" }, 113 [SMCA_MP5] = { "mp5", "Microprocessor 5 Unit" }, 114 [SMCA_MPDMA] = { "mpdma", "MPDMA Unit" }, 115 [SMCA_NBIO] = { "nbio", "Northbridge IO Unit" }, 116 [SMCA_PCIE ... SMCA_PCIE_V2] = { "pcie", "PCI Express Unit" }, 117 [SMCA_XGMI_PCS] = { "xgmi_pcs", "Ext Global Memory Interconnect PCS Unit" }, 118 [SMCA_NBIF] = { "nbif", "NBIF Unit" }, 119 [SMCA_SHUB] = { "shub", "System Hub Unit" }, 120 [SMCA_SATA] = { "sata", "SATA Unit" }, 121 [SMCA_USB] = { "usb", "USB Unit" }, 122 [SMCA_GMI_PCS] = { "gmi_pcs", "Global Memory Interconnect PCS Unit" }, 123 [SMCA_XGMI_PHY] = { "xgmi_phy", "Ext Global Memory Interconnect PHY Unit" }, 124 [SMCA_WAFL_PHY] = { "wafl_phy", "WAFL PHY Unit" }, 125 [SMCA_GMI_PHY] = { "gmi_phy", "Global Memory Interconnect PHY Unit" }, 126 }; 127 128 static const char *smca_get_name(enum smca_bank_types t) 129 { 130 if (t >= N_SMCA_BANK_TYPES) 131 return NULL; 132 133 return smca_names[t].name; 134 } 135 136 const char *smca_get_long_name(enum smca_bank_types t) 137 { 138 if (t >= N_SMCA_BANK_TYPES) 139 return NULL; 140 141 return smca_names[t].long_name; 142 } 143 EXPORT_SYMBOL_GPL(smca_get_long_name); 144 145 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) 146 { 147 struct smca_bank *b; 148 149 if (bank >= MAX_NR_BANKS) 150 return N_SMCA_BANK_TYPES; 151 152 b = &per_cpu(smca_banks, cpu)[bank]; 153 if (!b->hwid) 154 return N_SMCA_BANK_TYPES; 155 156 return b->hwid->bank_type; 157 } 158 EXPORT_SYMBOL_GPL(smca_get_bank_type); 159 160 static const struct smca_hwid smca_hwid_mcatypes[] = { 161 /* { bank_type, hwid_mcatype } */ 162 163 /* Reserved type */ 164 { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) }, 165 166 /* ZN Core (HWID=0xB0) MCA types */ 167 { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) }, 168 { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) }, 169 { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) }, 170 { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) }, 171 { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) }, 172 /* HWID 0xB0 MCATYPE 0x4 is Reserved */ 173 { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) }, 174 { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) }, 175 { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) }, 176 177 /* Data Fabric MCA types */ 178 { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, 179 { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, 180 { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, 181 182 /* Unified Memory Controller MCA type */ 183 { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, 184 { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) }, 185 186 /* Parameter Block MCA type */ 187 { SMCA_PB, HWID_MCATYPE(0x05, 0x0) }, 188 189 /* Platform Security Processor MCA type */ 190 { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) }, 191 { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) }, 192 193 /* System Management Unit MCA type */ 194 { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) }, 195 { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) }, 196 197 /* Microprocessor 5 Unit MCA type */ 198 { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) }, 199 200 /* MPDMA MCA type */ 201 { SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) }, 202 203 /* Northbridge IO Unit MCA type */ 204 { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) }, 205 206 /* PCI Express Unit MCA type */ 207 { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) }, 208 { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) }, 209 210 { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) }, 211 { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) }, 212 { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) }, 213 { SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) }, 214 { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) }, 215 { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) }, 216 { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) }, 217 { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) }, 218 { SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) }, 219 }; 220 221 /* 222 * In SMCA enabled processors, we can have multiple banks for a given IP type. 223 * So to define a unique name for each bank, we use a temp c-string to append 224 * the MCA_IPID[InstanceId] to type's name in get_name(). 225 * 226 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN 227 * is greater than 8 plus 1 (for underscore) plus length of longest type name. 228 */ 229 #define MAX_MCATYPE_NAME_LEN 30 230 static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; 231 232 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); 233 234 /* 235 * A list of the banks enabled on each logical CPU. Controls which respective 236 * descriptors to initialize later in mce_threshold_create_device(). 237 */ 238 static DEFINE_PER_CPU(unsigned int, bank_map); 239 240 /* Map of banks that have more than MCA_MISC0 available. */ 241 static DEFINE_PER_CPU(u32, smca_misc_banks_map); 242 243 static void amd_threshold_interrupt(void); 244 static void amd_deferred_error_interrupt(void); 245 246 static void default_deferred_error_interrupt(void) 247 { 248 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); 249 } 250 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; 251 252 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) 253 { 254 u32 low, high; 255 256 /* 257 * For SMCA enabled processors, BLKPTR field of the first MISC register 258 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). 259 */ 260 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) 261 return; 262 263 if (!(low & MCI_CONFIG_MCAX)) 264 return; 265 266 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) 267 return; 268 269 if (low & MASK_BLKPTR_LO) 270 per_cpu(smca_misc_banks_map, cpu) |= BIT(bank); 271 272 } 273 274 static void smca_configure(unsigned int bank, unsigned int cpu) 275 { 276 u8 *bank_counts = this_cpu_ptr(smca_bank_counts); 277 const struct smca_hwid *s_hwid; 278 unsigned int i, hwid_mcatype; 279 u32 high, low; 280 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); 281 282 /* Set appropriate bits in MCA_CONFIG */ 283 if (!rdmsr_safe(smca_config, &low, &high)) { 284 /* 285 * OS is required to set the MCAX bit to acknowledge that it is 286 * now using the new MSR ranges and new registers under each 287 * bank. It also means that the OS will configure deferred 288 * errors in the new MCx_CONFIG register. If the bit is not set, 289 * uncorrectable errors will cause a system panic. 290 * 291 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) 292 */ 293 high |= BIT(0); 294 295 /* 296 * SMCA sets the Deferred Error Interrupt type per bank. 297 * 298 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us 299 * if the DeferredIntType bit field is available. 300 * 301 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the 302 * high portion of the MSR). OS should set this to 0x1 to enable 303 * APIC based interrupt. First, check that no interrupt has been 304 * set. 305 */ 306 if ((low & BIT(5)) && !((high >> 5) & 0x3)) 307 high |= BIT(5); 308 309 this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); 310 311 wrmsr(smca_config, low, high); 312 } 313 314 smca_set_misc_banks_map(bank, cpu); 315 316 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { 317 pr_warn("Failed to read MCA_IPID for bank %d\n", bank); 318 return; 319 } 320 321 hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, 322 (high & MCI_IPID_MCATYPE) >> 16); 323 324 for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { 325 s_hwid = &smca_hwid_mcatypes[i]; 326 327 if (hwid_mcatype == s_hwid->hwid_mcatype) { 328 this_cpu_ptr(smca_banks)[bank].hwid = s_hwid; 329 this_cpu_ptr(smca_banks)[bank].id = low; 330 this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++; 331 break; 332 } 333 } 334 } 335 336 struct thresh_restart { 337 struct threshold_block *b; 338 int reset; 339 int set_lvt_off; 340 int lvt_off; 341 u16 old_limit; 342 }; 343 344 static inline bool is_shared_bank(int bank) 345 { 346 /* 347 * Scalable MCA provides for only one core to have access to the MSRs of 348 * a shared bank. 349 */ 350 if (mce_flags.smca) 351 return false; 352 353 /* Bank 4 is for northbridge reporting and is thus shared */ 354 return (bank == 4); 355 } 356 357 static const char *bank4_names(const struct threshold_block *b) 358 { 359 switch (b->address) { 360 /* MSR4_MISC0 */ 361 case 0x00000413: 362 return "dram"; 363 364 case 0xc0000408: 365 return "ht_links"; 366 367 case 0xc0000409: 368 return "l3_cache"; 369 370 default: 371 WARN(1, "Funny MSR: 0x%08x\n", b->address); 372 return ""; 373 } 374 }; 375 376 377 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) 378 { 379 /* 380 * bank 4 supports APIC LVT interrupts implicitly since forever. 381 */ 382 if (bank == 4) 383 return true; 384 385 /* 386 * IntP: interrupt present; if this bit is set, the thresholding 387 * bank can generate APIC LVT interrupts 388 */ 389 return msr_high_bits & BIT(28); 390 } 391 392 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) 393 { 394 int msr = (hi & MASK_LVTOFF_HI) >> 20; 395 396 if (apic < 0) { 397 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " 398 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, 399 b->bank, b->block, b->address, hi, lo); 400 return 0; 401 } 402 403 if (apic != msr) { 404 /* 405 * On SMCA CPUs, LVT offset is programmed at a different MSR, and 406 * the BIOS provides the value. The original field where LVT offset 407 * was set is reserved. Return early here: 408 */ 409 if (mce_flags.smca) 410 return 0; 411 412 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " 413 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", 414 b->cpu, apic, b->bank, b->block, b->address, hi, lo); 415 return 0; 416 } 417 418 return 1; 419 }; 420 421 /* Reprogram MCx_MISC MSR behind this threshold bank. */ 422 static void threshold_restart_bank(void *_tr) 423 { 424 struct thresh_restart *tr = _tr; 425 u32 hi, lo; 426 427 /* sysfs write might race against an offline operation */ 428 if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off) 429 return; 430 431 rdmsr(tr->b->address, lo, hi); 432 433 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) 434 tr->reset = 1; /* limit cannot be lower than err count */ 435 436 if (tr->reset) { /* reset err count and overflow bit */ 437 hi = 438 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | 439 (THRESHOLD_MAX - tr->b->threshold_limit); 440 } else if (tr->old_limit) { /* change limit w/o reset */ 441 int new_count = (hi & THRESHOLD_MAX) + 442 (tr->old_limit - tr->b->threshold_limit); 443 444 hi = (hi & ~MASK_ERR_COUNT_HI) | 445 (new_count & THRESHOLD_MAX); 446 } 447 448 /* clear IntType */ 449 hi &= ~MASK_INT_TYPE_HI; 450 451 if (!tr->b->interrupt_capable) 452 goto done; 453 454 if (tr->set_lvt_off) { 455 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { 456 /* set new lvt offset */ 457 hi &= ~MASK_LVTOFF_HI; 458 hi |= tr->lvt_off << 20; 459 } 460 } 461 462 if (tr->b->interrupt_enable) 463 hi |= INT_TYPE_APIC; 464 465 done: 466 467 hi |= MASK_COUNT_EN_HI; 468 wrmsr(tr->b->address, lo, hi); 469 } 470 471 static void mce_threshold_block_init(struct threshold_block *b, int offset) 472 { 473 struct thresh_restart tr = { 474 .b = b, 475 .set_lvt_off = 1, 476 .lvt_off = offset, 477 }; 478 479 b->threshold_limit = THRESHOLD_MAX; 480 threshold_restart_bank(&tr); 481 }; 482 483 static int setup_APIC_mce_threshold(int reserved, int new) 484 { 485 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, 486 APIC_EILVT_MSG_FIX, 0)) 487 return new; 488 489 return reserved; 490 } 491 492 static int setup_APIC_deferred_error(int reserved, int new) 493 { 494 if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, 495 APIC_EILVT_MSG_FIX, 0)) 496 return new; 497 498 return reserved; 499 } 500 501 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) 502 { 503 u32 low = 0, high = 0; 504 int def_offset = -1, def_new; 505 506 if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) 507 return; 508 509 def_new = (low & MASK_DEF_LVTOFF) >> 4; 510 if (!(low & MASK_DEF_LVTOFF)) { 511 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); 512 def_new = DEF_LVT_OFF; 513 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); 514 } 515 516 def_offset = setup_APIC_deferred_error(def_offset, def_new); 517 if ((def_offset == def_new) && 518 (deferred_error_int_vector != amd_deferred_error_interrupt)) 519 deferred_error_int_vector = amd_deferred_error_interrupt; 520 521 if (!mce_flags.smca) 522 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; 523 524 wrmsr(MSR_CU_DEF_ERR, low, high); 525 } 526 527 static u32 smca_get_block_address(unsigned int bank, unsigned int block, 528 unsigned int cpu) 529 { 530 if (!block) 531 return MSR_AMD64_SMCA_MCx_MISC(bank); 532 533 if (!(per_cpu(smca_misc_banks_map, cpu) & BIT(bank))) 534 return 0; 535 536 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); 537 } 538 539 static u32 get_block_address(u32 current_addr, u32 low, u32 high, 540 unsigned int bank, unsigned int block, 541 unsigned int cpu) 542 { 543 u32 addr = 0, offset = 0; 544 545 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) 546 return addr; 547 548 if (mce_flags.smca) 549 return smca_get_block_address(bank, block, cpu); 550 551 /* Fall back to method we used for older processors: */ 552 switch (block) { 553 case 0: 554 addr = mca_msr_reg(bank, MCA_MISC); 555 break; 556 case 1: 557 offset = ((low & MASK_BLKPTR_LO) >> 21); 558 if (offset) 559 addr = MCG_XBLK_ADDR + offset; 560 break; 561 default: 562 addr = ++current_addr; 563 } 564 return addr; 565 } 566 567 static int 568 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 569 int offset, u32 misc_high) 570 { 571 unsigned int cpu = smp_processor_id(); 572 u32 smca_low, smca_high; 573 struct threshold_block b; 574 int new; 575 576 if (!block) 577 per_cpu(bank_map, cpu) |= (1 << bank); 578 579 memset(&b, 0, sizeof(b)); 580 b.cpu = cpu; 581 b.bank = bank; 582 b.block = block; 583 b.address = addr; 584 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); 585 586 if (!b.interrupt_capable) 587 goto done; 588 589 b.interrupt_enable = 1; 590 591 if (!mce_flags.smca) { 592 new = (misc_high & MASK_LVTOFF_HI) >> 20; 593 goto set_offset; 594 } 595 596 /* Gather LVT offset for thresholding: */ 597 if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) 598 goto out; 599 600 new = (smca_low & SMCA_THR_LVT_OFF) >> 12; 601 602 set_offset: 603 offset = setup_APIC_mce_threshold(offset, new); 604 if (offset == new) 605 thresholding_irq_en = true; 606 607 done: 608 mce_threshold_block_init(&b, offset); 609 610 out: 611 return offset; 612 } 613 614 bool amd_filter_mce(struct mce *m) 615 { 616 enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); 617 struct cpuinfo_x86 *c = &boot_cpu_data; 618 619 /* See Family 17h Models 10h-2Fh Erratum #1114. */ 620 if (c->x86 == 0x17 && 621 c->x86_model >= 0x10 && c->x86_model <= 0x2F && 622 bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10) 623 return true; 624 625 /* NB GART TLB error reporting is disabled by default. */ 626 if (c->x86 < 0x17) { 627 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5) 628 return true; 629 } 630 631 return false; 632 } 633 634 /* 635 * Turn off thresholding banks for the following conditions: 636 * - MC4_MISC thresholding is not supported on Family 0x15. 637 * - Prevent possible spurious interrupts from the IF bank on Family 0x17 638 * Models 0x10-0x2F due to Erratum #1114. 639 */ 640 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) 641 { 642 int i, num_msrs; 643 u64 hwcr; 644 bool need_toggle; 645 u32 msrs[NR_BLOCKS]; 646 647 if (c->x86 == 0x15 && bank == 4) { 648 msrs[0] = 0x00000413; /* MC4_MISC0 */ 649 msrs[1] = 0xc0000408; /* MC4_MISC1 */ 650 num_msrs = 2; 651 } else if (c->x86 == 0x17 && 652 (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { 653 654 if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF) 655 return; 656 657 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); 658 num_msrs = 1; 659 } else { 660 return; 661 } 662 663 rdmsrl(MSR_K7_HWCR, hwcr); 664 665 /* McStatusWrEn has to be set */ 666 need_toggle = !(hwcr & BIT(18)); 667 if (need_toggle) 668 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); 669 670 /* Clear CntP bit safely */ 671 for (i = 0; i < num_msrs; i++) 672 msr_clear_bit(msrs[i], 62); 673 674 /* restore old settings */ 675 if (need_toggle) 676 wrmsrl(MSR_K7_HWCR, hwcr); 677 } 678 679 /* cpu init entry point, called from mce.c with preempt off */ 680 void mce_amd_feature_init(struct cpuinfo_x86 *c) 681 { 682 unsigned int bank, block, cpu = smp_processor_id(); 683 u32 low = 0, high = 0, address = 0; 684 int offset = -1; 685 686 687 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 688 if (mce_flags.smca) 689 smca_configure(bank, cpu); 690 691 disable_err_thresholding(c, bank); 692 693 for (block = 0; block < NR_BLOCKS; ++block) { 694 address = get_block_address(address, low, high, bank, block, cpu); 695 if (!address) 696 break; 697 698 if (rdmsr_safe(address, &low, &high)) 699 break; 700 701 if (!(high & MASK_VALID_HI)) 702 continue; 703 704 if (!(high & MASK_CNTP_HI) || 705 (high & MASK_LOCKED_HI)) 706 continue; 707 708 offset = prepare_threshold_block(bank, block, address, offset, high); 709 } 710 } 711 712 if (mce_flags.succor) 713 deferred_error_interrupt_enable(c); 714 } 715 716 bool amd_mce_is_memory_error(struct mce *m) 717 { 718 /* ErrCodeExt[20:16] */ 719 u8 xec = (m->status >> 16) & 0x1f; 720 721 if (mce_flags.smca) 722 return smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC && xec == 0x0; 723 724 return m->bank == 4 && xec == 0x8; 725 } 726 727 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) 728 { 729 struct mce m; 730 731 mce_setup(&m); 732 733 m.status = status; 734 m.misc = misc; 735 m.bank = bank; 736 m.tsc = rdtsc(); 737 738 if (m.status & MCI_STATUS_ADDRV) { 739 m.addr = addr; 740 741 smca_extract_err_addr(&m); 742 } 743 744 if (mce_flags.smca) { 745 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); 746 747 if (m.status & MCI_STATUS_SYNDV) 748 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); 749 } 750 751 mce_log(&m); 752 } 753 754 DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) 755 { 756 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); 757 inc_irq_stat(irq_deferred_error_count); 758 deferred_error_int_vector(); 759 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); 760 ack_APIC_irq(); 761 } 762 763 /* 764 * Returns true if the logged error is deferred. False, otherwise. 765 */ 766 static inline bool 767 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) 768 { 769 u64 status, addr = 0; 770 771 rdmsrl(msr_stat, status); 772 if (!(status & MCI_STATUS_VAL)) 773 return false; 774 775 if (status & MCI_STATUS_ADDRV) 776 rdmsrl(msr_addr, addr); 777 778 __log_error(bank, status, addr, misc); 779 780 wrmsrl(msr_stat, 0); 781 782 return status & MCI_STATUS_DEFERRED; 783 } 784 785 static bool _log_error_deferred(unsigned int bank, u32 misc) 786 { 787 if (!_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), 788 mca_msr_reg(bank, MCA_ADDR), misc)) 789 return false; 790 791 /* 792 * Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers. 793 * Return true here to avoid accessing these registers. 794 */ 795 if (!mce_flags.smca) 796 return true; 797 798 /* Clear MCA_DESTAT if the deferred error was logged from MCA_STATUS. */ 799 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); 800 return true; 801 } 802 803 /* 804 * We have three scenarios for checking for Deferred errors: 805 * 806 * 1) Non-SMCA systems check MCA_STATUS and log error if found. 807 * 2) SMCA systems check MCA_STATUS. If error is found then log it and also 808 * clear MCA_DESTAT. 809 * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and 810 * log it. 811 */ 812 static void log_error_deferred(unsigned int bank) 813 { 814 if (_log_error_deferred(bank, 0)) 815 return; 816 817 /* 818 * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check 819 * for a valid error. 820 */ 821 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), 822 MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); 823 } 824 825 /* APIC interrupt handler for deferred errors */ 826 static void amd_deferred_error_interrupt(void) 827 { 828 unsigned int bank; 829 830 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) 831 log_error_deferred(bank); 832 } 833 834 static void log_error_thresholding(unsigned int bank, u64 misc) 835 { 836 _log_error_deferred(bank, misc); 837 } 838 839 static void log_and_reset_block(struct threshold_block *block) 840 { 841 struct thresh_restart tr; 842 u32 low = 0, high = 0; 843 844 if (!block) 845 return; 846 847 if (rdmsr_safe(block->address, &low, &high)) 848 return; 849 850 if (!(high & MASK_OVERFLOW_HI)) 851 return; 852 853 /* Log the MCE which caused the threshold event. */ 854 log_error_thresholding(block->bank, ((u64)high << 32) | low); 855 856 /* Reset threshold block after logging error. */ 857 memset(&tr, 0, sizeof(tr)); 858 tr.b = block; 859 threshold_restart_bank(&tr); 860 } 861 862 /* 863 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt 864 * goes off when error_count reaches threshold_limit. 865 */ 866 static void amd_threshold_interrupt(void) 867 { 868 struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; 869 struct threshold_bank **bp = this_cpu_read(threshold_banks); 870 unsigned int bank, cpu = smp_processor_id(); 871 872 /* 873 * Validate that the threshold bank has been initialized already. The 874 * handler is installed at boot time, but on a hotplug event the 875 * interrupt might fire before the data has been initialized. 876 */ 877 if (!bp) 878 return; 879 880 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 881 if (!(per_cpu(bank_map, cpu) & (1 << bank))) 882 continue; 883 884 first_block = bp[bank]->blocks; 885 if (!first_block) 886 continue; 887 888 /* 889 * The first block is also the head of the list. Check it first 890 * before iterating over the rest. 891 */ 892 log_and_reset_block(first_block); 893 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) 894 log_and_reset_block(block); 895 } 896 } 897 898 /* 899 * Sysfs Interface 900 */ 901 902 struct threshold_attr { 903 struct attribute attr; 904 ssize_t (*show) (struct threshold_block *, char *); 905 ssize_t (*store) (struct threshold_block *, const char *, size_t count); 906 }; 907 908 #define SHOW_FIELDS(name) \ 909 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ 910 { \ 911 return sprintf(buf, "%lu\n", (unsigned long) b->name); \ 912 } 913 SHOW_FIELDS(interrupt_enable) 914 SHOW_FIELDS(threshold_limit) 915 916 static ssize_t 917 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) 918 { 919 struct thresh_restart tr; 920 unsigned long new; 921 922 if (!b->interrupt_capable) 923 return -EINVAL; 924 925 if (kstrtoul(buf, 0, &new) < 0) 926 return -EINVAL; 927 928 b->interrupt_enable = !!new; 929 930 memset(&tr, 0, sizeof(tr)); 931 tr.b = b; 932 933 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 934 return -ENODEV; 935 936 return size; 937 } 938 939 static ssize_t 940 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) 941 { 942 struct thresh_restart tr; 943 unsigned long new; 944 945 if (kstrtoul(buf, 0, &new) < 0) 946 return -EINVAL; 947 948 if (new > THRESHOLD_MAX) 949 new = THRESHOLD_MAX; 950 if (new < 1) 951 new = 1; 952 953 memset(&tr, 0, sizeof(tr)); 954 tr.old_limit = b->threshold_limit; 955 b->threshold_limit = new; 956 tr.b = b; 957 958 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 959 return -ENODEV; 960 961 return size; 962 } 963 964 static ssize_t show_error_count(struct threshold_block *b, char *buf) 965 { 966 u32 lo, hi; 967 968 /* CPU might be offline by now */ 969 if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi)) 970 return -ENODEV; 971 972 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - 973 (THRESHOLD_MAX - b->threshold_limit))); 974 } 975 976 static struct threshold_attr error_count = { 977 .attr = {.name = __stringify(error_count), .mode = 0444 }, 978 .show = show_error_count, 979 }; 980 981 #define RW_ATTR(val) \ 982 static struct threshold_attr val = { \ 983 .attr = {.name = __stringify(val), .mode = 0644 }, \ 984 .show = show_## val, \ 985 .store = store_## val, \ 986 }; 987 988 RW_ATTR(interrupt_enable); 989 RW_ATTR(threshold_limit); 990 991 static struct attribute *default_attrs[] = { 992 &threshold_limit.attr, 993 &error_count.attr, 994 NULL, /* possibly interrupt_enable if supported, see below */ 995 NULL, 996 }; 997 ATTRIBUTE_GROUPS(default); 998 999 #define to_block(k) container_of(k, struct threshold_block, kobj) 1000 #define to_attr(a) container_of(a, struct threshold_attr, attr) 1001 1002 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) 1003 { 1004 struct threshold_block *b = to_block(kobj); 1005 struct threshold_attr *a = to_attr(attr); 1006 ssize_t ret; 1007 1008 ret = a->show ? a->show(b, buf) : -EIO; 1009 1010 return ret; 1011 } 1012 1013 static ssize_t store(struct kobject *kobj, struct attribute *attr, 1014 const char *buf, size_t count) 1015 { 1016 struct threshold_block *b = to_block(kobj); 1017 struct threshold_attr *a = to_attr(attr); 1018 ssize_t ret; 1019 1020 ret = a->store ? a->store(b, buf, count) : -EIO; 1021 1022 return ret; 1023 } 1024 1025 static const struct sysfs_ops threshold_ops = { 1026 .show = show, 1027 .store = store, 1028 }; 1029 1030 static void threshold_block_release(struct kobject *kobj); 1031 1032 static struct kobj_type threshold_ktype = { 1033 .sysfs_ops = &threshold_ops, 1034 .default_groups = default_groups, 1035 .release = threshold_block_release, 1036 }; 1037 1038 static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b) 1039 { 1040 enum smca_bank_types bank_type; 1041 1042 if (!mce_flags.smca) { 1043 if (b && bank == 4) 1044 return bank4_names(b); 1045 1046 return th_names[bank]; 1047 } 1048 1049 bank_type = smca_get_bank_type(cpu, bank); 1050 if (bank_type >= N_SMCA_BANK_TYPES) 1051 return NULL; 1052 1053 if (b && bank_type == SMCA_UMC) { 1054 if (b->block < ARRAY_SIZE(smca_umc_block_names)) 1055 return smca_umc_block_names[b->block]; 1056 return NULL; 1057 } 1058 1059 if (per_cpu(smca_bank_counts, cpu)[bank_type] == 1) 1060 return smca_get_name(bank_type); 1061 1062 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, 1063 "%s_%u", smca_get_name(bank_type), 1064 per_cpu(smca_banks, cpu)[bank].sysfs_id); 1065 return buf_mcatype; 1066 } 1067 1068 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb, 1069 unsigned int bank, unsigned int block, 1070 u32 address) 1071 { 1072 struct threshold_block *b = NULL; 1073 u32 low, high; 1074 int err; 1075 1076 if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS)) 1077 return 0; 1078 1079 if (rdmsr_safe(address, &low, &high)) 1080 return 0; 1081 1082 if (!(high & MASK_VALID_HI)) { 1083 if (block) 1084 goto recurse; 1085 else 1086 return 0; 1087 } 1088 1089 if (!(high & MASK_CNTP_HI) || 1090 (high & MASK_LOCKED_HI)) 1091 goto recurse; 1092 1093 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); 1094 if (!b) 1095 return -ENOMEM; 1096 1097 b->block = block; 1098 b->bank = bank; 1099 b->cpu = cpu; 1100 b->address = address; 1101 b->interrupt_enable = 0; 1102 b->interrupt_capable = lvt_interrupt_supported(bank, high); 1103 b->threshold_limit = THRESHOLD_MAX; 1104 1105 if (b->interrupt_capable) { 1106 default_attrs[2] = &interrupt_enable.attr; 1107 b->interrupt_enable = 1; 1108 } else { 1109 default_attrs[2] = NULL; 1110 } 1111 1112 INIT_LIST_HEAD(&b->miscj); 1113 1114 /* This is safe as @tb is not visible yet */ 1115 if (tb->blocks) 1116 list_add(&b->miscj, &tb->blocks->miscj); 1117 else 1118 tb->blocks = b; 1119 1120 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b)); 1121 if (err) 1122 goto out_free; 1123 recurse: 1124 address = get_block_address(address, low, high, bank, ++block, cpu); 1125 if (!address) 1126 return 0; 1127 1128 err = allocate_threshold_blocks(cpu, tb, bank, block, address); 1129 if (err) 1130 goto out_free; 1131 1132 if (b) 1133 kobject_uevent(&b->kobj, KOBJ_ADD); 1134 1135 return 0; 1136 1137 out_free: 1138 if (b) { 1139 list_del(&b->miscj); 1140 kobject_put(&b->kobj); 1141 } 1142 return err; 1143 } 1144 1145 static int __threshold_add_blocks(struct threshold_bank *b) 1146 { 1147 struct list_head *head = &b->blocks->miscj; 1148 struct threshold_block *pos = NULL; 1149 struct threshold_block *tmp = NULL; 1150 int err = 0; 1151 1152 err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); 1153 if (err) 1154 return err; 1155 1156 list_for_each_entry_safe(pos, tmp, head, miscj) { 1157 1158 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); 1159 if (err) { 1160 list_for_each_entry_safe_reverse(pos, tmp, head, miscj) 1161 kobject_del(&pos->kobj); 1162 1163 return err; 1164 } 1165 } 1166 return err; 1167 } 1168 1169 static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu, 1170 unsigned int bank) 1171 { 1172 struct device *dev = this_cpu_read(mce_device); 1173 struct amd_northbridge *nb = NULL; 1174 struct threshold_bank *b = NULL; 1175 const char *name = get_name(cpu, bank, NULL); 1176 int err = 0; 1177 1178 if (!dev) 1179 return -ENODEV; 1180 1181 if (is_shared_bank(bank)) { 1182 nb = node_to_amd_nb(topology_die_id(cpu)); 1183 1184 /* threshold descriptor already initialized on this node? */ 1185 if (nb && nb->bank4) { 1186 /* yes, use it */ 1187 b = nb->bank4; 1188 err = kobject_add(b->kobj, &dev->kobj, name); 1189 if (err) 1190 goto out; 1191 1192 bp[bank] = b; 1193 refcount_inc(&b->cpus); 1194 1195 err = __threshold_add_blocks(b); 1196 1197 goto out; 1198 } 1199 } 1200 1201 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); 1202 if (!b) { 1203 err = -ENOMEM; 1204 goto out; 1205 } 1206 1207 /* Associate the bank with the per-CPU MCE device */ 1208 b->kobj = kobject_create_and_add(name, &dev->kobj); 1209 if (!b->kobj) { 1210 err = -EINVAL; 1211 goto out_free; 1212 } 1213 1214 if (is_shared_bank(bank)) { 1215 b->shared = 1; 1216 refcount_set(&b->cpus, 1); 1217 1218 /* nb is already initialized, see above */ 1219 if (nb) { 1220 WARN_ON(nb->bank4); 1221 nb->bank4 = b; 1222 } 1223 } 1224 1225 err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC)); 1226 if (err) 1227 goto out_kobj; 1228 1229 bp[bank] = b; 1230 return 0; 1231 1232 out_kobj: 1233 kobject_put(b->kobj); 1234 out_free: 1235 kfree(b); 1236 out: 1237 return err; 1238 } 1239 1240 static void threshold_block_release(struct kobject *kobj) 1241 { 1242 kfree(to_block(kobj)); 1243 } 1244 1245 static void deallocate_threshold_blocks(struct threshold_bank *bank) 1246 { 1247 struct threshold_block *pos, *tmp; 1248 1249 list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) { 1250 list_del(&pos->miscj); 1251 kobject_put(&pos->kobj); 1252 } 1253 1254 kobject_put(&bank->blocks->kobj); 1255 } 1256 1257 static void __threshold_remove_blocks(struct threshold_bank *b) 1258 { 1259 struct threshold_block *pos = NULL; 1260 struct threshold_block *tmp = NULL; 1261 1262 kobject_del(b->kobj); 1263 1264 list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) 1265 kobject_del(&pos->kobj); 1266 } 1267 1268 static void threshold_remove_bank(struct threshold_bank *bank) 1269 { 1270 struct amd_northbridge *nb; 1271 1272 if (!bank->blocks) 1273 goto out_free; 1274 1275 if (!bank->shared) 1276 goto out_dealloc; 1277 1278 if (!refcount_dec_and_test(&bank->cpus)) { 1279 __threshold_remove_blocks(bank); 1280 return; 1281 } else { 1282 /* 1283 * The last CPU on this node using the shared bank is going 1284 * away, remove that bank now. 1285 */ 1286 nb = node_to_amd_nb(topology_die_id(smp_processor_id())); 1287 nb->bank4 = NULL; 1288 } 1289 1290 out_dealloc: 1291 deallocate_threshold_blocks(bank); 1292 1293 out_free: 1294 kobject_put(bank->kobj); 1295 kfree(bank); 1296 } 1297 1298 static void __threshold_remove_device(struct threshold_bank **bp) 1299 { 1300 unsigned int bank, numbanks = this_cpu_read(mce_num_banks); 1301 1302 for (bank = 0; bank < numbanks; bank++) { 1303 if (!bp[bank]) 1304 continue; 1305 1306 threshold_remove_bank(bp[bank]); 1307 bp[bank] = NULL; 1308 } 1309 kfree(bp); 1310 } 1311 1312 int mce_threshold_remove_device(unsigned int cpu) 1313 { 1314 struct threshold_bank **bp = this_cpu_read(threshold_banks); 1315 1316 if (!bp) 1317 return 0; 1318 1319 /* 1320 * Clear the pointer before cleaning up, so that the interrupt won't 1321 * touch anything of this. 1322 */ 1323 this_cpu_write(threshold_banks, NULL); 1324 1325 __threshold_remove_device(bp); 1326 return 0; 1327 } 1328 1329 /** 1330 * mce_threshold_create_device - Create the per-CPU MCE threshold device 1331 * @cpu: The plugged in CPU 1332 * 1333 * Create directories and files for all valid threshold banks. 1334 * 1335 * This is invoked from the CPU hotplug callback which was installed in 1336 * mcheck_init_device(). The invocation happens in context of the hotplug 1337 * thread running on @cpu. The callback is invoked on all CPUs which are 1338 * online when the callback is installed or during a real hotplug event. 1339 */ 1340 int mce_threshold_create_device(unsigned int cpu) 1341 { 1342 unsigned int numbanks, bank; 1343 struct threshold_bank **bp; 1344 int err; 1345 1346 if (!mce_flags.amd_threshold) 1347 return 0; 1348 1349 bp = this_cpu_read(threshold_banks); 1350 if (bp) 1351 return 0; 1352 1353 numbanks = this_cpu_read(mce_num_banks); 1354 bp = kcalloc(numbanks, sizeof(*bp), GFP_KERNEL); 1355 if (!bp) 1356 return -ENOMEM; 1357 1358 for (bank = 0; bank < numbanks; ++bank) { 1359 if (!(this_cpu_read(bank_map) & (1 << bank))) 1360 continue; 1361 err = threshold_create_bank(bp, cpu, bank); 1362 if (err) { 1363 __threshold_remove_device(bp); 1364 return err; 1365 } 1366 } 1367 this_cpu_write(threshold_banks, bp); 1368 1369 if (thresholding_irq_en) 1370 mce_threshold_vector = amd_threshold_interrupt; 1371 return 0; 1372 } 1373