1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (c) 2005-2016 Advanced Micro Devices, Inc. 4 * 5 * Written by Jacob Shin - AMD, Inc. 6 * Maintained by: Borislav Petkov <bp@alien8.de> 7 * 8 * All MC4_MISCi registers are shared between cores on a node. 9 */ 10 #include <linux/interrupt.h> 11 #include <linux/notifier.h> 12 #include <linux/kobject.h> 13 #include <linux/percpu.h> 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/sysfs.h> 17 #include <linux/slab.h> 18 #include <linux/init.h> 19 #include <linux/cpu.h> 20 #include <linux/smp.h> 21 #include <linux/string.h> 22 23 #include <asm/amd_nb.h> 24 #include <asm/traps.h> 25 #include <asm/apic.h> 26 #include <asm/mce.h> 27 #include <asm/msr.h> 28 #include <asm/trace/irq_vectors.h> 29 30 #include "internal.h" 31 32 #define NR_BLOCKS 5 33 #define THRESHOLD_MAX 0xFFF 34 #define INT_TYPE_APIC 0x00020000 35 #define MASK_VALID_HI 0x80000000 36 #define MASK_CNTP_HI 0x40000000 37 #define MASK_LOCKED_HI 0x20000000 38 #define MASK_LVTOFF_HI 0x00F00000 39 #define MASK_COUNT_EN_HI 0x00080000 40 #define MASK_INT_TYPE_HI 0x00060000 41 #define MASK_OVERFLOW_HI 0x00010000 42 #define MASK_ERR_COUNT_HI 0x00000FFF 43 #define MASK_BLKPTR_LO 0xFF000000 44 #define MCG_XBLK_ADDR 0xC0000400 45 46 /* Deferred error settings */ 47 #define MSR_CU_DEF_ERR 0xC0000410 48 #define MASK_DEF_LVTOFF 0x000000F0 49 #define MASK_DEF_INT_TYPE 0x00000006 50 #define DEF_LVT_OFF 0x2 51 #define DEF_INT_TYPE_APIC 0x2 52 53 /* Scalable MCA: */ 54 55 /* Threshold LVT offset is at MSR0xC0000410[15:12] */ 56 #define SMCA_THR_LVT_OFF 0xF000 57 58 static bool thresholding_irq_en; 59 60 static const char * const th_names[] = { 61 "load_store", 62 "insn_fetch", 63 "combined_unit", 64 "decode_unit", 65 "northbridge", 66 "execution_unit", 67 }; 68 69 static const char * const smca_umc_block_names[] = { 70 "dram_ecc", 71 "misc_umc" 72 }; 73 74 struct smca_bank_name { 75 const char *name; /* Short name for sysfs */ 76 const char *long_name; /* Long name for pretty-printing */ 77 }; 78 79 static struct smca_bank_name smca_names[] = { 80 [SMCA_LS] = { "load_store", "Load Store Unit" }, 81 [SMCA_LS_V2] = { "load_store", "Load Store Unit" }, 82 [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, 83 [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, 84 [SMCA_DE] = { "decode_unit", "Decode Unit" }, 85 [SMCA_RESERVED] = { "reserved", "Reserved" }, 86 [SMCA_EX] = { "execution_unit", "Execution Unit" }, 87 [SMCA_FP] = { "floating_point", "Floating Point Unit" }, 88 [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, 89 [SMCA_CS] = { "coherent_slave", "Coherent Slave" }, 90 [SMCA_CS_V2] = { "coherent_slave", "Coherent Slave" }, 91 [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, 92 [SMCA_UMC] = { "umc", "Unified Memory Controller" }, 93 [SMCA_PB] = { "param_block", "Parameter Block" }, 94 [SMCA_PSP] = { "psp", "Platform Security Processor" }, 95 [SMCA_PSP_V2] = { "psp", "Platform Security Processor" }, 96 [SMCA_SMU] = { "smu", "System Management Unit" }, 97 [SMCA_SMU_V2] = { "smu", "System Management Unit" }, 98 [SMCA_MP5] = { "mp5", "Microprocessor 5 Unit" }, 99 [SMCA_NBIO] = { "nbio", "Northbridge IO Unit" }, 100 [SMCA_PCIE] = { "pcie", "PCI Express Unit" }, 101 }; 102 103 static const char *smca_get_name(enum smca_bank_types t) 104 { 105 if (t >= N_SMCA_BANK_TYPES) 106 return NULL; 107 108 return smca_names[t].name; 109 } 110 111 const char *smca_get_long_name(enum smca_bank_types t) 112 { 113 if (t >= N_SMCA_BANK_TYPES) 114 return NULL; 115 116 return smca_names[t].long_name; 117 } 118 EXPORT_SYMBOL_GPL(smca_get_long_name); 119 120 static enum smca_bank_types smca_get_bank_type(unsigned int bank) 121 { 122 struct smca_bank *b; 123 124 if (bank >= MAX_NR_BANKS) 125 return N_SMCA_BANK_TYPES; 126 127 b = &smca_banks[bank]; 128 if (!b->hwid) 129 return N_SMCA_BANK_TYPES; 130 131 return b->hwid->bank_type; 132 } 133 134 static struct smca_hwid smca_hwid_mcatypes[] = { 135 /* { bank_type, hwid_mcatype, xec_bitmap } */ 136 137 /* Reserved type */ 138 { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 }, 139 140 /* ZN Core (HWID=0xB0) MCA types */ 141 { SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFFF }, 142 { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10), 0xFFFFFF }, 143 { SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF }, 144 { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF }, 145 { SMCA_DE, HWID_MCATYPE(0xB0, 0x3), 0x1FF }, 146 /* HWID 0xB0 MCATYPE 0x4 is Reserved */ 147 { SMCA_EX, HWID_MCATYPE(0xB0, 0x5), 0xFFF }, 148 { SMCA_FP, HWID_MCATYPE(0xB0, 0x6), 0x7F }, 149 { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF }, 150 151 /* Data Fabric MCA types */ 152 { SMCA_CS, HWID_MCATYPE(0x2E, 0x0), 0x1FF }, 153 { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1), 0x1F }, 154 { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2), 0x3FFF }, 155 156 /* Unified Memory Controller MCA type */ 157 { SMCA_UMC, HWID_MCATYPE(0x96, 0x0), 0xFF }, 158 159 /* Parameter Block MCA type */ 160 { SMCA_PB, HWID_MCATYPE(0x05, 0x0), 0x1 }, 161 162 /* Platform Security Processor MCA type */ 163 { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0), 0x1 }, 164 { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1), 0x3FFFF }, 165 166 /* System Management Unit MCA type */ 167 { SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 }, 168 { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1), 0x7FF }, 169 170 /* Microprocessor 5 Unit MCA type */ 171 { SMCA_MP5, HWID_MCATYPE(0x01, 0x2), 0x3FF }, 172 173 /* Northbridge IO Unit MCA type */ 174 { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0), 0x1F }, 175 176 /* PCI Express Unit MCA type */ 177 { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0), 0x1F }, 178 }; 179 180 struct smca_bank smca_banks[MAX_NR_BANKS]; 181 EXPORT_SYMBOL_GPL(smca_banks); 182 183 /* 184 * In SMCA enabled processors, we can have multiple banks for a given IP type. 185 * So to define a unique name for each bank, we use a temp c-string to append 186 * the MCA_IPID[InstanceId] to type's name in get_name(). 187 * 188 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN 189 * is greater than 8 plus 1 (for underscore) plus length of longest type name. 190 */ 191 #define MAX_MCATYPE_NAME_LEN 30 192 static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; 193 194 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); 195 196 /* 197 * A list of the banks enabled on each logical CPU. Controls which respective 198 * descriptors to initialize later in mce_threshold_create_device(). 199 */ 200 static DEFINE_PER_CPU(unsigned int, bank_map); 201 202 /* Map of banks that have more than MCA_MISC0 available. */ 203 static DEFINE_PER_CPU(u32, smca_misc_banks_map); 204 205 static void amd_threshold_interrupt(void); 206 static void amd_deferred_error_interrupt(void); 207 208 static void default_deferred_error_interrupt(void) 209 { 210 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); 211 } 212 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; 213 214 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) 215 { 216 u32 low, high; 217 218 /* 219 * For SMCA enabled processors, BLKPTR field of the first MISC register 220 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). 221 */ 222 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) 223 return; 224 225 if (!(low & MCI_CONFIG_MCAX)) 226 return; 227 228 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) 229 return; 230 231 if (low & MASK_BLKPTR_LO) 232 per_cpu(smca_misc_banks_map, cpu) |= BIT(bank); 233 234 } 235 236 static void smca_configure(unsigned int bank, unsigned int cpu) 237 { 238 unsigned int i, hwid_mcatype; 239 struct smca_hwid *s_hwid; 240 u32 high, low; 241 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); 242 243 /* Set appropriate bits in MCA_CONFIG */ 244 if (!rdmsr_safe(smca_config, &low, &high)) { 245 /* 246 * OS is required to set the MCAX bit to acknowledge that it is 247 * now using the new MSR ranges and new registers under each 248 * bank. It also means that the OS will configure deferred 249 * errors in the new MCx_CONFIG register. If the bit is not set, 250 * uncorrectable errors will cause a system panic. 251 * 252 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) 253 */ 254 high |= BIT(0); 255 256 /* 257 * SMCA sets the Deferred Error Interrupt type per bank. 258 * 259 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us 260 * if the DeferredIntType bit field is available. 261 * 262 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the 263 * high portion of the MSR). OS should set this to 0x1 to enable 264 * APIC based interrupt. First, check that no interrupt has been 265 * set. 266 */ 267 if ((low & BIT(5)) && !((high >> 5) & 0x3)) 268 high |= BIT(5); 269 270 wrmsr(smca_config, low, high); 271 } 272 273 smca_set_misc_banks_map(bank, cpu); 274 275 /* Return early if this bank was already initialized. */ 276 if (smca_banks[bank].hwid && smca_banks[bank].hwid->hwid_mcatype != 0) 277 return; 278 279 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { 280 pr_warn("Failed to read MCA_IPID for bank %d\n", bank); 281 return; 282 } 283 284 hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, 285 (high & MCI_IPID_MCATYPE) >> 16); 286 287 for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { 288 s_hwid = &smca_hwid_mcatypes[i]; 289 if (hwid_mcatype == s_hwid->hwid_mcatype) { 290 smca_banks[bank].hwid = s_hwid; 291 smca_banks[bank].id = low; 292 smca_banks[bank].sysfs_id = s_hwid->count++; 293 break; 294 } 295 } 296 } 297 298 struct thresh_restart { 299 struct threshold_block *b; 300 int reset; 301 int set_lvt_off; 302 int lvt_off; 303 u16 old_limit; 304 }; 305 306 static inline bool is_shared_bank(int bank) 307 { 308 /* 309 * Scalable MCA provides for only one core to have access to the MSRs of 310 * a shared bank. 311 */ 312 if (mce_flags.smca) 313 return false; 314 315 /* Bank 4 is for northbridge reporting and is thus shared */ 316 return (bank == 4); 317 } 318 319 static const char *bank4_names(const struct threshold_block *b) 320 { 321 switch (b->address) { 322 /* MSR4_MISC0 */ 323 case 0x00000413: 324 return "dram"; 325 326 case 0xc0000408: 327 return "ht_links"; 328 329 case 0xc0000409: 330 return "l3_cache"; 331 332 default: 333 WARN(1, "Funny MSR: 0x%08x\n", b->address); 334 return ""; 335 } 336 }; 337 338 339 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) 340 { 341 /* 342 * bank 4 supports APIC LVT interrupts implicitly since forever. 343 */ 344 if (bank == 4) 345 return true; 346 347 /* 348 * IntP: interrupt present; if this bit is set, the thresholding 349 * bank can generate APIC LVT interrupts 350 */ 351 return msr_high_bits & BIT(28); 352 } 353 354 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) 355 { 356 int msr = (hi & MASK_LVTOFF_HI) >> 20; 357 358 if (apic < 0) { 359 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " 360 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, 361 b->bank, b->block, b->address, hi, lo); 362 return 0; 363 } 364 365 if (apic != msr) { 366 /* 367 * On SMCA CPUs, LVT offset is programmed at a different MSR, and 368 * the BIOS provides the value. The original field where LVT offset 369 * was set is reserved. Return early here: 370 */ 371 if (mce_flags.smca) 372 return 0; 373 374 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " 375 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", 376 b->cpu, apic, b->bank, b->block, b->address, hi, lo); 377 return 0; 378 } 379 380 return 1; 381 }; 382 383 /* Reprogram MCx_MISC MSR behind this threshold bank. */ 384 static void threshold_restart_bank(void *_tr) 385 { 386 struct thresh_restart *tr = _tr; 387 u32 hi, lo; 388 389 /* sysfs write might race against an offline operation */ 390 if (this_cpu_read(threshold_banks)) 391 return; 392 393 rdmsr(tr->b->address, lo, hi); 394 395 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) 396 tr->reset = 1; /* limit cannot be lower than err count */ 397 398 if (tr->reset) { /* reset err count and overflow bit */ 399 hi = 400 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | 401 (THRESHOLD_MAX - tr->b->threshold_limit); 402 } else if (tr->old_limit) { /* change limit w/o reset */ 403 int new_count = (hi & THRESHOLD_MAX) + 404 (tr->old_limit - tr->b->threshold_limit); 405 406 hi = (hi & ~MASK_ERR_COUNT_HI) | 407 (new_count & THRESHOLD_MAX); 408 } 409 410 /* clear IntType */ 411 hi &= ~MASK_INT_TYPE_HI; 412 413 if (!tr->b->interrupt_capable) 414 goto done; 415 416 if (tr->set_lvt_off) { 417 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { 418 /* set new lvt offset */ 419 hi &= ~MASK_LVTOFF_HI; 420 hi |= tr->lvt_off << 20; 421 } 422 } 423 424 if (tr->b->interrupt_enable) 425 hi |= INT_TYPE_APIC; 426 427 done: 428 429 hi |= MASK_COUNT_EN_HI; 430 wrmsr(tr->b->address, lo, hi); 431 } 432 433 static void mce_threshold_block_init(struct threshold_block *b, int offset) 434 { 435 struct thresh_restart tr = { 436 .b = b, 437 .set_lvt_off = 1, 438 .lvt_off = offset, 439 }; 440 441 b->threshold_limit = THRESHOLD_MAX; 442 threshold_restart_bank(&tr); 443 }; 444 445 static int setup_APIC_mce_threshold(int reserved, int new) 446 { 447 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, 448 APIC_EILVT_MSG_FIX, 0)) 449 return new; 450 451 return reserved; 452 } 453 454 static int setup_APIC_deferred_error(int reserved, int new) 455 { 456 if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, 457 APIC_EILVT_MSG_FIX, 0)) 458 return new; 459 460 return reserved; 461 } 462 463 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) 464 { 465 u32 low = 0, high = 0; 466 int def_offset = -1, def_new; 467 468 if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) 469 return; 470 471 def_new = (low & MASK_DEF_LVTOFF) >> 4; 472 if (!(low & MASK_DEF_LVTOFF)) { 473 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); 474 def_new = DEF_LVT_OFF; 475 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); 476 } 477 478 def_offset = setup_APIC_deferred_error(def_offset, def_new); 479 if ((def_offset == def_new) && 480 (deferred_error_int_vector != amd_deferred_error_interrupt)) 481 deferred_error_int_vector = amd_deferred_error_interrupt; 482 483 if (!mce_flags.smca) 484 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; 485 486 wrmsr(MSR_CU_DEF_ERR, low, high); 487 } 488 489 static u32 smca_get_block_address(unsigned int bank, unsigned int block, 490 unsigned int cpu) 491 { 492 if (!block) 493 return MSR_AMD64_SMCA_MCx_MISC(bank); 494 495 if (!(per_cpu(smca_misc_banks_map, cpu) & BIT(bank))) 496 return 0; 497 498 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); 499 } 500 501 static u32 get_block_address(u32 current_addr, u32 low, u32 high, 502 unsigned int bank, unsigned int block, 503 unsigned int cpu) 504 { 505 u32 addr = 0, offset = 0; 506 507 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) 508 return addr; 509 510 if (mce_flags.smca) 511 return smca_get_block_address(bank, block, cpu); 512 513 /* Fall back to method we used for older processors: */ 514 switch (block) { 515 case 0: 516 addr = msr_ops.misc(bank); 517 break; 518 case 1: 519 offset = ((low & MASK_BLKPTR_LO) >> 21); 520 if (offset) 521 addr = MCG_XBLK_ADDR + offset; 522 break; 523 default: 524 addr = ++current_addr; 525 } 526 return addr; 527 } 528 529 static int 530 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 531 int offset, u32 misc_high) 532 { 533 unsigned int cpu = smp_processor_id(); 534 u32 smca_low, smca_high; 535 struct threshold_block b; 536 int new; 537 538 if (!block) 539 per_cpu(bank_map, cpu) |= (1 << bank); 540 541 memset(&b, 0, sizeof(b)); 542 b.cpu = cpu; 543 b.bank = bank; 544 b.block = block; 545 b.address = addr; 546 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); 547 548 if (!b.interrupt_capable) 549 goto done; 550 551 b.interrupt_enable = 1; 552 553 if (!mce_flags.smca) { 554 new = (misc_high & MASK_LVTOFF_HI) >> 20; 555 goto set_offset; 556 } 557 558 /* Gather LVT offset for thresholding: */ 559 if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) 560 goto out; 561 562 new = (smca_low & SMCA_THR_LVT_OFF) >> 12; 563 564 set_offset: 565 offset = setup_APIC_mce_threshold(offset, new); 566 if (offset == new) 567 thresholding_irq_en = true; 568 569 done: 570 mce_threshold_block_init(&b, offset); 571 572 out: 573 return offset; 574 } 575 576 bool amd_filter_mce(struct mce *m) 577 { 578 enum smca_bank_types bank_type = smca_get_bank_type(m->bank); 579 struct cpuinfo_x86 *c = &boot_cpu_data; 580 u8 xec = (m->status >> 16) & 0x3F; 581 582 /* See Family 17h Models 10h-2Fh Erratum #1114. */ 583 if (c->x86 == 0x17 && 584 c->x86_model >= 0x10 && c->x86_model <= 0x2F && 585 bank_type == SMCA_IF && xec == 10) 586 return true; 587 588 return false; 589 } 590 591 /* 592 * Turn off thresholding banks for the following conditions: 593 * - MC4_MISC thresholding is not supported on Family 0x15. 594 * - Prevent possible spurious interrupts from the IF bank on Family 0x17 595 * Models 0x10-0x2F due to Erratum #1114. 596 */ 597 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) 598 { 599 int i, num_msrs; 600 u64 hwcr; 601 bool need_toggle; 602 u32 msrs[NR_BLOCKS]; 603 604 if (c->x86 == 0x15 && bank == 4) { 605 msrs[0] = 0x00000413; /* MC4_MISC0 */ 606 msrs[1] = 0xc0000408; /* MC4_MISC1 */ 607 num_msrs = 2; 608 } else if (c->x86 == 0x17 && 609 (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { 610 611 if (smca_get_bank_type(bank) != SMCA_IF) 612 return; 613 614 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); 615 num_msrs = 1; 616 } else { 617 return; 618 } 619 620 rdmsrl(MSR_K7_HWCR, hwcr); 621 622 /* McStatusWrEn has to be set */ 623 need_toggle = !(hwcr & BIT(18)); 624 if (need_toggle) 625 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); 626 627 /* Clear CntP bit safely */ 628 for (i = 0; i < num_msrs; i++) 629 msr_clear_bit(msrs[i], 62); 630 631 /* restore old settings */ 632 if (need_toggle) 633 wrmsrl(MSR_K7_HWCR, hwcr); 634 } 635 636 /* cpu init entry point, called from mce.c with preempt off */ 637 void mce_amd_feature_init(struct cpuinfo_x86 *c) 638 { 639 unsigned int bank, block, cpu = smp_processor_id(); 640 u32 low = 0, high = 0, address = 0; 641 int offset = -1; 642 643 644 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 645 if (mce_flags.smca) 646 smca_configure(bank, cpu); 647 648 disable_err_thresholding(c, bank); 649 650 for (block = 0; block < NR_BLOCKS; ++block) { 651 address = get_block_address(address, low, high, bank, block, cpu); 652 if (!address) 653 break; 654 655 if (rdmsr_safe(address, &low, &high)) 656 break; 657 658 if (!(high & MASK_VALID_HI)) 659 continue; 660 661 if (!(high & MASK_CNTP_HI) || 662 (high & MASK_LOCKED_HI)) 663 continue; 664 665 offset = prepare_threshold_block(bank, block, address, offset, high); 666 } 667 } 668 669 if (mce_flags.succor) 670 deferred_error_interrupt_enable(c); 671 } 672 673 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) 674 { 675 u64 dram_base_addr, dram_limit_addr, dram_hole_base; 676 /* We start from the normalized address */ 677 u64 ret_addr = norm_addr; 678 679 u32 tmp; 680 681 u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; 682 u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; 683 u8 intlv_addr_sel, intlv_addr_bit; 684 u8 num_intlv_bits, hashed_bit; 685 u8 lgcy_mmio_hole_en, base = 0; 686 u8 cs_mask, cs_id = 0; 687 bool hash_enabled = false; 688 689 /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ 690 if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) 691 goto out_err; 692 693 /* Remove HiAddrOffset from normalized address, if enabled: */ 694 if (tmp & BIT(0)) { 695 u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; 696 697 if (norm_addr >= hi_addr_offset) { 698 ret_addr -= hi_addr_offset; 699 base = 1; 700 } 701 } 702 703 /* Read D18F0x110 (DramBaseAddress). */ 704 if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) 705 goto out_err; 706 707 /* Check if address range is valid. */ 708 if (!(tmp & BIT(0))) { 709 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", 710 __func__, tmp); 711 goto out_err; 712 } 713 714 lgcy_mmio_hole_en = tmp & BIT(1); 715 intlv_num_chan = (tmp >> 4) & 0xF; 716 intlv_addr_sel = (tmp >> 8) & 0x7; 717 dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; 718 719 /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ 720 if (intlv_addr_sel > 3) { 721 pr_err("%s: Invalid interleave address select %d.\n", 722 __func__, intlv_addr_sel); 723 goto out_err; 724 } 725 726 /* Read D18F0x114 (DramLimitAddress). */ 727 if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) 728 goto out_err; 729 730 intlv_num_sockets = (tmp >> 8) & 0x1; 731 intlv_num_dies = (tmp >> 10) & 0x3; 732 dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); 733 734 intlv_addr_bit = intlv_addr_sel + 8; 735 736 /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ 737 switch (intlv_num_chan) { 738 case 0: intlv_num_chan = 0; break; 739 case 1: intlv_num_chan = 1; break; 740 case 3: intlv_num_chan = 2; break; 741 case 5: intlv_num_chan = 3; break; 742 case 7: intlv_num_chan = 4; break; 743 744 case 8: intlv_num_chan = 1; 745 hash_enabled = true; 746 break; 747 default: 748 pr_err("%s: Invalid number of interleaved channels %d.\n", 749 __func__, intlv_num_chan); 750 goto out_err; 751 } 752 753 num_intlv_bits = intlv_num_chan; 754 755 if (intlv_num_dies > 2) { 756 pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", 757 __func__, intlv_num_dies); 758 goto out_err; 759 } 760 761 num_intlv_bits += intlv_num_dies; 762 763 /* Add a bit if sockets are interleaved. */ 764 num_intlv_bits += intlv_num_sockets; 765 766 /* Assert num_intlv_bits <= 4 */ 767 if (num_intlv_bits > 4) { 768 pr_err("%s: Invalid interleave bits %d.\n", 769 __func__, num_intlv_bits); 770 goto out_err; 771 } 772 773 if (num_intlv_bits > 0) { 774 u64 temp_addr_x, temp_addr_i, temp_addr_y; 775 u8 die_id_bit, sock_id_bit, cs_fabric_id; 776 777 /* 778 * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. 779 * This is the fabric id for this coherent slave. Use 780 * umc/channel# as instance id of the coherent slave 781 * for FICAA. 782 */ 783 if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) 784 goto out_err; 785 786 cs_fabric_id = (tmp >> 8) & 0xFF; 787 die_id_bit = 0; 788 789 /* If interleaved over more than 1 channel: */ 790 if (intlv_num_chan) { 791 die_id_bit = intlv_num_chan; 792 cs_mask = (1 << die_id_bit) - 1; 793 cs_id = cs_fabric_id & cs_mask; 794 } 795 796 sock_id_bit = die_id_bit; 797 798 /* Read D18F1x208 (SystemFabricIdMask). */ 799 if (intlv_num_dies || intlv_num_sockets) 800 if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) 801 goto out_err; 802 803 /* If interleaved over more than 1 die. */ 804 if (intlv_num_dies) { 805 sock_id_bit = die_id_bit + intlv_num_dies; 806 die_id_shift = (tmp >> 24) & 0xF; 807 die_id_mask = (tmp >> 8) & 0xFF; 808 809 cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; 810 } 811 812 /* If interleaved over more than 1 socket. */ 813 if (intlv_num_sockets) { 814 socket_id_shift = (tmp >> 28) & 0xF; 815 socket_id_mask = (tmp >> 16) & 0xFF; 816 817 cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; 818 } 819 820 /* 821 * The pre-interleaved address consists of XXXXXXIIIYYYYY 822 * where III is the ID for this CS, and XXXXXXYYYYY are the 823 * address bits from the post-interleaved address. 824 * "num_intlv_bits" has been calculated to tell us how many "I" 825 * bits there are. "intlv_addr_bit" tells us how many "Y" bits 826 * there are (where "I" starts). 827 */ 828 temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); 829 temp_addr_i = (cs_id << intlv_addr_bit); 830 temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; 831 ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; 832 } 833 834 /* Add dram base address */ 835 ret_addr += dram_base_addr; 836 837 /* If legacy MMIO hole enabled */ 838 if (lgcy_mmio_hole_en) { 839 if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) 840 goto out_err; 841 842 dram_hole_base = tmp & GENMASK(31, 24); 843 if (ret_addr >= dram_hole_base) 844 ret_addr += (BIT_ULL(32) - dram_hole_base); 845 } 846 847 if (hash_enabled) { 848 /* Save some parentheses and grab ls-bit at the end. */ 849 hashed_bit = (ret_addr >> 12) ^ 850 (ret_addr >> 18) ^ 851 (ret_addr >> 21) ^ 852 (ret_addr >> 30) ^ 853 cs_id; 854 855 hashed_bit &= BIT(0); 856 857 if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) 858 ret_addr ^= BIT(intlv_addr_bit); 859 } 860 861 /* Is calculated system address is above DRAM limit address? */ 862 if (ret_addr > dram_limit_addr) 863 goto out_err; 864 865 *sys_addr = ret_addr; 866 return 0; 867 868 out_err: 869 return -EINVAL; 870 } 871 EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr); 872 873 bool amd_mce_is_memory_error(struct mce *m) 874 { 875 /* ErrCodeExt[20:16] */ 876 u8 xec = (m->status >> 16) & 0x1f; 877 878 if (mce_flags.smca) 879 return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0; 880 881 return m->bank == 4 && xec == 0x8; 882 } 883 884 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) 885 { 886 struct mce m; 887 888 mce_setup(&m); 889 890 m.status = status; 891 m.misc = misc; 892 m.bank = bank; 893 m.tsc = rdtsc(); 894 895 if (m.status & MCI_STATUS_ADDRV) { 896 m.addr = addr; 897 898 /* 899 * Extract [55:<lsb>] where lsb is the least significant 900 * *valid* bit of the address bits. 901 */ 902 if (mce_flags.smca) { 903 u8 lsb = (m.addr >> 56) & 0x3f; 904 905 m.addr &= GENMASK_ULL(55, lsb); 906 } 907 } 908 909 if (mce_flags.smca) { 910 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); 911 912 if (m.status & MCI_STATUS_SYNDV) 913 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); 914 } 915 916 mce_log(&m); 917 } 918 919 asmlinkage __visible void __irq_entry smp_deferred_error_interrupt(struct pt_regs *regs) 920 { 921 entering_irq(); 922 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); 923 inc_irq_stat(irq_deferred_error_count); 924 deferred_error_int_vector(); 925 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); 926 exiting_ack_irq(); 927 } 928 929 /* 930 * Returns true if the logged error is deferred. False, otherwise. 931 */ 932 static inline bool 933 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) 934 { 935 u64 status, addr = 0; 936 937 rdmsrl(msr_stat, status); 938 if (!(status & MCI_STATUS_VAL)) 939 return false; 940 941 if (status & MCI_STATUS_ADDRV) 942 rdmsrl(msr_addr, addr); 943 944 __log_error(bank, status, addr, misc); 945 946 wrmsrl(msr_stat, 0); 947 948 return status & MCI_STATUS_DEFERRED; 949 } 950 951 /* 952 * We have three scenarios for checking for Deferred errors: 953 * 954 * 1) Non-SMCA systems check MCA_STATUS and log error if found. 955 * 2) SMCA systems check MCA_STATUS. If error is found then log it and also 956 * clear MCA_DESTAT. 957 * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and 958 * log it. 959 */ 960 static void log_error_deferred(unsigned int bank) 961 { 962 bool defrd; 963 964 defrd = _log_error_bank(bank, msr_ops.status(bank), 965 msr_ops.addr(bank), 0); 966 967 if (!mce_flags.smca) 968 return; 969 970 /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */ 971 if (defrd) { 972 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); 973 return; 974 } 975 976 /* 977 * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check 978 * for a valid error. 979 */ 980 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), 981 MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); 982 } 983 984 /* APIC interrupt handler for deferred errors */ 985 static void amd_deferred_error_interrupt(void) 986 { 987 unsigned int bank; 988 989 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) 990 log_error_deferred(bank); 991 } 992 993 static void log_error_thresholding(unsigned int bank, u64 misc) 994 { 995 _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc); 996 } 997 998 static void log_and_reset_block(struct threshold_block *block) 999 { 1000 struct thresh_restart tr; 1001 u32 low = 0, high = 0; 1002 1003 if (!block) 1004 return; 1005 1006 if (rdmsr_safe(block->address, &low, &high)) 1007 return; 1008 1009 if (!(high & MASK_OVERFLOW_HI)) 1010 return; 1011 1012 /* Log the MCE which caused the threshold event. */ 1013 log_error_thresholding(block->bank, ((u64)high << 32) | low); 1014 1015 /* Reset threshold block after logging error. */ 1016 memset(&tr, 0, sizeof(tr)); 1017 tr.b = block; 1018 threshold_restart_bank(&tr); 1019 } 1020 1021 /* 1022 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt 1023 * goes off when error_count reaches threshold_limit. 1024 */ 1025 static void amd_threshold_interrupt(void) 1026 { 1027 struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; 1028 struct threshold_bank **bp = this_cpu_read(threshold_banks); 1029 unsigned int bank, cpu = smp_processor_id(); 1030 1031 /* 1032 * Validate that the threshold bank has been initialized already. The 1033 * handler is installed at boot time, but on a hotplug event the 1034 * interrupt might fire before the data has been initialized. 1035 */ 1036 if (!bp) 1037 return; 1038 1039 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 1040 if (!(per_cpu(bank_map, cpu) & (1 << bank))) 1041 continue; 1042 1043 first_block = bp[bank]->blocks; 1044 if (!first_block) 1045 continue; 1046 1047 /* 1048 * The first block is also the head of the list. Check it first 1049 * before iterating over the rest. 1050 */ 1051 log_and_reset_block(first_block); 1052 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) 1053 log_and_reset_block(block); 1054 } 1055 } 1056 1057 /* 1058 * Sysfs Interface 1059 */ 1060 1061 struct threshold_attr { 1062 struct attribute attr; 1063 ssize_t (*show) (struct threshold_block *, char *); 1064 ssize_t (*store) (struct threshold_block *, const char *, size_t count); 1065 }; 1066 1067 #define SHOW_FIELDS(name) \ 1068 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ 1069 { \ 1070 return sprintf(buf, "%lu\n", (unsigned long) b->name); \ 1071 } 1072 SHOW_FIELDS(interrupt_enable) 1073 SHOW_FIELDS(threshold_limit) 1074 1075 static ssize_t 1076 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) 1077 { 1078 struct thresh_restart tr; 1079 unsigned long new; 1080 1081 if (!b->interrupt_capable) 1082 return -EINVAL; 1083 1084 if (kstrtoul(buf, 0, &new) < 0) 1085 return -EINVAL; 1086 1087 b->interrupt_enable = !!new; 1088 1089 memset(&tr, 0, sizeof(tr)); 1090 tr.b = b; 1091 1092 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 1093 return -ENODEV; 1094 1095 return size; 1096 } 1097 1098 static ssize_t 1099 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) 1100 { 1101 struct thresh_restart tr; 1102 unsigned long new; 1103 1104 if (kstrtoul(buf, 0, &new) < 0) 1105 return -EINVAL; 1106 1107 if (new > THRESHOLD_MAX) 1108 new = THRESHOLD_MAX; 1109 if (new < 1) 1110 new = 1; 1111 1112 memset(&tr, 0, sizeof(tr)); 1113 tr.old_limit = b->threshold_limit; 1114 b->threshold_limit = new; 1115 tr.b = b; 1116 1117 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 1118 return -ENODEV; 1119 1120 return size; 1121 } 1122 1123 static ssize_t show_error_count(struct threshold_block *b, char *buf) 1124 { 1125 u32 lo, hi; 1126 1127 /* CPU might be offline by now */ 1128 if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi)) 1129 return -ENODEV; 1130 1131 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - 1132 (THRESHOLD_MAX - b->threshold_limit))); 1133 } 1134 1135 static struct threshold_attr error_count = { 1136 .attr = {.name = __stringify(error_count), .mode = 0444 }, 1137 .show = show_error_count, 1138 }; 1139 1140 #define RW_ATTR(val) \ 1141 static struct threshold_attr val = { \ 1142 .attr = {.name = __stringify(val), .mode = 0644 }, \ 1143 .show = show_## val, \ 1144 .store = store_## val, \ 1145 }; 1146 1147 RW_ATTR(interrupt_enable); 1148 RW_ATTR(threshold_limit); 1149 1150 static struct attribute *default_attrs[] = { 1151 &threshold_limit.attr, 1152 &error_count.attr, 1153 NULL, /* possibly interrupt_enable if supported, see below */ 1154 NULL, 1155 }; 1156 1157 #define to_block(k) container_of(k, struct threshold_block, kobj) 1158 #define to_attr(a) container_of(a, struct threshold_attr, attr) 1159 1160 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) 1161 { 1162 struct threshold_block *b = to_block(kobj); 1163 struct threshold_attr *a = to_attr(attr); 1164 ssize_t ret; 1165 1166 ret = a->show ? a->show(b, buf) : -EIO; 1167 1168 return ret; 1169 } 1170 1171 static ssize_t store(struct kobject *kobj, struct attribute *attr, 1172 const char *buf, size_t count) 1173 { 1174 struct threshold_block *b = to_block(kobj); 1175 struct threshold_attr *a = to_attr(attr); 1176 ssize_t ret; 1177 1178 ret = a->store ? a->store(b, buf, count) : -EIO; 1179 1180 return ret; 1181 } 1182 1183 static const struct sysfs_ops threshold_ops = { 1184 .show = show, 1185 .store = store, 1186 }; 1187 1188 static void threshold_block_release(struct kobject *kobj); 1189 1190 static struct kobj_type threshold_ktype = { 1191 .sysfs_ops = &threshold_ops, 1192 .default_attrs = default_attrs, 1193 .release = threshold_block_release, 1194 }; 1195 1196 static const char *get_name(unsigned int bank, struct threshold_block *b) 1197 { 1198 enum smca_bank_types bank_type; 1199 1200 if (!mce_flags.smca) { 1201 if (b && bank == 4) 1202 return bank4_names(b); 1203 1204 return th_names[bank]; 1205 } 1206 1207 bank_type = smca_get_bank_type(bank); 1208 if (bank_type >= N_SMCA_BANK_TYPES) 1209 return NULL; 1210 1211 if (b && bank_type == SMCA_UMC) { 1212 if (b->block < ARRAY_SIZE(smca_umc_block_names)) 1213 return smca_umc_block_names[b->block]; 1214 return NULL; 1215 } 1216 1217 if (smca_banks[bank].hwid->count == 1) 1218 return smca_get_name(bank_type); 1219 1220 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, 1221 "%s_%x", smca_get_name(bank_type), 1222 smca_banks[bank].sysfs_id); 1223 return buf_mcatype; 1224 } 1225 1226 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb, 1227 unsigned int bank, unsigned int block, 1228 u32 address) 1229 { 1230 struct threshold_block *b = NULL; 1231 u32 low, high; 1232 int err; 1233 1234 if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS)) 1235 return 0; 1236 1237 if (rdmsr_safe(address, &low, &high)) 1238 return 0; 1239 1240 if (!(high & MASK_VALID_HI)) { 1241 if (block) 1242 goto recurse; 1243 else 1244 return 0; 1245 } 1246 1247 if (!(high & MASK_CNTP_HI) || 1248 (high & MASK_LOCKED_HI)) 1249 goto recurse; 1250 1251 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); 1252 if (!b) 1253 return -ENOMEM; 1254 1255 b->block = block; 1256 b->bank = bank; 1257 b->cpu = cpu; 1258 b->address = address; 1259 b->interrupt_enable = 0; 1260 b->interrupt_capable = lvt_interrupt_supported(bank, high); 1261 b->threshold_limit = THRESHOLD_MAX; 1262 1263 if (b->interrupt_capable) { 1264 threshold_ktype.default_attrs[2] = &interrupt_enable.attr; 1265 b->interrupt_enable = 1; 1266 } else { 1267 threshold_ktype.default_attrs[2] = NULL; 1268 } 1269 1270 INIT_LIST_HEAD(&b->miscj); 1271 1272 /* This is safe as @tb is not visible yet */ 1273 if (tb->blocks) 1274 list_add(&b->miscj, &tb->blocks->miscj); 1275 else 1276 tb->blocks = b; 1277 1278 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(bank, b)); 1279 if (err) 1280 goto out_free; 1281 recurse: 1282 address = get_block_address(address, low, high, bank, ++block, cpu); 1283 if (!address) 1284 return 0; 1285 1286 err = allocate_threshold_blocks(cpu, tb, bank, block, address); 1287 if (err) 1288 goto out_free; 1289 1290 if (b) 1291 kobject_uevent(&b->kobj, KOBJ_ADD); 1292 1293 return 0; 1294 1295 out_free: 1296 if (b) { 1297 list_del(&b->miscj); 1298 kobject_put(&b->kobj); 1299 } 1300 return err; 1301 } 1302 1303 static int __threshold_add_blocks(struct threshold_bank *b) 1304 { 1305 struct list_head *head = &b->blocks->miscj; 1306 struct threshold_block *pos = NULL; 1307 struct threshold_block *tmp = NULL; 1308 int err = 0; 1309 1310 err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); 1311 if (err) 1312 return err; 1313 1314 list_for_each_entry_safe(pos, tmp, head, miscj) { 1315 1316 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); 1317 if (err) { 1318 list_for_each_entry_safe_reverse(pos, tmp, head, miscj) 1319 kobject_del(&pos->kobj); 1320 1321 return err; 1322 } 1323 } 1324 return err; 1325 } 1326 1327 static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu, 1328 unsigned int bank) 1329 { 1330 struct device *dev = this_cpu_read(mce_device); 1331 struct amd_northbridge *nb = NULL; 1332 struct threshold_bank *b = NULL; 1333 const char *name = get_name(bank, NULL); 1334 int err = 0; 1335 1336 if (!dev) 1337 return -ENODEV; 1338 1339 if (is_shared_bank(bank)) { 1340 nb = node_to_amd_nb(amd_get_nb_id(cpu)); 1341 1342 /* threshold descriptor already initialized on this node? */ 1343 if (nb && nb->bank4) { 1344 /* yes, use it */ 1345 b = nb->bank4; 1346 err = kobject_add(b->kobj, &dev->kobj, name); 1347 if (err) 1348 goto out; 1349 1350 bp[bank] = b; 1351 refcount_inc(&b->cpus); 1352 1353 err = __threshold_add_blocks(b); 1354 1355 goto out; 1356 } 1357 } 1358 1359 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); 1360 if (!b) { 1361 err = -ENOMEM; 1362 goto out; 1363 } 1364 1365 /* Associate the bank with the per-CPU MCE device */ 1366 b->kobj = kobject_create_and_add(name, &dev->kobj); 1367 if (!b->kobj) { 1368 err = -EINVAL; 1369 goto out_free; 1370 } 1371 1372 if (is_shared_bank(bank)) { 1373 b->shared = 1; 1374 refcount_set(&b->cpus, 1); 1375 1376 /* nb is already initialized, see above */ 1377 if (nb) { 1378 WARN_ON(nb->bank4); 1379 nb->bank4 = b; 1380 } 1381 } 1382 1383 err = allocate_threshold_blocks(cpu, b, bank, 0, msr_ops.misc(bank)); 1384 if (err) 1385 goto out_kobj; 1386 1387 bp[bank] = b; 1388 return 0; 1389 1390 out_kobj: 1391 kobject_put(b->kobj); 1392 out_free: 1393 kfree(b); 1394 out: 1395 return err; 1396 } 1397 1398 static void threshold_block_release(struct kobject *kobj) 1399 { 1400 kfree(to_block(kobj)); 1401 } 1402 1403 static void deallocate_threshold_blocks(struct threshold_bank *bank) 1404 { 1405 struct threshold_block *pos, *tmp; 1406 1407 list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) { 1408 list_del(&pos->miscj); 1409 kobject_put(&pos->kobj); 1410 } 1411 1412 kobject_put(&bank->blocks->kobj); 1413 } 1414 1415 static void __threshold_remove_blocks(struct threshold_bank *b) 1416 { 1417 struct threshold_block *pos = NULL; 1418 struct threshold_block *tmp = NULL; 1419 1420 kobject_del(b->kobj); 1421 1422 list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) 1423 kobject_del(&pos->kobj); 1424 } 1425 1426 static void threshold_remove_bank(struct threshold_bank *bank) 1427 { 1428 struct amd_northbridge *nb; 1429 1430 if (!bank->blocks) 1431 goto out_free; 1432 1433 if (!bank->shared) 1434 goto out_dealloc; 1435 1436 if (!refcount_dec_and_test(&bank->cpus)) { 1437 __threshold_remove_blocks(bank); 1438 return; 1439 } else { 1440 /* 1441 * The last CPU on this node using the shared bank is going 1442 * away, remove that bank now. 1443 */ 1444 nb = node_to_amd_nb(amd_get_nb_id(smp_processor_id())); 1445 nb->bank4 = NULL; 1446 } 1447 1448 out_dealloc: 1449 deallocate_threshold_blocks(bank); 1450 1451 out_free: 1452 kobject_put(bank->kobj); 1453 kfree(bank); 1454 } 1455 1456 int mce_threshold_remove_device(unsigned int cpu) 1457 { 1458 struct threshold_bank **bp = this_cpu_read(threshold_banks); 1459 unsigned int bank, numbanks = this_cpu_read(mce_num_banks); 1460 1461 if (!bp) 1462 return 0; 1463 1464 /* 1465 * Clear the pointer before cleaning up, so that the interrupt won't 1466 * touch anything of this. 1467 */ 1468 this_cpu_write(threshold_banks, NULL); 1469 1470 for (bank = 0; bank < numbanks; bank++) { 1471 if (bp[bank]) { 1472 threshold_remove_bank(bp[bank]); 1473 bp[bank] = NULL; 1474 } 1475 } 1476 kfree(bp); 1477 return 0; 1478 } 1479 1480 /** 1481 * mce_threshold_create_device - Create the per-CPU MCE threshold device 1482 * @cpu: The plugged in CPU 1483 * 1484 * Create directories and files for all valid threshold banks. 1485 * 1486 * This is invoked from the CPU hotplug callback which was installed in 1487 * mcheck_init_device(). The invocation happens in context of the hotplug 1488 * thread running on @cpu. The callback is invoked on all CPUs which are 1489 * online when the callback is installed or during a real hotplug event. 1490 */ 1491 int mce_threshold_create_device(unsigned int cpu) 1492 { 1493 unsigned int numbanks, bank; 1494 struct threshold_bank **bp; 1495 int err; 1496 1497 if (!mce_flags.amd_threshold) 1498 return 0; 1499 1500 bp = this_cpu_read(threshold_banks); 1501 if (bp) 1502 return 0; 1503 1504 numbanks = this_cpu_read(mce_num_banks); 1505 bp = kcalloc(numbanks, sizeof(*bp), GFP_KERNEL); 1506 if (!bp) 1507 return -ENOMEM; 1508 1509 for (bank = 0; bank < numbanks; ++bank) { 1510 if (!(this_cpu_read(bank_map) & (1 << bank))) 1511 continue; 1512 err = threshold_create_bank(bp, cpu, bank); 1513 if (err) 1514 goto out_err; 1515 } 1516 this_cpu_write(threshold_banks, bp); 1517 1518 if (thresholding_irq_en) 1519 mce_threshold_vector = amd_threshold_interrupt; 1520 return 0; 1521 out_err: 1522 mce_threshold_remove_device(cpu); 1523 return err; 1524 } 1525