1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (c) 2005-2016 Advanced Micro Devices, Inc. 4 * 5 * Written by Jacob Shin - AMD, Inc. 6 * Maintained by: Borislav Petkov <bp@alien8.de> 7 * 8 * All MC4_MISCi registers are shared between cores on a node. 9 */ 10 #include <linux/interrupt.h> 11 #include <linux/notifier.h> 12 #include <linux/kobject.h> 13 #include <linux/percpu.h> 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/sysfs.h> 17 #include <linux/slab.h> 18 #include <linux/init.h> 19 #include <linux/cpu.h> 20 #include <linux/smp.h> 21 #include <linux/string.h> 22 23 #include <asm/amd_nb.h> 24 #include <asm/traps.h> 25 #include <asm/apic.h> 26 #include <asm/mce.h> 27 #include <asm/msr.h> 28 #include <asm/trace/irq_vectors.h> 29 30 #include "internal.h" 31 32 #define NR_BLOCKS 5 33 #define THRESHOLD_MAX 0xFFF 34 #define INT_TYPE_APIC 0x00020000 35 #define MASK_VALID_HI 0x80000000 36 #define MASK_CNTP_HI 0x40000000 37 #define MASK_LOCKED_HI 0x20000000 38 #define MASK_LVTOFF_HI 0x00F00000 39 #define MASK_COUNT_EN_HI 0x00080000 40 #define MASK_INT_TYPE_HI 0x00060000 41 #define MASK_OVERFLOW_HI 0x00010000 42 #define MASK_ERR_COUNT_HI 0x00000FFF 43 #define MASK_BLKPTR_LO 0xFF000000 44 #define MCG_XBLK_ADDR 0xC0000400 45 46 /* Deferred error settings */ 47 #define MSR_CU_DEF_ERR 0xC0000410 48 #define MASK_DEF_LVTOFF 0x000000F0 49 #define MASK_DEF_INT_TYPE 0x00000006 50 #define DEF_LVT_OFF 0x2 51 #define DEF_INT_TYPE_APIC 0x2 52 53 /* Scalable MCA: */ 54 55 /* Threshold LVT offset is at MSR0xC0000410[15:12] */ 56 #define SMCA_THR_LVT_OFF 0xF000 57 58 static bool thresholding_irq_en; 59 60 static const char * const th_names[] = { 61 "load_store", 62 "insn_fetch", 63 "combined_unit", 64 "decode_unit", 65 "northbridge", 66 "execution_unit", 67 }; 68 69 static const char * const smca_umc_block_names[] = { 70 "dram_ecc", 71 "misc_umc" 72 }; 73 74 struct smca_bank_name { 75 const char *name; /* Short name for sysfs */ 76 const char *long_name; /* Long name for pretty-printing */ 77 }; 78 79 static struct smca_bank_name smca_names[] = { 80 [SMCA_LS ... SMCA_LS_V2] = { "load_store", "Load Store Unit" }, 81 [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, 82 [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, 83 [SMCA_DE] = { "decode_unit", "Decode Unit" }, 84 [SMCA_RESERVED] = { "reserved", "Reserved" }, 85 [SMCA_EX] = { "execution_unit", "Execution Unit" }, 86 [SMCA_FP] = { "floating_point", "Floating Point Unit" }, 87 [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, 88 [SMCA_CS ... SMCA_CS_V2] = { "coherent_slave", "Coherent Slave" }, 89 [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, 90 91 /* UMC v2 is separate because both of them can exist in a single system. */ 92 [SMCA_UMC] = { "umc", "Unified Memory Controller" }, 93 [SMCA_UMC_V2] = { "umc_v2", "Unified Memory Controller v2" }, 94 [SMCA_PB] = { "param_block", "Parameter Block" }, 95 [SMCA_PSP ... SMCA_PSP_V2] = { "psp", "Platform Security Processor" }, 96 [SMCA_SMU ... SMCA_SMU_V2] = { "smu", "System Management Unit" }, 97 [SMCA_MP5] = { "mp5", "Microprocessor 5 Unit" }, 98 [SMCA_NBIO] = { "nbio", "Northbridge IO Unit" }, 99 [SMCA_PCIE ... SMCA_PCIE_V2] = { "pcie", "PCI Express Unit" }, 100 [SMCA_XGMI_PCS] = { "xgmi_pcs", "Ext Global Memory Interconnect PCS Unit" }, 101 [SMCA_XGMI_PHY] = { "xgmi_phy", "Ext Global Memory Interconnect PHY Unit" }, 102 [SMCA_WAFL_PHY] = { "wafl_phy", "WAFL PHY Unit" }, 103 }; 104 105 static const char *smca_get_name(enum smca_bank_types t) 106 { 107 if (t >= N_SMCA_BANK_TYPES) 108 return NULL; 109 110 return smca_names[t].name; 111 } 112 113 const char *smca_get_long_name(enum smca_bank_types t) 114 { 115 if (t >= N_SMCA_BANK_TYPES) 116 return NULL; 117 118 return smca_names[t].long_name; 119 } 120 EXPORT_SYMBOL_GPL(smca_get_long_name); 121 122 static enum smca_bank_types smca_get_bank_type(unsigned int bank) 123 { 124 struct smca_bank *b; 125 126 if (bank >= MAX_NR_BANKS) 127 return N_SMCA_BANK_TYPES; 128 129 b = &smca_banks[bank]; 130 if (!b->hwid) 131 return N_SMCA_BANK_TYPES; 132 133 return b->hwid->bank_type; 134 } 135 136 static struct smca_hwid smca_hwid_mcatypes[] = { 137 /* { bank_type, hwid_mcatype } */ 138 139 /* Reserved type */ 140 { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) }, 141 142 /* ZN Core (HWID=0xB0) MCA types */ 143 { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) }, 144 { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) }, 145 { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) }, 146 { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) }, 147 { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) }, 148 /* HWID 0xB0 MCATYPE 0x4 is Reserved */ 149 { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) }, 150 { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) }, 151 { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) }, 152 153 /* Data Fabric MCA types */ 154 { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, 155 { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, 156 { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, 157 158 /* Unified Memory Controller MCA type */ 159 { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, 160 { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) }, 161 162 /* Parameter Block MCA type */ 163 { SMCA_PB, HWID_MCATYPE(0x05, 0x0) }, 164 165 /* Platform Security Processor MCA type */ 166 { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) }, 167 { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) }, 168 169 /* System Management Unit MCA type */ 170 { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) }, 171 { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) }, 172 173 /* Microprocessor 5 Unit MCA type */ 174 { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) }, 175 176 /* Northbridge IO Unit MCA type */ 177 { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) }, 178 179 /* PCI Express Unit MCA type */ 180 { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) }, 181 { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) }, 182 183 /* xGMI PCS MCA type */ 184 { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) }, 185 186 /* xGMI PHY MCA type */ 187 { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) }, 188 189 /* WAFL PHY MCA type */ 190 { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) }, 191 }; 192 193 struct smca_bank smca_banks[MAX_NR_BANKS]; 194 EXPORT_SYMBOL_GPL(smca_banks); 195 196 /* 197 * In SMCA enabled processors, we can have multiple banks for a given IP type. 198 * So to define a unique name for each bank, we use a temp c-string to append 199 * the MCA_IPID[InstanceId] to type's name in get_name(). 200 * 201 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN 202 * is greater than 8 plus 1 (for underscore) plus length of longest type name. 203 */ 204 #define MAX_MCATYPE_NAME_LEN 30 205 static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; 206 207 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); 208 209 /* 210 * A list of the banks enabled on each logical CPU. Controls which respective 211 * descriptors to initialize later in mce_threshold_create_device(). 212 */ 213 static DEFINE_PER_CPU(unsigned int, bank_map); 214 215 /* Map of banks that have more than MCA_MISC0 available. */ 216 static DEFINE_PER_CPU(u32, smca_misc_banks_map); 217 218 static void amd_threshold_interrupt(void); 219 static void amd_deferred_error_interrupt(void); 220 221 static void default_deferred_error_interrupt(void) 222 { 223 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); 224 } 225 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; 226 227 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) 228 { 229 u32 low, high; 230 231 /* 232 * For SMCA enabled processors, BLKPTR field of the first MISC register 233 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). 234 */ 235 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) 236 return; 237 238 if (!(low & MCI_CONFIG_MCAX)) 239 return; 240 241 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) 242 return; 243 244 if (low & MASK_BLKPTR_LO) 245 per_cpu(smca_misc_banks_map, cpu) |= BIT(bank); 246 247 } 248 249 static void smca_configure(unsigned int bank, unsigned int cpu) 250 { 251 unsigned int i, hwid_mcatype; 252 struct smca_hwid *s_hwid; 253 u32 high, low; 254 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); 255 256 /* Set appropriate bits in MCA_CONFIG */ 257 if (!rdmsr_safe(smca_config, &low, &high)) { 258 /* 259 * OS is required to set the MCAX bit to acknowledge that it is 260 * now using the new MSR ranges and new registers under each 261 * bank. It also means that the OS will configure deferred 262 * errors in the new MCx_CONFIG register. If the bit is not set, 263 * uncorrectable errors will cause a system panic. 264 * 265 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) 266 */ 267 high |= BIT(0); 268 269 /* 270 * SMCA sets the Deferred Error Interrupt type per bank. 271 * 272 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us 273 * if the DeferredIntType bit field is available. 274 * 275 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the 276 * high portion of the MSR). OS should set this to 0x1 to enable 277 * APIC based interrupt. First, check that no interrupt has been 278 * set. 279 */ 280 if ((low & BIT(5)) && !((high >> 5) & 0x3)) 281 high |= BIT(5); 282 283 wrmsr(smca_config, low, high); 284 } 285 286 smca_set_misc_banks_map(bank, cpu); 287 288 /* Return early if this bank was already initialized. */ 289 if (smca_banks[bank].hwid && smca_banks[bank].hwid->hwid_mcatype != 0) 290 return; 291 292 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { 293 pr_warn("Failed to read MCA_IPID for bank %d\n", bank); 294 return; 295 } 296 297 hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, 298 (high & MCI_IPID_MCATYPE) >> 16); 299 300 for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { 301 s_hwid = &smca_hwid_mcatypes[i]; 302 if (hwid_mcatype == s_hwid->hwid_mcatype) { 303 smca_banks[bank].hwid = s_hwid; 304 smca_banks[bank].id = low; 305 smca_banks[bank].sysfs_id = s_hwid->count++; 306 break; 307 } 308 } 309 } 310 311 struct thresh_restart { 312 struct threshold_block *b; 313 int reset; 314 int set_lvt_off; 315 int lvt_off; 316 u16 old_limit; 317 }; 318 319 static inline bool is_shared_bank(int bank) 320 { 321 /* 322 * Scalable MCA provides for only one core to have access to the MSRs of 323 * a shared bank. 324 */ 325 if (mce_flags.smca) 326 return false; 327 328 /* Bank 4 is for northbridge reporting and is thus shared */ 329 return (bank == 4); 330 } 331 332 static const char *bank4_names(const struct threshold_block *b) 333 { 334 switch (b->address) { 335 /* MSR4_MISC0 */ 336 case 0x00000413: 337 return "dram"; 338 339 case 0xc0000408: 340 return "ht_links"; 341 342 case 0xc0000409: 343 return "l3_cache"; 344 345 default: 346 WARN(1, "Funny MSR: 0x%08x\n", b->address); 347 return ""; 348 } 349 }; 350 351 352 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) 353 { 354 /* 355 * bank 4 supports APIC LVT interrupts implicitly since forever. 356 */ 357 if (bank == 4) 358 return true; 359 360 /* 361 * IntP: interrupt present; if this bit is set, the thresholding 362 * bank can generate APIC LVT interrupts 363 */ 364 return msr_high_bits & BIT(28); 365 } 366 367 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) 368 { 369 int msr = (hi & MASK_LVTOFF_HI) >> 20; 370 371 if (apic < 0) { 372 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " 373 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, 374 b->bank, b->block, b->address, hi, lo); 375 return 0; 376 } 377 378 if (apic != msr) { 379 /* 380 * On SMCA CPUs, LVT offset is programmed at a different MSR, and 381 * the BIOS provides the value. The original field where LVT offset 382 * was set is reserved. Return early here: 383 */ 384 if (mce_flags.smca) 385 return 0; 386 387 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " 388 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", 389 b->cpu, apic, b->bank, b->block, b->address, hi, lo); 390 return 0; 391 } 392 393 return 1; 394 }; 395 396 /* Reprogram MCx_MISC MSR behind this threshold bank. */ 397 static void threshold_restart_bank(void *_tr) 398 { 399 struct thresh_restart *tr = _tr; 400 u32 hi, lo; 401 402 /* sysfs write might race against an offline operation */ 403 if (this_cpu_read(threshold_banks)) 404 return; 405 406 rdmsr(tr->b->address, lo, hi); 407 408 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) 409 tr->reset = 1; /* limit cannot be lower than err count */ 410 411 if (tr->reset) { /* reset err count and overflow bit */ 412 hi = 413 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | 414 (THRESHOLD_MAX - tr->b->threshold_limit); 415 } else if (tr->old_limit) { /* change limit w/o reset */ 416 int new_count = (hi & THRESHOLD_MAX) + 417 (tr->old_limit - tr->b->threshold_limit); 418 419 hi = (hi & ~MASK_ERR_COUNT_HI) | 420 (new_count & THRESHOLD_MAX); 421 } 422 423 /* clear IntType */ 424 hi &= ~MASK_INT_TYPE_HI; 425 426 if (!tr->b->interrupt_capable) 427 goto done; 428 429 if (tr->set_lvt_off) { 430 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { 431 /* set new lvt offset */ 432 hi &= ~MASK_LVTOFF_HI; 433 hi |= tr->lvt_off << 20; 434 } 435 } 436 437 if (tr->b->interrupt_enable) 438 hi |= INT_TYPE_APIC; 439 440 done: 441 442 hi |= MASK_COUNT_EN_HI; 443 wrmsr(tr->b->address, lo, hi); 444 } 445 446 static void mce_threshold_block_init(struct threshold_block *b, int offset) 447 { 448 struct thresh_restart tr = { 449 .b = b, 450 .set_lvt_off = 1, 451 .lvt_off = offset, 452 }; 453 454 b->threshold_limit = THRESHOLD_MAX; 455 threshold_restart_bank(&tr); 456 }; 457 458 static int setup_APIC_mce_threshold(int reserved, int new) 459 { 460 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, 461 APIC_EILVT_MSG_FIX, 0)) 462 return new; 463 464 return reserved; 465 } 466 467 static int setup_APIC_deferred_error(int reserved, int new) 468 { 469 if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, 470 APIC_EILVT_MSG_FIX, 0)) 471 return new; 472 473 return reserved; 474 } 475 476 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) 477 { 478 u32 low = 0, high = 0; 479 int def_offset = -1, def_new; 480 481 if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) 482 return; 483 484 def_new = (low & MASK_DEF_LVTOFF) >> 4; 485 if (!(low & MASK_DEF_LVTOFF)) { 486 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); 487 def_new = DEF_LVT_OFF; 488 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); 489 } 490 491 def_offset = setup_APIC_deferred_error(def_offset, def_new); 492 if ((def_offset == def_new) && 493 (deferred_error_int_vector != amd_deferred_error_interrupt)) 494 deferred_error_int_vector = amd_deferred_error_interrupt; 495 496 if (!mce_flags.smca) 497 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; 498 499 wrmsr(MSR_CU_DEF_ERR, low, high); 500 } 501 502 static u32 smca_get_block_address(unsigned int bank, unsigned int block, 503 unsigned int cpu) 504 { 505 if (!block) 506 return MSR_AMD64_SMCA_MCx_MISC(bank); 507 508 if (!(per_cpu(smca_misc_banks_map, cpu) & BIT(bank))) 509 return 0; 510 511 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); 512 } 513 514 static u32 get_block_address(u32 current_addr, u32 low, u32 high, 515 unsigned int bank, unsigned int block, 516 unsigned int cpu) 517 { 518 u32 addr = 0, offset = 0; 519 520 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) 521 return addr; 522 523 if (mce_flags.smca) 524 return smca_get_block_address(bank, block, cpu); 525 526 /* Fall back to method we used for older processors: */ 527 switch (block) { 528 case 0: 529 addr = msr_ops.misc(bank); 530 break; 531 case 1: 532 offset = ((low & MASK_BLKPTR_LO) >> 21); 533 if (offset) 534 addr = MCG_XBLK_ADDR + offset; 535 break; 536 default: 537 addr = ++current_addr; 538 } 539 return addr; 540 } 541 542 static int 543 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 544 int offset, u32 misc_high) 545 { 546 unsigned int cpu = smp_processor_id(); 547 u32 smca_low, smca_high; 548 struct threshold_block b; 549 int new; 550 551 if (!block) 552 per_cpu(bank_map, cpu) |= (1 << bank); 553 554 memset(&b, 0, sizeof(b)); 555 b.cpu = cpu; 556 b.bank = bank; 557 b.block = block; 558 b.address = addr; 559 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); 560 561 if (!b.interrupt_capable) 562 goto done; 563 564 b.interrupt_enable = 1; 565 566 if (!mce_flags.smca) { 567 new = (misc_high & MASK_LVTOFF_HI) >> 20; 568 goto set_offset; 569 } 570 571 /* Gather LVT offset for thresholding: */ 572 if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) 573 goto out; 574 575 new = (smca_low & SMCA_THR_LVT_OFF) >> 12; 576 577 set_offset: 578 offset = setup_APIC_mce_threshold(offset, new); 579 if (offset == new) 580 thresholding_irq_en = true; 581 582 done: 583 mce_threshold_block_init(&b, offset); 584 585 out: 586 return offset; 587 } 588 589 bool amd_filter_mce(struct mce *m) 590 { 591 enum smca_bank_types bank_type = smca_get_bank_type(m->bank); 592 struct cpuinfo_x86 *c = &boot_cpu_data; 593 594 /* See Family 17h Models 10h-2Fh Erratum #1114. */ 595 if (c->x86 == 0x17 && 596 c->x86_model >= 0x10 && c->x86_model <= 0x2F && 597 bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10) 598 return true; 599 600 /* NB GART TLB error reporting is disabled by default. */ 601 if (c->x86 < 0x17) { 602 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5) 603 return true; 604 } 605 606 return false; 607 } 608 609 /* 610 * Turn off thresholding banks for the following conditions: 611 * - MC4_MISC thresholding is not supported on Family 0x15. 612 * - Prevent possible spurious interrupts from the IF bank on Family 0x17 613 * Models 0x10-0x2F due to Erratum #1114. 614 */ 615 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) 616 { 617 int i, num_msrs; 618 u64 hwcr; 619 bool need_toggle; 620 u32 msrs[NR_BLOCKS]; 621 622 if (c->x86 == 0x15 && bank == 4) { 623 msrs[0] = 0x00000413; /* MC4_MISC0 */ 624 msrs[1] = 0xc0000408; /* MC4_MISC1 */ 625 num_msrs = 2; 626 } else if (c->x86 == 0x17 && 627 (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { 628 629 if (smca_get_bank_type(bank) != SMCA_IF) 630 return; 631 632 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); 633 num_msrs = 1; 634 } else { 635 return; 636 } 637 638 rdmsrl(MSR_K7_HWCR, hwcr); 639 640 /* McStatusWrEn has to be set */ 641 need_toggle = !(hwcr & BIT(18)); 642 if (need_toggle) 643 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); 644 645 /* Clear CntP bit safely */ 646 for (i = 0; i < num_msrs; i++) 647 msr_clear_bit(msrs[i], 62); 648 649 /* restore old settings */ 650 if (need_toggle) 651 wrmsrl(MSR_K7_HWCR, hwcr); 652 } 653 654 /* cpu init entry point, called from mce.c with preempt off */ 655 void mce_amd_feature_init(struct cpuinfo_x86 *c) 656 { 657 unsigned int bank, block, cpu = smp_processor_id(); 658 u32 low = 0, high = 0, address = 0; 659 int offset = -1; 660 661 662 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 663 if (mce_flags.smca) 664 smca_configure(bank, cpu); 665 666 disable_err_thresholding(c, bank); 667 668 for (block = 0; block < NR_BLOCKS; ++block) { 669 address = get_block_address(address, low, high, bank, block, cpu); 670 if (!address) 671 break; 672 673 if (rdmsr_safe(address, &low, &high)) 674 break; 675 676 if (!(high & MASK_VALID_HI)) 677 continue; 678 679 if (!(high & MASK_CNTP_HI) || 680 (high & MASK_LOCKED_HI)) 681 continue; 682 683 offset = prepare_threshold_block(bank, block, address, offset, high); 684 } 685 } 686 687 if (mce_flags.succor) 688 deferred_error_interrupt_enable(c); 689 } 690 691 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) 692 { 693 u64 dram_base_addr, dram_limit_addr, dram_hole_base; 694 /* We start from the normalized address */ 695 u64 ret_addr = norm_addr; 696 697 u32 tmp; 698 699 u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; 700 u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; 701 u8 intlv_addr_sel, intlv_addr_bit; 702 u8 num_intlv_bits, hashed_bit; 703 u8 lgcy_mmio_hole_en, base = 0; 704 u8 cs_mask, cs_id = 0; 705 bool hash_enabled = false; 706 707 /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ 708 if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) 709 goto out_err; 710 711 /* Remove HiAddrOffset from normalized address, if enabled: */ 712 if (tmp & BIT(0)) { 713 u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; 714 715 if (norm_addr >= hi_addr_offset) { 716 ret_addr -= hi_addr_offset; 717 base = 1; 718 } 719 } 720 721 /* Read D18F0x110 (DramBaseAddress). */ 722 if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) 723 goto out_err; 724 725 /* Check if address range is valid. */ 726 if (!(tmp & BIT(0))) { 727 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", 728 __func__, tmp); 729 goto out_err; 730 } 731 732 lgcy_mmio_hole_en = tmp & BIT(1); 733 intlv_num_chan = (tmp >> 4) & 0xF; 734 intlv_addr_sel = (tmp >> 8) & 0x7; 735 dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; 736 737 /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ 738 if (intlv_addr_sel > 3) { 739 pr_err("%s: Invalid interleave address select %d.\n", 740 __func__, intlv_addr_sel); 741 goto out_err; 742 } 743 744 /* Read D18F0x114 (DramLimitAddress). */ 745 if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) 746 goto out_err; 747 748 intlv_num_sockets = (tmp >> 8) & 0x1; 749 intlv_num_dies = (tmp >> 10) & 0x3; 750 dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); 751 752 intlv_addr_bit = intlv_addr_sel + 8; 753 754 /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ 755 switch (intlv_num_chan) { 756 case 0: intlv_num_chan = 0; break; 757 case 1: intlv_num_chan = 1; break; 758 case 3: intlv_num_chan = 2; break; 759 case 5: intlv_num_chan = 3; break; 760 case 7: intlv_num_chan = 4; break; 761 762 case 8: intlv_num_chan = 1; 763 hash_enabled = true; 764 break; 765 default: 766 pr_err("%s: Invalid number of interleaved channels %d.\n", 767 __func__, intlv_num_chan); 768 goto out_err; 769 } 770 771 num_intlv_bits = intlv_num_chan; 772 773 if (intlv_num_dies > 2) { 774 pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", 775 __func__, intlv_num_dies); 776 goto out_err; 777 } 778 779 num_intlv_bits += intlv_num_dies; 780 781 /* Add a bit if sockets are interleaved. */ 782 num_intlv_bits += intlv_num_sockets; 783 784 /* Assert num_intlv_bits <= 4 */ 785 if (num_intlv_bits > 4) { 786 pr_err("%s: Invalid interleave bits %d.\n", 787 __func__, num_intlv_bits); 788 goto out_err; 789 } 790 791 if (num_intlv_bits > 0) { 792 u64 temp_addr_x, temp_addr_i, temp_addr_y; 793 u8 die_id_bit, sock_id_bit, cs_fabric_id; 794 795 /* 796 * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. 797 * This is the fabric id for this coherent slave. Use 798 * umc/channel# as instance id of the coherent slave 799 * for FICAA. 800 */ 801 if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) 802 goto out_err; 803 804 cs_fabric_id = (tmp >> 8) & 0xFF; 805 die_id_bit = 0; 806 807 /* If interleaved over more than 1 channel: */ 808 if (intlv_num_chan) { 809 die_id_bit = intlv_num_chan; 810 cs_mask = (1 << die_id_bit) - 1; 811 cs_id = cs_fabric_id & cs_mask; 812 } 813 814 sock_id_bit = die_id_bit; 815 816 /* Read D18F1x208 (SystemFabricIdMask). */ 817 if (intlv_num_dies || intlv_num_sockets) 818 if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) 819 goto out_err; 820 821 /* If interleaved over more than 1 die. */ 822 if (intlv_num_dies) { 823 sock_id_bit = die_id_bit + intlv_num_dies; 824 die_id_shift = (tmp >> 24) & 0xF; 825 die_id_mask = (tmp >> 8) & 0xFF; 826 827 cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; 828 } 829 830 /* If interleaved over more than 1 socket. */ 831 if (intlv_num_sockets) { 832 socket_id_shift = (tmp >> 28) & 0xF; 833 socket_id_mask = (tmp >> 16) & 0xFF; 834 835 cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; 836 } 837 838 /* 839 * The pre-interleaved address consists of XXXXXXIIIYYYYY 840 * where III is the ID for this CS, and XXXXXXYYYYY are the 841 * address bits from the post-interleaved address. 842 * "num_intlv_bits" has been calculated to tell us how many "I" 843 * bits there are. "intlv_addr_bit" tells us how many "Y" bits 844 * there are (where "I" starts). 845 */ 846 temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); 847 temp_addr_i = (cs_id << intlv_addr_bit); 848 temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; 849 ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; 850 } 851 852 /* Add dram base address */ 853 ret_addr += dram_base_addr; 854 855 /* If legacy MMIO hole enabled */ 856 if (lgcy_mmio_hole_en) { 857 if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) 858 goto out_err; 859 860 dram_hole_base = tmp & GENMASK(31, 24); 861 if (ret_addr >= dram_hole_base) 862 ret_addr += (BIT_ULL(32) - dram_hole_base); 863 } 864 865 if (hash_enabled) { 866 /* Save some parentheses and grab ls-bit at the end. */ 867 hashed_bit = (ret_addr >> 12) ^ 868 (ret_addr >> 18) ^ 869 (ret_addr >> 21) ^ 870 (ret_addr >> 30) ^ 871 cs_id; 872 873 hashed_bit &= BIT(0); 874 875 if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) 876 ret_addr ^= BIT(intlv_addr_bit); 877 } 878 879 /* Is calculated system address is above DRAM limit address? */ 880 if (ret_addr > dram_limit_addr) 881 goto out_err; 882 883 *sys_addr = ret_addr; 884 return 0; 885 886 out_err: 887 return -EINVAL; 888 } 889 EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr); 890 891 bool amd_mce_is_memory_error(struct mce *m) 892 { 893 /* ErrCodeExt[20:16] */ 894 u8 xec = (m->status >> 16) & 0x1f; 895 896 if (mce_flags.smca) 897 return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0; 898 899 return m->bank == 4 && xec == 0x8; 900 } 901 902 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) 903 { 904 struct mce m; 905 906 mce_setup(&m); 907 908 m.status = status; 909 m.misc = misc; 910 m.bank = bank; 911 m.tsc = rdtsc(); 912 913 if (m.status & MCI_STATUS_ADDRV) { 914 m.addr = addr; 915 916 /* 917 * Extract [55:<lsb>] where lsb is the least significant 918 * *valid* bit of the address bits. 919 */ 920 if (mce_flags.smca) { 921 u8 lsb = (m.addr >> 56) & 0x3f; 922 923 m.addr &= GENMASK_ULL(55, lsb); 924 } 925 } 926 927 if (mce_flags.smca) { 928 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); 929 930 if (m.status & MCI_STATUS_SYNDV) 931 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); 932 } 933 934 mce_log(&m); 935 } 936 937 DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) 938 { 939 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); 940 inc_irq_stat(irq_deferred_error_count); 941 deferred_error_int_vector(); 942 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); 943 ack_APIC_irq(); 944 } 945 946 /* 947 * Returns true if the logged error is deferred. False, otherwise. 948 */ 949 static inline bool 950 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) 951 { 952 u64 status, addr = 0; 953 954 rdmsrl(msr_stat, status); 955 if (!(status & MCI_STATUS_VAL)) 956 return false; 957 958 if (status & MCI_STATUS_ADDRV) 959 rdmsrl(msr_addr, addr); 960 961 __log_error(bank, status, addr, misc); 962 963 wrmsrl(msr_stat, 0); 964 965 return status & MCI_STATUS_DEFERRED; 966 } 967 968 /* 969 * We have three scenarios for checking for Deferred errors: 970 * 971 * 1) Non-SMCA systems check MCA_STATUS and log error if found. 972 * 2) SMCA systems check MCA_STATUS. If error is found then log it and also 973 * clear MCA_DESTAT. 974 * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and 975 * log it. 976 */ 977 static void log_error_deferred(unsigned int bank) 978 { 979 bool defrd; 980 981 defrd = _log_error_bank(bank, msr_ops.status(bank), 982 msr_ops.addr(bank), 0); 983 984 if (!mce_flags.smca) 985 return; 986 987 /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */ 988 if (defrd) { 989 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); 990 return; 991 } 992 993 /* 994 * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check 995 * for a valid error. 996 */ 997 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), 998 MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); 999 } 1000 1001 /* APIC interrupt handler for deferred errors */ 1002 static void amd_deferred_error_interrupt(void) 1003 { 1004 unsigned int bank; 1005 1006 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) 1007 log_error_deferred(bank); 1008 } 1009 1010 static void log_error_thresholding(unsigned int bank, u64 misc) 1011 { 1012 _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc); 1013 } 1014 1015 static void log_and_reset_block(struct threshold_block *block) 1016 { 1017 struct thresh_restart tr; 1018 u32 low = 0, high = 0; 1019 1020 if (!block) 1021 return; 1022 1023 if (rdmsr_safe(block->address, &low, &high)) 1024 return; 1025 1026 if (!(high & MASK_OVERFLOW_HI)) 1027 return; 1028 1029 /* Log the MCE which caused the threshold event. */ 1030 log_error_thresholding(block->bank, ((u64)high << 32) | low); 1031 1032 /* Reset threshold block after logging error. */ 1033 memset(&tr, 0, sizeof(tr)); 1034 tr.b = block; 1035 threshold_restart_bank(&tr); 1036 } 1037 1038 /* 1039 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt 1040 * goes off when error_count reaches threshold_limit. 1041 */ 1042 static void amd_threshold_interrupt(void) 1043 { 1044 struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; 1045 struct threshold_bank **bp = this_cpu_read(threshold_banks); 1046 unsigned int bank, cpu = smp_processor_id(); 1047 1048 /* 1049 * Validate that the threshold bank has been initialized already. The 1050 * handler is installed at boot time, but on a hotplug event the 1051 * interrupt might fire before the data has been initialized. 1052 */ 1053 if (!bp) 1054 return; 1055 1056 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { 1057 if (!(per_cpu(bank_map, cpu) & (1 << bank))) 1058 continue; 1059 1060 first_block = bp[bank]->blocks; 1061 if (!first_block) 1062 continue; 1063 1064 /* 1065 * The first block is also the head of the list. Check it first 1066 * before iterating over the rest. 1067 */ 1068 log_and_reset_block(first_block); 1069 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) 1070 log_and_reset_block(block); 1071 } 1072 } 1073 1074 /* 1075 * Sysfs Interface 1076 */ 1077 1078 struct threshold_attr { 1079 struct attribute attr; 1080 ssize_t (*show) (struct threshold_block *, char *); 1081 ssize_t (*store) (struct threshold_block *, const char *, size_t count); 1082 }; 1083 1084 #define SHOW_FIELDS(name) \ 1085 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ 1086 { \ 1087 return sprintf(buf, "%lu\n", (unsigned long) b->name); \ 1088 } 1089 SHOW_FIELDS(interrupt_enable) 1090 SHOW_FIELDS(threshold_limit) 1091 1092 static ssize_t 1093 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) 1094 { 1095 struct thresh_restart tr; 1096 unsigned long new; 1097 1098 if (!b->interrupt_capable) 1099 return -EINVAL; 1100 1101 if (kstrtoul(buf, 0, &new) < 0) 1102 return -EINVAL; 1103 1104 b->interrupt_enable = !!new; 1105 1106 memset(&tr, 0, sizeof(tr)); 1107 tr.b = b; 1108 1109 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 1110 return -ENODEV; 1111 1112 return size; 1113 } 1114 1115 static ssize_t 1116 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) 1117 { 1118 struct thresh_restart tr; 1119 unsigned long new; 1120 1121 if (kstrtoul(buf, 0, &new) < 0) 1122 return -EINVAL; 1123 1124 if (new > THRESHOLD_MAX) 1125 new = THRESHOLD_MAX; 1126 if (new < 1) 1127 new = 1; 1128 1129 memset(&tr, 0, sizeof(tr)); 1130 tr.old_limit = b->threshold_limit; 1131 b->threshold_limit = new; 1132 tr.b = b; 1133 1134 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) 1135 return -ENODEV; 1136 1137 return size; 1138 } 1139 1140 static ssize_t show_error_count(struct threshold_block *b, char *buf) 1141 { 1142 u32 lo, hi; 1143 1144 /* CPU might be offline by now */ 1145 if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi)) 1146 return -ENODEV; 1147 1148 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - 1149 (THRESHOLD_MAX - b->threshold_limit))); 1150 } 1151 1152 static struct threshold_attr error_count = { 1153 .attr = {.name = __stringify(error_count), .mode = 0444 }, 1154 .show = show_error_count, 1155 }; 1156 1157 #define RW_ATTR(val) \ 1158 static struct threshold_attr val = { \ 1159 .attr = {.name = __stringify(val), .mode = 0644 }, \ 1160 .show = show_## val, \ 1161 .store = store_## val, \ 1162 }; 1163 1164 RW_ATTR(interrupt_enable); 1165 RW_ATTR(threshold_limit); 1166 1167 static struct attribute *default_attrs[] = { 1168 &threshold_limit.attr, 1169 &error_count.attr, 1170 NULL, /* possibly interrupt_enable if supported, see below */ 1171 NULL, 1172 }; 1173 1174 #define to_block(k) container_of(k, struct threshold_block, kobj) 1175 #define to_attr(a) container_of(a, struct threshold_attr, attr) 1176 1177 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) 1178 { 1179 struct threshold_block *b = to_block(kobj); 1180 struct threshold_attr *a = to_attr(attr); 1181 ssize_t ret; 1182 1183 ret = a->show ? a->show(b, buf) : -EIO; 1184 1185 return ret; 1186 } 1187 1188 static ssize_t store(struct kobject *kobj, struct attribute *attr, 1189 const char *buf, size_t count) 1190 { 1191 struct threshold_block *b = to_block(kobj); 1192 struct threshold_attr *a = to_attr(attr); 1193 ssize_t ret; 1194 1195 ret = a->store ? a->store(b, buf, count) : -EIO; 1196 1197 return ret; 1198 } 1199 1200 static const struct sysfs_ops threshold_ops = { 1201 .show = show, 1202 .store = store, 1203 }; 1204 1205 static void threshold_block_release(struct kobject *kobj); 1206 1207 static struct kobj_type threshold_ktype = { 1208 .sysfs_ops = &threshold_ops, 1209 .default_attrs = default_attrs, 1210 .release = threshold_block_release, 1211 }; 1212 1213 static const char *get_name(unsigned int bank, struct threshold_block *b) 1214 { 1215 enum smca_bank_types bank_type; 1216 1217 if (!mce_flags.smca) { 1218 if (b && bank == 4) 1219 return bank4_names(b); 1220 1221 return th_names[bank]; 1222 } 1223 1224 bank_type = smca_get_bank_type(bank); 1225 if (bank_type >= N_SMCA_BANK_TYPES) 1226 return NULL; 1227 1228 if (b && bank_type == SMCA_UMC) { 1229 if (b->block < ARRAY_SIZE(smca_umc_block_names)) 1230 return smca_umc_block_names[b->block]; 1231 return NULL; 1232 } 1233 1234 if (smca_banks[bank].hwid->count == 1) 1235 return smca_get_name(bank_type); 1236 1237 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, 1238 "%s_%x", smca_get_name(bank_type), 1239 smca_banks[bank].sysfs_id); 1240 return buf_mcatype; 1241 } 1242 1243 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb, 1244 unsigned int bank, unsigned int block, 1245 u32 address) 1246 { 1247 struct threshold_block *b = NULL; 1248 u32 low, high; 1249 int err; 1250 1251 if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS)) 1252 return 0; 1253 1254 if (rdmsr_safe(address, &low, &high)) 1255 return 0; 1256 1257 if (!(high & MASK_VALID_HI)) { 1258 if (block) 1259 goto recurse; 1260 else 1261 return 0; 1262 } 1263 1264 if (!(high & MASK_CNTP_HI) || 1265 (high & MASK_LOCKED_HI)) 1266 goto recurse; 1267 1268 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); 1269 if (!b) 1270 return -ENOMEM; 1271 1272 b->block = block; 1273 b->bank = bank; 1274 b->cpu = cpu; 1275 b->address = address; 1276 b->interrupt_enable = 0; 1277 b->interrupt_capable = lvt_interrupt_supported(bank, high); 1278 b->threshold_limit = THRESHOLD_MAX; 1279 1280 if (b->interrupt_capable) { 1281 threshold_ktype.default_attrs[2] = &interrupt_enable.attr; 1282 b->interrupt_enable = 1; 1283 } else { 1284 threshold_ktype.default_attrs[2] = NULL; 1285 } 1286 1287 INIT_LIST_HEAD(&b->miscj); 1288 1289 /* This is safe as @tb is not visible yet */ 1290 if (tb->blocks) 1291 list_add(&b->miscj, &tb->blocks->miscj); 1292 else 1293 tb->blocks = b; 1294 1295 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(bank, b)); 1296 if (err) 1297 goto out_free; 1298 recurse: 1299 address = get_block_address(address, low, high, bank, ++block, cpu); 1300 if (!address) 1301 return 0; 1302 1303 err = allocate_threshold_blocks(cpu, tb, bank, block, address); 1304 if (err) 1305 goto out_free; 1306 1307 if (b) 1308 kobject_uevent(&b->kobj, KOBJ_ADD); 1309 1310 return 0; 1311 1312 out_free: 1313 if (b) { 1314 list_del(&b->miscj); 1315 kobject_put(&b->kobj); 1316 } 1317 return err; 1318 } 1319 1320 static int __threshold_add_blocks(struct threshold_bank *b) 1321 { 1322 struct list_head *head = &b->blocks->miscj; 1323 struct threshold_block *pos = NULL; 1324 struct threshold_block *tmp = NULL; 1325 int err = 0; 1326 1327 err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); 1328 if (err) 1329 return err; 1330 1331 list_for_each_entry_safe(pos, tmp, head, miscj) { 1332 1333 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); 1334 if (err) { 1335 list_for_each_entry_safe_reverse(pos, tmp, head, miscj) 1336 kobject_del(&pos->kobj); 1337 1338 return err; 1339 } 1340 } 1341 return err; 1342 } 1343 1344 static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu, 1345 unsigned int bank) 1346 { 1347 struct device *dev = this_cpu_read(mce_device); 1348 struct amd_northbridge *nb = NULL; 1349 struct threshold_bank *b = NULL; 1350 const char *name = get_name(bank, NULL); 1351 int err = 0; 1352 1353 if (!dev) 1354 return -ENODEV; 1355 1356 if (is_shared_bank(bank)) { 1357 nb = node_to_amd_nb(topology_die_id(cpu)); 1358 1359 /* threshold descriptor already initialized on this node? */ 1360 if (nb && nb->bank4) { 1361 /* yes, use it */ 1362 b = nb->bank4; 1363 err = kobject_add(b->kobj, &dev->kobj, name); 1364 if (err) 1365 goto out; 1366 1367 bp[bank] = b; 1368 refcount_inc(&b->cpus); 1369 1370 err = __threshold_add_blocks(b); 1371 1372 goto out; 1373 } 1374 } 1375 1376 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); 1377 if (!b) { 1378 err = -ENOMEM; 1379 goto out; 1380 } 1381 1382 /* Associate the bank with the per-CPU MCE device */ 1383 b->kobj = kobject_create_and_add(name, &dev->kobj); 1384 if (!b->kobj) { 1385 err = -EINVAL; 1386 goto out_free; 1387 } 1388 1389 if (is_shared_bank(bank)) { 1390 b->shared = 1; 1391 refcount_set(&b->cpus, 1); 1392 1393 /* nb is already initialized, see above */ 1394 if (nb) { 1395 WARN_ON(nb->bank4); 1396 nb->bank4 = b; 1397 } 1398 } 1399 1400 err = allocate_threshold_blocks(cpu, b, bank, 0, msr_ops.misc(bank)); 1401 if (err) 1402 goto out_kobj; 1403 1404 bp[bank] = b; 1405 return 0; 1406 1407 out_kobj: 1408 kobject_put(b->kobj); 1409 out_free: 1410 kfree(b); 1411 out: 1412 return err; 1413 } 1414 1415 static void threshold_block_release(struct kobject *kobj) 1416 { 1417 kfree(to_block(kobj)); 1418 } 1419 1420 static void deallocate_threshold_blocks(struct threshold_bank *bank) 1421 { 1422 struct threshold_block *pos, *tmp; 1423 1424 list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) { 1425 list_del(&pos->miscj); 1426 kobject_put(&pos->kobj); 1427 } 1428 1429 kobject_put(&bank->blocks->kobj); 1430 } 1431 1432 static void __threshold_remove_blocks(struct threshold_bank *b) 1433 { 1434 struct threshold_block *pos = NULL; 1435 struct threshold_block *tmp = NULL; 1436 1437 kobject_del(b->kobj); 1438 1439 list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) 1440 kobject_del(&pos->kobj); 1441 } 1442 1443 static void threshold_remove_bank(struct threshold_bank *bank) 1444 { 1445 struct amd_northbridge *nb; 1446 1447 if (!bank->blocks) 1448 goto out_free; 1449 1450 if (!bank->shared) 1451 goto out_dealloc; 1452 1453 if (!refcount_dec_and_test(&bank->cpus)) { 1454 __threshold_remove_blocks(bank); 1455 return; 1456 } else { 1457 /* 1458 * The last CPU on this node using the shared bank is going 1459 * away, remove that bank now. 1460 */ 1461 nb = node_to_amd_nb(topology_die_id(smp_processor_id())); 1462 nb->bank4 = NULL; 1463 } 1464 1465 out_dealloc: 1466 deallocate_threshold_blocks(bank); 1467 1468 out_free: 1469 kobject_put(bank->kobj); 1470 kfree(bank); 1471 } 1472 1473 int mce_threshold_remove_device(unsigned int cpu) 1474 { 1475 struct threshold_bank **bp = this_cpu_read(threshold_banks); 1476 unsigned int bank, numbanks = this_cpu_read(mce_num_banks); 1477 1478 if (!bp) 1479 return 0; 1480 1481 /* 1482 * Clear the pointer before cleaning up, so that the interrupt won't 1483 * touch anything of this. 1484 */ 1485 this_cpu_write(threshold_banks, NULL); 1486 1487 for (bank = 0; bank < numbanks; bank++) { 1488 if (bp[bank]) { 1489 threshold_remove_bank(bp[bank]); 1490 bp[bank] = NULL; 1491 } 1492 } 1493 kfree(bp); 1494 return 0; 1495 } 1496 1497 /** 1498 * mce_threshold_create_device - Create the per-CPU MCE threshold device 1499 * @cpu: The plugged in CPU 1500 * 1501 * Create directories and files for all valid threshold banks. 1502 * 1503 * This is invoked from the CPU hotplug callback which was installed in 1504 * mcheck_init_device(). The invocation happens in context of the hotplug 1505 * thread running on @cpu. The callback is invoked on all CPUs which are 1506 * online when the callback is installed or during a real hotplug event. 1507 */ 1508 int mce_threshold_create_device(unsigned int cpu) 1509 { 1510 unsigned int numbanks, bank; 1511 struct threshold_bank **bp; 1512 int err; 1513 1514 if (!mce_flags.amd_threshold) 1515 return 0; 1516 1517 bp = this_cpu_read(threshold_banks); 1518 if (bp) 1519 return 0; 1520 1521 numbanks = this_cpu_read(mce_num_banks); 1522 bp = kcalloc(numbanks, sizeof(*bp), GFP_KERNEL); 1523 if (!bp) 1524 return -ENOMEM; 1525 1526 for (bank = 0; bank < numbanks; ++bank) { 1527 if (!(this_cpu_read(bank_map) & (1 << bank))) 1528 continue; 1529 err = threshold_create_bank(bp, cpu, bank); 1530 if (err) 1531 goto out_err; 1532 } 1533 this_cpu_write(threshold_banks, bp); 1534 1535 if (thresholding_irq_en) 1536 mce_threshold_vector = amd_threshold_interrupt; 1537 return 0; 1538 out_err: 1539 mce_threshold_remove_device(cpu); 1540 return err; 1541 } 1542