1 /* 2 * (c) 2005-2016 Advanced Micro Devices, Inc. 3 * Your use of this code is subject to the terms and conditions of the 4 * GNU general public license version 2. See "COPYING" or 5 * http://www.gnu.org/licenses/gpl.html 6 * 7 * Written by Jacob Shin - AMD, Inc. 8 * Maintained by: Borislav Petkov <bp@alien8.de> 9 * 10 * All MC4_MISCi registers are shared between cores on a node. 11 */ 12 #include <linux/interrupt.h> 13 #include <linux/notifier.h> 14 #include <linux/kobject.h> 15 #include <linux/percpu.h> 16 #include <linux/errno.h> 17 #include <linux/sched.h> 18 #include <linux/sysfs.h> 19 #include <linux/slab.h> 20 #include <linux/init.h> 21 #include <linux/cpu.h> 22 #include <linux/smp.h> 23 #include <linux/string.h> 24 25 #include <asm/amd_nb.h> 26 #include <asm/traps.h> 27 #include <asm/apic.h> 28 #include <asm/mce.h> 29 #include <asm/msr.h> 30 #include <asm/trace/irq_vectors.h> 31 32 #include "internal.h" 33 34 #define NR_BLOCKS 5 35 #define THRESHOLD_MAX 0xFFF 36 #define INT_TYPE_APIC 0x00020000 37 #define MASK_VALID_HI 0x80000000 38 #define MASK_CNTP_HI 0x40000000 39 #define MASK_LOCKED_HI 0x20000000 40 #define MASK_LVTOFF_HI 0x00F00000 41 #define MASK_COUNT_EN_HI 0x00080000 42 #define MASK_INT_TYPE_HI 0x00060000 43 #define MASK_OVERFLOW_HI 0x00010000 44 #define MASK_ERR_COUNT_HI 0x00000FFF 45 #define MASK_BLKPTR_LO 0xFF000000 46 #define MCG_XBLK_ADDR 0xC0000400 47 48 /* Deferred error settings */ 49 #define MSR_CU_DEF_ERR 0xC0000410 50 #define MASK_DEF_LVTOFF 0x000000F0 51 #define MASK_DEF_INT_TYPE 0x00000006 52 #define DEF_LVT_OFF 0x2 53 #define DEF_INT_TYPE_APIC 0x2 54 55 /* Scalable MCA: */ 56 57 /* Threshold LVT offset is at MSR0xC0000410[15:12] */ 58 #define SMCA_THR_LVT_OFF 0xF000 59 60 static bool thresholding_irq_en; 61 62 static const char * const th_names[] = { 63 "load_store", 64 "insn_fetch", 65 "combined_unit", 66 "decode_unit", 67 "northbridge", 68 "execution_unit", 69 }; 70 71 static const char * const smca_umc_block_names[] = { 72 "dram_ecc", 73 "misc_umc" 74 }; 75 76 struct smca_bank_name { 77 const char *name; /* Short name for sysfs */ 78 const char *long_name; /* Long name for pretty-printing */ 79 }; 80 81 static struct smca_bank_name smca_names[] = { 82 [SMCA_LS] = { "load_store", "Load Store Unit" }, 83 [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, 84 [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, 85 [SMCA_DE] = { "decode_unit", "Decode Unit" }, 86 [SMCA_RESERVED] = { "reserved", "Reserved" }, 87 [SMCA_EX] = { "execution_unit", "Execution Unit" }, 88 [SMCA_FP] = { "floating_point", "Floating Point Unit" }, 89 [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, 90 [SMCA_CS] = { "coherent_slave", "Coherent Slave" }, 91 [SMCA_CS_V2] = { "coherent_slave", "Coherent Slave" }, 92 [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, 93 [SMCA_UMC] = { "umc", "Unified Memory Controller" }, 94 [SMCA_PB] = { "param_block", "Parameter Block" }, 95 [SMCA_PSP] = { "psp", "Platform Security Processor" }, 96 [SMCA_PSP_V2] = { "psp", "Platform Security Processor" }, 97 [SMCA_SMU] = { "smu", "System Management Unit" }, 98 [SMCA_SMU_V2] = { "smu", "System Management Unit" }, 99 [SMCA_MP5] = { "mp5", "Microprocessor 5 Unit" }, 100 [SMCA_NBIO] = { "nbio", "Northbridge IO Unit" }, 101 [SMCA_PCIE] = { "pcie", "PCI Express Unit" }, 102 }; 103 104 static u32 smca_bank_addrs[MAX_NR_BANKS][NR_BLOCKS] __ro_after_init = 105 { 106 [0 ... MAX_NR_BANKS - 1] = { [0 ... NR_BLOCKS - 1] = -1 } 107 }; 108 109 static const char *smca_get_name(enum smca_bank_types t) 110 { 111 if (t >= N_SMCA_BANK_TYPES) 112 return NULL; 113 114 return smca_names[t].name; 115 } 116 117 const char *smca_get_long_name(enum smca_bank_types t) 118 { 119 if (t >= N_SMCA_BANK_TYPES) 120 return NULL; 121 122 return smca_names[t].long_name; 123 } 124 EXPORT_SYMBOL_GPL(smca_get_long_name); 125 126 static enum smca_bank_types smca_get_bank_type(unsigned int bank) 127 { 128 struct smca_bank *b; 129 130 if (bank >= MAX_NR_BANKS) 131 return N_SMCA_BANK_TYPES; 132 133 b = &smca_banks[bank]; 134 if (!b->hwid) 135 return N_SMCA_BANK_TYPES; 136 137 return b->hwid->bank_type; 138 } 139 140 static struct smca_hwid smca_hwid_mcatypes[] = { 141 /* { bank_type, hwid_mcatype, xec_bitmap } */ 142 143 /* Reserved type */ 144 { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 }, 145 146 /* ZN Core (HWID=0xB0) MCA types */ 147 { SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFFF }, 148 { SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF }, 149 { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF }, 150 { SMCA_DE, HWID_MCATYPE(0xB0, 0x3), 0x1FF }, 151 /* HWID 0xB0 MCATYPE 0x4 is Reserved */ 152 { SMCA_EX, HWID_MCATYPE(0xB0, 0x5), 0xFFF }, 153 { SMCA_FP, HWID_MCATYPE(0xB0, 0x6), 0x7F }, 154 { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF }, 155 156 /* Data Fabric MCA types */ 157 { SMCA_CS, HWID_MCATYPE(0x2E, 0x0), 0x1FF }, 158 { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1), 0x1F }, 159 { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2), 0x3FFF }, 160 161 /* Unified Memory Controller MCA type */ 162 { SMCA_UMC, HWID_MCATYPE(0x96, 0x0), 0xFF }, 163 164 /* Parameter Block MCA type */ 165 { SMCA_PB, HWID_MCATYPE(0x05, 0x0), 0x1 }, 166 167 /* Platform Security Processor MCA type */ 168 { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0), 0x1 }, 169 { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1), 0x3FFFF }, 170 171 /* System Management Unit MCA type */ 172 { SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 }, 173 { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1), 0x7FF }, 174 175 /* Microprocessor 5 Unit MCA type */ 176 { SMCA_MP5, HWID_MCATYPE(0x01, 0x2), 0x3FF }, 177 178 /* Northbridge IO Unit MCA type */ 179 { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0), 0x1F }, 180 181 /* PCI Express Unit MCA type */ 182 { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0), 0x1F }, 183 }; 184 185 struct smca_bank smca_banks[MAX_NR_BANKS]; 186 EXPORT_SYMBOL_GPL(smca_banks); 187 188 /* 189 * In SMCA enabled processors, we can have multiple banks for a given IP type. 190 * So to define a unique name for each bank, we use a temp c-string to append 191 * the MCA_IPID[InstanceId] to type's name in get_name(). 192 * 193 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN 194 * is greater than 8 plus 1 (for underscore) plus length of longest type name. 195 */ 196 #define MAX_MCATYPE_NAME_LEN 30 197 static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; 198 199 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); 200 static DEFINE_PER_CPU(unsigned int, bank_map); /* see which banks are on */ 201 202 static void amd_threshold_interrupt(void); 203 static void amd_deferred_error_interrupt(void); 204 205 static void default_deferred_error_interrupt(void) 206 { 207 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); 208 } 209 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; 210 211 static void smca_configure(unsigned int bank, unsigned int cpu) 212 { 213 unsigned int i, hwid_mcatype; 214 struct smca_hwid *s_hwid; 215 u32 high, low; 216 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); 217 218 /* Set appropriate bits in MCA_CONFIG */ 219 if (!rdmsr_safe(smca_config, &low, &high)) { 220 /* 221 * OS is required to set the MCAX bit to acknowledge that it is 222 * now using the new MSR ranges and new registers under each 223 * bank. It also means that the OS will configure deferred 224 * errors in the new MCx_CONFIG register. If the bit is not set, 225 * uncorrectable errors will cause a system panic. 226 * 227 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) 228 */ 229 high |= BIT(0); 230 231 /* 232 * SMCA sets the Deferred Error Interrupt type per bank. 233 * 234 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us 235 * if the DeferredIntType bit field is available. 236 * 237 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the 238 * high portion of the MSR). OS should set this to 0x1 to enable 239 * APIC based interrupt. First, check that no interrupt has been 240 * set. 241 */ 242 if ((low & BIT(5)) && !((high >> 5) & 0x3)) 243 high |= BIT(5); 244 245 wrmsr(smca_config, low, high); 246 } 247 248 /* Return early if this bank was already initialized. */ 249 if (smca_banks[bank].hwid) 250 return; 251 252 if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { 253 pr_warn("Failed to read MCA_IPID for bank %d\n", bank); 254 return; 255 } 256 257 hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, 258 (high & MCI_IPID_MCATYPE) >> 16); 259 260 for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { 261 s_hwid = &smca_hwid_mcatypes[i]; 262 if (hwid_mcatype == s_hwid->hwid_mcatype) { 263 smca_banks[bank].hwid = s_hwid; 264 smca_banks[bank].id = low; 265 smca_banks[bank].sysfs_id = s_hwid->count++; 266 break; 267 } 268 } 269 } 270 271 struct thresh_restart { 272 struct threshold_block *b; 273 int reset; 274 int set_lvt_off; 275 int lvt_off; 276 u16 old_limit; 277 }; 278 279 static inline bool is_shared_bank(int bank) 280 { 281 /* 282 * Scalable MCA provides for only one core to have access to the MSRs of 283 * a shared bank. 284 */ 285 if (mce_flags.smca) 286 return false; 287 288 /* Bank 4 is for northbridge reporting and is thus shared */ 289 return (bank == 4); 290 } 291 292 static const char *bank4_names(const struct threshold_block *b) 293 { 294 switch (b->address) { 295 /* MSR4_MISC0 */ 296 case 0x00000413: 297 return "dram"; 298 299 case 0xc0000408: 300 return "ht_links"; 301 302 case 0xc0000409: 303 return "l3_cache"; 304 305 default: 306 WARN(1, "Funny MSR: 0x%08x\n", b->address); 307 return ""; 308 } 309 }; 310 311 312 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) 313 { 314 /* 315 * bank 4 supports APIC LVT interrupts implicitly since forever. 316 */ 317 if (bank == 4) 318 return true; 319 320 /* 321 * IntP: interrupt present; if this bit is set, the thresholding 322 * bank can generate APIC LVT interrupts 323 */ 324 return msr_high_bits & BIT(28); 325 } 326 327 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) 328 { 329 int msr = (hi & MASK_LVTOFF_HI) >> 20; 330 331 if (apic < 0) { 332 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " 333 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, 334 b->bank, b->block, b->address, hi, lo); 335 return 0; 336 } 337 338 if (apic != msr) { 339 /* 340 * On SMCA CPUs, LVT offset is programmed at a different MSR, and 341 * the BIOS provides the value. The original field where LVT offset 342 * was set is reserved. Return early here: 343 */ 344 if (mce_flags.smca) 345 return 0; 346 347 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " 348 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", 349 b->cpu, apic, b->bank, b->block, b->address, hi, lo); 350 return 0; 351 } 352 353 return 1; 354 }; 355 356 /* Reprogram MCx_MISC MSR behind this threshold bank. */ 357 static void threshold_restart_bank(void *_tr) 358 { 359 struct thresh_restart *tr = _tr; 360 u32 hi, lo; 361 362 rdmsr(tr->b->address, lo, hi); 363 364 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) 365 tr->reset = 1; /* limit cannot be lower than err count */ 366 367 if (tr->reset) { /* reset err count and overflow bit */ 368 hi = 369 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | 370 (THRESHOLD_MAX - tr->b->threshold_limit); 371 } else if (tr->old_limit) { /* change limit w/o reset */ 372 int new_count = (hi & THRESHOLD_MAX) + 373 (tr->old_limit - tr->b->threshold_limit); 374 375 hi = (hi & ~MASK_ERR_COUNT_HI) | 376 (new_count & THRESHOLD_MAX); 377 } 378 379 /* clear IntType */ 380 hi &= ~MASK_INT_TYPE_HI; 381 382 if (!tr->b->interrupt_capable) 383 goto done; 384 385 if (tr->set_lvt_off) { 386 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { 387 /* set new lvt offset */ 388 hi &= ~MASK_LVTOFF_HI; 389 hi |= tr->lvt_off << 20; 390 } 391 } 392 393 if (tr->b->interrupt_enable) 394 hi |= INT_TYPE_APIC; 395 396 done: 397 398 hi |= MASK_COUNT_EN_HI; 399 wrmsr(tr->b->address, lo, hi); 400 } 401 402 static void mce_threshold_block_init(struct threshold_block *b, int offset) 403 { 404 struct thresh_restart tr = { 405 .b = b, 406 .set_lvt_off = 1, 407 .lvt_off = offset, 408 }; 409 410 b->threshold_limit = THRESHOLD_MAX; 411 threshold_restart_bank(&tr); 412 }; 413 414 static int setup_APIC_mce_threshold(int reserved, int new) 415 { 416 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, 417 APIC_EILVT_MSG_FIX, 0)) 418 return new; 419 420 return reserved; 421 } 422 423 static int setup_APIC_deferred_error(int reserved, int new) 424 { 425 if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, 426 APIC_EILVT_MSG_FIX, 0)) 427 return new; 428 429 return reserved; 430 } 431 432 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) 433 { 434 u32 low = 0, high = 0; 435 int def_offset = -1, def_new; 436 437 if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) 438 return; 439 440 def_new = (low & MASK_DEF_LVTOFF) >> 4; 441 if (!(low & MASK_DEF_LVTOFF)) { 442 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); 443 def_new = DEF_LVT_OFF; 444 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); 445 } 446 447 def_offset = setup_APIC_deferred_error(def_offset, def_new); 448 if ((def_offset == def_new) && 449 (deferred_error_int_vector != amd_deferred_error_interrupt)) 450 deferred_error_int_vector = amd_deferred_error_interrupt; 451 452 if (!mce_flags.smca) 453 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; 454 455 wrmsr(MSR_CU_DEF_ERR, low, high); 456 } 457 458 static u32 smca_get_block_address(unsigned int bank, unsigned int block) 459 { 460 u32 low, high; 461 u32 addr = 0; 462 463 if (smca_get_bank_type(bank) == SMCA_RESERVED) 464 return addr; 465 466 if (!block) 467 return MSR_AMD64_SMCA_MCx_MISC(bank); 468 469 /* Check our cache first: */ 470 if (smca_bank_addrs[bank][block] != -1) 471 return smca_bank_addrs[bank][block]; 472 473 /* 474 * For SMCA enabled processors, BLKPTR field of the first MISC register 475 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). 476 */ 477 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) 478 goto out; 479 480 if (!(low & MCI_CONFIG_MCAX)) 481 goto out; 482 483 if (!rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && 484 (low & MASK_BLKPTR_LO)) 485 addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); 486 487 out: 488 smca_bank_addrs[bank][block] = addr; 489 return addr; 490 } 491 492 static u32 get_block_address(u32 current_addr, u32 low, u32 high, 493 unsigned int bank, unsigned int block) 494 { 495 u32 addr = 0, offset = 0; 496 497 if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) 498 return addr; 499 500 if (mce_flags.smca) 501 return smca_get_block_address(bank, block); 502 503 /* Fall back to method we used for older processors: */ 504 switch (block) { 505 case 0: 506 addr = msr_ops.misc(bank); 507 break; 508 case 1: 509 offset = ((low & MASK_BLKPTR_LO) >> 21); 510 if (offset) 511 addr = MCG_XBLK_ADDR + offset; 512 break; 513 default: 514 addr = ++current_addr; 515 } 516 return addr; 517 } 518 519 static int 520 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, 521 int offset, u32 misc_high) 522 { 523 unsigned int cpu = smp_processor_id(); 524 u32 smca_low, smca_high; 525 struct threshold_block b; 526 int new; 527 528 if (!block) 529 per_cpu(bank_map, cpu) |= (1 << bank); 530 531 memset(&b, 0, sizeof(b)); 532 b.cpu = cpu; 533 b.bank = bank; 534 b.block = block; 535 b.address = addr; 536 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); 537 538 if (!b.interrupt_capable) 539 goto done; 540 541 b.interrupt_enable = 1; 542 543 if (!mce_flags.smca) { 544 new = (misc_high & MASK_LVTOFF_HI) >> 20; 545 goto set_offset; 546 } 547 548 /* Gather LVT offset for thresholding: */ 549 if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) 550 goto out; 551 552 new = (smca_low & SMCA_THR_LVT_OFF) >> 12; 553 554 set_offset: 555 offset = setup_APIC_mce_threshold(offset, new); 556 if (offset == new) 557 thresholding_irq_en = true; 558 559 done: 560 mce_threshold_block_init(&b, offset); 561 562 out: 563 return offset; 564 } 565 566 /* 567 * Turn off MC4_MISC thresholding banks on all family 0x15 models since 568 * they're not supported there. 569 */ 570 void disable_err_thresholding(struct cpuinfo_x86 *c) 571 { 572 int i; 573 u64 hwcr; 574 bool need_toggle; 575 u32 msrs[] = { 576 0x00000413, /* MC4_MISC0 */ 577 0xc0000408, /* MC4_MISC1 */ 578 }; 579 580 if (c->x86 != 0x15) 581 return; 582 583 rdmsrl(MSR_K7_HWCR, hwcr); 584 585 /* McStatusWrEn has to be set */ 586 need_toggle = !(hwcr & BIT(18)); 587 588 if (need_toggle) 589 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); 590 591 /* Clear CntP bit safely */ 592 for (i = 0; i < ARRAY_SIZE(msrs); i++) 593 msr_clear_bit(msrs[i], 62); 594 595 /* restore old settings */ 596 if (need_toggle) 597 wrmsrl(MSR_K7_HWCR, hwcr); 598 } 599 600 /* cpu init entry point, called from mce.c with preempt off */ 601 void mce_amd_feature_init(struct cpuinfo_x86 *c) 602 { 603 u32 low = 0, high = 0, address = 0; 604 unsigned int bank, block, cpu = smp_processor_id(); 605 int offset = -1; 606 607 disable_err_thresholding(c); 608 609 for (bank = 0; bank < mca_cfg.banks; ++bank) { 610 if (mce_flags.smca) 611 smca_configure(bank, cpu); 612 613 for (block = 0; block < NR_BLOCKS; ++block) { 614 address = get_block_address(address, low, high, bank, block); 615 if (!address) 616 break; 617 618 if (rdmsr_safe(address, &low, &high)) 619 break; 620 621 if (!(high & MASK_VALID_HI)) 622 continue; 623 624 if (!(high & MASK_CNTP_HI) || 625 (high & MASK_LOCKED_HI)) 626 continue; 627 628 offset = prepare_threshold_block(bank, block, address, offset, high); 629 } 630 } 631 632 if (mce_flags.succor) 633 deferred_error_interrupt_enable(c); 634 } 635 636 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) 637 { 638 u64 dram_base_addr, dram_limit_addr, dram_hole_base; 639 /* We start from the normalized address */ 640 u64 ret_addr = norm_addr; 641 642 u32 tmp; 643 644 u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; 645 u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; 646 u8 intlv_addr_sel, intlv_addr_bit; 647 u8 num_intlv_bits, hashed_bit; 648 u8 lgcy_mmio_hole_en, base = 0; 649 u8 cs_mask, cs_id = 0; 650 bool hash_enabled = false; 651 652 /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ 653 if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) 654 goto out_err; 655 656 /* Remove HiAddrOffset from normalized address, if enabled: */ 657 if (tmp & BIT(0)) { 658 u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; 659 660 if (norm_addr >= hi_addr_offset) { 661 ret_addr -= hi_addr_offset; 662 base = 1; 663 } 664 } 665 666 /* Read D18F0x110 (DramBaseAddress). */ 667 if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) 668 goto out_err; 669 670 /* Check if address range is valid. */ 671 if (!(tmp & BIT(0))) { 672 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", 673 __func__, tmp); 674 goto out_err; 675 } 676 677 lgcy_mmio_hole_en = tmp & BIT(1); 678 intlv_num_chan = (tmp >> 4) & 0xF; 679 intlv_addr_sel = (tmp >> 8) & 0x7; 680 dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; 681 682 /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ 683 if (intlv_addr_sel > 3) { 684 pr_err("%s: Invalid interleave address select %d.\n", 685 __func__, intlv_addr_sel); 686 goto out_err; 687 } 688 689 /* Read D18F0x114 (DramLimitAddress). */ 690 if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) 691 goto out_err; 692 693 intlv_num_sockets = (tmp >> 8) & 0x1; 694 intlv_num_dies = (tmp >> 10) & 0x3; 695 dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); 696 697 intlv_addr_bit = intlv_addr_sel + 8; 698 699 /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ 700 switch (intlv_num_chan) { 701 case 0: intlv_num_chan = 0; break; 702 case 1: intlv_num_chan = 1; break; 703 case 3: intlv_num_chan = 2; break; 704 case 5: intlv_num_chan = 3; break; 705 case 7: intlv_num_chan = 4; break; 706 707 case 8: intlv_num_chan = 1; 708 hash_enabled = true; 709 break; 710 default: 711 pr_err("%s: Invalid number of interleaved channels %d.\n", 712 __func__, intlv_num_chan); 713 goto out_err; 714 } 715 716 num_intlv_bits = intlv_num_chan; 717 718 if (intlv_num_dies > 2) { 719 pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", 720 __func__, intlv_num_dies); 721 goto out_err; 722 } 723 724 num_intlv_bits += intlv_num_dies; 725 726 /* Add a bit if sockets are interleaved. */ 727 num_intlv_bits += intlv_num_sockets; 728 729 /* Assert num_intlv_bits <= 4 */ 730 if (num_intlv_bits > 4) { 731 pr_err("%s: Invalid interleave bits %d.\n", 732 __func__, num_intlv_bits); 733 goto out_err; 734 } 735 736 if (num_intlv_bits > 0) { 737 u64 temp_addr_x, temp_addr_i, temp_addr_y; 738 u8 die_id_bit, sock_id_bit, cs_fabric_id; 739 740 /* 741 * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. 742 * This is the fabric id for this coherent slave. Use 743 * umc/channel# as instance id of the coherent slave 744 * for FICAA. 745 */ 746 if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) 747 goto out_err; 748 749 cs_fabric_id = (tmp >> 8) & 0xFF; 750 die_id_bit = 0; 751 752 /* If interleaved over more than 1 channel: */ 753 if (intlv_num_chan) { 754 die_id_bit = intlv_num_chan; 755 cs_mask = (1 << die_id_bit) - 1; 756 cs_id = cs_fabric_id & cs_mask; 757 } 758 759 sock_id_bit = die_id_bit; 760 761 /* Read D18F1x208 (SystemFabricIdMask). */ 762 if (intlv_num_dies || intlv_num_sockets) 763 if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) 764 goto out_err; 765 766 /* If interleaved over more than 1 die. */ 767 if (intlv_num_dies) { 768 sock_id_bit = die_id_bit + intlv_num_dies; 769 die_id_shift = (tmp >> 24) & 0xF; 770 die_id_mask = (tmp >> 8) & 0xFF; 771 772 cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; 773 } 774 775 /* If interleaved over more than 1 socket. */ 776 if (intlv_num_sockets) { 777 socket_id_shift = (tmp >> 28) & 0xF; 778 socket_id_mask = (tmp >> 16) & 0xFF; 779 780 cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; 781 } 782 783 /* 784 * The pre-interleaved address consists of XXXXXXIIIYYYYY 785 * where III is the ID for this CS, and XXXXXXYYYYY are the 786 * address bits from the post-interleaved address. 787 * "num_intlv_bits" has been calculated to tell us how many "I" 788 * bits there are. "intlv_addr_bit" tells us how many "Y" bits 789 * there are (where "I" starts). 790 */ 791 temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); 792 temp_addr_i = (cs_id << intlv_addr_bit); 793 temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; 794 ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; 795 } 796 797 /* Add dram base address */ 798 ret_addr += dram_base_addr; 799 800 /* If legacy MMIO hole enabled */ 801 if (lgcy_mmio_hole_en) { 802 if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) 803 goto out_err; 804 805 dram_hole_base = tmp & GENMASK(31, 24); 806 if (ret_addr >= dram_hole_base) 807 ret_addr += (BIT_ULL(32) - dram_hole_base); 808 } 809 810 if (hash_enabled) { 811 /* Save some parentheses and grab ls-bit at the end. */ 812 hashed_bit = (ret_addr >> 12) ^ 813 (ret_addr >> 18) ^ 814 (ret_addr >> 21) ^ 815 (ret_addr >> 30) ^ 816 cs_id; 817 818 hashed_bit &= BIT(0); 819 820 if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) 821 ret_addr ^= BIT(intlv_addr_bit); 822 } 823 824 /* Is calculated system address is above DRAM limit address? */ 825 if (ret_addr > dram_limit_addr) 826 goto out_err; 827 828 *sys_addr = ret_addr; 829 return 0; 830 831 out_err: 832 return -EINVAL; 833 } 834 EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr); 835 836 bool amd_mce_is_memory_error(struct mce *m) 837 { 838 /* ErrCodeExt[20:16] */ 839 u8 xec = (m->status >> 16) & 0x1f; 840 841 if (mce_flags.smca) 842 return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0; 843 844 return m->bank == 4 && xec == 0x8; 845 } 846 847 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) 848 { 849 struct mce m; 850 851 mce_setup(&m); 852 853 m.status = status; 854 m.misc = misc; 855 m.bank = bank; 856 m.tsc = rdtsc(); 857 858 if (m.status & MCI_STATUS_ADDRV) { 859 m.addr = addr; 860 861 /* 862 * Extract [55:<lsb>] where lsb is the least significant 863 * *valid* bit of the address bits. 864 */ 865 if (mce_flags.smca) { 866 u8 lsb = (m.addr >> 56) & 0x3f; 867 868 m.addr &= GENMASK_ULL(55, lsb); 869 } 870 } 871 872 if (mce_flags.smca) { 873 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); 874 875 if (m.status & MCI_STATUS_SYNDV) 876 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); 877 } 878 879 mce_log(&m); 880 } 881 882 asmlinkage __visible void __irq_entry smp_deferred_error_interrupt(struct pt_regs *regs) 883 { 884 entering_irq(); 885 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); 886 inc_irq_stat(irq_deferred_error_count); 887 deferred_error_int_vector(); 888 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); 889 exiting_ack_irq(); 890 } 891 892 /* 893 * Returns true if the logged error is deferred. False, otherwise. 894 */ 895 static inline bool 896 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) 897 { 898 u64 status, addr = 0; 899 900 rdmsrl(msr_stat, status); 901 if (!(status & MCI_STATUS_VAL)) 902 return false; 903 904 if (status & MCI_STATUS_ADDRV) 905 rdmsrl(msr_addr, addr); 906 907 __log_error(bank, status, addr, misc); 908 909 wrmsrl(msr_stat, 0); 910 911 return status & MCI_STATUS_DEFERRED; 912 } 913 914 /* 915 * We have three scenarios for checking for Deferred errors: 916 * 917 * 1) Non-SMCA systems check MCA_STATUS and log error if found. 918 * 2) SMCA systems check MCA_STATUS. If error is found then log it and also 919 * clear MCA_DESTAT. 920 * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and 921 * log it. 922 */ 923 static void log_error_deferred(unsigned int bank) 924 { 925 bool defrd; 926 927 defrd = _log_error_bank(bank, msr_ops.status(bank), 928 msr_ops.addr(bank), 0); 929 930 if (!mce_flags.smca) 931 return; 932 933 /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */ 934 if (defrd) { 935 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); 936 return; 937 } 938 939 /* 940 * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check 941 * for a valid error. 942 */ 943 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), 944 MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); 945 } 946 947 /* APIC interrupt handler for deferred errors */ 948 static void amd_deferred_error_interrupt(void) 949 { 950 unsigned int bank; 951 952 for (bank = 0; bank < mca_cfg.banks; ++bank) 953 log_error_deferred(bank); 954 } 955 956 static void log_error_thresholding(unsigned int bank, u64 misc) 957 { 958 _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc); 959 } 960 961 static void log_and_reset_block(struct threshold_block *block) 962 { 963 struct thresh_restart tr; 964 u32 low = 0, high = 0; 965 966 if (!block) 967 return; 968 969 if (rdmsr_safe(block->address, &low, &high)) 970 return; 971 972 if (!(high & MASK_OVERFLOW_HI)) 973 return; 974 975 /* Log the MCE which caused the threshold event. */ 976 log_error_thresholding(block->bank, ((u64)high << 32) | low); 977 978 /* Reset threshold block after logging error. */ 979 memset(&tr, 0, sizeof(tr)); 980 tr.b = block; 981 threshold_restart_bank(&tr); 982 } 983 984 /* 985 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt 986 * goes off when error_count reaches threshold_limit. 987 */ 988 static void amd_threshold_interrupt(void) 989 { 990 struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; 991 unsigned int bank, cpu = smp_processor_id(); 992 993 for (bank = 0; bank < mca_cfg.banks; ++bank) { 994 if (!(per_cpu(bank_map, cpu) & (1 << bank))) 995 continue; 996 997 first_block = per_cpu(threshold_banks, cpu)[bank]->blocks; 998 if (!first_block) 999 continue; 1000 1001 /* 1002 * The first block is also the head of the list. Check it first 1003 * before iterating over the rest. 1004 */ 1005 log_and_reset_block(first_block); 1006 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) 1007 log_and_reset_block(block); 1008 } 1009 } 1010 1011 /* 1012 * Sysfs Interface 1013 */ 1014 1015 struct threshold_attr { 1016 struct attribute attr; 1017 ssize_t (*show) (struct threshold_block *, char *); 1018 ssize_t (*store) (struct threshold_block *, const char *, size_t count); 1019 }; 1020 1021 #define SHOW_FIELDS(name) \ 1022 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ 1023 { \ 1024 return sprintf(buf, "%lu\n", (unsigned long) b->name); \ 1025 } 1026 SHOW_FIELDS(interrupt_enable) 1027 SHOW_FIELDS(threshold_limit) 1028 1029 static ssize_t 1030 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) 1031 { 1032 struct thresh_restart tr; 1033 unsigned long new; 1034 1035 if (!b->interrupt_capable) 1036 return -EINVAL; 1037 1038 if (kstrtoul(buf, 0, &new) < 0) 1039 return -EINVAL; 1040 1041 b->interrupt_enable = !!new; 1042 1043 memset(&tr, 0, sizeof(tr)); 1044 tr.b = b; 1045 1046 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); 1047 1048 return size; 1049 } 1050 1051 static ssize_t 1052 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) 1053 { 1054 struct thresh_restart tr; 1055 unsigned long new; 1056 1057 if (kstrtoul(buf, 0, &new) < 0) 1058 return -EINVAL; 1059 1060 if (new > THRESHOLD_MAX) 1061 new = THRESHOLD_MAX; 1062 if (new < 1) 1063 new = 1; 1064 1065 memset(&tr, 0, sizeof(tr)); 1066 tr.old_limit = b->threshold_limit; 1067 b->threshold_limit = new; 1068 tr.b = b; 1069 1070 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); 1071 1072 return size; 1073 } 1074 1075 static ssize_t show_error_count(struct threshold_block *b, char *buf) 1076 { 1077 u32 lo, hi; 1078 1079 rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); 1080 1081 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - 1082 (THRESHOLD_MAX - b->threshold_limit))); 1083 } 1084 1085 static struct threshold_attr error_count = { 1086 .attr = {.name = __stringify(error_count), .mode = 0444 }, 1087 .show = show_error_count, 1088 }; 1089 1090 #define RW_ATTR(val) \ 1091 static struct threshold_attr val = { \ 1092 .attr = {.name = __stringify(val), .mode = 0644 }, \ 1093 .show = show_## val, \ 1094 .store = store_## val, \ 1095 }; 1096 1097 RW_ATTR(interrupt_enable); 1098 RW_ATTR(threshold_limit); 1099 1100 static struct attribute *default_attrs[] = { 1101 &threshold_limit.attr, 1102 &error_count.attr, 1103 NULL, /* possibly interrupt_enable if supported, see below */ 1104 NULL, 1105 }; 1106 1107 #define to_block(k) container_of(k, struct threshold_block, kobj) 1108 #define to_attr(a) container_of(a, struct threshold_attr, attr) 1109 1110 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) 1111 { 1112 struct threshold_block *b = to_block(kobj); 1113 struct threshold_attr *a = to_attr(attr); 1114 ssize_t ret; 1115 1116 ret = a->show ? a->show(b, buf) : -EIO; 1117 1118 return ret; 1119 } 1120 1121 static ssize_t store(struct kobject *kobj, struct attribute *attr, 1122 const char *buf, size_t count) 1123 { 1124 struct threshold_block *b = to_block(kobj); 1125 struct threshold_attr *a = to_attr(attr); 1126 ssize_t ret; 1127 1128 ret = a->store ? a->store(b, buf, count) : -EIO; 1129 1130 return ret; 1131 } 1132 1133 static const struct sysfs_ops threshold_ops = { 1134 .show = show, 1135 .store = store, 1136 }; 1137 1138 static struct kobj_type threshold_ktype = { 1139 .sysfs_ops = &threshold_ops, 1140 .default_attrs = default_attrs, 1141 }; 1142 1143 static const char *get_name(unsigned int bank, struct threshold_block *b) 1144 { 1145 enum smca_bank_types bank_type; 1146 1147 if (!mce_flags.smca) { 1148 if (b && bank == 4) 1149 return bank4_names(b); 1150 1151 return th_names[bank]; 1152 } 1153 1154 bank_type = smca_get_bank_type(bank); 1155 if (bank_type >= N_SMCA_BANK_TYPES) 1156 return NULL; 1157 1158 if (b && bank_type == SMCA_UMC) { 1159 if (b->block < ARRAY_SIZE(smca_umc_block_names)) 1160 return smca_umc_block_names[b->block]; 1161 return NULL; 1162 } 1163 1164 if (smca_banks[bank].hwid->count == 1) 1165 return smca_get_name(bank_type); 1166 1167 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, 1168 "%s_%x", smca_get_name(bank_type), 1169 smca_banks[bank].sysfs_id); 1170 return buf_mcatype; 1171 } 1172 1173 static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, 1174 unsigned int block, u32 address) 1175 { 1176 struct threshold_block *b = NULL; 1177 u32 low, high; 1178 int err; 1179 1180 if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) 1181 return 0; 1182 1183 if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) 1184 return 0; 1185 1186 if (!(high & MASK_VALID_HI)) { 1187 if (block) 1188 goto recurse; 1189 else 1190 return 0; 1191 } 1192 1193 if (!(high & MASK_CNTP_HI) || 1194 (high & MASK_LOCKED_HI)) 1195 goto recurse; 1196 1197 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); 1198 if (!b) 1199 return -ENOMEM; 1200 1201 b->block = block; 1202 b->bank = bank; 1203 b->cpu = cpu; 1204 b->address = address; 1205 b->interrupt_enable = 0; 1206 b->interrupt_capable = lvt_interrupt_supported(bank, high); 1207 b->threshold_limit = THRESHOLD_MAX; 1208 1209 if (b->interrupt_capable) { 1210 threshold_ktype.default_attrs[2] = &interrupt_enable.attr; 1211 b->interrupt_enable = 1; 1212 } else { 1213 threshold_ktype.default_attrs[2] = NULL; 1214 } 1215 1216 INIT_LIST_HEAD(&b->miscj); 1217 1218 if (per_cpu(threshold_banks, cpu)[bank]->blocks) { 1219 list_add(&b->miscj, 1220 &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); 1221 } else { 1222 per_cpu(threshold_banks, cpu)[bank]->blocks = b; 1223 } 1224 1225 err = kobject_init_and_add(&b->kobj, &threshold_ktype, 1226 per_cpu(threshold_banks, cpu)[bank]->kobj, 1227 get_name(bank, b)); 1228 if (err) 1229 goto out_free; 1230 recurse: 1231 address = get_block_address(address, low, high, bank, ++block); 1232 if (!address) 1233 return 0; 1234 1235 err = allocate_threshold_blocks(cpu, bank, block, address); 1236 if (err) 1237 goto out_free; 1238 1239 if (b) 1240 kobject_uevent(&b->kobj, KOBJ_ADD); 1241 1242 return err; 1243 1244 out_free: 1245 if (b) { 1246 kobject_put(&b->kobj); 1247 list_del(&b->miscj); 1248 kfree(b); 1249 } 1250 return err; 1251 } 1252 1253 static int __threshold_add_blocks(struct threshold_bank *b) 1254 { 1255 struct list_head *head = &b->blocks->miscj; 1256 struct threshold_block *pos = NULL; 1257 struct threshold_block *tmp = NULL; 1258 int err = 0; 1259 1260 err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); 1261 if (err) 1262 return err; 1263 1264 list_for_each_entry_safe(pos, tmp, head, miscj) { 1265 1266 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); 1267 if (err) { 1268 list_for_each_entry_safe_reverse(pos, tmp, head, miscj) 1269 kobject_del(&pos->kobj); 1270 1271 return err; 1272 } 1273 } 1274 return err; 1275 } 1276 1277 static int threshold_create_bank(unsigned int cpu, unsigned int bank) 1278 { 1279 struct device *dev = per_cpu(mce_device, cpu); 1280 struct amd_northbridge *nb = NULL; 1281 struct threshold_bank *b = NULL; 1282 const char *name = get_name(bank, NULL); 1283 int err = 0; 1284 1285 if (!dev) 1286 return -ENODEV; 1287 1288 if (is_shared_bank(bank)) { 1289 nb = node_to_amd_nb(amd_get_nb_id(cpu)); 1290 1291 /* threshold descriptor already initialized on this node? */ 1292 if (nb && nb->bank4) { 1293 /* yes, use it */ 1294 b = nb->bank4; 1295 err = kobject_add(b->kobj, &dev->kobj, name); 1296 if (err) 1297 goto out; 1298 1299 per_cpu(threshold_banks, cpu)[bank] = b; 1300 refcount_inc(&b->cpus); 1301 1302 err = __threshold_add_blocks(b); 1303 1304 goto out; 1305 } 1306 } 1307 1308 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); 1309 if (!b) { 1310 err = -ENOMEM; 1311 goto out; 1312 } 1313 1314 b->kobj = kobject_create_and_add(name, &dev->kobj); 1315 if (!b->kobj) { 1316 err = -EINVAL; 1317 goto out_free; 1318 } 1319 1320 per_cpu(threshold_banks, cpu)[bank] = b; 1321 1322 if (is_shared_bank(bank)) { 1323 refcount_set(&b->cpus, 1); 1324 1325 /* nb is already initialized, see above */ 1326 if (nb) { 1327 WARN_ON(nb->bank4); 1328 nb->bank4 = b; 1329 } 1330 } 1331 1332 err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank)); 1333 if (!err) 1334 goto out; 1335 1336 out_free: 1337 kfree(b); 1338 1339 out: 1340 return err; 1341 } 1342 1343 static void deallocate_threshold_block(unsigned int cpu, 1344 unsigned int bank) 1345 { 1346 struct threshold_block *pos = NULL; 1347 struct threshold_block *tmp = NULL; 1348 struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; 1349 1350 if (!head) 1351 return; 1352 1353 list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { 1354 kobject_put(&pos->kobj); 1355 list_del(&pos->miscj); 1356 kfree(pos); 1357 } 1358 1359 kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); 1360 per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; 1361 } 1362 1363 static void __threshold_remove_blocks(struct threshold_bank *b) 1364 { 1365 struct threshold_block *pos = NULL; 1366 struct threshold_block *tmp = NULL; 1367 1368 kobject_del(b->kobj); 1369 1370 list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) 1371 kobject_del(&pos->kobj); 1372 } 1373 1374 static void threshold_remove_bank(unsigned int cpu, int bank) 1375 { 1376 struct amd_northbridge *nb; 1377 struct threshold_bank *b; 1378 1379 b = per_cpu(threshold_banks, cpu)[bank]; 1380 if (!b) 1381 return; 1382 1383 if (!b->blocks) 1384 goto free_out; 1385 1386 if (is_shared_bank(bank)) { 1387 if (!refcount_dec_and_test(&b->cpus)) { 1388 __threshold_remove_blocks(b); 1389 per_cpu(threshold_banks, cpu)[bank] = NULL; 1390 return; 1391 } else { 1392 /* 1393 * the last CPU on this node using the shared bank is 1394 * going away, remove that bank now. 1395 */ 1396 nb = node_to_amd_nb(amd_get_nb_id(cpu)); 1397 nb->bank4 = NULL; 1398 } 1399 } 1400 1401 deallocate_threshold_block(cpu, bank); 1402 1403 free_out: 1404 kobject_del(b->kobj); 1405 kobject_put(b->kobj); 1406 kfree(b); 1407 per_cpu(threshold_banks, cpu)[bank] = NULL; 1408 } 1409 1410 int mce_threshold_remove_device(unsigned int cpu) 1411 { 1412 unsigned int bank; 1413 1414 for (bank = 0; bank < mca_cfg.banks; ++bank) { 1415 if (!(per_cpu(bank_map, cpu) & (1 << bank))) 1416 continue; 1417 threshold_remove_bank(cpu, bank); 1418 } 1419 kfree(per_cpu(threshold_banks, cpu)); 1420 per_cpu(threshold_banks, cpu) = NULL; 1421 return 0; 1422 } 1423 1424 /* create dir/files for all valid threshold banks */ 1425 int mce_threshold_create_device(unsigned int cpu) 1426 { 1427 unsigned int bank; 1428 struct threshold_bank **bp; 1429 int err = 0; 1430 1431 bp = per_cpu(threshold_banks, cpu); 1432 if (bp) 1433 return 0; 1434 1435 bp = kcalloc(mca_cfg.banks, sizeof(struct threshold_bank *), 1436 GFP_KERNEL); 1437 if (!bp) 1438 return -ENOMEM; 1439 1440 per_cpu(threshold_banks, cpu) = bp; 1441 1442 for (bank = 0; bank < mca_cfg.banks; ++bank) { 1443 if (!(per_cpu(bank_map, cpu) & (1 << bank))) 1444 continue; 1445 err = threshold_create_bank(cpu, bank); 1446 if (err) 1447 goto err; 1448 } 1449 return err; 1450 err: 1451 mce_threshold_remove_device(cpu); 1452 return err; 1453 } 1454 1455 static __init int threshold_init_device(void) 1456 { 1457 unsigned lcpu = 0; 1458 1459 /* to hit CPUs online before the notifier is up */ 1460 for_each_online_cpu(lcpu) { 1461 int err = mce_threshold_create_device(lcpu); 1462 1463 if (err) 1464 return err; 1465 } 1466 1467 if (thresholding_irq_en) 1468 mce_threshold_vector = amd_threshold_interrupt; 1469 1470 return 0; 1471 } 1472 /* 1473 * there are 3 funcs which need to be _initcalled in a logic sequence: 1474 * 1. xen_late_init_mcelog 1475 * 2. mcheck_init_device 1476 * 3. threshold_init_device 1477 * 1478 * xen_late_init_mcelog must register xen_mce_chrdev_device before 1479 * native mce_chrdev_device registration if running under xen platform; 1480 * 1481 * mcheck_init_device should be inited before threshold_init_device to 1482 * initialize mce_device, otherwise a NULL ptr dereference will cause panic. 1483 * 1484 * so we use following _initcalls 1485 * 1. device_initcall(xen_late_init_mcelog); 1486 * 2. device_initcall_sync(mcheck_init_device); 1487 * 3. late_initcall(threshold_init_device); 1488 * 1489 * when running under xen, the initcall order is 1,2,3; 1490 * on baremetal, we skip 1 and we do only 2 and 3. 1491 */ 1492 late_initcall(threshold_init_device); 1493